1*b7fc3726Sstsp /* $OpenBSD: if_dwqe_pci.c,v 1.3 2023/11/11 16:50:25 stsp Exp $ */
26e9149a4Sstsp
36e9149a4Sstsp /*
46e9149a4Sstsp * Copyright (c) 2023 Stefan Sperling <stsp@openbsd.org>
56e9149a4Sstsp *
66e9149a4Sstsp * Permission to use, copy, modify, and distribute this software for any
76e9149a4Sstsp * purpose with or without fee is hereby granted, provided that the above
86e9149a4Sstsp * copyright notice and this permission notice appear in all copies.
96e9149a4Sstsp *
106e9149a4Sstsp * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
116e9149a4Sstsp * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
126e9149a4Sstsp * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
136e9149a4Sstsp * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
146e9149a4Sstsp * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
156e9149a4Sstsp * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
166e9149a4Sstsp * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
176e9149a4Sstsp */
186e9149a4Sstsp
196e9149a4Sstsp /*
206e9149a4Sstsp * Driver for the Intel Elkhart Lake ethernet controller.
216e9149a4Sstsp */
226e9149a4Sstsp
236e9149a4Sstsp #include <sys/param.h>
246e9149a4Sstsp #include <sys/systm.h>
256e9149a4Sstsp #include <sys/device.h>
266e9149a4Sstsp
276e9149a4Sstsp #include <dev/pci/pcireg.h>
286e9149a4Sstsp #include <dev/pci/pcivar.h>
296e9149a4Sstsp #include <dev/pci/pcidevs.h>
306e9149a4Sstsp
316e9149a4Sstsp #include <net/if.h>
326e9149a4Sstsp #include <net/if_media.h>
336e9149a4Sstsp
346e9149a4Sstsp #include <netinet/in.h>
356e9149a4Sstsp #include <netinet/if_ether.h>
366e9149a4Sstsp
376e9149a4Sstsp #include <dev/mii/miivar.h>
386e9149a4Sstsp
396e9149a4Sstsp #include <dev/ic/dwqereg.h>
406e9149a4Sstsp #include <dev/ic/dwqevar.h>
416e9149a4Sstsp
426e9149a4Sstsp static const struct pci_matchid dwqe_pci_devices[] = {
436e9149a4Sstsp { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G },
446e9149a4Sstsp { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_1G },
456e9149a4Sstsp { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_2G },
46*b7fc3726Sstsp #if 0
476e9149a4Sstsp { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_RGMII_1G },
48*b7fc3726Sstsp #endif
496e9149a4Sstsp { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_1G },
506e9149a4Sstsp { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_2G },
516e9149a4Sstsp };
526e9149a4Sstsp
536e9149a4Sstsp struct dwqe_pci_softc {
546e9149a4Sstsp struct dwqe_softc sc_sc;
556e9149a4Sstsp pci_chipset_tag_t sc_pct;
566e9149a4Sstsp pcitag_t sc_pcitag;
576e9149a4Sstsp bus_size_t sc_mapsize;
586e9149a4Sstsp };
596e9149a4Sstsp
606e9149a4Sstsp int
dwqe_pci_match(struct device * parent,void * cfdata,void * aux)616e9149a4Sstsp dwqe_pci_match(struct device *parent, void *cfdata, void *aux)
626e9149a4Sstsp {
636e9149a4Sstsp struct pci_attach_args *pa = aux;
646e9149a4Sstsp return pci_matchbyid(pa, dwqe_pci_devices, nitems(dwqe_pci_devices));
656e9149a4Sstsp }
666e9149a4Sstsp
676e9149a4Sstsp void
dwqe_pci_attach(struct device * parent,struct device * self,void * aux)686e9149a4Sstsp dwqe_pci_attach(struct device *parent, struct device *self, void *aux)
696e9149a4Sstsp {
706e9149a4Sstsp struct pci_attach_args *pa = aux;
716e9149a4Sstsp struct dwqe_pci_softc *psc = (void *)self;
726e9149a4Sstsp struct dwqe_softc *sc = &psc->sc_sc;
736e9149a4Sstsp pci_intr_handle_t ih;
746e9149a4Sstsp pcireg_t memtype;
756e9149a4Sstsp int err;
766e9149a4Sstsp const char *intrstr;
776e9149a4Sstsp
786e9149a4Sstsp psc->sc_pct = pa->pa_pc;
796e9149a4Sstsp psc->sc_pcitag = pa->pa_tag;
806e9149a4Sstsp
816e9149a4Sstsp sc->sc_dmat = pa->pa_dmat;
826e9149a4Sstsp
836e9149a4Sstsp memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START);
846e9149a4Sstsp err = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0,
856e9149a4Sstsp &sc->sc_iot, &sc->sc_ioh, NULL, &psc->sc_mapsize, 0);
866e9149a4Sstsp if (err) {
876e9149a4Sstsp printf("%s: can't map mem space\n", DEVNAME(sc));
886e9149a4Sstsp return;
896e9149a4Sstsp }
906e9149a4Sstsp
916e9149a4Sstsp if (pci_intr_map_msi(pa, &ih) && pci_intr_map(pa, &ih)) {
926e9149a4Sstsp printf("%s: can't map interrupt\n", DEVNAME(sc));
936e9149a4Sstsp return;
946e9149a4Sstsp }
956e9149a4Sstsp
966e9149a4Sstsp intrstr = pci_intr_string(psc->sc_pct, ih);
976e9149a4Sstsp sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET | IPL_MPSAFE,
986e9149a4Sstsp dwqe_intr, psc, sc->sc_dev.dv_xname);
996e9149a4Sstsp if (sc->sc_ih == NULL) {
1006e9149a4Sstsp printf(": can't establish interrupt");
1016e9149a4Sstsp if (intrstr != NULL)
1026e9149a4Sstsp printf(" at %s", intrstr);
1036e9149a4Sstsp printf("\n");
1046e9149a4Sstsp return;
1056e9149a4Sstsp }
1066e9149a4Sstsp
1076e9149a4Sstsp switch (PCI_PRODUCT(pa->pa_id)) {
1086e9149a4Sstsp case PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G:
1096e9149a4Sstsp sc->sc_phy_mode = DWQE_PHY_MODE_RGMII_ID;
1106e9149a4Sstsp sc->sc_clk = GMAC_MAC_MDIO_ADDR_CR_250_300;
1116e9149a4Sstsp sc->sc_clkrate = 200000000;
1126e9149a4Sstsp break;
113*b7fc3726Sstsp case PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_1G:
114*b7fc3726Sstsp case PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_2G:
115*b7fc3726Sstsp case PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_1G:
116*b7fc3726Sstsp case PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_2G:
117*b7fc3726Sstsp sc->sc_phy_mode = DWQE_PHY_MODE_SGMII;
118*b7fc3726Sstsp sc->sc_clk = GMAC_MAC_MDIO_ADDR_CR_250_300;
119*b7fc3726Sstsp sc->sc_clkrate = 200000000;
120*b7fc3726Sstsp break;
1216e9149a4Sstsp default:
1226e9149a4Sstsp sc->sc_phy_mode = DWQE_PHY_MODE_UNKNOWN;
1236e9149a4Sstsp break;
1246e9149a4Sstsp }
1256e9149a4Sstsp
1266e9149a4Sstsp sc->sc_phyloc = MII_PHY_ANY;
1276e9149a4Sstsp sc->sc_8xpbl = 1;
1286e9149a4Sstsp sc->sc_txpbl = 32;
1296e9149a4Sstsp sc->sc_rxpbl = 32;
1306e9149a4Sstsp sc->sc_txfifo_size = 32768;
1316e9149a4Sstsp sc->sc_rxfifo_size = 32768;
1326e9149a4Sstsp
1336e9149a4Sstsp sc->sc_axi_config = 1;
1346e9149a4Sstsp sc->sc_wr_osr_lmt = 1;
1356e9149a4Sstsp sc->sc_rd_osr_lmt = 1;
1366e9149a4Sstsp sc->sc_blen[0] = 4;
1376e9149a4Sstsp sc->sc_blen[1] = 8;
1386e9149a4Sstsp sc->sc_blen[2] = 16;
1396e9149a4Sstsp
1406e9149a4Sstsp dwqe_lladdr_read(sc, sc->sc_lladdr);
1416e9149a4Sstsp
1426e9149a4Sstsp dwqe_reset(sc);
1436e9149a4Sstsp dwqe_attach(sc);
1446e9149a4Sstsp }
1456e9149a4Sstsp
1466e9149a4Sstsp const struct cfattach dwqe_pci_ca = {
1476e9149a4Sstsp sizeof(struct dwqe_softc), dwqe_pci_match, dwqe_pci_attach
1486e9149a4Sstsp };
149