1 /* $OpenBSD: if_epic_pci.c,v 1.16 2015/11/24 17:11:39 mpi Exp $ */ 2 /* $NetBSD: if_epic_pci.c,v 1.28 2005/02/27 00:27:32 perry Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus front-end for the Standard Microsystems Corp. 83C170 36 * Ethernet PCI Integrated Controller (EPIC/100) driver. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/ioctl.h> 46 #include <sys/errno.h> 47 #include <sys/device.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 58 #include <dev/mii/miivar.h> 59 60 #include <dev/ic/smc83c170reg.h> 61 #include <dev/ic/smc83c170var.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 /* 68 * PCI configuration space registers used by the EPIC. 69 */ 70 #define EPIC_PCI_IOBA 0x10 /* i/o mapped base */ 71 #define EPIC_PCI_MMBA 0x14 /* memory mapped base */ 72 73 struct epic_pci_softc { 74 struct epic_softc sc_epic; /* real EPIC softc */ 75 76 /* PCI-specific goo. */ 77 void *sc_ih; /* interrupt handle */ 78 }; 79 80 int epic_pci_match(struct device *, void *, void *); 81 void epic_pci_attach(struct device *, struct device *, void *); 82 83 struct cfattach epic_pci_ca = { 84 sizeof(struct epic_pci_softc), epic_pci_match, epic_pci_attach 85 }; 86 87 const struct pci_matchid epic_pci_devices[] = { 88 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C170 }, 89 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C175 }, 90 }; 91 92 static const struct epic_pci_subsys_info { 93 pcireg_t subsysid; 94 int flags; 95 } epic_pci_subsys_info[] = { 96 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa015), /* SMC9432BTX */ 97 EPIC_HAS_BNC }, 98 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa024), /* SMC9432BTX1 */ 99 EPIC_HAS_BNC }, 100 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa016), /* SMC9432FTX */ 101 EPIC_HAS_MII_FIBER | EPIC_DUPLEXLED_ON_694 }, 102 { 0xffffffff, 103 0 } 104 }; 105 106 static const struct epic_pci_subsys_info * 107 epic_pci_subsys_lookup(const struct pci_attach_args *pa) 108 { 109 pci_chipset_tag_t pc = pa->pa_pc; 110 pcireg_t reg; 111 const struct epic_pci_subsys_info *esp; 112 113 reg = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 114 115 for (esp = epic_pci_subsys_info; esp->subsysid != 0xffffffff; esp++) 116 if (esp->subsysid == reg) 117 return (esp); 118 119 return (NULL); 120 } 121 122 int 123 epic_pci_match(struct device *parent, void *match, void *aux) 124 { 125 return (pci_matchbyid((struct pci_attach_args *)aux, epic_pci_devices, 126 nitems(epic_pci_devices))); 127 } 128 129 void 130 epic_pci_attach(struct device *parent, struct device *self, void *aux) 131 { 132 struct epic_pci_softc *psc = (struct epic_pci_softc *)self; 133 struct epic_softc *sc = &psc->sc_epic; 134 struct pci_attach_args *pa = aux; 135 pci_chipset_tag_t pc = pa->pa_pc; 136 pci_intr_handle_t ih; 137 const char *intrstr = NULL; 138 const struct epic_pci_subsys_info *esp; 139 bus_space_tag_t iot, memt; 140 bus_space_handle_t ioh, memh; 141 int ioh_valid, memh_valid; 142 143 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 144 145 /* 146 * Map the device. 147 */ 148 ioh_valid = (pci_mapreg_map(pa, EPIC_PCI_IOBA, 149 PCI_MAPREG_TYPE_IO, 0, 150 &iot, &ioh, NULL, NULL, 0) == 0); 151 memh_valid = (pci_mapreg_map(pa, EPIC_PCI_MMBA, 152 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 153 &memt, &memh, NULL, NULL, 0) == 0); 154 155 if (memh_valid) { 156 sc->sc_st = memt; 157 sc->sc_sh = memh; 158 } else if (ioh_valid) { 159 sc->sc_st = iot; 160 sc->sc_sh = ioh; 161 } else { 162 printf(": unable to map device registers\n"); 163 return; 164 } 165 166 sc->sc_dmat = pa->pa_dmat; 167 168 /* 169 * Map and establish our interrupt. 170 */ 171 if (pci_intr_map(pa, &ih)) { 172 printf(": unable to map interrupt\n"); 173 return; 174 } 175 intrstr = pci_intr_string(pc, ih); 176 psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, epic_intr, sc, 177 self->dv_xname); 178 if (psc->sc_ih == NULL) { 179 printf(": unable to establish interrupt"); 180 if (intrstr != NULL) 181 printf(" at %s", intrstr); 182 printf("\n"); 183 return; 184 } 185 186 esp = epic_pci_subsys_lookup(pa); 187 if (esp) 188 sc->sc_hwflags = esp->flags; 189 190 /* 191 * Finish off the attach. 192 */ 193 epic_attach(sc, intrstr); 194 } 195