1 /* $OpenBSD: if_iwnreg.h,v 1.56 2019/07/29 10:50:08 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2008 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define IWN_TX_RING_COUNT 256 21 #define IWN_TX_RING_LOMARK 192 22 #define IWN_TX_RING_HIMARK 224 23 #define IWN_RX_RING_COUNT_LOG 6 24 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 25 26 #define IWN4965_NTXQUEUES 16 27 #define IWN4965_FIRST_AGG_TXQUEUE 7 28 #define IWN5000_NTXQUEUES 20 29 #define IWN5000_FIRST_AGG_TXQUEUE 10 30 31 #define IWN4965_NDMACHNLS 7 32 #define IWN5000_NDMACHNLS 8 33 34 #define IWN_SRVC_DMACHNL 9 35 36 #define IWN_ICT_SIZE 4096 37 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 38 39 /* Maximum number of DMA segments for TX. */ 40 #define IWN_MAX_SCATTER 20 41 42 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 43 #define IWN_RBUF_SIZE (4 * 1024) 44 45 #if defined(__LP64__) 46 /* HW supports 36-bit DMA addresses. */ 47 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 48 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 49 #else 50 #define IWN_LOADDR(paddr) (paddr) 51 #define IWN_HIADDR(paddr) (0) 52 #endif 53 54 /* Base Address Register. */ 55 #define IWN_PCI_BAR0 PCI_MAPREG_START 56 57 /* 58 * Control and status registers. 59 */ 60 #define IWN_HW_IF_CONFIG 0x000 61 #define IWN_INT_COALESCING 0x004 62 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 63 #define IWN_INT 0x008 64 #define IWN_INT_MASK 0x00c 65 #define IWN_FH_INT 0x010 66 #define IWN_RESET 0x020 67 #define IWN_GP_CNTRL 0x024 68 #define IWN_HW_REV 0x028 69 #define IWN_EEPROM 0x02c 70 #define IWN_EEPROM_GP 0x030 71 #define IWN_OTP_GP 0x034 72 #define IWN_GIO 0x03c 73 #define IWN_GP_DRIVER 0x050 74 #define IWN_UCODE_GP1_CLR 0x05c 75 #define IWN_LED 0x094 76 #define IWN_DRAM_INT_TBL 0x0a0 77 #define IWN_SHADOW_REG_CTRL 0x0a8 78 #define IWN_GIO_CHICKEN 0x100 79 #define IWN_ANA_PLL 0x20c 80 #define IWN_HW_REV_WA 0x22c 81 #define IWN_DBG_HPET_MEM 0x240 82 #define IWN_DBG_LINK_PWR_MGMT 0x250 83 #define IWN_MEM_RADDR 0x40c 84 #define IWN_MEM_WADDR 0x410 85 #define IWN_MEM_WDATA 0x418 86 #define IWN_MEM_RDATA 0x41c 87 #define IWN_PRPH_WADDR 0x444 88 #define IWN_PRPH_RADDR 0x448 89 #define IWN_PRPH_WDATA 0x44c 90 #define IWN_PRPH_RDATA 0x450 91 #define IWN_HBUS_TARG_WRPTR 0x460 92 93 /* 94 * Flow-Handler registers. 95 */ 96 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 97 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 98 #define IWN_FH_KW_ADDR 0x197c 99 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 100 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 101 #define IWN_FH_STATUS_WPTR 0x1bc0 102 #define IWN_FH_RX_BASE 0x1bc4 103 #define IWN_FH_RX_WPTR 0x1bc8 104 #define IWN_FH_RX_CONFIG 0x1c00 105 #define IWN_FH_RX_STATUS 0x1c44 106 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 107 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 108 #define IWN_FH_TX_CHICKEN 0x1e98 109 #define IWN_FH_TX_STATUS 0x1eb0 110 111 /* 112 * TX scheduler registers. 113 */ 114 #define IWN_SCHED_BASE 0xa02c00 115 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 116 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 117 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 118 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 119 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 120 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 121 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 122 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 123 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 124 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 125 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 126 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 127 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 128 #define IWN5000_SCHED_CHAINEXT_EN (IWN_SCHED_BASE + 0x244) 129 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 130 131 /* 132 * Offsets in TX scheduler's SRAM. 133 */ 134 #define IWN4965_SCHED_CTX_OFF 0x380 135 #define IWN4965_SCHED_CTX_LEN 416 136 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 137 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 138 #define IWN5000_SCHED_CTX_OFF 0x600 139 #define IWN5000_SCHED_CTX_LEN 520 140 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 141 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 142 143 /* 144 * NIC internal memory offsets. 145 */ 146 #define IWN_APMG_CLK_CTRL 0x3000 147 #define IWN_APMG_CLK_EN 0x3004 148 #define IWN_APMG_CLK_DIS 0x3008 149 #define IWN_APMG_PS 0x300c 150 #define IWN_APMG_DIGITAL_SVR 0x3058 151 #define IWN_APMG_ANALOG_SVR 0x306c 152 #define IWN_APMG_PCI_STT 0x3010 153 #define IWN_BSM_WR_CTRL 0x3400 154 #define IWN_BSM_WR_MEM_SRC 0x3404 155 #define IWN_BSM_WR_MEM_DST 0x3408 156 #define IWN_BSM_WR_DWCOUNT 0x340c 157 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 158 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 159 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 160 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 161 #define IWN_BSM_SRAM_BASE 0x3800 162 163 /* Possible flags for register IWN_HW_IF_CONFIG. */ 164 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 165 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 166 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 167 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 168 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 169 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 170 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 171 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 172 173 /* Possible values for register IWN_INT_PERIODIC. */ 174 #define IWN_INT_PERIODIC_DIS 0x00 175 #define IWN_INT_PERIODIC_ENA 0xff 176 177 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 178 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 179 180 /* Possible values for IWN_BSM_WR_MEM_DST. */ 181 #define IWN_FW_TEXT_BASE 0x00000000 182 #define IWN_FW_DATA_BASE 0x00800000 183 184 /* Possible flags for register IWN_RESET. */ 185 #define IWN_RESET_NEVO (1U << 0) 186 #define IWN_RESET_SW (1U << 7) 187 #define IWN_RESET_MASTER_DISABLED (1U << 8) 188 #define IWN_RESET_STOP_MASTER (1U << 9) 189 #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 190 191 /* Possible flags for register IWN_GP_CNTRL. */ 192 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 193 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 194 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 195 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 196 #define IWN_GP_CNTRL_SLEEP (1 << 4) 197 #define IWN_GP_CNTRL_RFKILL (1 << 27) 198 199 /* Possible flags for register IWN_HW_REV. */ 200 #define IWN_HW_REV_TYPE_SHIFT 4 201 #define IWN_HW_REV_TYPE_MASK 0x000001f0 202 #define IWN_HW_REV_TYPE_4965 0 203 #define IWN_HW_REV_TYPE_5300 2 204 #define IWN_HW_REV_TYPE_5350 3 205 #define IWN_HW_REV_TYPE_5150 4 206 #define IWN_HW_REV_TYPE_5100 5 207 #define IWN_HW_REV_TYPE_1000 6 208 #define IWN_HW_REV_TYPE_6000 7 209 #define IWN_HW_REV_TYPE_6050 8 210 #define IWN_HW_REV_TYPE_6005 11 211 #define IWN_HW_REV_TYPE_2030 12 212 #define IWN_HW_REV_TYPE_2000 16 213 #define IWN_HW_REV_TYPE_105 17 214 #define IWN_HW_REV_TYPE_135 18 215 216 217 /* Possible flags for register IWN_GIO_CHICKEN. */ 218 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 219 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 220 221 /* Possible flags for register IWN_GIO. */ 222 #define IWN_GIO_L0S_ENA (1 << 1) 223 224 /* Possible flags for register IWN_GP_DRIVER. */ 225 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 226 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 227 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 228 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 229 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 230 #define IWN_GP_DRIVER_RADIO_IQ_INVERT (1 << 7) 231 232 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 233 #define IWN_UCODE_GP1_RFKILL (1 << 1) 234 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 235 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 236 237 /* Possible flags/values for register IWN_LED. */ 238 #define IWN_LED_BSM_CTRL (1 << 5) 239 #define IWN_LED_OFF 0x00000038 240 #define IWN_LED_ON 0x00000078 241 242 /* Possible flags for register IWN_DRAM_INT_TBL. */ 243 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1U << 27) 244 #define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 245 246 /* Possible values for register IWN_ANA_PLL. */ 247 #define IWN_ANA_PLL_INIT 0x00880300 248 249 /* Possible flags for register IWN_FH_RX_STATUS. */ 250 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 251 252 /* Possible flags for register IWN_BSM_WR_CTRL. */ 253 #define IWN_BSM_WR_CTRL_START_EN (1U << 30) 254 #define IWN_BSM_WR_CTRL_START (1U << 31) 255 256 /* Possible flags for register IWN_INT. */ 257 #define IWN_INT_ALIVE (1U << 0) 258 #define IWN_INT_WAKEUP (1U << 1) 259 #define IWN_INT_SW_RX (1U << 3) 260 #define IWN_INT_CT_REACHED (1U << 6) 261 #define IWN_INT_RF_TOGGLED (1U << 7) 262 #define IWN_INT_SW_ERR (1U << 25) 263 #define IWN_INT_SCHED (1U << 26) 264 #define IWN_INT_FH_TX (1U << 27) 265 #define IWN_INT_RX_PERIODIC (1U << 28) 266 #define IWN_INT_HW_ERR (1U << 29) 267 #define IWN_INT_FH_RX (1U << 31) 268 269 /* Shortcut. */ 270 #define IWN_INT_MASK_DEF \ 271 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 272 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 273 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 274 275 /* Possible flags for register IWN_FH_INT. */ 276 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 277 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 278 #define IWN_FH_INT_HI_PRIOR (1 << 30) 279 /* Shortcuts for the above. */ 280 #define IWN_FH_INT_TX \ 281 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 282 #define IWN_FH_INT_RX \ 283 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 284 285 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 286 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 287 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 288 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1U << 20) 289 290 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 291 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 292 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 293 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 294 295 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 296 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 297 298 /* Possible flags for register IWN_FH_TX_STATUS. */ 299 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 300 301 /* Possible flags for register IWN_FH_RX_CONFIG. */ 302 #define IWN_FH_RX_CONFIG_ENA (1U << 31) 303 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 304 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1U << 16) 305 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1U << 15) 306 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1U << 12) 307 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) /* units 32 usec */ 308 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1U << 2) 309 310 /* Possible flags for register IWN_FH_TX_CONFIG. */ 311 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 312 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1U << 3) 313 314 /* Possible flags for register IWN_EEPROM. */ 315 #define IWN_EEPROM_READ_VALID (1 << 0) 316 #define IWN_EEPROM_CMD (1 << 1) 317 318 /* Possible flags for register IWN_EEPROM_GP. */ 319 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 320 321 /* Possible flags for register IWN_OTP_GP. */ 322 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 323 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 324 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 325 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 326 327 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 328 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 329 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 330 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 331 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 332 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 333 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 334 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 335 336 /* Possible flags for registers IWN_APMG_CLK_*. */ 337 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 338 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 339 340 /* Possible flags for register IWN_APMG_PS. */ 341 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 342 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 343 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 344 #define IWN_APMG_PS_PWR_SRC_VAUX 2 345 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 346 #define IWN_APMG_PS_RESET_REQ (1 << 26) 347 348 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 349 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 350 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 351 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 352 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 353 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 354 355 /* Possible flags for IWN_APMG_PCI_STT. */ 356 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 357 358 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 359 #define IWN_FW_UPDATED (1U << 31) 360 361 #define IWN_SCHED_WINSZ 64 362 #define IWN_SCHED_LIMIT 64 363 #define IWN4965_SCHED_COUNT 512 364 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 365 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 366 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 367 368 struct iwn_tx_desc { 369 uint8_t reserved1[3]; 370 uint8_t nsegs; 371 struct { 372 uint32_t addr; 373 uint16_t len; 374 } __packed segs[IWN_MAX_SCATTER]; 375 /* Pad to 128 bytes. */ 376 uint32_t reserved2; 377 } __packed; 378 379 struct iwn_rx_status { 380 uint16_t closed_count; 381 uint16_t closed_rx_count; 382 uint16_t finished_count; 383 uint16_t finished_rx_count; 384 uint32_t reserved[2]; 385 } __packed; 386 387 struct iwn_rx_desc { 388 uint32_t len; 389 #define IWN_RX_DESC_LEN_MASK 0x00003fff 390 #define IWN_RX_DESC_LEN_SHIFT 0 391 #define IWN_RX_DESC_FLAG_FLUSH_RB_REQ 0x80000000 392 #define IWN_RX_DESC_FLAG_IGNORE_TC 0x40000000 393 #define IWN_RX_DESC_FLAG_FAST_IRQ 0x20000000 394 395 uint8_t type; 396 #define IWN_UC_READY 1 397 #define IWN_ADD_NODE_DONE 24 398 #define IWN_TX_DONE 28 399 #define IWN5000_CALIBRATION_RESULT 102 400 #define IWN5000_CALIBRATION_DONE 103 401 #define IWN_START_SCAN 130 402 #define IWN_STOP_SCAN 132 403 #define IWN_RX_STATISTICS 156 404 #define IWN_BEACON_STATISTICS 157 405 #define IWN_STATE_CHANGED 161 406 #define IWN_BEACON_MISSED 162 407 #define IWN_RX_PHY 192 408 #define IWN_MPDU_RX_DONE 193 409 #define IWN_RX_DONE 195 410 #define IWN_RX_COMPRESSED_BA 197 411 412 uint8_t flags; /* XXX iwlwifi calls this "group_id" */ 413 uint8_t idx; 414 uint8_t qid; 415 } __packed; 416 417 /* Possible RX status flags. */ 418 #define IWN_RX_NO_CRC_ERR (1 << 0) 419 #define IWN_RX_NO_OVFL_ERR (1 << 1) 420 /* Shortcut for the above. */ 421 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 422 #define IWN_RX_MPDU_MIC_OK (1 << 6) 423 #define IWN_RX_CIPHER_MASK (7 << 8) 424 #define IWN_RX_CIPHER_CCMP (2 << 8) 425 #define IWN_RX_MPDU_DEC (1 << 11) 426 #define IWN_RX_DECRYPT_MASK (3 << 11) 427 #define IWN_RX_DECRYPT_OK (3 << 11) 428 429 struct iwn_tx_cmd { 430 uint8_t code; 431 #define IWN_CMD_RXON 16 432 #define IWN_CMD_RXON_ASSOC 17 433 #define IWN_CMD_EDCA_PARAMS 19 434 #define IWN_CMD_TIMING 20 435 #define IWN_CMD_ADD_NODE 24 436 #define IWN_CMD_TX_DATA 28 437 #define IWN_CMD_LINK_QUALITY 78 438 #define IWN_CMD_SET_LED 72 439 #define IWN5000_CMD_WIMAX_COEX 90 440 #define IWN5000_CMD_CALIB_CONFIG 101 441 #define IWN_CMD_SET_POWER_MODE 119 442 #define IWN_CMD_SCAN 128 443 #define IWN_CMD_SCAN_ABORT 129 444 #define IWN_CMD_TXPOWER_DBM 149 445 #define IWN_CMD_TXPOWER 151 446 #define IWN5000_CMD_TX_ANT_CONFIG 152 447 #define IWN_CMD_BT_COEX 155 448 #define IWN_CMD_GET_STATISTICS 156 449 #define IWN_CMD_SET_CRITICAL_TEMP 164 450 #define IWN_CMD_SET_SENSITIVITY 168 451 #define IWN_CMD_PHY_CALIB 176 452 #define IWN_CMD_BT_COEX_PRIOTABLE 204 453 #define IWN_CMD_BT_COEX_PROT 205 454 455 uint8_t flags; 456 uint8_t idx; 457 uint8_t qid; 458 uint8_t data[136]; 459 } __packed; 460 461 /* Antenna flags, used in various commands. */ 462 #define IWN_ANT_A (1 << 0) 463 #define IWN_ANT_B (1 << 1) 464 #define IWN_ANT_C (1 << 2) 465 /* Shortcuts. */ 466 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 467 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 468 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 469 470 /* Structure for command IWN_CMD_RXON. */ 471 struct iwn_rxon { 472 uint8_t myaddr[IEEE80211_ADDR_LEN]; 473 uint16_t reserved1; 474 uint8_t bssid[IEEE80211_ADDR_LEN]; 475 uint16_t reserved2; 476 uint8_t wlap[IEEE80211_ADDR_LEN]; 477 uint16_t reserved3; 478 uint8_t mode; 479 #define IWN_MODE_HOSTAP 1 480 #define IWN_MODE_STA 3 481 #define IWN_MODE_IBSS 4 482 #define IWN_MODE_MONITOR 6 483 484 uint8_t air; 485 uint16_t rxchain; 486 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 487 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 488 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 489 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 490 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 491 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 492 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 493 494 uint8_t ofdm_mask; 495 uint8_t cck_mask; 496 uint16_t associd; 497 uint32_t flags; 498 #define IWN_RXON_24GHZ (1 << 0) 499 #define IWN_RXON_CCK (1 << 1) 500 #define IWN_RXON_AUTO (1 << 2) 501 #define IWN_RXON_TGG_PROT (1 << 3) 502 #define IWN_RXON_SHSLOT (1 << 4) 503 #define IWN_RXON_SHPREAMBLE (1 << 5) 504 #define IWN_RXON_NODIVERSITY (1 << 7) 505 #define IWN_RXON_ANTENNA_A (1 << 8) 506 #define IWN_RXON_ANTENNA_B (1 << 9) 507 #define IWN_RXON_TSF (1 << 15) 508 #define IWN_RXON_HT_HT40MINUS (1 << 22) 509 #define IWN_RXON_HT_PROTMODE(x) ((x) << 23) /* 2 bits */ 510 #define IWN_RXON_HT_CHANMODE_PURE40 (1 << 25) 511 #define IWN_RXON_HT_CHANMODE_MIXED2040 (2 << 25) 512 #define IWN_RXON_CTS_TO_SELF (1 << 30) 513 514 uint32_t filter; 515 #define IWN_FILTER_PROMISC (1 << 0) 516 #define IWN_FILTER_CTL (1 << 1) 517 #define IWN_FILTER_MULTICAST (1 << 2) 518 #define IWN_FILTER_NODECRYPT (1 << 3) 519 #define IWN_FILTER_BSS (1 << 5) 520 #define IWN_FILTER_BEACON (1 << 6) 521 522 uint8_t chan; 523 uint8_t reserved4; 524 uint8_t ht_single_mask; 525 uint8_t ht_dual_mask; 526 /* The following fields are for >=5000 Series only. */ 527 uint8_t ht_triple_mask; 528 uint8_t reserved5; 529 uint16_t acquisition; 530 uint16_t reserved6; 531 } __packed; 532 533 /* Structure for command IWN_CMD_RXON_ASSOC. */ 534 struct iwn_rxon_assoc { 535 uint32_t flags; 536 uint32_t filter; 537 uint8_t ofdm_mask; 538 uint8_t cck_mask; 539 uint16_t reserved1; 540 uint8_t ht_single_mask; 541 uint8_t ht_dual_mask; 542 uint8_t ht_triple_mask; 543 uint8_t reserved2; 544 uint16_t rxchain; 545 uint16_t acquisition; 546 uint32_t reserved3; 547 } __packed; 548 549 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 550 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 551 552 /* Structure for command IWN_CMD_ASSOCIATE. */ 553 struct iwn_assoc { 554 uint32_t flags; 555 uint32_t filter; 556 uint8_t ofdm_mask; 557 uint8_t cck_mask; 558 uint16_t reserved; 559 } __packed; 560 561 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 562 struct iwn_edca_params { 563 uint32_t flags; 564 #define IWN_EDCA_UPDATE (1 << 0) 565 #define IWN_EDCA_TXOP (1 << 4) 566 567 struct { 568 uint16_t cwmin; 569 uint16_t cwmax; 570 uint8_t aifsn; 571 uint8_t reserved; 572 uint16_t txoplimit; 573 } __packed ac[EDCA_NUM_AC]; 574 } __packed; 575 576 /* Structure for command IWN_CMD_TIMING. */ 577 struct iwn_cmd_timing { 578 uint64_t tstamp; 579 uint16_t bintval; 580 uint16_t atim; 581 uint32_t binitval; 582 uint16_t lintval; 583 uint16_t reserved; 584 } __packed; 585 586 /* Structure for command IWN_CMD_ADD_NODE. */ 587 struct iwn_node_info { 588 uint8_t control; 589 #define IWN_NODE_UPDATE (1 << 0) 590 591 uint8_t reserved1[3]; 592 593 uint8_t macaddr[IEEE80211_ADDR_LEN]; 594 uint16_t reserved2; 595 uint8_t id; 596 #define IWN_ID_BSS 0 597 #define IWN5000_ID_BROADCAST 15 598 #define IWN4965_ID_BROADCAST 31 599 600 uint8_t flags; 601 #define IWN_FLAG_SET_KEY (1 << 0) 602 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 603 #define IWN_FLAG_SET_TXRATE (1 << 2) 604 #define IWN_FLAG_SET_ADDBA (1 << 3) 605 #define IWN_FLAG_SET_DELBA (1 << 4) 606 607 uint16_t reserved3; 608 uint16_t kflags; 609 #define IWN_KFLAG_CCMP (1 << 1) 610 #define IWN_KFLAG_MAP (1 << 3) 611 #define IWN_KFLAG_KID(kid) ((kid) << 8) 612 #define IWN_KFLAG_INVALID (1 << 11) 613 #define IWN_KFLAG_GROUP (1 << 14) 614 615 uint8_t tsc2; /* TKIP TSC2 */ 616 uint8_t reserved4; 617 uint16_t ttak[5]; 618 uint8_t kid; 619 uint8_t reserved5; 620 uint8_t key[16]; 621 /* The following 3 fields are for 5000 Series only. */ 622 uint64_t tsc; 623 uint8_t rxmic[IEEE80211_TKIP_MICLEN]; 624 uint8_t txmic[IEEE80211_TKIP_MICLEN]; 625 626 uint32_t htflags; 627 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 628 #define IWN_AMDPU_SIZE_FACTOR_MASK ((0x3) << 19) 629 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 630 #define IWN_AMDPU_DENSITY_MASK ((0x7) << 23) 631 632 uint32_t htmask; 633 uint16_t disable_tid; 634 uint16_t reserved6; 635 uint8_t addba_tid; 636 uint8_t delba_tid; 637 uint16_t addba_ssn; 638 uint32_t reserved7; 639 } __packed; 640 641 struct iwn4965_node_info { 642 uint8_t control; 643 uint8_t reserved1[3]; 644 uint8_t macaddr[IEEE80211_ADDR_LEN]; 645 uint16_t reserved2; 646 uint8_t id; 647 uint8_t flags; 648 uint16_t reserved3; 649 uint16_t kflags; 650 uint8_t tsc2; /* TKIP TSC2 */ 651 uint8_t reserved4; 652 uint16_t ttak[5]; 653 uint8_t kid; 654 uint8_t reserved5; 655 uint8_t key[16]; 656 uint32_t htflags; 657 uint32_t htmask; 658 uint16_t disable_tid; 659 uint16_t reserved6; 660 uint8_t addba_tid; 661 uint8_t delba_tid; 662 uint16_t addba_ssn; 663 uint32_t reserved7; 664 } __packed; 665 666 #define IWN_RFLAG_MCS (1 << 0) 667 #define IWN_RFLAG_CCK (1 << 1) 668 #define IWN_RFLAG_GREENFIELD (1 << 2) 669 #define IWN_RFLAG_HT40 (1 << 3) 670 #define IWN_RFLAG_DUPLICATE (1 << 4) 671 #define IWN_RFLAG_SGI (1 << 5) 672 #define IWN_RFLAG_ANT(x) ((x) << 6) 673 674 /* Structure for command IWN_CMD_TX_DATA. */ 675 struct iwn_cmd_data { 676 uint16_t len; 677 uint16_t lnext; 678 uint32_t flags; 679 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 680 #define IWN_TX_NEED_RTS (1 << 1) 681 #define IWN_TX_NEED_CTS (1 << 2) 682 #define IWN_TX_NEED_ACK (1 << 3) 683 #define IWN_TX_LINKQ (1 << 4) 684 #define IWN_TX_IMM_BA (1 << 6) 685 #define IWN_TX_FULL_TXOP (1 << 7) 686 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 687 #define IWN_TX_AUTO_SEQ (1 << 13) 688 #define IWN_TX_MORE_FRAG (1 << 14) 689 #define IWN_TX_INSERT_TSTAMP (1 << 16) 690 #define IWN_TX_NEED_PADDING (1 << 20) 691 #define IWN_TX_AMPDU_CCMP (1 << 22) 692 693 uint32_t scratch; 694 uint8_t plcp; 695 uint8_t rflags; 696 uint16_t xrflags; 697 698 uint8_t id; 699 uint8_t security; 700 #define IWN_CIPHER_WEP40 1 701 #define IWN_CIPHER_CCMP 2 702 #define IWN_CIPHER_TKIP 3 703 #define IWN_CIPHER_WEP104 9 704 705 uint8_t linkq; 706 uint8_t reserved2; 707 uint8_t key[16]; 708 uint16_t fnext; 709 uint16_t reserved3; 710 uint32_t lifetime; 711 #define IWN_LIFETIME_INFINITE 0xffffffff 712 713 uint32_t loaddr; 714 uint8_t hiaddr; 715 uint8_t rts_ntries; 716 uint8_t data_ntries; 717 uint8_t tid; 718 uint16_t timeout; 719 uint16_t txop; 720 } __packed; 721 722 /* Structure for command IWN_CMD_LINK_QUALITY. */ 723 #define IWN_MAX_TX_RETRIES 16 724 struct iwn_cmd_link_quality { 725 uint8_t id; 726 uint8_t reserved1; 727 uint16_t ctl; 728 uint8_t flags; 729 uint8_t mimo; 730 uint8_t antmsk_1stream; 731 uint8_t antmsk_2stream; 732 uint8_t ridx[EDCA_NUM_AC]; 733 uint16_t ampdu_limit; 734 uint8_t ampdu_threshold; 735 uint8_t ampdu_max; 736 #define IWN_AMPDU_MAX_UNLIMITED 0 737 #define IWN_AMPDU_MAX_NO_AGG 1 738 #define IWN_AMPDU_MAX 63 739 uint32_t reserved2; 740 struct { 741 uint8_t plcp; 742 uint8_t rflags; 743 uint16_t xrflags; 744 } __packed retry[IWN_MAX_TX_RETRIES]; 745 uint32_t reserved3; 746 } __packed; 747 748 /* Structure for command IWN_CMD_SET_LED. */ 749 struct iwn_cmd_led { 750 uint32_t unit; /* multiplier (in usecs) */ 751 uint8_t which; 752 #define IWN_LED_ACTIVITY 1 753 #define IWN_LED_LINK 2 754 755 uint8_t off; 756 uint8_t on; 757 uint8_t reserved; 758 } __packed; 759 760 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 761 struct iwn5000_wimax_coex { 762 uint32_t flags; 763 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 764 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 765 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 766 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 767 768 struct iwn5000_wimax_event { 769 uint8_t request; 770 uint8_t window; 771 uint8_t reserved; 772 uint8_t flags; 773 } __packed events[16]; 774 } __packed; 775 776 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 777 struct iwn5000_calib_elem { 778 uint32_t enable; 779 uint32_t start; 780 #define IWN5000_CALIB_DC (1 << 1) 781 782 uint32_t send; 783 uint32_t apply; 784 uint32_t reserved; 785 } __packed; 786 787 struct iwn5000_calib_status { 788 struct iwn5000_calib_elem once; 789 struct iwn5000_calib_elem perd; 790 uint32_t flags; 791 } __packed; 792 793 struct iwn5000_calib_config { 794 struct iwn5000_calib_status ucode; 795 struct iwn5000_calib_status driver; 796 uint32_t reserved; 797 } __packed; 798 799 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 800 struct iwn_pmgt_cmd { 801 uint16_t flags; 802 #define IWN_PS_ALLOW_SLEEP (1 << 0) 803 #define IWN_PS_NOTIFY (1 << 1) 804 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 805 #define IWN_PS_PCI_PMGT (1 << 3) 806 #define IWN_PS_FAST_PD (1 << 4) 807 808 uint8_t keepalive; 809 uint8_t debug; 810 uint32_t rxtimeout; 811 uint32_t txtimeout; 812 uint32_t intval[5]; 813 uint32_t beacons; 814 } __packed; 815 816 /* Structures for command IWN_CMD_SCAN. */ 817 struct iwn_scan_essid { 818 uint8_t id; 819 uint8_t len; 820 uint8_t data[IEEE80211_NWID_LEN]; 821 } __packed; 822 823 struct iwn_scan_hdr { 824 uint16_t len; 825 uint8_t reserved1; 826 uint8_t nchan; 827 uint16_t quiet_time; 828 uint16_t quiet_threshold; 829 uint16_t crc_threshold; 830 uint16_t rxchain; 831 uint32_t max_out; /* (in usec) background scans */ 832 uint32_t pause_scan; /* (in usec) background scans */ 833 uint32_t flags; 834 uint32_t filter; 835 836 /* Followed by a struct iwn_cmd_data. */ 837 /* Followed by an array of 20 structs iwn_scan_essid. */ 838 /* Followed by probe request body. */ 839 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 840 } __packed; 841 842 struct iwn_scan_chan { 843 uint32_t flags; 844 #define IWN_CHAN_PASSIVE (0 << 0) 845 #define IWN_CHAN_ACTIVE (1 << 0) 846 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 847 848 uint16_t chan; 849 uint8_t rf_gain; 850 uint8_t dsp_gain; 851 uint16_t active; /* msecs */ 852 uint16_t passive; /* msecs */ 853 } __packed; 854 855 /* Maximum size of a scan command. */ 856 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 857 858 /* 859 * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 860 * sending probe req. This should be set long enough to hear probe responses 861 * from more than one AP. 862 */ 863 #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 864 #define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 865 #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 866 #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 867 868 /* 869 * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 870 * Must be set longer than active dwell time. 871 * For the most reliable scan, set > AP beacon interval (typically 100msec). 872 */ 873 #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 874 #define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 875 #define IWN_PASSIVE_DWELL_BASE (100) 876 #define IWN_CHANNEL_TUNE_TIME (5) 877 878 /* 879 * If active scanning is requested but a certain channel is 880 * marked passive, we can do active scanning if we detect 881 * transmissions. 882 * 883 * There is an issue with some firmware versions that triggers 884 * a sysassert on a "good CRC threshold" of zero (== disabled), 885 * on a radar channel even though this means that we should NOT 886 * send probes. 887 * 888 * The "good CRC threshold" is the number of frames that we 889 * need to receive during our dwell time on a channel before 890 * sending out probes -- setting this to a huge value will 891 * mean we never reach it, but at the same time work around 892 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 893 * here instead of IWN_GOOD_CRC_TH_DISABLED. 894 * 895 * This was fixed in later versions along with some other 896 * scan changes, and the threshold behaves as a flag in those 897 * versions. 898 */ 899 #define IWN_GOOD_CRC_TH_DISABLED 0 900 #define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 901 #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 902 903 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 904 #define IWN_RIDX_MAX 32 905 struct iwn4965_cmd_txpower { 906 uint8_t band; 907 uint8_t reserved1; 908 uint8_t chan; 909 uint8_t reserved2; 910 struct { 911 uint8_t rf_gain[2]; 912 uint8_t dsp_gain[2]; 913 } __packed power[IWN_RIDX_MAX + 1]; 914 } __packed; 915 916 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 917 struct iwn5000_cmd_txpower { 918 int8_t global_limit; /* in half-dBm */ 919 #define IWN5000_TXPOWER_AUTO 0x7f 920 #define IWN5000_TXPOWER_MAX_DBM 16 921 922 uint8_t flags; 923 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 924 925 int8_t srv_limit; /* in half-dBm */ 926 uint8_t reserved; 927 } __packed; 928 929 /* Structures for command IWN_CMD_BLUETOOTH. */ 930 struct iwn_bluetooth { 931 uint8_t flags; 932 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 933 #define IWN_BT_COEX_BT_PRIO (1 << 1) 934 #define IWN_BT_COEX_2_WIRE (1 << 2) 935 936 uint8_t lead_time; 937 #define IWN_BT_LEAD_TIME_DEF 30 938 939 uint8_t max_kill; 940 #define IWN_BT_MAX_KILL_DEF 5 941 942 uint8_t reserved; 943 uint32_t kill_ack; 944 uint32_t kill_cts; 945 } __packed; 946 947 struct iwn6000_btcoex_config { 948 uint8_t flags; 949 #define IWN_BT_COEX6000_CHAN_INHIBITION 1 950 #define IWN_BT_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5)) 951 #define IWN_BT_COEX6000_MODE_SHIFT 3 952 #define IWN_BT_COEX6000_MODE_DISABLED 0 953 #define IWN_BT_COEX6000_MODE_LEGACY_2W 1 954 #define IWN_BT_COEX6000_MODE_3W 2 955 #define IWN_BT_COEX6000_MODE_4W 3 956 #define IWN_BT_UCODE_DEFAULT (1<<6) 957 #define IWN_BT_SYNC_2_BT_DISABLE (1<<7) 958 959 uint8_t lead_time; 960 uint8_t max_kill; 961 uint8_t bt3_t7_timer; 962 uint32_t kill_ack; 963 uint32_t kill_cts; 964 uint8_t sample_time; 965 uint8_t bt3_t2_timer; 966 uint16_t bt4_reaction; 967 uint32_t lookup_table[12]; 968 uint16_t bt4_decision; 969 uint16_t valid; 970 uint8_t prio_boost; 971 uint8_t tx_prio_boost; 972 uint16_t rx_prio_boost; 973 } __packed; 974 975 struct iwn2000_btcoex_config { 976 uint8_t flags; /* same as in iwn6000_btcoex_config */ 977 uint8_t lead_time; 978 uint8_t max_kill; 979 uint8_t bt3_t7_timer; 980 uint32_t kill_ack; 981 uint32_t kill_cts; 982 uint8_t sample_time; 983 uint8_t bt3_t2_timer; 984 uint16_t bt4_reaction; 985 uint32_t lookup_table[12]; 986 uint16_t bt4_decision; 987 uint16_t valid; 988 uint32_t prio_boost; 989 uint8_t reserved; 990 uint8_t tx_prio_boost; 991 uint16_t rx_prio_boost; 992 } __packed; 993 994 /* Structure for command IWN_CMD_BT_COEX_PRIOTABLE */ 995 struct iwn_btcoex_priotable { 996 uint8_t calib_init1; 997 uint8_t calib_init2; 998 uint8_t calib_periodic_low1; 999 uint8_t calib_periodic_low2; 1000 uint8_t calib_periodic_high1; 1001 uint8_t calib_periodic_high2; 1002 uint8_t dtim; 1003 uint8_t scan52; 1004 uint8_t scan24; 1005 uint8_t reserved[7]; 1006 } __packed; 1007 1008 /* Structure for command IWN_CMD_BT_COEX_PROT */ 1009 struct iwn_btcoex_prot { 1010 uint8_t open; 1011 uint8_t type; 1012 uint8_t reserved[2]; 1013 } __packed; 1014 1015 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1016 struct iwn_critical_temp { 1017 uint32_t reserved; 1018 uint32_t tempM; 1019 uint32_t tempR; 1020 /* degK <-> degC conversion macros. */ 1021 #define IWN_CTOK(c) ((c) + 273) 1022 #define IWN_KTOC(k) ((k) - 273) 1023 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1024 } __packed; 1025 1026 /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1027 struct iwn_sensitivity_cmd { 1028 uint16_t which; 1029 #define IWN_SENSITIVITY_DEFAULTTBL 0 1030 #define IWN_SENSITIVITY_WORKTBL 1 1031 1032 uint16_t energy_cck; 1033 uint16_t energy_ofdm; 1034 uint16_t corr_ofdm_x1; 1035 uint16_t corr_ofdm_mrc_x1; 1036 uint16_t corr_cck_mrc_x4; 1037 uint16_t corr_ofdm_x4; 1038 uint16_t corr_ofdm_mrc_x4; 1039 uint16_t corr_barker; 1040 uint16_t corr_barker_mrc; 1041 uint16_t corr_cck_x4; 1042 uint16_t energy_ofdm_th; 1043 } __packed; 1044 1045 struct iwn_enhanced_sensitivity_cmd { 1046 uint16_t which; 1047 uint16_t energy_cck; 1048 uint16_t energy_ofdm; 1049 uint16_t corr_ofdm_x1; 1050 uint16_t corr_ofdm_mrc_x1; 1051 uint16_t corr_cck_mrc_x4; 1052 uint16_t corr_ofdm_x4; 1053 uint16_t corr_ofdm_mrc_x4; 1054 uint16_t corr_barker; 1055 uint16_t corr_barker_mrc; 1056 uint16_t corr_cck_x4; 1057 uint16_t energy_ofdm_th; 1058 /* "Enhanced" part. */ 1059 uint16_t ina_det_ofdm; 1060 uint16_t ina_det_cck; 1061 uint16_t corr_11_9_en; 1062 uint16_t ofdm_det_slope_mrc; 1063 uint16_t ofdm_det_icept_mrc; 1064 uint16_t ofdm_det_slope; 1065 uint16_t ofdm_det_icept; 1066 uint16_t cck_det_slope_mrc; 1067 uint16_t cck_det_icept_mrc; 1068 uint16_t cck_det_slope; 1069 uint16_t cck_det_icept; 1070 uint16_t reserved; 1071 } __packed; 1072 1073 /* Structures for command IWN_CMD_PHY_CALIB. */ 1074 struct iwn_phy_calib { 1075 uint8_t code; 1076 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 1077 #define IWN5000_PHY_CALIB_DC 8 1078 #define IWN5000_PHY_CALIB_LO 9 1079 #define IWN5000_PHY_CALIB_TX_IQ 11 1080 #define IWN5000_PHY_CALIB_CRYSTAL 15 1081 #define IWN5000_PHY_CALIB_BASE_BAND 16 1082 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1083 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1084 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 1085 1086 #define IWN6000_PHY_CALIB_TEMP_OFFSET 18 1087 #define IWN2000_PHY_CALIB_TEMP_OFFSET 18 1088 1089 #define IWN5000_PHY_CALIB_MAX 253 1090 1091 uint8_t group; 1092 uint8_t ngroups; 1093 uint8_t isvalid; 1094 } __packed; 1095 1096 struct iwn5000_phy_calib_crystal { 1097 uint8_t code; 1098 uint8_t group; 1099 uint8_t ngroups; 1100 uint8_t isvalid; 1101 1102 uint8_t cap_pin[2]; 1103 uint8_t reserved[2]; 1104 } __packed; 1105 1106 struct iwn6000_phy_calib_temp_offset { 1107 uint8_t code; 1108 uint8_t group; 1109 uint8_t ngroups; 1110 uint8_t isvalid; 1111 int16_t offset; 1112 #define IWN_DEFAULT_TEMP_OFFSET 2700 1113 1114 uint16_t reserved; 1115 } __packed; 1116 1117 struct iwn2000_phy_calib_temp_offset { 1118 uint8_t code; 1119 uint8_t group; 1120 uint8_t ngroups; 1121 uint8_t isvalid; 1122 int16_t offset_high; 1123 int16_t offset_low; 1124 int16_t burnt_voltage_ref; 1125 int16_t reserved; 1126 } __packed; 1127 1128 struct iwn_phy_calib_gain { 1129 uint8_t code; 1130 uint8_t group; 1131 uint8_t ngroups; 1132 uint8_t isvalid; 1133 1134 int8_t gain[3]; 1135 uint8_t reserved; 1136 } __packed; 1137 1138 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1139 struct iwn_spectrum_cmd { 1140 uint16_t len; 1141 uint8_t token; 1142 uint8_t id; 1143 uint8_t origin; 1144 uint8_t periodic; 1145 uint16_t timeout; 1146 uint32_t start; 1147 uint32_t reserved1; 1148 uint32_t flags; 1149 uint32_t filter; 1150 uint16_t nchan; 1151 uint16_t reserved2; 1152 struct { 1153 uint32_t duration; 1154 uint8_t chan; 1155 uint8_t type; 1156 #define IWN_MEASUREMENT_BASIC (1 << 0) 1157 #define IWN_MEASUREMENT_CCA (1 << 1) 1158 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1159 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1160 #define IWN_MEASUREMENT_FRAME (1 << 4) 1161 #define IWN_MEASUREMENT_IDLE (1 << 7) 1162 1163 uint16_t reserved; 1164 } __packed chan[10]; 1165 } __packed; 1166 1167 /* Structure for IWN_UC_READY notification. */ 1168 #define IWN_NATTEN_GROUPS 5 1169 struct iwn_ucode_info { 1170 uint8_t minor; 1171 uint8_t major; 1172 uint16_t reserved1; 1173 uint8_t revision[8]; 1174 uint8_t type; 1175 uint8_t subtype; 1176 #define IWN_UCODE_RUNTIME 0 1177 #define IWN_UCODE_INIT 9 1178 1179 uint16_t reserved2; 1180 uint32_t logptr; 1181 uint32_t errptr; 1182 uint32_t tstamp; 1183 uint32_t valid; 1184 1185 /* The following fields are for UCODE_INIT only. */ 1186 int32_t volt; 1187 struct { 1188 int32_t chan20MHz; 1189 int32_t chan40MHz; 1190 } __packed temp[4]; 1191 int32_t atten[IWN_NATTEN_GROUPS][2]; 1192 } __packed; 1193 1194 /* Structures for IWN_TX_DONE notification. */ 1195 1196 /* Tx status for aggregated frames (A-MPDU). */ 1197 struct iwn_txagg_status { 1198 uint16_t status; 1199 #define IWN_AGG_TX_STATE_TRANSMITTED 0x0000 1200 #define IWN_AGG_TX_STATE_UNDERRUN 0x0001 1201 #define IWN_AGG_TX_STATE_BT_PRIO 0x0002 1202 #define IWN_AGG_TX_STATE_FEW_BYTES 0x0004 1203 #define IWN_AGG_TX_STATE_ABORT 0x0008 1204 #define IWN_AGG_TX_STATE_LAST_SENT_TTL 0x0010 1205 #define IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020 1206 #define IWN_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040 1207 #define IWN_AGG_TX_STATE_SCD_QUERY 0x0080 1208 #define IWN_AGG_TX_STATE_TEST_BAD_CRC32 0x0100 1209 #define IWN_AGG_TX_STATE_RESPONSE_MASK 0x01ff 1210 #define IWN_AGG_TX_STATE_DUMP_TX 0x0200 1211 #define IWN_AGG_TX_STATE_DELAY_TX 0x0400 1212 #define IWN_AGG_TX_STATUS_MASK 0x0fff 1213 /* Number of TX attempts for first frame in aggregation: */ 1214 #define IWN_AGG_TX_TRY 0xf000 1215 #define IWN_AGG_TX_TRY_SHIFT 12 1216 1217 /* Copied from Tx command we have sent to the firmware. */ 1218 uint8_t idx; 1219 uint8_t qid; 1220 } __packed; 1221 1222 /* For aggregation queues, index must be aligned to frame sequence number. */ 1223 #define IWN_AGG_SSN_TO_TXQ_IDX(x) ((x) & (IWN_TX_RING_COUNT - 1)) 1224 1225 /* Tx status codes for non-aggregated frames. */ 1226 #define IWN_TX_STATUS_SUCCESS 0x01 1227 #define IWN_TX_STATUS_DIRECT_DONE 0x02 1228 #define IWN_TX_STATUS_POSTPONE_DELAY 0x40 1229 #define IWN_TX_STATUS_POSTPONE_FEW_BYTES 0x41 1230 #define IWN_TX_STATUS_POSTPONE_BT_PRIO 0x42 1231 #define IWN_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 1232 #define IWN_TX_STATUS_POSTPONE_CALC_TTAK 0x44 1233 #define IWN_TX_STATUS_FAIL_CROSSED_RETRY 0x81 1234 #define IWN_TX_STATUS_FAIL_SHORT_LIMIT 0x82 1235 #define IWN_TX_STATUS_FAIL_LONG_LIMIT 0x83 1236 #define IWN_TX_STATUS_FAIL_FIFO_UNDERRUN 0x84 1237 #define IWN_TX_STATUS_FAIL_DRAIN_FLOW 0x85 1238 #define IWN_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 1239 #define IWN_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 1240 #define IWN_TX_STATUS_FAIL_DEST_PS 0x88 1241 #define IWN_TX_STATUS_FAIL_HOST_ABORTED 0x89 1242 #define IWN_TX_STATUS_FAIL_BT_RETRY 0x8a 1243 #define IWN_TX_STATUS_FAIL_STA_INVALID 0x8b 1244 #define IWN_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 1245 #define IWN_TX_STATUS_FAIL_TID_DISABLE 0x8d 1246 #define IWN_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 1247 #define IWN_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 1248 #define IWN_TX_STATUS_FAIL_PASSIVE_NO_RX 0x90 1249 #define IWN_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 1250 1251 struct iwn4965_tx_stat { 1252 uint8_t nframes; 1253 uint8_t btkillcnt; 1254 uint8_t rtsfailcnt; 1255 uint8_t ackfailcnt; 1256 uint8_t rate; 1257 uint8_t rflags; 1258 uint16_t xrflags; 1259 uint16_t duration; 1260 uint16_t reserved; 1261 uint32_t power[2]; 1262 union { 1263 uint32_t status; /* if nframes == 1 */ 1264 struct iwn_txagg_status agg_status[0]; /* nframes elements */ 1265 } stat; 1266 /* Followed by current scheduler SSN (uint32_t). */ 1267 } __packed; 1268 1269 struct iwn5000_tx_stat { 1270 uint8_t nframes; 1271 uint8_t btkillcnt; 1272 uint8_t rtsfailcnt; 1273 uint8_t ackfailcnt; 1274 uint8_t rate; 1275 uint8_t rflags; 1276 uint16_t xrflags; 1277 uint16_t duration; 1278 uint16_t reserved; 1279 uint32_t power[2]; 1280 uint32_t info; 1281 uint16_t seq; 1282 uint16_t len; 1283 uint8_t tlc; 1284 uint8_t ratid; 1285 #define IWN_TX_RES_TID_SHIFT 0 1286 #define IWN_TX_RES_TID 0x0f 1287 #define IWN_TX_RES_RA_SHIFT 4 1288 #define IWN_TX_RES_RA 0xf0 1289 uint8_t fc[2]; 1290 union { 1291 uint32_t status; /* if nframes == 1 */ 1292 struct iwn_txagg_status agg_status[0]; /* nframes elements */ 1293 } stat; 1294 /* Followed by current scheduler SSN (uint32_t). */ 1295 } __packed; 1296 1297 /* Structure for IWN_BEACON_MISSED notification. */ 1298 struct iwn_beacon_missed { 1299 uint32_t consecutive; 1300 uint32_t total; 1301 uint32_t expected; 1302 uint32_t received; 1303 } __packed; 1304 1305 /* Structure for IWN_MPDU_RX_DONE notification. */ 1306 struct iwn_rx_mpdu { 1307 uint16_t len; 1308 uint16_t reserved; 1309 } __packed; 1310 1311 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1312 struct iwn4965_rx_phystat { 1313 uint16_t antenna; 1314 uint16_t agc; 1315 uint8_t rssi[6]; 1316 } __packed; 1317 1318 struct iwn5000_rx_phystat { 1319 uint32_t reserved1; 1320 uint32_t agc; 1321 uint16_t rssi[3]; 1322 } __packed; 1323 1324 struct iwn_rx_stat { 1325 uint8_t phy_len; 1326 uint8_t cfg_phy_len; 1327 #define IWN_STAT_MAXLEN 20 1328 1329 uint8_t id; 1330 uint8_t reserved1; 1331 uint64_t tstamp; 1332 uint32_t beacon; 1333 uint16_t flags; 1334 #define IWN_STAT_FLAG_24GHZ (1 << 0) 1335 #define IWN_STAT_FLAG_MOD_CCK (1 << 1) 1336 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1337 #define IWN_STAT_FLAG_NARROW_BAND (1 << 3) 1338 #define IWN_STAT_FLAG_ANT(x) ((x) << 4) /* 3 bits */ 1339 #define IWN_STAT_FLAG_AGG (1 << 7) 1340 1341 uint16_t chan; 1342 uint8_t phybuf[32]; 1343 uint8_t rate; 1344 uint8_t rflags; 1345 uint16_t xrflags; 1346 uint16_t len; 1347 uint16_t reserve3; 1348 } __packed; 1349 1350 #define IWN_RSSI_TO_DBM 44 1351 1352 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1353 struct iwn_compressed_ba { 1354 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1355 uint16_t reserved; 1356 uint8_t id; 1357 uint8_t tid; 1358 uint16_t seq; 1359 uint64_t bitmap; 1360 uint16_t qid; 1361 uint16_t ssn; 1362 uint8_t nframes_sent; 1363 uint8_t nframes_acked; 1364 uint16_t reserved2; 1365 } __packed; 1366 1367 /* Structure for IWN_START_SCAN notification. */ 1368 struct iwn_start_scan { 1369 uint64_t tstamp; 1370 uint32_t tbeacon; 1371 uint8_t chan; 1372 uint8_t band; 1373 uint16_t reserved; 1374 uint32_t status; 1375 } __packed; 1376 1377 /* Structure for IWN_STOP_SCAN notification. */ 1378 struct iwn_stop_scan { 1379 uint8_t nchan; 1380 uint8_t status; 1381 uint8_t reserved; 1382 uint8_t chan; 1383 uint64_t tsf; 1384 } __packed; 1385 1386 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1387 struct iwn_spectrum_notif { 1388 uint8_t id; 1389 uint8_t token; 1390 uint8_t idx; 1391 uint8_t state; 1392 #define IWN_MEASUREMENT_START 0 1393 #define IWN_MEASUREMENT_STOP 1 1394 1395 uint32_t start; 1396 uint8_t band; 1397 uint8_t chan; 1398 uint8_t type; 1399 uint8_t reserved1; 1400 uint32_t cca_ofdm; 1401 uint32_t cca_cck; 1402 uint32_t cca_time; 1403 uint8_t basic; 1404 uint8_t reserved2[3]; 1405 uint32_t ofdm[8]; 1406 uint32_t cck[8]; 1407 uint32_t stop; 1408 uint32_t status; 1409 #define IWN_MEASUREMENT_OK 0 1410 #define IWN_MEASUREMENT_CONCURRENT 1 1411 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1412 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1413 #define IWN_MEASUREMENT_STOPPED 6 1414 #define IWN_MEASUREMENT_TIMEOUT 7 1415 #define IWN_MEASUREMENT_FAILED 8 1416 } __packed; 1417 1418 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1419 struct iwn_rx_phy_stats { 1420 uint32_t ina; 1421 uint32_t fina; 1422 uint32_t bad_plcp; 1423 uint32_t bad_crc32; 1424 uint32_t overrun; 1425 uint32_t eoverrun; 1426 uint32_t good_crc32; 1427 uint32_t fa; 1428 uint32_t bad_fina_sync; 1429 uint32_t sfd_timeout; 1430 uint32_t fina_timeout; 1431 uint32_t no_rts_ack; 1432 uint32_t rxe_limit; 1433 uint32_t ack; 1434 uint32_t cts; 1435 uint32_t ba_resp; 1436 uint32_t dsp_kill; 1437 uint32_t bad_mh; 1438 uint32_t rssi_sum; 1439 uint32_t reserved; 1440 } __packed; 1441 1442 struct iwn_rx_general_stats { 1443 uint32_t bad_cts; 1444 uint32_t bad_ack; 1445 uint32_t not_bss; 1446 uint32_t filtered; 1447 uint32_t bad_chan; 1448 uint32_t beacons; 1449 uint32_t missed_beacons; 1450 uint32_t adc_saturated; /* time in 0.8us */ 1451 uint32_t ina_searched; /* time in 0.8us */ 1452 uint32_t noise[3]; 1453 uint32_t flags; 1454 uint32_t load; 1455 uint32_t fa; 1456 uint32_t rssi[3]; 1457 uint32_t energy[3]; 1458 } __packed; 1459 1460 struct iwn_rx_ht_phy_stats { 1461 uint32_t bad_plcp; 1462 uint32_t overrun; 1463 uint32_t eoverrun; 1464 uint32_t good_crc32; 1465 uint32_t bad_crc32; 1466 uint32_t bad_mh; 1467 uint32_t good_ampdu_crc32; 1468 uint32_t ampdu; 1469 uint32_t fragment; 1470 uint32_t reserved; 1471 } __packed; 1472 1473 struct iwn_rx_stats { 1474 struct iwn_rx_phy_stats ofdm; 1475 struct iwn_rx_phy_stats cck; 1476 struct iwn_rx_general_stats general; 1477 struct iwn_rx_ht_phy_stats ht; 1478 } __packed; 1479 1480 struct iwn_tx_stats { 1481 uint32_t preamble; 1482 uint32_t rx_detected; 1483 uint32_t bt_defer; 1484 uint32_t bt_kill; 1485 uint32_t short_len; 1486 uint32_t cts_timeout; 1487 uint32_t ack_timeout; 1488 uint32_t exp_ack; 1489 uint32_t ack; 1490 uint32_t msdu; 1491 uint32_t busrt_err1; 1492 uint32_t burst_err2; 1493 uint32_t cts_collision; 1494 uint32_t ack_collision; 1495 uint32_t ba_timeout; 1496 uint32_t ba_resched; 1497 uint32_t query_ampdu; 1498 uint32_t query; 1499 uint32_t query_ampdu_frag; 1500 uint32_t query_mismatch; 1501 uint32_t not_ready; 1502 uint32_t underrun; 1503 uint32_t bt_ht_kill; 1504 uint32_t rx_ba_resp; 1505 uint32_t reserved[2]; 1506 } __packed; 1507 1508 struct iwn_general_stats { 1509 uint32_t temp; 1510 uint32_t temp_m; 1511 uint32_t burst_check; 1512 uint32_t burst; 1513 uint32_t reserved1[4]; 1514 uint32_t sleep; 1515 uint32_t slot_out; 1516 uint32_t slot_idle; 1517 uint32_t ttl_tstamp; 1518 uint32_t tx_ant_a; 1519 uint32_t tx_ant_b; 1520 uint32_t exec; 1521 uint32_t probe; 1522 uint32_t reserved2[2]; 1523 uint32_t rx_enabled; 1524 uint32_t reserved3[3]; 1525 } __packed; 1526 1527 struct iwn_stats { 1528 uint32_t flags; 1529 struct iwn_rx_stats rx; 1530 struct iwn_tx_stats tx; 1531 struct iwn_general_stats general; 1532 } __packed; 1533 1534 1535 /* Firmware error dump. */ 1536 struct iwn_fw_dump { 1537 uint32_t valid; 1538 uint32_t id; 1539 uint32_t pc; 1540 uint32_t branch_link[2]; 1541 uint32_t interrupt_link[2]; 1542 uint32_t error_data[2]; 1543 uint32_t src_line; 1544 uint32_t tsf; 1545 uint32_t time[2]; 1546 } __packed; 1547 1548 /* TLV firmware header. */ 1549 struct iwn_fw_tlv_hdr { 1550 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1551 uint32_t signature; 1552 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1553 1554 uint8_t descr[64]; 1555 uint32_t rev; 1556 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1557 1558 uint32_t build; 1559 uint64_t altmask; 1560 } __packed; 1561 1562 /* TLV header. */ 1563 struct iwn_fw_tlv { 1564 uint16_t type; 1565 #define IWN_FW_TLV_MAIN_TEXT 1 1566 #define IWN_FW_TLV_MAIN_DATA 2 1567 #define IWN_FW_TLV_INIT_TEXT 3 1568 #define IWN_FW_TLV_INIT_DATA 4 1569 #define IWN_FW_TLV_BOOT_TEXT 5 1570 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1571 #define IWN_FW_TLV_ENH_SENS 14 1572 #define IWN_FW_TLV_PHY_CALIB 15 1573 #define IWN_FW_TLV_FLAGS 18 1574 1575 uint16_t alt; 1576 uint32_t len; 1577 } __packed; 1578 1579 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1580 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1581 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1582 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1583 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1584 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1585 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1586 1587 /* 1588 * Microcode flags TLV (18.) 1589 */ 1590 1591 /** 1592 * enum iwn_ucode_tlv_flag - ucode API flags 1593 * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1594 * was a separate TLV but moved here to save space. 1595 * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1596 * treats good CRC threshold as a boolean 1597 * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1598 * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1599 * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1600 * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1601 * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1602 * offload profile config command. 1603 * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1604 * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1605 * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1606 * (rather than two) IPv6 addresses 1607 * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1608 * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1609 * from the probe request template. 1610 * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1611 * connection when going back to D0 1612 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1613 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1614 * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1615 * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1616 * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1617 * containing CAM (Continuous Active Mode) indication. 1618 */ 1619 enum iwn_ucode_tlv_flag { 1620 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1621 IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1622 IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1623 IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1624 IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1625 IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1626 IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1627 IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1628 IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1629 IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1630 IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1631 IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1632 IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1633 IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1634 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1635 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1636 IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1637 IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1638 IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1639 }; 1640 1641 /* 1642 * Offsets into EEPROM. 1643 */ 1644 #define IWN_EEPROM_MAC 0x015 1645 #define IWN_EEPROM_SKU_CAP 0x045 1646 #define IWN_EEPROM_RFCFG 0x048 1647 #define IWN4965_EEPROM_DOMAIN 0x060 1648 #define IWN4965_EEPROM_BAND1 0x063 1649 #define IWN5000_EEPROM_REG 0x066 1650 #define IWN5000_EEPROM_CAL 0x067 1651 #define IWN4965_EEPROM_BAND2 0x072 1652 #define IWN4965_EEPROM_BAND3 0x080 1653 #define IWN4965_EEPROM_BAND4 0x08d 1654 #define IWN4965_EEPROM_BAND5 0x099 1655 #define IWN4965_EEPROM_BAND6 0x0a0 1656 #define IWN4965_EEPROM_BAND7 0x0a8 1657 #define IWN4965_EEPROM_MAXPOW 0x0e8 1658 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1659 #define IWN4965_EEPROM_BANDS 0x0ea 1660 /* Indirect offsets. */ 1661 #define IWN5000_EEPROM_DOMAIN 0x001 1662 #define IWN5000_EEPROM_BAND1 0x004 1663 #define IWN5000_EEPROM_BAND2 0x013 1664 #define IWN5000_EEPROM_BAND3 0x021 1665 #define IWN5000_EEPROM_BAND4 0x02e 1666 #define IWN5000_EEPROM_BAND5 0x03a 1667 #define IWN5000_EEPROM_BAND6 0x041 1668 #define IWN5000_EEPROM_BAND7 0x049 1669 #define IWN6000_EEPROM_ENHINFO 0x054 1670 #define IWN5000_EEPROM_CRYSTAL 0x128 1671 #define IWN5000_EEPROM_TEMP 0x12a 1672 #define IWN5000_EEPROM_VOLT 0x12b 1673 #define IWN2000_EEPROM_RAWTEMP 0x12b 1674 1675 /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1676 #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1677 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1678 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1679 1680 /* Possible flags for IWN_EEPROM_RFCFG. */ 1681 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1682 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1683 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1684 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1685 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1686 1687 struct iwn_eeprom_chan { 1688 uint8_t flags; 1689 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1690 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1691 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1692 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1693 1694 int8_t maxpwr; 1695 } __packed; 1696 1697 struct iwn_eeprom_enhinfo { 1698 uint16_t chan; 1699 int8_t chain[3]; /* max power in half-dBm */ 1700 uint8_t reserved; 1701 int8_t mimo2; /* max power in half-dBm */ 1702 int8_t mimo3; /* max power in half-dBm */ 1703 } __packed; 1704 1705 struct iwn5000_eeprom_calib_hdr { 1706 uint8_t version; 1707 uint8_t pa_type; 1708 uint16_t volt; 1709 } __packed; 1710 1711 #define IWN_NSAMPLES 3 1712 struct iwn4965_eeprom_chan_samples { 1713 uint8_t num; 1714 struct { 1715 uint8_t temp; 1716 uint8_t gain; 1717 uint8_t power; 1718 int8_t pa_det; 1719 } samples[2][IWN_NSAMPLES]; 1720 } __packed; 1721 1722 #define IWN_NBANDS 8 1723 struct iwn4965_eeprom_band { 1724 uint8_t lo; /* low channel number */ 1725 uint8_t hi; /* high channel number */ 1726 struct iwn4965_eeprom_chan_samples chans[2]; 1727 } __packed; 1728 1729 /* 1730 * Offsets of channels descriptions in EEPROM. 1731 */ 1732 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1733 IWN4965_EEPROM_BAND1, 1734 IWN4965_EEPROM_BAND2, 1735 IWN4965_EEPROM_BAND3, 1736 IWN4965_EEPROM_BAND4, 1737 IWN4965_EEPROM_BAND5, 1738 IWN4965_EEPROM_BAND6, 1739 IWN4965_EEPROM_BAND7 1740 }; 1741 1742 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1743 IWN5000_EEPROM_BAND1, 1744 IWN5000_EEPROM_BAND2, 1745 IWN5000_EEPROM_BAND3, 1746 IWN5000_EEPROM_BAND4, 1747 IWN5000_EEPROM_BAND5, 1748 IWN5000_EEPROM_BAND6, 1749 IWN5000_EEPROM_BAND7 1750 }; 1751 1752 #define IWN_CHAN_BANDS_COUNT 7 1753 #define IWN_MAX_CHAN_PER_BAND 14 1754 static const struct iwn_chan_band { 1755 uint8_t nchan; 1756 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1757 } iwn_bands[] = { 1758 /* 20MHz channels, 2GHz band. */ 1759 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1760 /* 20MHz channels, 5GHz band. */ 1761 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1762 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1763 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1764 { 6, { 145, 149, 153, 157, 161, 165 } }, 1765 /* 40MHz channels (primary channels), 2GHz band. */ 1766 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1767 /* 40MHz channels (primary channels), 5GHz band. */ 1768 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1769 }; 1770 1771 #define IWN1000_OTP_NBLOCKS 3 1772 #define IWN6000_OTP_NBLOCKS 4 1773 #define IWN6050_OTP_NBLOCKS 7 1774 1775 /* HW rate indices. */ 1776 #define IWN_RIDX_CCK1 0 1777 #define IWN_RIDX_OFDM6 4 1778 1779 #define IWN_PLCP_INVALID 0xff 1780 1781 static const struct iwn_rate { 1782 uint8_t rate; 1783 uint8_t plcp; 1784 uint8_t flags; 1785 uint8_t ht_plcp; 1786 uint8_t ht_flags; 1787 } iwn_rates[IWN_RIDX_MAX + 1] = { 1788 /* Legacy */ /* HT */ 1789 { 2, 10, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1790 { 4, 20, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1791 { 11, 55, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1792 { 22, 110, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, 1793 { 12, 0xd, 0, 0, IWN_RFLAG_MCS }, 1794 { 18, 0xf, 0, IWN_PLCP_INVALID, 0 }, 1795 { 24, 0x5, 0, 1, IWN_RFLAG_MCS }, 1796 { 36, 0x7, 0, 2, IWN_RFLAG_MCS, }, 1797 { 48, 0x9, 0, 3, IWN_RFLAG_MCS, }, 1798 { 72, 0xb, 0, 4, IWN_RFLAG_MCS, }, 1799 { 96, 0x1, 0, 5, IWN_RFLAG_MCS, }, 1800 { 108, 0x3, 0, 6, IWN_RFLAG_MCS, }, 1801 { 128, IWN_PLCP_INVALID, 0, 7, IWN_RFLAG_MCS, } 1802 }; 1803 1804 /* Convert an MCS index into an iwn_rates[] index. */ 1805 const int iwn_mcs2ridx[] = { 4, 6, 7, 8, 9, 10, 11, 12 }; 1806 1807 #define IWN4965_MAX_PWR_INDEX 107 1808 1809 /* 1810 * RF Tx gain values from highest to lowest power (values obtained from 1811 * the reference driver.) 1812 */ 1813 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1814 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1815 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1816 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1817 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1818 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1819 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1820 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1821 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1822 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1823 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1824 }; 1825 1826 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1827 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1828 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1829 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1830 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1831 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1832 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1833 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1834 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1835 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1836 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1837 }; 1838 1839 /* 1840 * DSP pre-DAC gain values from highest to lowest power (values obtained 1841 * from the reference driver.) 1842 */ 1843 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1844 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1845 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1846 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1847 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1848 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1849 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1850 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1851 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1852 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1853 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1854 }; 1855 1856 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1857 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1858 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1859 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1860 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1861 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1862 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1863 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1864 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1865 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1866 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1867 }; 1868 1869 /* 1870 * Power saving settings (values obtained from the reference driver.) 1871 */ 1872 #define IWN_NDTIMRANGES 3 1873 #define IWN_NPOWERLEVELS 6 1874 static const struct iwn_pmgt { 1875 uint32_t rxtimeout; 1876 uint32_t txtimeout; 1877 uint32_t intval[5]; 1878 int skip_dtim; 1879 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1880 /* DTIM <= 2 */ 1881 { 1882 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1883 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1884 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1885 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1886 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1887 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1888 }, 1889 /* 3 <= DTIM <= 10 */ 1890 { 1891 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1892 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1893 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1894 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1895 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1896 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1897 }, 1898 /* DTIM >= 11 */ 1899 { 1900 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1901 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1902 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1903 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1904 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1905 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1906 } 1907 }; 1908 1909 struct iwn_sensitivity_limits { 1910 uint32_t min_ofdm_x1; 1911 uint32_t max_ofdm_x1; 1912 uint32_t min_ofdm_mrc_x1; 1913 uint32_t max_ofdm_mrc_x1; 1914 uint32_t min_ofdm_x4; 1915 uint32_t max_ofdm_x4; 1916 uint32_t min_ofdm_mrc_x4; 1917 uint32_t max_ofdm_mrc_x4; 1918 uint32_t min_cck_x4; 1919 uint32_t max_cck_x4; 1920 uint32_t min_cck_mrc_x4; 1921 uint32_t max_cck_mrc_x4; 1922 uint32_t min_energy_cck; 1923 uint32_t energy_cck; 1924 uint32_t energy_ofdm; 1925 }; 1926 1927 /* 1928 * RX sensitivity limits (values obtained from the reference driver.) 1929 */ 1930 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1931 105, 140, 1932 220, 270, 1933 85, 120, 1934 170, 210, 1935 125, 200, 1936 200, 400, 1937 97, 1938 100, 1939 100 1940 }; 1941 1942 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1943 120, 120, /* min = max for performance bug in DSP. */ 1944 240, 240, /* min = max for performance bug in DSP. */ 1945 90, 120, 1946 170, 210, 1947 125, 200, 1948 170, 400, 1949 95, 1950 95, 1951 95 1952 }; 1953 1954 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1955 105, 105, /* min = max for performance bug in DSP. */ 1956 220, 220, /* min = max for performance bug in DSP. */ 1957 90, 120, 1958 170, 210, 1959 125, 200, 1960 170, 400, 1961 95, 1962 95, 1963 95 1964 }; 1965 1966 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1967 120, 155, 1968 240, 290, 1969 90, 120, 1970 170, 210, 1971 125, 200, 1972 170, 400, 1973 95, 1974 95, 1975 95 1976 }; 1977 1978 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1979 105, 110, 1980 192, 232, 1981 80, 145, 1982 128, 232, 1983 125, 175, 1984 160, 310, 1985 97, 1986 97, 1987 100 1988 }; 1989 1990 static const struct iwn_sensitivity_limits iwn2000_sensitivity_limits = { 1991 105, 110, 1992 192, 232, 1993 80, 145, 1994 128, 232, 1995 125, 175, 1996 160, 310, 1997 97, 1998 97, 1999 100 2000 }; 2001 2002 /* Map TID to TX scheduler's FIFO. */ 2003 #define IWN_NUM_AMPDU_TID 8 2004 #define IWN_NONQOS_TID IWN_NUM_AMPDU_TID 2005 #define IWN_TX_FIFO_BK 0 2006 #define IWN_TX_FIFO_BE 1 2007 #define IWN_TX_FIFO_VI 2 2008 #define IWN_TX_FIFO_VO 3 2009 static const uint8_t iwn_tid2fifo[IWN_NUM_AMPDU_TID] = { 2010 IWN_TX_FIFO_VO, IWN_TX_FIFO_VI, IWN_TX_FIFO_BE, IWN_TX_FIFO_BK, 2011 IWN_TX_FIFO_VO, IWN_TX_FIFO_VI, IWN_TX_FIFO_BE, IWN_TX_FIFO_BK 2012 }; 2013 2014 /* WiFi/WiMAX coexist event priority table for 6050. */ 2015 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 2016 { 0x04, 0x03, 0x00, 0x00 }, 2017 { 0x04, 0x03, 0x00, 0x03 }, 2018 { 0x04, 0x03, 0x00, 0x03 }, 2019 { 0x04, 0x03, 0x00, 0x03 }, 2020 { 0x04, 0x03, 0x00, 0x00 }, 2021 { 0x04, 0x03, 0x00, 0x07 }, 2022 { 0x04, 0x03, 0x00, 0x00 }, 2023 { 0x04, 0x03, 0x00, 0x03 }, 2024 { 0x04, 0x03, 0x00, 0x03 }, 2025 { 0x04, 0x03, 0x00, 0x00 }, 2026 { 0x06, 0x03, 0x00, 0x07 }, 2027 { 0x04, 0x03, 0x00, 0x00 }, 2028 { 0x06, 0x06, 0x00, 0x03 }, 2029 { 0x04, 0x03, 0x00, 0x07 }, 2030 { 0x04, 0x03, 0x00, 0x00 }, 2031 { 0x04, 0x03, 0x00, 0x00 } 2032 }; 2033 2034 /* Firmware errors. */ 2035 static const char * const iwn_fw_errmsg[] = { 2036 "OK", 2037 "FAIL", 2038 "BAD_PARAM", 2039 "BAD_CHECKSUM", 2040 "NMI_INTERRUPT_WDG", 2041 "SYSASSERT", 2042 "FATAL_ERROR", 2043 "BAD_COMMAND", 2044 "HW_ERROR_TUNE_LOCK", 2045 "HW_ERROR_TEMPERATURE", 2046 "ILLEGAL_CHAN_FREQ", 2047 "VCC_NOT_STABLE", 2048 "FH_ERROR", 2049 "NMI_INTERRUPT_HOST", 2050 "NMI_INTERRUPT_ACTION_PT", 2051 "NMI_INTERRUPT_UNKNOWN", 2052 "UCODE_VERSION_MISMATCH", 2053 "HW_ERROR_ABS_LOCK", 2054 "HW_ERROR_CAL_LOCK_FAIL", 2055 "NMI_INTERRUPT_INST_ACTION_PT", 2056 "NMI_INTERRUPT_DATA_ACTION_PT", 2057 "NMI_TRM_HW_ER", 2058 "NMI_INTERRUPT_TRM", 2059 "NMI_INTERRUPT_BREAKPOINT", 2060 "DEBUG_0", 2061 "DEBUG_1", 2062 "DEBUG_2", 2063 "DEBUG_3", 2064 "ADVANCED_SYSASSERT" 2065 }; 2066 2067 /* Find least significant bit that is set. */ 2068 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2069 2070 #define IWN_READ(sc, reg) \ 2071 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2072 2073 #define IWN_WRITE(sc, reg, val) \ 2074 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2075 2076 #define IWN_WRITE_1(sc, reg, val) \ 2077 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2078 2079 #define IWN_SETBITS(sc, reg, mask) \ 2080 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2081 2082 #define IWN_CLRBITS(sc, reg, mask) \ 2083 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2084 2085 #define IWN_BARRIER_WRITE(sc) \ 2086 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2087 BUS_SPACE_BARRIER_WRITE) 2088 2089 #define IWN_BARRIER_READ_WRITE(sc) \ 2090 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2091 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2092