1 /* $OpenBSD: if_ix.h,v 1.41 2020/06/07 23:52:05 dlg Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2012, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe.h,v 1.38 2012/12/20 22:29:29 svnexp Exp $*/ 36 37 #ifndef _IX_H_ 38 #define _IX_H_ 39 40 #include <dev/pci/ixgbe.h> 41 42 /* Tunables */ 43 44 /* 45 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 46 * number of transmit descriptors allocated by the driver. Increasing this 47 * value allows the driver to queue more transmits. Each descriptor is 16 48 * bytes. Performance tests have show the 2K value to be optimal for top 49 * performance. 50 */ 51 #define DEFAULT_TXD 256 52 #define PERFORM_TXD 2048 53 #define MAX_TXD 4096 54 #define MIN_TXD 64 55 56 /* 57 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 58 * number of receive descriptors allocated for each RX queue. Increasing this 59 * value allows the driver to buffer more incoming packets. Each descriptor 60 * is 16 bytes. A receive buffer is also allocated for each descriptor. 61 * 62 * Note: with 8 rings and a dual port card, it is possible to bump up 63 * against the system mbuf pool limit, you can tune nmbclusters 64 * to adjust for this. 65 */ 66 #define DEFAULT_RXD 256 67 #define PERFORM_RXD 2048 68 #define MAX_RXD 4096 69 #define MIN_RXD 64 70 71 /* Alignment for rings */ 72 #define DBA_ALIGN 128 73 74 /* 75 * This parameter controls the duration of transmit watchdog timer. 76 */ 77 #define IXGBE_TX_TIMEOUT 5 /* set to 5 seconds */ 78 79 /* 80 * Thise parameter controls the minimum number of available transmit 81 * descriptors needed before we attempt transmission of a packet. 82 */ 83 #define IXGBE_TX_OP_THRESHOLD (sc->num_segs + 2) 84 85 #define IXGBE_MAX_FRAME_SIZE 9216 86 87 /* Flow control constants */ 88 #define IXGBE_FC_PAUSE 0xFFFF 89 #define IXGBE_FC_HI 0x20000 90 #define IXGBE_FC_LO 0x10000 91 92 /* Defines for printing debug information */ 93 #define DEBUG_INIT 0 94 #define DEBUG_IOCTL 0 95 #define DEBUG_HW 0 96 97 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 98 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 99 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 100 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 101 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 102 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 103 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 104 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 105 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 106 107 #define MAX_NUM_MULTICAST_ADDRESSES 128 108 #define IXGBE_82598_SCATTER 100 109 #define IXGBE_82599_SCATTER 32 110 #define MSIX_82598_BAR 3 111 #define MSIX_82599_BAR 4 112 #define IXGBE_TSO_SIZE 262140 113 #define IXGBE_TX_BUFFER_SIZE ((uint32_t) 1514) 114 #define IXGBE_RX_HDR 128 115 #define IXGBE_VFTA_SIZE 128 116 #define IXGBE_BR_SIZE 4096 117 #define IXGBE_QUEUE_MIN_FREE 32 118 119 /* 120 * Interrupt Moderation parameters 121 */ 122 #define IXGBE_INTS_PER_SEC 8000 123 #define IXGBE_LINK_ITR 1000 124 125 struct ixgbe_tx_buf { 126 uint32_t eop_index; 127 struct mbuf *m_head; 128 bus_dmamap_t map; 129 }; 130 131 struct ixgbe_rx_buf { 132 struct mbuf *buf; 133 struct mbuf *fmp; 134 bus_dmamap_t map; 135 }; 136 137 /* 138 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 139 */ 140 struct ixgbe_dma_alloc { 141 caddr_t dma_vaddr; 142 bus_dma_tag_t dma_tag; 143 bus_dmamap_t dma_map; 144 bus_dma_segment_t dma_seg; 145 bus_size_t dma_size; 146 int dma_nseg; 147 }; 148 149 /* 150 * Driver queue struct: this is the interrupt container 151 * for the associated tx and rx ring. 152 */ 153 struct ix_queue { 154 struct ix_softc *sc; 155 uint32_t msix; /* This queue's MSIX vector */ 156 uint32_t eims; /* This queue's EIMS bit */ 157 uint32_t eitr_setting; 158 char name[8]; 159 pci_intr_handle_t ih; 160 void *tag; 161 struct tx_ring *txr; 162 struct rx_ring *rxr; 163 }; 164 165 /* 166 * The transmit ring, one per tx queue 167 */ 168 struct tx_ring { 169 struct ix_softc *sc; 170 struct ifqueue *ifq; 171 uint32_t me; 172 uint32_t watchdog_timer; 173 union ixgbe_adv_tx_desc *tx_base; 174 struct ixgbe_tx_buf *tx_buffers; 175 struct ixgbe_dma_alloc txdma; 176 uint32_t next_avail_desc; 177 uint32_t next_to_clean; 178 enum { 179 IXGBE_QUEUE_IDLE, 180 IXGBE_QUEUE_WORKING, 181 IXGBE_QUEUE_HUNG, 182 } queue_status; 183 uint32_t txd_cmd; 184 bus_dma_tag_t txtag; 185 uint32_t bytes; /* Used for AIM calc */ 186 uint32_t packets; 187 /* Soft Stats */ 188 uint64_t tx_packets; 189 }; 190 191 192 /* 193 * The Receive ring, one per rx queue 194 */ 195 struct rx_ring { 196 struct ix_softc *sc; 197 struct ifiqueue *ifiq; 198 uint32_t me; 199 union ixgbe_adv_rx_desc *rx_base; 200 struct ixgbe_dma_alloc rxdma; 201 #if 0 202 struct lro_ctrl lro; 203 #endif 204 bool lro_enabled; 205 bool hw_rsc; 206 bool discard; 207 uint next_to_refresh; 208 uint next_to_check; 209 uint last_desc_filled; 210 struct timeout rx_refill; 211 struct if_rxring rx_ring; 212 struct ixgbe_rx_buf *rx_buffers; 213 214 uint32_t bytes; /* Used for AIM calc */ 215 uint32_t packets; 216 217 /* Soft stats */ 218 uint64_t rx_irq; 219 uint64_t rx_packets; 220 uint64_t rx_bytes; 221 uint64_t rx_discarded; 222 uint64_t rsc_num; 223 }; 224 225 /* Our adapter structure */ 226 struct ix_softc { 227 struct device dev; 228 struct arpcom arpcom; 229 230 struct ixgbe_hw hw; 231 struct ixgbe_osdep osdep; 232 233 void *tag; 234 235 struct ifmedia media; 236 struct timeout timer; 237 int msix; 238 int if_flags; 239 240 uint16_t num_vlans; 241 uint16_t num_queues; 242 243 /* 244 * Shadow VFTA table, this is needed because 245 * the real vlan filter table gets cleared during 246 * a soft reset and the driver needs to be able 247 * to repopulate it. 248 */ 249 uint32_t shadow_vfta[IXGBE_VFTA_SIZE]; 250 251 /* Info about the interface */ 252 uint64_t phy_layer; 253 uint32_t fc; /* local flow ctrl setting */ 254 uint16_t max_frame_size; 255 uint16_t num_segs; 256 uint32_t link_speed; 257 bool link_up; 258 uint32_t linkvec; 259 struct rwlock sfflock; 260 261 /* Mbuf cluster size */ 262 uint32_t rx_mbuf_sz; 263 264 /* 265 * Queues: 266 * This is the irq holder, it has 267 * and RX/TX pair or rings associated 268 * with it. 269 */ 270 struct ix_queue *queues; 271 272 /* 273 * Transmit rings: 274 * Allocated at run time, an array of rings. 275 */ 276 struct tx_ring *tx_rings; 277 int num_tx_desc; 278 279 /* 280 * Receive rings: 281 * Allocated at run time, an array of rings. 282 */ 283 struct rx_ring *rx_rings; 284 uint64_t que_mask; 285 int num_rx_desc; 286 287 /* Multicast array memory */ 288 uint8_t *mta; 289 290 /* Misc stats maintained by the driver */ 291 unsigned long dropped_pkts; 292 unsigned long no_tx_map_avail; 293 unsigned long no_tx_dma_setup; 294 unsigned long watchdog_events; 295 unsigned long tso_tx; 296 unsigned long link_irq; 297 298 struct ixgbe_hw_stats stats; 299 }; 300 301 #endif /* _IX_H_ */ 302