1f2ce9f98Sbrad /************************************************************************** 2f2ce9f98Sbrad 3f2ce9f98Sbrad Copyright (c) 2001-2005, Intel Corporation 4f2ce9f98Sbrad All rights reserved. 5f2ce9f98Sbrad 6f2ce9f98Sbrad Redistribution and use in source and binary forms, with or without 7f2ce9f98Sbrad modification, are permitted provided that the following conditions are met: 8f2ce9f98Sbrad 9f2ce9f98Sbrad 1. Redistributions of source code must retain the above copyright notice, 10f2ce9f98Sbrad this list of conditions and the following disclaimer. 11f2ce9f98Sbrad 12f2ce9f98Sbrad 2. Redistributions in binary form must reproduce the above copyright 13f2ce9f98Sbrad notice, this list of conditions and the following disclaimer in the 14f2ce9f98Sbrad documentation and/or other materials provided with the distribution. 15f2ce9f98Sbrad 16f2ce9f98Sbrad 3. Neither the name of the Intel Corporation nor the names of its 17f2ce9f98Sbrad contributors may be used to endorse or promote products derived from 18f2ce9f98Sbrad this software without specific prior written permission. 19f2ce9f98Sbrad 20f2ce9f98Sbrad THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21f2ce9f98Sbrad AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22f2ce9f98Sbrad IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23f2ce9f98Sbrad ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24f2ce9f98Sbrad LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25f2ce9f98Sbrad CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26f2ce9f98Sbrad SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27f2ce9f98Sbrad INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28f2ce9f98Sbrad CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29f2ce9f98Sbrad ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30f2ce9f98Sbrad POSSIBILITY OF SUCH DAMAGE. 31f2ce9f98Sbrad 32f2ce9f98Sbrad ***************************************************************************/ 33f2ce9f98Sbrad 34*32f46ff2Smpi /* $OpenBSD: if_ixgb.h,v 1.19 2015/11/24 17:11:39 mpi Exp $ */ 35f2ce9f98Sbrad 36f2ce9f98Sbrad #ifndef _IXGB_H_DEFINED_ 37f2ce9f98Sbrad #define _IXGB_H_DEFINED_ 38f2ce9f98Sbrad 39f2ce9f98Sbrad #include "bpfilter.h" 40f2ce9f98Sbrad #include "vlan.h" 41f2ce9f98Sbrad 42f2ce9f98Sbrad #include <sys/param.h> 43f2ce9f98Sbrad #include <sys/systm.h> 44f2ce9f98Sbrad #include <sys/sockio.h> 45f2ce9f98Sbrad #include <sys/mbuf.h> 46f2ce9f98Sbrad #include <sys/malloc.h> 47f2ce9f98Sbrad #include <sys/kernel.h> 48f2ce9f98Sbrad #include <sys/device.h> 49f2ce9f98Sbrad #include <sys/socket.h> 509b074ffaStedu #include <sys/timeout.h> 51f2ce9f98Sbrad 52f2ce9f98Sbrad #include <net/if.h> 53f2ce9f98Sbrad #include <net/if_media.h> 54f2ce9f98Sbrad 55f2ce9f98Sbrad #include <netinet/in.h> 56f2ce9f98Sbrad #include <netinet/ip.h> 57f2ce9f98Sbrad #include <netinet/if_ether.h> 58f2ce9f98Sbrad #include <netinet/tcp.h> 59f2ce9f98Sbrad #include <netinet/udp.h> 60f2ce9f98Sbrad 61f2ce9f98Sbrad #if NBPFILTER > 0 62f2ce9f98Sbrad #include <net/bpf.h> 63f2ce9f98Sbrad #endif 64f2ce9f98Sbrad 651792d869Sderaadt typedef int boolean_t; 661792d869Sderaadt #define TRUE 1 671792d869Sderaadt #define FALSE 0 68f2ce9f98Sbrad 69f2ce9f98Sbrad #include <dev/pci/pcireg.h> 70f2ce9f98Sbrad #include <dev/pci/pcivar.h> 71f2ce9f98Sbrad #include <dev/pci/pcidevs.h> 72f2ce9f98Sbrad 73f2ce9f98Sbrad #include <dev/pci/ixgb_hw.h> 74f2ce9f98Sbrad #include <dev/pci/ixgb_ee.h> 75f2ce9f98Sbrad #include <dev/pci/ixgb_ids.h> 76f2ce9f98Sbrad 77f2ce9f98Sbrad /* Tunables */ 78f2ce9f98Sbrad 79f2ce9f98Sbrad /* 803a1df264Sbrad * TxDescriptors Valid Range: 64-4096 Default Value: 2048 This value is the 81f2ce9f98Sbrad * number of transmit descriptors allocated by the driver. Increasing this 82f2ce9f98Sbrad * value allows the driver to queue more transmits. Each descriptor is 16 83f2ce9f98Sbrad * bytes. 84f2ce9f98Sbrad */ 853a1df264Sbrad #define IXGB_MAX_TXD 2048 86f2ce9f98Sbrad 87f2ce9f98Sbrad /* 886e319d6aSbrad * RxDescriptors Valid Range: 64-4096 Default Value: 1024 This value is the 89f2ce9f98Sbrad * number of receive descriptors allocated by the driver. Increasing this 90f2ce9f98Sbrad * value allows the driver to buffer more incoming packets. Each descriptor 91f2ce9f98Sbrad * is 16 bytes. A receive buffer is also allocated for each descriptor. The 92f2ce9f98Sbrad * maximum MTU size is 16110. 93f2ce9f98Sbrad */ 946e319d6aSbrad #define IXGB_MAX_RXD 1024 95f2ce9f98Sbrad 96f2ce9f98Sbrad /* 97f2ce9f98Sbrad * TxIntDelay Valid Range: 0-65535 (0=off) Default Value: 32 This value 98f2ce9f98Sbrad * delays the generation of transmit interrupts in units of 1.024 99f2ce9f98Sbrad * microseconds. Transmit interrupt reduction can improve CPU efficiency if 100f2ce9f98Sbrad * properly tuned for specific network traffic. If the system is reporting 101f2ce9f98Sbrad * dropped transmits, this value may be set too high causing the driver to 102f2ce9f98Sbrad * run out of available transmit descriptors. 103f2ce9f98Sbrad */ 104f2ce9f98Sbrad #define TIDV 32 105f2ce9f98Sbrad 106f2ce9f98Sbrad /* 107f2ce9f98Sbrad * RxIntDelay Valid Range: 0-65535 (0=off) Default Value: 72 This value 108f2ce9f98Sbrad * delays the generation of receive interrupts in units of 1.024 109f2ce9f98Sbrad * microseconds. Receive interrupt reduction can improve CPU efficiency if 110f2ce9f98Sbrad * properly tuned for specific network traffic. Increasing this value adds 111f2ce9f98Sbrad * extra latency to frame reception and can end up decreasing the throughput 112f2ce9f98Sbrad * of TCP traffic. If the system is reporting dropped receives, this value 113f2ce9f98Sbrad * may be set too high, causing the driver to run out of available receive 114f2ce9f98Sbrad * descriptors. 115f2ce9f98Sbrad */ 116f2ce9f98Sbrad #define RDTR 72 117f2ce9f98Sbrad 118f2ce9f98Sbrad /* 119f2ce9f98Sbrad * This parameter controls the duration of transmit watchdog timer. 120f2ce9f98Sbrad */ 121f2ce9f98Sbrad #define IXGB_TX_TIMEOUT 5 /* set to 5 seconds */ 122f2ce9f98Sbrad 123f2ce9f98Sbrad /* 124f2ce9f98Sbrad * This parameter controls when the driver calls the routine to reclaim 125f2ce9f98Sbrad * transmit descriptors. 126f2ce9f98Sbrad */ 127f8df603eSbrad #define IXGB_TX_CLEANUP_THRESHOLD (sc->num_tx_desc / 8) 128f2ce9f98Sbrad 129f2ce9f98Sbrad /* 130f2ce9f98Sbrad * Flow Control Types. 131f2ce9f98Sbrad * 1. ixgb_fc_none - Flow Control Disabled 132f2ce9f98Sbrad * 2. ixgb_fc_rx_pause - Flow Control Receive Only 133f2ce9f98Sbrad * 3. ixgb_fc_tx_pause - Flow Control Transmit Only 134f2ce9f98Sbrad * 4. ixgb_fc_full - Flow Control Enabled 135f2ce9f98Sbrad */ 136f2ce9f98Sbrad #define FLOW_CONTROL_NONE ixgb_fc_none 137f2ce9f98Sbrad #define FLOW_CONTROL_RX_PAUSE ixgb_fc_rx_pause 138f2ce9f98Sbrad #define FLOW_CONTROL_TX_PAUSE ixgb_fc_tx_pause 139f2ce9f98Sbrad #define FLOW_CONTROL_FULL ixgb_fc_full 140f2ce9f98Sbrad 141f2ce9f98Sbrad /* 142f2ce9f98Sbrad * Set the flow control type. Assign one of the above flow control types to be enabled. 143f2ce9f98Sbrad * Default Value: FLOW_CONTROL_FULL 144f2ce9f98Sbrad */ 145f2ce9f98Sbrad #define FLOW_CONTROL FLOW_CONTROL_FULL 146f2ce9f98Sbrad 147f2ce9f98Sbrad /* 148f2ce9f98Sbrad * Receive Flow control low threshold (when we send a resume frame) (FCRTL) 149f2ce9f98Sbrad * Valid Range: 64 - 262,136 (0x40 - 0x3FFF8, 8 byte granularity) must be 150f2ce9f98Sbrad * less than high threshold by at least 8 bytes Default Value: 163,840 151f2ce9f98Sbrad * (0x28000) 152f2ce9f98Sbrad */ 153f2ce9f98Sbrad #define FCRTL 0x28000 154f2ce9f98Sbrad 155f2ce9f98Sbrad /* 156f2ce9f98Sbrad * Receive Flow control high threshold (when we send a pause frame) (FCRTH) 157f2ce9f98Sbrad * Valid Range: 1,536 - 262,136 (0x600 - 0x3FFF8, 8 byte granularity) Default 158f2ce9f98Sbrad * Value: 196,608 (0x30000) 159f2ce9f98Sbrad */ 160f2ce9f98Sbrad #define FCRTH 0x30000 161f2ce9f98Sbrad 162f2ce9f98Sbrad /* 163f2ce9f98Sbrad * Flow control request timeout (how long to pause the link partner's tx) 164f2ce9f98Sbrad * (PAP 15:0) Valid Range: 1 - 65535 Default Value: 256 (0x100) 165f2ce9f98Sbrad */ 166f2ce9f98Sbrad #define FCPAUSE 0x100 167f2ce9f98Sbrad 168f2ce9f98Sbrad /* Tunables -- End */ 169f2ce9f98Sbrad 170f2ce9f98Sbrad #define IXGB_MMBA 0x0010 /* Mem base address */ 171f2ce9f98Sbrad #define IXGB_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 172f2ce9f98Sbrad 173f2ce9f98Sbrad #define MAX_NUM_MULTICAST_ADDRESSES 128 174f2ce9f98Sbrad 175f2ce9f98Sbrad /* Defines for printing debug information */ 176f2ce9f98Sbrad #define DEBUG_INIT 0 177f2ce9f98Sbrad #define DEBUG_IOCTL 0 178f2ce9f98Sbrad #define DEBUG_HW 0 179f2ce9f98Sbrad 180f2ce9f98Sbrad #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 181f2ce9f98Sbrad #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 182f2ce9f98Sbrad #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 183f2ce9f98Sbrad #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 184f2ce9f98Sbrad #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 185f2ce9f98Sbrad #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 186f2ce9f98Sbrad #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 187f2ce9f98Sbrad #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 188f2ce9f98Sbrad #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 189f2ce9f98Sbrad 190f2ce9f98Sbrad /* Supported RX Buffer Sizes */ 191f2ce9f98Sbrad #define IXGB_RXBUFFER_2048 2048 192f2ce9f98Sbrad #define IXGB_RXBUFFER_4096 4096 193f2ce9f98Sbrad #define IXGB_RXBUFFER_8192 8192 194f2ce9f98Sbrad #define IXGB_RXBUFFER_16384 16384 195f2ce9f98Sbrad 196f2ce9f98Sbrad #define IXGB_MAX_SCATTER 100 197f2ce9f98Sbrad 198f2ce9f98Sbrad struct ixgb_buffer { 199f2ce9f98Sbrad struct mbuf *m_head; 200f2ce9f98Sbrad bus_dmamap_t map; /* bus_dma map for packet */ 201f2ce9f98Sbrad }; 202f2ce9f98Sbrad 203f2ce9f98Sbrad /* 204f8df603eSbrad * Bus dma allocation structure used by 205f8df603eSbrad * ixgb_dma_malloc and ixgb_dma_free. 206f2ce9f98Sbrad */ 207f2ce9f98Sbrad struct ixgb_dma_alloc { 208f2ce9f98Sbrad bus_addr_t dma_paddr; 209f2ce9f98Sbrad caddr_t dma_vaddr; 210f2ce9f98Sbrad bus_dma_tag_t dma_tag; 211f2ce9f98Sbrad bus_dmamap_t dma_map; 212f2ce9f98Sbrad bus_dma_segment_t dma_seg; 213f2ce9f98Sbrad bus_size_t dma_size; 214f2ce9f98Sbrad int dma_nseg; 215f2ce9f98Sbrad }; 216f2ce9f98Sbrad 217f2ce9f98Sbrad typedef enum _XSUM_CONTEXT_T { 218f2ce9f98Sbrad OFFLOAD_NONE, 219f2ce9f98Sbrad OFFLOAD_TCP_IP, 220f2ce9f98Sbrad OFFLOAD_UDP_IP 221f2ce9f98Sbrad } XSUM_CONTEXT_T; 222f2ce9f98Sbrad 223f2ce9f98Sbrad /* Our adapter structure */ 224f2ce9f98Sbrad struct ixgb_softc { 225f2ce9f98Sbrad struct device sc_dv; 226f2ce9f98Sbrad struct arpcom interface_data; 227f2ce9f98Sbrad struct ixgb_hw hw; 228f2ce9f98Sbrad 229f2ce9f98Sbrad /* OpenBSD operating-system-specific structures */ 230f2ce9f98Sbrad struct ixgb_osdep osdep; 231f2ce9f98Sbrad struct ifmedia media; 232f2ce9f98Sbrad int io_rid; 233f2ce9f98Sbrad 234f2ce9f98Sbrad void *sc_intrhand; 235f2ce9f98Sbrad struct timeout ixgb_intr_enable; 236f2ce9f98Sbrad struct timeout timer_handle; 237e300026aSbrad int if_flags; 238f2ce9f98Sbrad 239f2ce9f98Sbrad /* Info about the board itself */ 240f2ce9f98Sbrad u_int32_t part_num; 241f2ce9f98Sbrad u_int8_t link_active; 242f2ce9f98Sbrad u_int16_t link_speed; 243f2ce9f98Sbrad u_int16_t link_duplex; 244f2ce9f98Sbrad u_int32_t tx_int_delay; 245f2ce9f98Sbrad u_int32_t tx_abs_int_delay; 246f2ce9f98Sbrad u_int32_t rx_int_delay; 247f2ce9f98Sbrad u_int32_t rx_abs_int_delay; 248f2ce9f98Sbrad 249f2ce9f98Sbrad int raidc; 250f2ce9f98Sbrad 251f2ce9f98Sbrad XSUM_CONTEXT_T active_checksum_context; 252f2ce9f98Sbrad 253f2ce9f98Sbrad /* 254f2ce9f98Sbrad * Transmit definitions 255f2ce9f98Sbrad * 256f2ce9f98Sbrad * We have an array of num_tx_desc descriptors (handled by the 257f2ce9f98Sbrad * controller) paired with an array of tx_buffers (at 258f2ce9f98Sbrad * tx_buffer_area). The index of the next available descriptor is 259f2ce9f98Sbrad * next_avail_tx_desc. The number of remaining tx_desc is 260f2ce9f98Sbrad * num_tx_desc_avail. 261f2ce9f98Sbrad */ 262f2ce9f98Sbrad struct ixgb_dma_alloc txdma; /* bus_dma glue for tx desc */ 263f2ce9f98Sbrad struct ixgb_tx_desc *tx_desc_base; 264f2ce9f98Sbrad u_int32_t next_avail_tx_desc; 265f2ce9f98Sbrad u_int32_t oldest_used_tx_desc; 266f2ce9f98Sbrad volatile u_int16_t num_tx_desc_avail; 267f2ce9f98Sbrad u_int16_t num_tx_desc; 268f2ce9f98Sbrad u_int32_t txd_cmd; 269f2ce9f98Sbrad struct ixgb_buffer *tx_buffer_area; 270f2ce9f98Sbrad bus_dma_tag_t txtag; /* dma tag for tx */ 271f2ce9f98Sbrad 272f2ce9f98Sbrad /* 273f2ce9f98Sbrad * Receive definitions 274f2ce9f98Sbrad * 275f2ce9f98Sbrad * we have an array of num_rx_desc rx_desc (handled by the controller), 276f2ce9f98Sbrad * and paired with an array of rx_buffers (at rx_buffer_area). The 277f2ce9f98Sbrad * next pair to check on receive is at offset next_rx_desc_to_check 278f2ce9f98Sbrad */ 279f2ce9f98Sbrad struct ixgb_dma_alloc rxdma; /* bus_dma glue for rx desc */ 280f2ce9f98Sbrad struct ixgb_rx_desc *rx_desc_base; 281f2ce9f98Sbrad u_int32_t next_rx_desc_to_check; 282f2ce9f98Sbrad u_int16_t num_rx_desc; 283f2ce9f98Sbrad u_int32_t rx_buffer_len; 284f2ce9f98Sbrad struct ixgb_buffer *rx_buffer_area; 285f2ce9f98Sbrad bus_dma_tag_t rxtag; /* dma tag for Rx */ 286f2ce9f98Sbrad u_int32_t next_rx_desc_to_use; 287f2ce9f98Sbrad 288baf31fceSbrad /* 289baf31fceSbrad * First/last mbuf pointers, for 290baf31fceSbrad * collecting multisegment RX packets. 291baf31fceSbrad */ 292f2ce9f98Sbrad struct mbuf *fmp; 293f2ce9f98Sbrad struct mbuf *lmp; 294f2ce9f98Sbrad 295f2ce9f98Sbrad /* Misc stats maintained by the driver */ 296f2ce9f98Sbrad unsigned long dropped_pkts; 297f2ce9f98Sbrad unsigned long mbuf_alloc_failed; 298f2ce9f98Sbrad unsigned long mbuf_cluster_failed; 299f2ce9f98Sbrad unsigned long no_tx_desc_avail1; 300f2ce9f98Sbrad unsigned long no_tx_desc_avail2; 301f2ce9f98Sbrad unsigned long no_tx_map_avail; 302f2ce9f98Sbrad unsigned long no_tx_dma_setup; 303f2ce9f98Sbrad unsigned long watchdog_events; 304f2ce9f98Sbrad 305f2ce9f98Sbrad struct ixgb_hw_stats stats; 306f2ce9f98Sbrad }; 307f2ce9f98Sbrad 308f2ce9f98Sbrad #endif /* _IXGB_H_DEFINED_ */ 309