1 /* $OpenBSD: if_jmereg.h,v 1.4 2008/12/01 09:12:59 jsg Exp $ */ 2 /*- 3 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.1 2008/05/27 01:42:01 yongari Exp $ 29 * $DragonFly: src/sys/dev/netif/jme/if_jmereg.h,v 1.3 2008/09/13 02:47:03 sephe Exp $ 30 */ 31 32 #ifndef _IF_JMEREG_H 33 #define _IF_JMEREG_H 34 35 #define JME_REV_JMC250_A1 0x01 36 #define JME_REV_JMC250_A2 0x11 37 38 /* JMC250 PCI configuration register. */ 39 #define JME_PCIR_BAR 0x10 40 41 #define JME_PCI_EROM 0x30 42 43 #define JME_PCI_DBG 0x9C 44 45 #define JME_PCI_SPI 0xB0 46 47 #define SPI_ENB 0x00000010 48 #define SPI_SO_STATUS 0x00000008 49 #define SPI_SI_CTRL 0x00000004 50 #define SPI_SCK_CTRL 0x00000002 51 #define SPI_CS_N_CTRL 0x00000001 52 53 #define JME_PCI_PHYCFG0 0xC0 54 55 #define JME_PCI_PHYCFG1 0xC4 56 57 #define JME_PCI_PHYCFG2 0xC8 58 59 #define JME_PCI_PHYCFG3 0xCC 60 61 #define JME_PCI_PIPECTL1 0xD0 62 63 #define JME_PCI_PIPECTL2 0xD4 64 65 /* PCIe link error/status. */ 66 #define JME_PCI_LES 0xD8 67 68 /* propeietary register 0. */ 69 #define JME_PCI_PE0 0xE0 70 #define PE0_SPI_EXIST 0x00200000 71 #define PE0_PME_D0 0x00100000 72 #define PE0_PME_D3H 0x00080000 73 #define PE0_PME_SPI_PAD 0x00040000 74 #define PE0_MASK_ASPM 0x00020000 75 #define PE0_EEPROM_RW_DIS 0x00008000 76 #define PE0_PCI_INTA 0x00001000 77 #define PE0_PCI_INTB 0x00002000 78 #define PE0_PCI_INTC 0x00003000 79 #define PE0_PCI_INTD 0x00004000 80 #define PE0_PCI_SVSSID_WR_ENB 0x00000800 81 #define PE0_MSIX_SIZE_8 0x00000700 82 #define PE0_MSIX_SIZE_7 0x00000600 83 #define PE0_MSIX_SIZE_6 0x00000500 84 #define PE0_MSIX_SIZE_5 0x00000400 85 #define PE0_MSIX_SIZE_4 0x00000300 86 #define PE0_MSIX_SIZE_3 0x00000200 87 #define PE0_MSIX_SIZE_2 0x00000100 88 #define PE0_MSIX_SIZE_1 0x00000000 89 #define PE0_MSIX_SIZE_DEF 0x00000700 90 #define PE0_MSIX_CAP_DIS 0x00000080 91 #define PE0_MSI_PVMC_ENB 0x00000040 92 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038 93 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038 94 #define PE0_PM_AUXC_MASK 0x00000007 95 #define PE0_PM_AUXC_DEF 0x00000007 96 97 #define JME_PCI_PE1 0xE4 98 99 #define JME_PCI_PHYTEST 0xF8 100 101 #define JME_PCI_GPR 0xFC 102 103 /* 104 * JMC Register Map. 105 * ----------------------------------------------------------------------- 106 * Register Size IO space Memory space 107 * ----------------------------------------------------------------------- 108 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 109 * BAR1 + 0x7F BAR0 + 0x7F 110 * ----------------------------------------------------------------------- 111 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 112 * BAR2 + 0x7F BAR0 + 0x47F 113 * ----------------------------------------------------------------------- 114 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 115 * BAR2 + 0x7F BAR0 + 0x87F 116 * ----------------------------------------------------------------------- 117 * To simplify register access fuctions and to get better performance 118 * this driver doesn't support IO space access. It could be implemented 119 * as a function which selects appropriate BARs to access requested 120 * register. 121 */ 122 123 /* Tx control and status. */ 124 #define JME_TXCSR 0x0000 125 #define TXCSR_QWEIGHT_MASK 0x0F000000 126 #define TXCSR_QWEIGHT_SHIFT 24 127 #define TXCSR_TXQ_SEL_MASK 0x00070000 128 #define TXCSR_TXQ_SEL_SHIFT 16 129 #define TXCSR_TXQ_START 0x00000001 130 #define TXCSR_TXQ_START_SHIFT 8 131 #define TXCSR_FIFO_THRESH_4QW 0x00000000 132 #define TXCSR_FIFO_THRESH_8QW 0x00000040 133 #define TXCSR_FIFO_THRESH_12QW 0x00000080 134 #define TXCSR_FIFO_THRESH_16QW 0x000000C0 135 #define TXCSR_DMA_SIZE_64 0x00000000 136 #define TXCSR_DMA_SIZE_128 0x00000010 137 #define TXCSR_DMA_SIZE_256 0x00000020 138 #define TXCSR_DMA_SIZE_512 0x00000030 139 #define TXCSR_DMA_BURST 0x00000004 140 #define TXCSR_TX_SUSPEND 0x00000002 141 #define TXCSR_TX_ENB 0x00000001 142 #define TXCSR_TXQ0 0 143 #define TXCSR_TXQ1 1 144 #define TXCSR_TXQ2 2 145 #define TXCSR_TXQ3 3 146 #define TXCSR_TXQ4 4 147 #define TXCSR_TXQ5 5 148 #define TXCSR_TXQ6 6 149 #define TXCSR_TXQ7 7 150 #define TXCSR_TXQ_WEIGHT(x) \ 151 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 152 #define TXCSR_TXQ_WEIGHT_MIN 0 153 #define TXCSR_TXQ_WEIGHT_MAX 15 154 #define TXCSR_TXQ_N_SEL(x) \ 155 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 156 #define TXCSR_TXQ_N_START(x) \ 157 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 158 159 /* Tx queue descriptor base address. 16bytes alignment required. */ 160 #define JME_TXDBA_LO 0x0004 161 #define JME_TXDBA_HI 0x0008 162 163 /* Tx queue descriptor count. multiple of 16(max = 1024). */ 164 #define JME_TXQDC 0x000C 165 #define TXQDC_MASK 0x0000007F0 166 167 /* Tx queue next descriptor address. */ 168 #define JME_TXNDA 0x0010 169 #define TXNDA_ADDR_MASK 0xFFFFFFF0 170 #define TXNDA_DESC_EMPTY 0x00000008 171 #define TXNDA_DESC_VALID 0x00000004 172 #define TXNDA_DESC_WAIT 0x00000002 173 #define TXNDA_DESC_FETCH 0x00000001 174 175 /* Tx MAC control ans status. */ 176 #define JME_TXMAC 0x0014 177 #define TXMAC_IFG2_MASK 0xC0000000 178 #define TXMAC_IFG2_DEFAULT 0x40000000 179 #define TXMAC_IFG1_MASK 0x30000000 180 #define TXMAC_IFG1_DEFAULT 0x20000000 181 #define TXMAC_THRESH_1_PKT 0x00000300 182 #define TXMAC_THRESH_1_2_PKT 0x00000200 183 #define TXMAC_THRESH_1_4_PKT 0x00000100 184 #define TXMAC_THRESH_1_8_PKT 0x00000000 185 #define TXMAC_FRAME_BURST 0x00000080 186 #define TXMAC_CARRIER_EXT 0x00000040 187 #define TXMAC_IFG_ENB 0x00000020 188 #define TXMAC_BACKOFF 0x00000010 189 #define TXMAC_CARRIER_SENSE 0x00000008 190 #define TXMAC_COLL_ENB 0x00000004 191 #define TXMAC_CRC_ENB 0x00000002 192 #define TXMAC_PAD_ENB 0x00000001 193 194 /* Tx pause frame control. */ 195 #define JME_TXPFC 0x0018 196 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000 197 #define TXPFC_VLAN_TAG_SHIFT 16 198 #define TXPFC_VLAN_ENB 0x00008000 199 #define TXPFC_PAUSE_ENB 0x00000001 200 201 /* Tx timer/retry at half duplex. */ 202 #define JME_TXTRHD 0x001C 203 #define TXTRHD_RT_PERIOD_ENB 0x80000000 204 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 205 #define TXTRHD_RT_PERIOD_SHIFT 8 206 #define TXTRHD_RT_LIMIT_ENB 0x00000080 207 #define TXTRHD_RT_LIMIT_MASK 0x0000007F 208 #define TXTRHD_RT_LIMIT_SHIFT 0 209 #define TXTRHD_RT_PERIOD_DEFAULT 8192 210 #define TXTRHD_RT_LIMIT_DEFAULT 8 211 212 /* Rx control & status. */ 213 #define JME_RXCSR 0x0020 214 #define RXCSR_FIFO_FTHRESH_16T 0x00000000 215 #define RXCSR_FIFO_FTHRESH_32T 0x10000000 216 #define RXCSR_FIFO_FTHRESH_64T 0x20000000 217 #define RXCSR_FIFO_FTHRESH_128T 0x30000000 218 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 219 #define RXCSR_FIFO_THRESH_16QW 0x00000000 220 #define RXCSR_FIFO_THRESH_32QW 0x04000000 221 #define RXCSR_FIFO_THRESH_64QW 0x08000000 222 #define RXCSR_FIFO_THRESH_128QW 0x0C000000 223 #define RXCSR_FIFO_THRESH_MASK 0x0C000000 224 #define RXCSR_DMA_SIZE_16 0x00000000 225 #define RXCSR_DMA_SIZE_32 0x01000000 226 #define RXCSR_DMA_SIZE_64 0x02000000 227 #define RXCSR_DMA_SIZE_128 0x03000000 228 #define RXCSR_RXQ_SEL_MASK 0x00030000 229 #define RXCSR_RXQ_SEL_SHIFT 16 230 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000 231 #define RXCSR_DESC_RT_GAP_SHIFT 12 232 #define RXCSR_DESC_RT_GAP_256 0x00000000 233 #define RXCSR_DESC_RT_GAP_512 0x00001000 234 #define RXCSR_DESC_RT_GAP_1024 0x00002000 235 #define RXCSR_DESC_RT_GAP_2048 0x00003000 236 #define RXCSR_DESC_RT_GAP_4096 0x00004000 237 #define RXCSR_DESC_RT_GAP_8192 0x00005000 238 #define RXCSR_DESC_RT_GAP_16384 0x00006000 239 #define RXCSR_DESC_RT_GAP_32768 0x00007000 240 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00 241 #define RXCSR_DESC_RT_CNT_SHIFT 8 242 #define RXCSR_PASS_WAKEUP_PKT 0x00000040 243 #define RXCSR_PASS_MAGIC_PKT 0x00000020 244 #define RXCSR_PASS_RUNT_PKT 0x00000010 245 #define RXCSR_PASS_BAD_PKT 0x00000008 246 #define RXCSR_RXQ_START 0x00000004 247 #define RXCSR_RX_SUSPEND 0x00000002 248 #define RXCSR_RX_ENB 0x00000001 249 250 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 251 #define RXCSR_RXQ0 0 252 #define RXCSR_RXQ1 1 253 #define RXCSR_RXQ2 2 254 #define RXCSR_RXQ3 3 255 #define RXCSR_DESC_RT_CNT(x) \ 256 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 257 #define RXCSR_DESC_RT_CNT_DEFAULT 32 258 259 /* Rx queue descriptor base address. 16bytes alignment needed. */ 260 #define JME_RXDBA_LO 0x0024 261 #define JME_RXDBA_HI 0x0028 262 263 /* Rx queue descriptor count. multiple of 16(max = 1024). */ 264 #define JME_RXQDC 0x002C 265 #define RXQDC_MASK 0x0000007F0 266 267 /* Rx queue next descriptor address. */ 268 #define JME_RXNDA 0x0030 269 #define RXNDA_ADDR_MASK 0xFFFFFFF0 270 #define RXNDA_DESC_EMPTY 0x00000008 271 #define RXNDA_DESC_VALID 0x00000004 272 #define RXNDA_DESC_WAIT 0x00000002 273 #define RXNDA_DESC_FETCH 0x00000001 274 275 /* Rx MAC control and status. */ 276 #define JME_RXMAC 0x0034 277 #define RXMAC_RSS_UNICAST 0x00000000 278 #define RXMAC_RSS_UNI_MULTICAST 0x00010000 279 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 280 #define RXMAC_RSS_ALLFRAME 0x00030000 281 #define RXMAC_PROMISC 0x00000800 282 #define RXMAC_BROADCAST 0x00000400 283 #define RXMAC_MULTICAST 0x00000200 284 #define RXMAC_UNICAST 0x00000100 285 #define RXMAC_ALLMULTI 0x00000080 286 #define RXMAC_MULTICAST_FILTER 0x00000040 287 #define RXMAC_COLL_DET_ENB 0x00000020 288 #define RXMAC_FC_ENB 0x00000008 289 #define RXMAC_VLAN_ENB 0x00000004 290 #define RXMAC_PAD_10BYTES 0x00000002 291 #define RXMAC_CSUM_ENB 0x00000001 292 293 /* Rx unicast MAC address. */ 294 #define JME_PAR0 0x0038 295 #define JME_PAR1 0x003C 296 297 /* Rx multicast address hash table. */ 298 #define JME_MAR0 0x0040 299 #define JME_MAR1 0x0044 300 301 /* Wakeup frame output data port. */ 302 #define JME_WFODP 0x0048 303 304 /* Wakeup frame output interface. */ 305 #define JME_WFOI 0x004C 306 #define WFOI_MASK_0_31 0x00000000 307 #define WFOI_MASK_31_63 0x00000010 308 #define WFOI_MASK_64_95 0x00000020 309 #define WFOI_MASK_96_127 0x00000030 310 #define WFOI_MASK_SEL 0x00000008 311 #define WFOI_CRC_SEL 0x00000000 312 #define WFOI_WAKEUP_FRAME_MASK 0x00000007 313 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 314 315 /* Station management interface. */ 316 #define JME_SMI 0x0050 317 #define SMI_DATA_MASK 0xFFFF0000 318 #define SMI_DATA_SHIFT 16 319 #define SMI_REG_ADDR_MASK 0x0000F800 320 #define SMI_REG_ADDR_SHIFT 11 321 #define SMI_PHY_ADDR_MASK 0x000007C0 322 #define SMI_PHY_ADDR_SHIFT 6 323 #define SMI_OP_WRITE 0x00000020 324 #define SMI_OP_READ 0x00000000 325 #define SMI_OP_EXECUTE 0x00000010 326 #define SMI_MDIO 0x00000008 327 #define SMI_MDOE 0x00000004 328 #define SMI_MDC 0x00000002 329 #define SMI_MDEN 0x00000001 330 #define SMI_REG_ADDR(x) \ 331 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 332 #define SMI_PHY_ADDR(x) \ 333 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 334 335 /* Global host control. */ 336 #define JME_GHC 0x0054 337 #define GHC_LOOPBACK 0x80000000 338 #define GHC_RESET 0x40000000 339 /* Tx offload engine clock source */ 340 #define GHC_TCPCK_10_100 0x00800000 341 #define GHC_TCPCK_1000 0x00400000 342 #define GHC_TCPCK_MASK 0x00c00000 343 /* Tx MAC clock source */ 344 #define GHC_TXCK_10_100 0x00200000 345 #define GHC_TXCK_1000 0x00100000 346 #define GHC_TXCK_MASK 0x00300000 347 #define GHC_FULL_DUPLEX 0x00000040 348 #define GHC_SPEED_UNKNOWN 0x00000000 349 #define GHC_SPEED_10 0x00000010 350 #define GHC_SPEED_100 0x00000020 351 #define GHC_SPEED_1000 0x00000030 352 #define GHC_SPEED_MASK 0x00000030 353 #define GHC_LINK_OFF 0x00000004 354 #define GHC_LINK_ON 0x00000002 355 #define GHC_LINK_STAT_POLLING 0x00000001 356 357 /* Power management control and status. */ 358 #define JME_PMCS 0x0060 359 #define PMCS_WAKEUP_FRAME_7 0x80000000 360 #define PMCS_WAKEUP_FRAME_6 0x40000000 361 #define PMCS_WAKEUP_FRAME_5 0x20000000 362 #define PMCS_WAKEUP_FRAME_4 0x10000000 363 #define PMCS_WAKEUP_FRAME_3 0x08000000 364 #define PMCS_WAKEUP_FRAME_2 0x04000000 365 #define PMCS_WAKEUP_FRAME_1 0x02000000 366 #define PMCS_WAKEUP_FRAME_0 0x01000000 367 #define PMCS_LINK_FAIL 0x00040000 368 #define PMCS_LINK_RISING 0x00020000 369 #define PMCS_MAGIC_FRAME 0x00010000 370 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 371 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 372 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 373 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 374 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 375 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 376 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 377 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 378 #define PMCS_LINK_FAIL_ENB 0x00000004 379 #define PMCS_LINK_RISING_ENB 0x00000002 380 #define PMCS_MAGIC_FRAME_ENB 0x00000001 381 #define PMCS_WOL_ENB_MASK 0x0000FFFF 382 383 /* Giga PHY & EEPROM registers. */ 384 #define JME_PHY_EEPROM_BASE_ADDR 0x0400 385 386 #define JME_GIGAR0LO 0x0400 387 #define JME_GIGAR0HI 0x0404 388 #define JME_GIGARALO 0x0408 389 #define JME_GIGARAHI 0x040C 390 #define JME_GIGARBLO 0x0410 391 #define JME_GIGARBHI 0x0414 392 #define JME_GIGARCLO 0x0418 393 #define JME_GIGARCHI 0x041C 394 #define JME_GIGARDLO 0x0420 395 #define JME_GIGARDHI 0x0424 396 397 /* BIST status and control. */ 398 #define JME_GIGACSR 0x0428 399 #define GIGACSR_STATUS 0x40000000 400 #define GIGACSR_CTRL_MASK 0x30000000 401 #define GIGACSR_CTRL_DEFAULT 0x30000000 402 #define GIGACSR_TX_CLK_MASK 0x0F000000 403 #define GIGACSR_RX_CLK_MASK 0x00F00000 404 #define GIGACSR_TX_CLK_INV 0x00080000 405 #define GIGACSR_RX_CLK_INV 0x00040000 406 #define GIGACSR_PHY_RST 0x00010000 407 #define GIGACSR_IRQ_N_O 0x00001000 408 #define GIGACSR_BIST_OK 0x00000200 409 #define GIGACSR_BIST_DONE 0x00000100 410 #define GIGACSR_BIST_LED_ENB 0x00000010 411 #define GIGACSR_BIST_MASK 0x00000003 412 413 /* PHY Link Status. */ 414 #define JME_LNKSTS 0x0430 415 #define LINKSTS_SPEED_10 0x00000000 416 #define LINKSTS_SPEED_100 0x00004000 417 #define LINKSTS_SPEED_1000 0x00008000 418 #define LINKSTS_FULL_DUPLEX 0x00002000 419 #define LINKSTS_PAGE_RCVD 0x00001000 420 #define LINKSTS_SPDDPX_RESOLVED 0x00000800 421 #define LINKSTS_UP 0x00000400 422 #define LINKSTS_ANEG_COMP 0x00000200 423 #define LINKSTS_MDI_CROSSOVR 0x00000040 424 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 425 #define LINKSTS_LPAR_PAUSE 0x00000001 426 427 /* SMB control and status. */ 428 #define JME_SMBCSR 0x0440 429 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 430 #define SMBCSR_WR_DATA_NACK 0x00040000 431 #define SMBCSR_CMD_NACK 0x00020000 432 #define SMBCSR_RELOAD 0x00010000 433 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00 434 #define SMBCSR_SCL_STAT 0x00000080 435 #define SMBCSR_SDA_STAT 0x00000040 436 #define SMBCSR_EEPROM_PRESENT 0x00000020 437 #define SMBCSR_INIT_LD_DONE 0x00000010 438 #define SMBCSR_HW_BUSY_MASK 0x0000000F 439 #define SMBCSR_HW_IDLE 0x00000000 440 441 /* SMB interface. */ 442 #define JME_SMBINTF 0x0444 443 #define SMBINTF_RD_DATA_MASK 0xFF000000 444 #define SMBINTF_RD_DATA_SHIFT 24 445 #define SMBINTF_WR_DATA_MASK 0x00FF0000 446 #define SMBINTF_WR_DATA_SHIFT 16 447 #define SMBINTF_ADDR_MASK 0x0000FF00 448 #define SMBINTF_ADDR_SHIFT 8 449 #define SMBINTF_RD 0x00000020 450 #define SMBINTF_WR 0x00000000 451 #define SMBINTF_CMD_TRIGGER 0x00000010 452 #define SMBINTF_BUSY 0x00000010 453 #define SMBINTF_FAST_MODE 0x00000008 454 #define SMBINTF_GPIO_SCL 0x00000004 455 #define SMBINTF_GPIO_SDA 0x00000002 456 #define SMBINTF_GPIO_ENB 0x00000001 457 458 #define JME_EEPROM_SIG0 0x55 459 #define JME_EEPROM_SIG1 0xAA 460 #define JME_EEPROM_DESC_BYTES 3 461 #define JME_EEPROM_DESC_END 0x80 462 #define JME_EEPROM_FUNC_MASK 0x70 463 #define JME_EEPROM_FUNC_SHIFT 4 464 #define JME_EEPROM_PAGE_MASK 0x0F 465 #define JME_EEPROM_PAGE_SHIFT 0 466 467 #define JME_EEPROM_FUNC0 0 468 /* PCI configuration space. */ 469 #define JME_EEPROM_PAGE_BAR0 0 470 /* 128 bytes I/O window. */ 471 #define JME_EEPROM_PAGE_BAR1 1 472 /* 256 bytes I/O window. */ 473 #define JME_EEPROM_PAGE_BAR2 2 474 475 #define JME_EEPROM_END 0xFF 476 477 #define JME_EEPROM_MKDESC(f, p) \ 478 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 479 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 480 481 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 482 #define JME_EEPINTF 0x0448 483 #define EEPINTF_DATA_MASK 0xFFFF0000 484 #define EEPINTF_DATA_SHIFT 16 485 #define EEPINTF_ADDR_MASK 0x0000FC00 486 #define EEPINTF_ADDR_SHIFT 10 487 #define EEPRINTF_OP_MASK 0x00000300 488 #define EEPINTF_OP_EXECUTE 0x00000080 489 #define EEPINTF_DATA_OUT 0x00000008 490 #define EEPINTF_DATA_IN 0x00000004 491 #define EEPINTF_CLK 0x00000002 492 #define EEPINTF_SEL 0x00000001 493 494 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 495 #define JME_EEPCSR 0x044C 496 #define EEPCSR_EEPROM_RELOAD 0x00000002 497 #define EEPCSR_EEPROM_PRESENT 0x00000001 498 499 /* Misc registers. */ 500 #define JME_MISC_BASE_ADDR 0x800 501 502 /* Timer control and status. */ 503 #define JME_TMCSR 0x0800 504 #define TMCSR_SW_INTR 0x80000000 505 #define TMCSR_TIMER_INTR 0x10000000 506 #define TMCSR_TIMER_ENB 0x01000000 507 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 508 509 /* GPIO control and status. */ 510 #define JME_GPIO 0x0804 511 #define GPIO_4_SPI_IN 0x80000000 512 #define GPIO_3_SPI_IN 0x40000000 513 #define GPIO_4_SPI_OUT 0x20000000 514 #define GPIO_4_SPI_OUT_ENB 0x10000000 515 #define GPIO_3_SPI_OUT 0x08000000 516 #define GPIO_3_SPI_OUT_ENB 0x04000000 517 #define GPIO_3_4_LED 0x00000000 518 #define GPIO_3_4_GPIO 0x02000000 519 #define GPIO_2_CLKREQN_IN 0x00100000 520 #define GPIO_2_CLKREQN_OUT 0x00040000 521 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000 522 #define GPIO_1_LED42_IN 0x00001000 523 #define GPIO_1_LED42_OUT 0x00000400 524 #define GPIO_1_LED42_OUT_ENB 0x00000200 525 #define GPIO_1_LED42_ENB 0x00000100 526 #define GPIO_0_SDA_IN 0x00000010 527 #define GPIO_0_SDA_OUT 0x00000004 528 #define GPIO_0_SDA_OUT_ENB 0x00000002 529 #define GPIO_0_SDA_ENB 0x00000001 530 531 /* General purpose register 0. */ 532 #define JME_GPREG0 0x0808 533 #define GPREG0_SH_POST_DW7_DIS 0x80000000 534 #define GPREG0_SH_POST_DW6_DIS 0x40000000 535 #define GPREG0_SH_POST_DW5_DIS 0x20000000 536 #define GPREG0_SH_POST_DW4_DIS 0x10000000 537 #define GPREG0_SH_POST_DW3_DIS 0x08000000 538 #define GPREG0_SH_POST_DW2_DIS 0x04000000 539 #define GPREG0_SH_POST_DW1_DIS 0x02000000 540 #define GPREG0_SH_POST_DW0_DIS 0x01000000 541 #define GPREG0_DMA_RD_REQ_8 0x00000000 542 #define GPREG0_DMA_RD_REQ_6 0x00100000 543 #define GPREG0_DMA_RD_REQ_5 0x00200000 544 #define GPREG0_DMA_RD_REQ_4 0x00300000 545 #define GPREG0_POST_DW0_ENB 0x00040000 546 #define GPREG0_PCC_CLR_DIS 0x00020000 547 #define GPREG0_FORCE_SCL_OUT 0x00010000 548 #define GPREG0_DL_RSTB_DIS 0x00008000 549 #define GPREG0_STICKY_RESET 0x00004000 550 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000 551 #define GPREG0_LINK_CHG_POLL 0x00001000 552 #define GPREG0_LINK_CHG_DIRECT 0x00000000 553 #define GPREG0_MSI_GEN_SEL 0x00000800 554 #define GPREG0_SMB_PAD_PU_DIS 0x00000400 555 #define GPREG0_PCC_UNIT_16US 0x00000000 556 #define GPREG0_PCC_UNIT_256US 0x00000100 557 #define GPREG0_PCC_UNIT_US 0x00000200 558 #define GPREG0_PCC_UNIT_MS 0x00000300 559 #define GPREG0_PCC_UNIT_MASK 0x00000300 560 #define GPREG0_INTR_EVENT_ENB 0x00000080 561 #define GPREG0_PME_ENB 0x00000020 562 #define GPREG0_PHY_ADDR_MASK 0x0000001F 563 #define GPREG0_PHY_ADDR_SHIFT 0 564 #define GPREG0_PHY_ADDR 1 565 566 /* General purpose register 1. */ 567 #define JME_GPREG1 0x080C 568 #define GPREG1_HALF_PATCH 0x00000020 /* 250A2 only, for 10/100 mode */ 569 #define GPREG1_RSS_PATCH 0x00000040 /* 250A2 only, for 10/100 mode */ 570 571 /* MSIX entry number of interrupt source. */ 572 #define JME_MSINUM_BASE 0x0810 573 #define JME_MSINUM_END 0x081F 574 #define MSINUM_MASK 0x7FFFFFFF 575 #define MSINUM_ENTRY_MASK 7 576 #define MSINUM_REG_INDEX(x) ((x) / 8) 577 #define MSINUM_INTR_SOURCE(x, y) \ 578 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 579 #define MSINUM_NUM_INTR_SOURCE 32 580 581 /* Interrupt event status. */ 582 #define JME_INTR_STATUS 0x0820 583 #define INTR_SW 0x80000000 584 #define INTR_TIMER 0x40000000 585 #define INTR_LINKCHG 0x20000000 586 #define INTR_PAUSE 0x10000000 587 #define INTR_MAGIC_PKT 0x08000000 588 #define INTR_WAKEUP_PKT 0x04000000 589 #define INTR_RXQ0_COAL_TO 0x02000000 590 #define INTR_RXQ1_COAL_TO 0x01000000 591 #define INTR_RXQ2_COAL_TO 0x00800000 592 #define INTR_RXQ3_COAL_TO 0x00400000 593 #define INTR_TXQ_COAL_TO 0x00200000 594 #define INTR_RXQ0_COAL 0x00100000 595 #define INTR_RXQ1_COAL 0x00080000 596 #define INTR_RXQ2_COAL 0x00040000 597 #define INTR_RXQ3_COAL 0x00020000 598 #define INTR_TXQ_COAL 0x00010000 599 #define INTR_RXQ3_DESC_EMPTY 0x00008000 600 #define INTR_RXQ2_DESC_EMPTY 0x00004000 601 #define INTR_RXQ1_DESC_EMPTY 0x00002000 602 #define INTR_RXQ0_DESC_EMPTY 0x00001000 603 #define INTR_RXQ3_COMP 0x00000800 604 #define INTR_RXQ2_COMP 0x00000400 605 #define INTR_RXQ1_COMP 0x00000200 606 #define INTR_RXQ0_COMP 0x00000100 607 #define INTR_TXQ7_COMP 0x00000080 608 #define INTR_TXQ6_COMP 0x00000040 609 #define INTR_TXQ5_COMP 0x00000020 610 #define INTR_TXQ4_COMP 0x00000010 611 #define INTR_TXQ3_COMP 0x00000008 612 #define INTR_TXQ2_COMP 0x00000004 613 #define INTR_TXQ1_COMP 0x00000002 614 #define INTR_TXQ0_COMP 0x00000001 615 616 #define INTR_RXQ_COAL_TO \ 617 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 618 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 619 620 #define INTR_RXQ_COAL \ 621 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 622 INTR_RXQ3_COAL) 623 624 #define INTR_RXQ_COMP \ 625 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 626 INTR_RXQ3_COMP) 627 628 #define INTR_RXQ_DESC_EMPTY \ 629 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 630 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 631 632 #define INTR_RXQ_COMP \ 633 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 634 INTR_RXQ3_COMP) 635 636 #define INTR_TXQ_COMP \ 637 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 638 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 639 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 640 641 #define JME_INTRS \ 642 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 643 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 644 645 #define N_INTR_SW 31 646 #define N_INTR_TIMER 30 647 #define N_INTR_LINKCHG 29 648 #define N_INTR_PAUSE 28 649 #define N_INTR_MAGIC_PKT 27 650 #define N_INTR_WAKEUP_PKT 26 651 #define N_INTR_RXQ0_COAL_TO 25 652 #define N_INTR_RXQ1_COAL_TO 24 653 #define N_INTR_RXQ2_COAL_TO 23 654 #define N_INTR_RXQ3_COAL_TO 22 655 #define N_INTR_TXQ_COAL_TO 21 656 #define N_INTR_RXQ0_COAL 20 657 #define N_INTR_RXQ1_COAL 19 658 #define N_INTR_RXQ2_COAL 18 659 #define N_INTR_RXQ3_COAL 17 660 #define N_INTR_TXQ_COAL 16 661 #define N_INTR_RXQ3_DESC_EMPTY 15 662 #define N_INTR_RXQ2_DESC_EMPTY 14 663 #define N_INTR_RXQ1_DESC_EMPTY 13 664 #define N_INTR_RXQ0_DESC_EMPTY 12 665 #define N_INTR_RXQ3_COMP 11 666 #define N_INTR_RXQ2_COMP 10 667 #define N_INTR_RXQ1_COMP 9 668 #define N_INTR_RXQ0_COMP 8 669 #define N_INTR_TXQ7_COMP 7 670 #define N_INTR_TXQ6_COMP 6 671 #define N_INTR_TXQ5_COMP 5 672 #define N_INTR_TXQ4_COMP 4 673 #define N_INTR_TXQ3_COMP 3 674 #define N_INTR_TXQ2_COMP 2 675 #define N_INTR_TXQ1_COMP 1 676 #define N_INTR_TXQ0_COMP 0 677 678 /* Interrupt request status. */ 679 #define JME_INTR_REQ_STATUS 0x0824 680 681 /* Interrupt enable - setting port. */ 682 #define JME_INTR_MASK_SET 0x0828 683 684 /* Interrupt enable - clearing port. */ 685 #define JME_INTR_MASK_CLR 0x082C 686 687 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 688 #define JME_PCCRX0 0x0830 689 #define JME_PCCRX1 0x0834 690 #define JME_PCCRX2 0x0838 691 #define JME_PCCRX3 0x083C 692 #define PCCRX_COAL_TO_MASK 0xFFFF0000 693 #define PCCRX_COAL_TO_SHIFT 16 694 #define PCCRX_COAL_PKT_MASK 0x0000FF00 695 #define PCCRX_COAL_PKT_SHIFT 8 696 697 #define PCCRX_COAL_TO_MIN 1 698 #define PCCRX_COAL_TO_DEFAULT 100 699 #define PCCRX_COAL_TO_MAX 65535 700 701 #define PCCRX_COAL_PKT_MIN 1 702 #define PCCRX_COAL_PKT_DEFAULT 64 703 #define PCCRX_COAL_PKT_MAX 255 704 705 /* Packet completion coalescing control of Tx queue. */ 706 #define JME_PCCTX 0x0840 707 #define PCCTX_COAL_TO_MASK 0xFFFF0000 708 #define PCCTX_COAL_TO_SHIFT 16 709 #define PCCTX_COAL_PKT_MASK 0x0000FF00 710 #define PCCTX_COAL_PKT_SHIFT 8 711 #define PCCTX_COAL_TXQ7 0x00000080 712 #define PCCTX_COAL_TXQ6 0x00000040 713 #define PCCTX_COAL_TXQ5 0x00000020 714 #define PCCTX_COAL_TXQ4 0x00000010 715 #define PCCTX_COAL_TXQ3 0x00000008 716 #define PCCTX_COAL_TXQ2 0x00000004 717 #define PCCTX_COAL_TXQ1 0x00000002 718 #define PCCTX_COAL_TXQ0 0x00000001 719 720 #define PCCTX_COAL_TO_MIN 1 721 #define PCCTX_COAL_TO_DEFAULT 65535 722 #define PCCTX_COAL_TO_MAX 65535 723 724 #define PCCTX_COAL_PKT_MIN 1 725 #define PCCTX_COAL_PKT_DEFAULT 64 726 #define PCCTX_COAL_PKT_MAX 255 727 728 /* Chip mode and FPGA version. */ 729 #define JME_CHIPMODE 0x0844 730 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 731 #define CHIPMODE_FPGA_REV_SHIFT 16 732 #define CHIPMODE_NOT_FPGA 0 733 #define CHIPMODE_REV_MASK 0x0000FF00 734 #define CHIPMODE_REV_SHIFT 8 735 #define CHIPMODE_REVFM_MASK 0x00000F00 736 #define CHIPMODE_REVFM_SHIFT 8 737 #define CHIPMODE_MODE_48P 0x0000000C 738 #define CHIPMODE_MODE_64P 0x00000004 739 #define CHIPMODE_MODE_128P_MAC 0x00000003 740 #define CHIPMODE_MODE_128P_DBG 0x00000002 741 #define CHIPMODE_MODE_128P_PHY 0x00000000 742 743 /* Shadow status base address high/low. */ 744 #define JME_SHBASE_ADDR_HI 0x0848 745 #define JME_SHBASE_ADDR_LO 0x084C 746 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 747 #define SHBASE_POST_FORCE 0x00000002 748 #define SHBASE_POST_ENB 0x00000001 749 750 /* Timer 1 and 2. */ 751 #define JME_TIMER1 0x0870 752 #define JME_TIMER2 0x0874 753 #define TIMER_ENB 0x01000000 754 #define TIMER_CNT_MASK 0x00FFFFFF 755 #define TIMER_CNT_SHIFT 0 756 #define TIMER_UNIT 1024 /* 1024us */ 757 758 /* Aggresive power mode control. */ 759 #define JME_APMC 0x087C 760 #define APMC_PCIE_SDOWN_STAT 0x80000000 761 #define APMC_PCIE_SDOWN_ENB 0x40000000 762 #define APMC_PSEUDO_HOT_PLUG 0x20000000 763 #define APMC_EXT_PLUGIN_ENB 0x04000000 764 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 765 #define APMC_DIS_SRAM 0x00000004 766 #define APMC_DIS_CLKPM 0x00000002 767 #define APMC_DIS_CLKTX 0x00000001 768 769 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 770 #define JME_PCCSRX_BASE 0x0880 771 #define JME_PCCSRX_END 0x088F 772 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 773 #define PCCSRX_TO_MASK 0xFFFF0000 774 #define PCCSRX_TO_SHIFT 16 775 #define PCCSRX_PKT_CNT_MASK 0x0000FF00 776 #define PCCSRX_PKT_CNT_SHIFT 8 777 778 /* Packet completion coalesing status of Tx queue. */ 779 #define JME_PCCSTX 0x0890 780 #define PCCSTX_TO_MASK 0xFFFF0000 781 #define PCCSTX_TO_SHIFT 16 782 #define PCCSTX_PKT_CNT_MASK 0x0000FF00 783 #define PCCSTX_PKT_CNT_SHIFT 8 784 785 /* Tx queues empty indicator. */ 786 #define JME_TXQEMPTY 0x0894 787 #define TXQEMPTY_TXQ7 0x00000080 788 #define TXQEMPTY_TXQ6 0x00000040 789 #define TXQEMPTY_TXQ5 0x00000020 790 #define TXQEMPTY_TXQ4 0x00000010 791 #define TXQEMPTY_TXQ3 0x00000008 792 #define TXQEMPTY_TXQ2 0x00000004 793 #define TXQEMPTY_TXQ1 0x00000002 794 #define TXQEMPTY_TXQ0 0x00000001 795 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 796 797 /* RSS control registers. */ 798 #define JME_RSS_BASE 0x0C00 799 800 #define JME_RSSC 0x0C00 801 #define RSSC_HASH_LEN_MASK 0x0000E000 802 #define RSSC_HASH_64_ENTRY 0x0000A000 803 #define RSSC_HASH_128_ENTRY 0x0000E000 804 #define RSSC_HASH_NONE 0x00001000 805 #define RSSC_HASH_IPV6 0x00000800 806 #define RSSC_HASH_IPV4 0x00000400 807 #define RSSC_HASH_IPV6_TCP 0x00000200 808 #define RSSC_HASH_IPV4_TCP 0x00000100 809 #define RSSC_NCPU_MASK 0x000000F8 810 #define RSSC_NCPU_SHIFT 3 811 #define RSSC_DIS_RSS 0x00000000 812 #define RSSC_2RXQ_ENB 0x00000001 813 #define RSSS_4RXQ_ENB 0x00000002 814 815 /* CPU vector. */ 816 #define JME_RSSCPU 0x0C04 817 #define RSSCPU_N_SEL(x) ((1 << (x)) 818 819 /* RSS Hash value. */ 820 #define JME_RSSHASH 0x0C10 821 822 #define JME_RSSHASH_STAT 0x0C14 823 824 #define JME_RSS_RDATA0 0x0C18 825 826 #define JME_RSS_RDATA1 0x0C1C 827 828 /* RSS secret key. */ 829 #define JME_RSSKEY_BASE 0x0C40 830 #define JME_RSSKEY_LAST 0x0C64 831 #define JME_RSSKEY_END 0x0C67 832 #define HASHKEY_NBYTES 40 833 #define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 834 #define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 835 836 /* RSS indirection table entries. */ 837 #define JME_RSSTBL_BASE 0x0C80 838 #define JME_RSSTBL_END 0x0CFF 839 #define RSSTBL_NENTRY 128 840 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 841 #define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 842 843 /* MSI-X table. */ 844 #define JME_MSIX_BASE_ADDR 0x2000 845 846 #define JME_MSIX_BASE 0x2000 847 #define JME_MSIX_END 0x207F 848 #define JME_MSIX_NENTRY 8 849 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 850 #define MSIX_ADDR_HI_OFF 0x00 851 #define MSIX_ADDR_LO_OFF 0x04 852 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC 853 #define MSIX_DATA_OFF 0x08 854 #define MSIX_VECTOR_OFF 0x0C 855 #define MSIX_VECTOR_RSVD 0x80000000 856 #define MSIX_VECTOR_DIS 0x00000001 857 858 /* MSI-X PBA. */ 859 #define JME_MSIX_PBA_BASE_ADDR 0x3000 860 861 #define JME_MSIX_PBA 0x3000 862 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00 863 #define MSIX_PBA_RSVD_SHIFT 8 864 #define MSIX_PBA_PEND_MASK 0x000000FF 865 #define MSIX_PBA_PEND_SHIFT 0 866 #define MSIX_PBA_PEND_ENTRY7 0x00000080 867 #define MSIX_PBA_PEND_ENTRY6 0x00000040 868 #define MSIX_PBA_PEND_ENTRY5 0x00000020 869 #define MSIX_PBA_PEND_ENTRY4 0x00000010 870 #define MSIX_PBA_PEND_ENTRY3 0x00000008 871 #define MSIX_PBA_PEND_ENTRY2 0x00000004 872 #define MSIX_PBA_PEND_ENTRY1 0x00000002 873 #define MSIX_PBA_PEND_ENTRY0 0x00000001 874 875 #define JME_PHY_OUI 0x001B8C 876 #define JME_PHY_MODEL 0x21 877 #define JME_PHY_REV 0x01 878 #define JME_PHY_ADDR 1 879 880 /* JMC250 shadow status block. */ 881 struct jme_ssb { 882 uint32_t dw0; 883 uint32_t dw1; 884 uint32_t dw2; 885 uint32_t dw3; 886 uint32_t dw4; 887 uint32_t dw5; 888 uint32_t dw6; 889 uint32_t dw7; 890 }; 891 892 /* JMC250 descriptor structures. */ 893 struct jme_desc { 894 uint32_t flags; 895 uint32_t buflen; 896 uint32_t addr_hi; 897 uint32_t addr_lo; 898 }; 899 900 #define JME_TD_OWN 0x80000000 901 #define JME_TD_INTR 0x40000000 902 #define JME_TD_64BIT 0x20000000 903 #define JME_TD_TCPCSUM 0x10000000 904 #define JME_TD_UDPCSUM 0x08000000 905 #define JME_TD_IPCSUM 0x04000000 906 #define JME_TD_TSO 0x02000000 907 #define JME_TD_VLAN_TAG 0x01000000 908 #define JME_TD_VLAN_MASK 0x0000FFFF 909 910 #define JME_TD_MSS_MASK 0xFFFC0000 911 #define JME_TD_MSS_SHIFT 18 912 #define JME_TD_BUF_LEN_MASK 0x0000FFFF 913 #define JME_TD_BUF_LEN_SHIFT 0 914 915 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF 916 #define JME_TD_FRAME_LEN_SHIFT 0 917 918 /* 919 * Only the first Tx descriptor of a packet is updated 920 * after packet transmission. 921 */ 922 #define JME_TD_TMOUT 0x20000000 923 #define JME_TD_RETRY_EXP 0x10000000 924 #define JME_TD_COLLISION 0x08000000 925 #define JME_TD_UNDERRUN 0x04000000 926 #define JME_TD_EHDR_SIZE_MASK 0x000000FF 927 #define JME_TD_EHDR_SIZE_SHIFT 0 928 929 #define JME_TD_SEG_CNT_MASK 0xFFFF0000 930 #define JME_TD_SEG_CNT_SHIFT 16 931 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF 932 #define JME_TD_RETRY_CNT_SHIFT 0 933 934 #define JME_RD_OWN 0x80000000 935 #define JME_RD_INTR 0x40000000 936 #define JME_RD_64BIT 0x20000000 937 938 #define JME_RD_BUF_LEN_MASK 0x0000FFFF 939 #define JME_RD_BUF_LEN_SHIFT 0 940 941 /* 942 * Only the first Rx descriptor of a packet is updated 943 * after packet reception. 944 */ 945 #define JME_RD_MORE_FRAG 0x20000000 946 #define JME_RD_TCP 0x10000000 947 #define JME_RD_UDP 0x08000000 948 #define JME_RD_IPCSUM 0x04000000 949 #define JME_RD_TCPCSUM 0x02000000 950 #define JME_RD_UDPCSUM 0x01000000 951 #define JME_RD_VLAN_TAG 0x00800000 952 #define JME_RD_IPV4 0x00400000 953 #define JME_RD_IPV6 0x00200000 954 #define JME_RD_PAUSE 0x00100000 955 #define JME_RD_MAGIC 0x00080000 956 #define JME_RD_WAKEUP 0x00040000 957 #define JME_RD_BCAST 0x00030000 958 #define JME_RD_MCAST 0x00020000 959 #define JME_RD_UCAST 0x00010000 960 #define JME_RD_VLAN_MASK 0x0000FFFF 961 #define JME_RD_VLAN_SHIFT 0 962 963 #define JME_RD_VALID 0x80000000 964 #define JME_RD_CNT_MASK 0x7F000000 965 #define JME_RD_CNT_SHIFT 24 966 #define JME_RD_GIANT 0x00800000 967 #define JME_RD_GMII_ERR 0x00400000 968 #define JME_RD_NBL_RCVD 0x00200000 969 #define JME_RD_COLL 0x00100000 970 #define JME_RD_ABORT 0x00080000 971 #define JME_RD_RUNT 0x00040000 972 #define JME_RD_FIFO_OVRN 0x00020000 973 #define JME_RD_CRC_ERR 0x00010000 974 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF 975 976 #define JME_RX_ERR_STAT \ 977 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 978 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 979 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 980 981 #define JME_RD_ERR_MASK 0x00FF0000 982 #define JME_RD_ERR_SHIFT 16 983 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 984 #define JME_RX_ERR_BITS "\20" \ 985 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 986 "\5COLL\6NBLRCVD\7GMIIERR\10" 987 988 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 989 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 990 #define JME_RX_PAD_BYTES 10 991 992 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 993 994 #define JME_RD_RSS_HASH_MASK 0x00003F00 995 #define JME_RD_RSS_HASH_SHIFT 8 996 #define JME_RD_RSS_HASH_NONE 0x00000000 997 #define JME_RD_RSS_HASH_IPV4 0x00000100 998 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200 999 #define JME_RD_RSS_HASH_IPV6 0x00000400 1000 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1001 #define JME_RD_HASH_FN_NONE 0x00000000 1002 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1003 1004 #endif 1005