1 /* $OpenBSD: if_lii.c,v 1.47 2024/05/24 06:02:53 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2007 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Driver for Attansic/Atheros's L2 Fast Ethernet controller 31 */ 32 33 #include "bpfilter.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/socket.h> 40 #include <sys/device.h> 41 #include <sys/timeout.h> 42 43 #include <machine/bus.h> 44 45 #include <net/if.h> 46 #include <net/if_media.h> 47 48 #if NBPFILTER > 0 49 #include <net/bpf.h> 50 #endif 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <dev/mii/miivar.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcidevs.h> 60 61 #include <dev/pci/if_liireg.h> 62 63 /*#define LII_DEBUG*/ 64 #ifdef LII_DEBUG 65 #define DPRINTF(x) printf x 66 #else 67 #define DPRINTF(x) 68 #endif 69 70 struct lii_softc { 71 struct device sc_dev; 72 pci_chipset_tag_t sc_pc; 73 pcitag_t sc_tag; 74 75 bus_space_tag_t sc_mmiot; 76 bus_space_handle_t sc_mmioh; 77 bus_size_t sc_mmios; 78 79 /* 80 * We allocate a big chunk of DMA-safe memory for all data exchanges. 81 * It is unfortunate that this chip doesn't seem to do scatter-gather. 82 */ 83 bus_dma_tag_t sc_dmat; 84 bus_dmamap_t sc_ringmap; 85 bus_dma_segment_t sc_ringseg; 86 87 uint8_t *sc_ring; /* the whole area */ 88 size_t sc_ringsize; 89 90 struct rx_pkt *sc_rxp; /* the part used for RX */ 91 struct tx_pkt_status *sc_txs; /* the parts used for TX */ 92 bus_addr_t sc_txsp; 93 char *sc_txdbase; 94 bus_addr_t sc_txdp; 95 96 unsigned int sc_rxcur; 97 /* the active area is [ack; cur[ */ 98 int sc_txs_cur; 99 int sc_txs_ack; 100 int sc_txd_cur; 101 int sc_txd_ack; 102 int sc_free_tx_slots; 103 104 void *sc_ih; 105 106 struct arpcom sc_ac; 107 struct mii_data sc_mii; 108 struct timeout sc_tick; 109 110 int (*sc_memread)(struct lii_softc *, uint32_t, 111 uint32_t *); 112 }; 113 114 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 115 116 int lii_match(struct device *, void *, void *); 117 void lii_attach(struct device *, struct device *, void *); 118 int lii_activate(struct device *, int); 119 120 struct cfdriver lii_cd = { 121 0, 122 "lii", 123 DV_IFNET 124 }; 125 126 const struct cfattach lii_ca = { 127 sizeof(struct lii_softc), 128 lii_match, 129 lii_attach, 130 NULL, 131 lii_activate 132 }; 133 134 int lii_reset(struct lii_softc *); 135 int lii_eeprom_present(struct lii_softc *); 136 void lii_read_macaddr(struct lii_softc *, uint8_t *); 137 int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); 138 void lii_spi_configure(struct lii_softc *); 139 int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); 140 void lii_iff(struct lii_softc *); 141 void lii_tick(void *); 142 143 int lii_alloc_rings(struct lii_softc *); 144 int lii_free_tx_space(struct lii_softc *); 145 void lii_tx_put(struct lii_softc *, struct mbuf *); 146 147 int lii_mii_readreg(struct device *, int, int); 148 void lii_mii_writereg(struct device *, int, int, int); 149 void lii_mii_statchg(struct device *); 150 151 int lii_media_change(struct ifnet *); 152 void lii_media_status(struct ifnet *, struct ifmediareq *); 153 154 int lii_init(struct ifnet *); 155 void lii_start(struct ifnet *); 156 void lii_stop(struct ifnet *); 157 void lii_watchdog(struct ifnet *); 158 int lii_ioctl(struct ifnet *, u_long, caddr_t); 159 160 int lii_intr(void *); 161 void lii_rxintr(struct lii_softc *); 162 void lii_txintr(struct lii_softc *); 163 164 const struct pci_matchid lii_devices[] = { 165 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2 } 166 }; 167 168 #define LII_READ_4(sc,reg) \ 169 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 170 #define LII_READ_2(sc,reg) \ 171 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 172 #define LII_READ_1(sc,reg) \ 173 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 174 #define LII_WRITE_4(sc,reg,val) \ 175 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 176 #define LII_WRITE_2(sc,reg,val) \ 177 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 178 #define LII_WRITE_1(sc,reg,val) \ 179 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 180 181 /* 182 * Those are the default Linux parameters. 183 */ 184 185 #define AT_TXD_NUM 64 186 #define AT_TXD_BUFFER_SIZE 8192 187 #define AT_RXD_NUM 64 188 189 /* Pad the RXD buffer so that the packets are on a 128-byte boundary. */ 190 #define AT_RXD_PADDING 120 191 192 int 193 lii_match(struct device *parent, void *match, void *aux) 194 { 195 return (pci_matchbyid((struct pci_attach_args *)aux, lii_devices, 196 nitems(lii_devices))); 197 } 198 199 void 200 lii_attach(struct device *parent, struct device *self, void *aux) 201 { 202 struct lii_softc *sc = (struct lii_softc *)self; 203 struct pci_attach_args *pa = aux; 204 struct ifnet *ifp = &sc->sc_ac.ac_if; 205 pci_intr_handle_t ih; 206 pcireg_t memtype; 207 208 sc->sc_pc = pa->pa_pc; 209 sc->sc_tag = pa->pa_tag; 210 sc->sc_dmat = pa->pa_dmat; 211 212 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START); 213 if (pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &sc->sc_mmiot, 214 &sc->sc_mmioh, NULL, &sc->sc_mmios, 0)) { 215 printf(": can't map mem space\n"); 216 return; 217 } 218 219 if (lii_reset(sc)) 220 goto unmap; 221 222 lii_spi_configure(sc); 223 224 if (lii_eeprom_present(sc)) 225 sc->sc_memread = lii_eeprom_read; 226 else 227 sc->sc_memread = lii_spi_read; 228 229 lii_read_macaddr(sc, sc->sc_ac.ac_enaddr); 230 231 if (pci_intr_map(pa, &ih) != 0) { 232 printf(": can't map interrupt\n"); 233 goto unmap; 234 } 235 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, 236 lii_intr, sc, DEVNAME(sc)); 237 if (sc->sc_ih == NULL) { 238 printf(": can't establish interrupt\n"); 239 goto unmap; 240 } 241 242 if (lii_alloc_rings(sc)) 243 goto deintr; 244 245 printf(": %s, address %s\n", pci_intr_string(sc->sc_pc, ih), 246 ether_sprintf(sc->sc_ac.ac_enaddr)); 247 248 timeout_set(&sc->sc_tick, lii_tick, sc); 249 250 sc->sc_mii.mii_ifp = ifp; 251 sc->sc_mii.mii_readreg = lii_mii_readreg; 252 sc->sc_mii.mii_writereg = lii_mii_writereg; 253 sc->sc_mii.mii_statchg = lii_mii_statchg; 254 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, 255 lii_media_status); 256 mii_attach(self, &sc->sc_mii, 0xffffffff, 1, 257 MII_OFFSET_ANY, 0); 258 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 259 260 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 261 ifp->if_softc = sc; 262 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 263 ifp->if_capabilities = IFCAP_VLAN_MTU; 264 ifp->if_ioctl = lii_ioctl; 265 ifp->if_start = lii_start; 266 ifp->if_watchdog = lii_watchdog; 267 268 if_attach(ifp); 269 ether_ifattach(ifp); 270 271 return; 272 273 deintr: 274 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 275 unmap: 276 bus_space_unmap(sc->sc_mmiot, sc->sc_mmioh, sc->sc_mmios); 277 return; 278 } 279 280 int 281 lii_activate(struct device *self, int act) 282 { 283 struct lii_softc *sc = (struct lii_softc *)self; 284 struct ifnet *ifp = &sc->sc_ac.ac_if; 285 int rv = 0; 286 287 switch (act) { 288 case DVACT_SUSPEND: 289 if (ifp->if_flags & IFF_RUNNING) 290 lii_stop(ifp); 291 rv = config_activate_children(self, act); 292 break; 293 case DVACT_RESUME: 294 if (ifp->if_flags & IFF_UP) 295 lii_init(ifp); 296 break; 297 default: 298 rv = config_activate_children(self, act); 299 break; 300 } 301 return (rv); 302 } 303 304 int 305 lii_reset(struct lii_softc *sc) 306 { 307 int i; 308 309 DPRINTF(("lii_reset\n")); 310 311 LII_WRITE_4(sc, LII_SMC, SMC_SOFT_RST); 312 DELAY(1000); 313 314 for (i = 0; i < 10; ++i) { 315 if (LII_READ_4(sc, LII_BIS) == 0) 316 break; 317 DELAY(1000); 318 } 319 320 if (i == 10) { 321 printf("%s: reset failed\n", DEVNAME(sc)); 322 return 1; 323 } 324 325 LII_WRITE_4(sc, LII_PHYC, PHYC_ENABLE); 326 DELAY(10); 327 328 /* Init PCI-Express module */ 329 /* Magic Numbers Warning */ 330 LII_WRITE_4(sc, 0x12fc, 0x00006500); 331 LII_WRITE_4(sc, 0x1008, 0x00008000 | 332 LII_READ_4(sc, 0x1008)); 333 334 return 0; 335 } 336 337 int 338 lii_eeprom_present(struct lii_softc *sc) 339 { 340 uint32_t val; 341 342 val = LII_READ_4(sc, LII_SFC); 343 if (val & SFC_EN_VPD) 344 LII_WRITE_4(sc, LII_SFC, val & ~(SFC_EN_VPD)); 345 346 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, 347 NULL, NULL) == 1; 348 } 349 350 int 351 lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 352 { 353 return pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); 354 } 355 356 void 357 lii_spi_configure(struct lii_softc *sc) 358 { 359 /* 360 * We don't offer a way to configure the SPI Flash vendor parameter, so 361 * the table is given for reference 362 */ 363 static const struct lii_spi_flash_vendor { 364 const char *sfv_name; 365 const uint8_t sfv_opcodes[9]; 366 } lii_sfv[] = { 367 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, 368 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, 369 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, 370 }; 371 #define SF_OPCODE_WRSR 0 372 #define SF_OPCODE_READ 1 373 #define SF_OPCODE_PRGM 2 374 #define SF_OPCODE_WREN 3 375 #define SF_OPCODE_WRDI 4 376 #define SF_OPCODE_RDSR 5 377 #define SF_OPCODE_RDID 6 378 #define SF_OPCODE_SECT_ER 7 379 #define SF_OPCODE_CHIP_ER 8 380 381 #define SF_DEFAULT_VENDOR 0 382 static const uint8_t vendor = SF_DEFAULT_VENDOR; 383 384 /* 385 * Why isn't WRDI used? Heck if I know. 386 */ 387 388 LII_WRITE_1(sc, LII_SFOP_WRSR, 389 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); 390 LII_WRITE_1(sc, LII_SFOP_READ, 391 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); 392 LII_WRITE_1(sc, LII_SFOP_PROGRAM, 393 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); 394 LII_WRITE_1(sc, LII_SFOP_WREN, 395 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); 396 LII_WRITE_1(sc, LII_SFOP_RDSR, 397 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); 398 LII_WRITE_1(sc, LII_SFOP_RDID, 399 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); 400 LII_WRITE_1(sc, LII_SFOP_SC_ERASE, 401 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); 402 LII_WRITE_1(sc, LII_SFOP_CHIP_ERASE, 403 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); 404 } 405 406 #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ 407 ( (((cssetup) & SFC_CS_SETUP_MASK) \ 408 << SFC_CS_SETUP_SHIFT) \ 409 | (((clkhi) & SFC_CLK_HI_MASK) \ 410 << SFC_CLK_HI_SHIFT) \ 411 | (((clklo) & SFC_CLK_LO_MASK) \ 412 << SFC_CLK_LO_SHIFT) \ 413 | (((cshold) & SFC_CS_HOLD_MASK) \ 414 << SFC_CS_HOLD_SHIFT) \ 415 | (((cshi) & SFC_CS_HI_MASK) \ 416 << SFC_CS_HI_SHIFT) \ 417 | (((ins) & SFC_INS_MASK) \ 418 << SFC_INS_SHIFT)) 419 420 #define CUSTOM_SPI_CS_SETUP 2 421 #define CUSTOM_SPI_CLK_HI 2 422 #define CUSTOM_SPI_CLK_LO 2 423 #define CUSTOM_SPI_CS_HOLD 2 424 #define CUSTOM_SPI_CS_HI 3 425 426 int 427 lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 428 { 429 uint32_t v; 430 int i; 431 432 LII_WRITE_4(sc, LII_SF_DATA, 0); 433 LII_WRITE_4(sc, LII_SF_ADDR, reg); 434 435 v = SFC_WAIT_READY | 436 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, 437 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); 438 439 LII_WRITE_4(sc, LII_SFC, v); 440 v |= SFC_START; 441 LII_WRITE_4(sc, LII_SFC, v); 442 443 for (i = 0; i < 10; ++i) { 444 DELAY(1000); 445 if (!(LII_READ_4(sc, LII_SFC) & SFC_START)) 446 break; 447 } 448 if (i == 10) 449 return EBUSY; 450 451 *val = LII_READ_4(sc, LII_SF_DATA); 452 return 0; 453 } 454 455 void 456 lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) 457 { 458 uint32_t offset = 0x100; 459 uint32_t val, val1, addr0 = 0, addr1 = 0; 460 uint8_t found = 0; 461 462 while ((*sc->sc_memread)(sc, offset, &val) == 0) { 463 offset += 4; 464 465 /* Each chunk of data starts with a signature */ 466 if ((val & 0xff) != 0x5a) 467 break; 468 if ((*sc->sc_memread)(sc, offset, &val1)) 469 break; 470 471 offset += 4; 472 473 val >>= 16; 474 switch (val) { 475 case LII_MAC_ADDR_0: 476 addr0 = val1; 477 ++found; 478 break; 479 case LII_MAC_ADDR_1: 480 addr1 = val1; 481 ++found; 482 break; 483 default: 484 continue; 485 } 486 } 487 488 #ifdef LII_DEBUG 489 if (found < 2) 490 printf(": error reading MAC address, using registers...\n"); 491 #endif 492 493 addr0 = htole32(addr0); 494 addr1 = htole32(addr1); 495 496 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || 497 (addr0 == 0 && (addr1 & 0xffff) == 0)) { 498 addr0 = htole32(LII_READ_4(sc, LII_MAC_ADDR_0)); 499 addr1 = htole32(LII_READ_4(sc, LII_MAC_ADDR_1)); 500 } 501 502 ea[0] = (addr1 & 0x0000ff00) >> 8; 503 ea[1] = (addr1 & 0x000000ff); 504 ea[2] = (addr0 & 0xff000000) >> 24; 505 ea[3] = (addr0 & 0x00ff0000) >> 16; 506 ea[4] = (addr0 & 0x0000ff00) >> 8; 507 ea[5] = (addr0 & 0x000000ff); 508 } 509 510 int 511 lii_mii_readreg(struct device *dev, int phy, int reg) 512 { 513 struct lii_softc *sc = (struct lii_softc *)dev; 514 uint32_t val; 515 int i; 516 517 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 518 519 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 520 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 521 522 val |= MDIOC_READ; 523 524 LII_WRITE_4(sc, LII_MDIOC, val); 525 526 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 527 DELAY(2); 528 val = LII_READ_4(sc, LII_MDIOC); 529 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 530 break; 531 } 532 533 if (i == MDIO_WAIT_TIMES) { 534 printf("%s: timeout reading PHY %d reg %d\n", DEVNAME(sc), phy, 535 reg); 536 } 537 538 return (val & 0x0000ffff); 539 } 540 541 void 542 lii_mii_writereg(struct device *dev, int phy, int reg, int data) 543 { 544 struct lii_softc *sc = (struct lii_softc *)dev; 545 uint32_t val; 546 int i; 547 548 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 549 val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; 550 551 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 552 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 553 554 /* val |= MDIOC_WRITE; */ 555 556 LII_WRITE_4(sc, LII_MDIOC, val); 557 558 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 559 DELAY(2); 560 val = LII_READ_4(sc, LII_MDIOC); 561 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 562 break; 563 } 564 565 if (i == MDIO_WAIT_TIMES) { 566 printf("%s: timeout writing PHY %d reg %d\n", DEVNAME(sc), phy, 567 reg); 568 } 569 } 570 571 void 572 lii_mii_statchg(struct device *dev) 573 { 574 struct lii_softc *sc = (struct lii_softc *)dev; 575 uint32_t val; 576 577 DPRINTF(("lii_mii_statchg\n")); 578 579 val = LII_READ_4(sc, LII_MACC); 580 581 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 582 val |= MACC_FDX; 583 else 584 val &= ~MACC_FDX; 585 586 LII_WRITE_4(sc, LII_MACC, val); 587 } 588 589 int 590 lii_media_change(struct ifnet *ifp) 591 { 592 struct lii_softc *sc = ifp->if_softc; 593 594 DPRINTF(("lii_media_change\n")); 595 596 if (ifp->if_flags & IFF_UP) 597 mii_mediachg(&sc->sc_mii); 598 return 0; 599 } 600 601 void 602 lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) 603 { 604 struct lii_softc *sc = ifp->if_softc; 605 606 DPRINTF(("lii_media_status\n")); 607 608 mii_pollstat(&sc->sc_mii); 609 imr->ifm_status = sc->sc_mii.mii_media_status; 610 imr->ifm_active = sc->sc_mii.mii_media_active; 611 } 612 613 int 614 lii_init(struct ifnet *ifp) 615 { 616 struct lii_softc *sc = ifp->if_softc; 617 uint32_t val; 618 int error; 619 620 DPRINTF(("lii_init\n")); 621 622 lii_stop(ifp); 623 624 memset(sc->sc_ring, 0, sc->sc_ringsize); 625 626 /* Disable all interrupts */ 627 LII_WRITE_4(sc, LII_ISR, 0xffffffff); 628 629 LII_WRITE_4(sc, LII_DESC_BASE_ADDR_HI, 0); 630 /* XXX 631 sc->sc_ringmap->dm_segs[0].ds_addr >> 32); 632 */ 633 LII_WRITE_4(sc, LII_RXD_BASE_ADDR_LO, 634 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) 635 + AT_RXD_PADDING); 636 LII_WRITE_4(sc, LII_TXS_BASE_ADDR_LO, 637 sc->sc_txsp & 0xffffffff); 638 LII_WRITE_4(sc, LII_TXD_BASE_ADDR_LO, 639 sc->sc_txdp & 0xffffffff); 640 641 LII_WRITE_2(sc, LII_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); 642 LII_WRITE_2(sc, LII_TXS_NUM_ENTRIES, AT_TXD_NUM); 643 LII_WRITE_2(sc, LII_RXD_NUM_ENTRIES, AT_RXD_NUM); 644 645 /* 646 * Inter Packet Gap Time = 0x60 (IPGT) 647 * Minimum inter-frame gap for RX = 0x50 (MIFG) 648 * 64-bit Carrier-Sense window = 0x40 (IPGR1) 649 * 96-bit IPG window = 0x60 (IPGR2) 650 */ 651 LII_WRITE_4(sc, LII_MIPFG, 0x60405060); 652 653 /* 654 * Collision window = 0x37 (LCOL) 655 * Maximum # of retrans = 0xf (RETRY) 656 * Maximum binary expansion # = 0xa (ABEBT) 657 * IPG to start jam = 0x7 (JAMIPG) 658 */ 659 LII_WRITE_4(sc, LII_MHDC, 0x07a0f037 | 660 MHDC_EXC_DEF_EN); 661 662 /* 100 means 200us */ 663 LII_WRITE_2(sc, LII_IMTIV, 100); 664 LII_WRITE_2(sc, LII_SMC, SMC_ITIMER_EN); 665 666 /* 500000 means 100ms */ 667 LII_WRITE_2(sc, LII_IALTIV, 50000); 668 669 LII_WRITE_4(sc, LII_MTU, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 670 671 /* unit unknown for TX cur-through threshold */ 672 LII_WRITE_4(sc, LII_TX_CUT_THRESH, 0x177); 673 674 LII_WRITE_2(sc, LII_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); 675 LII_WRITE_2(sc, LII_PAUSE_OFF_TH, AT_RXD_NUM / 12); 676 677 sc->sc_rxcur = 0; 678 sc->sc_txs_cur = sc->sc_txs_ack = 0; 679 sc->sc_txd_cur = sc->sc_txd_ack = 0; 680 sc->sc_free_tx_slots = 1; 681 LII_WRITE_2(sc, LII_MB_TXD_WR_IDX, sc->sc_txd_cur); 682 LII_WRITE_2(sc, LII_MB_RXD_RD_IDX, sc->sc_rxcur); 683 684 LII_WRITE_1(sc, LII_DMAR, DMAR_EN); 685 LII_WRITE_1(sc, LII_DMAW, DMAW_EN); 686 687 LII_WRITE_4(sc, LII_SMC, LII_READ_4(sc, LII_SMC) | SMC_MANUAL_INT); 688 689 error = ((LII_READ_4(sc, LII_ISR) & ISR_PHY_LINKDOWN) != 0); 690 LII_WRITE_4(sc, LII_ISR, 0x3fffffff); 691 LII_WRITE_4(sc, LII_ISR, 0); 692 if (error) { 693 printf("%s: init failed\n", DEVNAME(sc)); 694 goto out; 695 } 696 697 /* 698 * Initialise MAC. 699 */ 700 val = LII_READ_4(sc, LII_MACC) & MACC_FDX; 701 702 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | 703 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | MACC_ADD_CRC | 704 MACC_PAD; 705 706 val |= 7 << MACC_PREAMBLE_LEN_SHIFT; 707 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; 708 709 LII_WRITE_4(sc, LII_MACC, val); 710 711 /* Set the hardware MAC address. */ 712 LII_WRITE_4(sc, LII_MAC_ADDR_0, letoh32((sc->sc_ac.ac_enaddr[2] << 24) | 713 (sc->sc_ac.ac_enaddr[3] << 16) | (sc->sc_ac.ac_enaddr[4] << 8) | 714 sc->sc_ac.ac_enaddr[5])); 715 LII_WRITE_4(sc, LII_MAC_ADDR_1, 716 letoh32((sc->sc_ac.ac_enaddr[0] << 8) | sc->sc_ac.ac_enaddr[1])); 717 718 /* Program promiscuous mode and multicast filters. */ 719 lii_iff(sc); 720 721 mii_mediachg(&sc->sc_mii); 722 723 LII_WRITE_4(sc, LII_IMR, IMR_NORMAL_MASK); 724 725 timeout_add_sec(&sc->sc_tick, 1); 726 727 ifp->if_flags |= IFF_RUNNING; 728 ifq_clr_oactive(&ifp->if_snd); 729 730 out: 731 return error; 732 } 733 734 void 735 lii_tx_put(struct lii_softc *sc, struct mbuf *m) 736 { 737 int left; 738 struct tx_pkt_header *tph = 739 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); 740 741 memset(tph, 0, sizeof *tph); 742 tph->txph_size = m->m_pkthdr.len; 743 744 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; 745 746 /* 747 * We already know we have enough space, so if there is a part of the 748 * space ahead of txd_cur that is active, it doesn't matter because 749 * left will be large enough even without it. 750 */ 751 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; 752 753 if (left > m->m_pkthdr.len) { 754 m_copydata(m, 0, m->m_pkthdr.len, 755 sc->sc_txdbase + sc->sc_txd_cur); 756 sc->sc_txd_cur += m->m_pkthdr.len; 757 } else { 758 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); 759 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); 760 sc->sc_txd_cur = m->m_pkthdr.len - left; 761 } 762 763 /* Round to a 32-bit boundary */ 764 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE; 765 if (sc->sc_txd_cur == sc->sc_txd_ack) 766 sc->sc_free_tx_slots = 0; 767 } 768 769 int 770 lii_free_tx_space(struct lii_softc *sc) 771 { 772 int space; 773 774 if (sc->sc_txd_cur >= sc->sc_txd_ack) 775 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + 776 sc->sc_txd_ack; 777 else 778 space = sc->sc_txd_ack - sc->sc_txd_cur; 779 780 /* Account for the tx_pkt_header */ 781 return (space - 4); 782 } 783 784 void 785 lii_start(struct ifnet *ifp) 786 { 787 struct lii_softc *sc = ifp->if_softc; 788 struct mbuf *m0; 789 790 DPRINTF(("lii_start\n")); 791 792 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 793 return; 794 795 for (;;) { 796 m0 = ifq_deq_begin(&ifp->if_snd); 797 if (m0 == NULL) 798 break; 799 800 if (!sc->sc_free_tx_slots || 801 lii_free_tx_space(sc) < m0->m_pkthdr.len) { 802 ifq_deq_rollback(&ifp->if_snd, m0); 803 ifq_set_oactive(&ifp->if_snd); 804 break; 805 } 806 807 lii_tx_put(sc, m0); 808 809 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur)); 810 811 sc->sc_txs[sc->sc_txs_cur].txps_update = 0; 812 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; 813 if (sc->sc_txs_cur == sc->sc_txs_ack) 814 sc->sc_free_tx_slots = 0; 815 816 LII_WRITE_2(sc, LII_MB_TXD_WR_IDX, sc->sc_txd_cur/4); 817 818 ifq_deq_commit(&ifp->if_snd, m0); 819 820 #if NBPFILTER > 0 821 if (ifp->if_bpf != NULL) 822 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 823 #endif 824 m_freem(m0); 825 } 826 } 827 828 void 829 lii_stop(struct ifnet *ifp) 830 { 831 struct lii_softc *sc = ifp->if_softc; 832 833 timeout_del(&sc->sc_tick); 834 835 ifp->if_timer = 0; 836 ifp->if_flags &= ~IFF_RUNNING; 837 ifq_clr_oactive(&ifp->if_snd); 838 839 mii_down(&sc->sc_mii); 840 841 lii_reset(sc); 842 843 LII_WRITE_4(sc, LII_IMR, 0); 844 } 845 846 int 847 lii_intr(void *v) 848 { 849 struct lii_softc *sc = v; 850 uint32_t status; 851 852 status = LII_READ_4(sc, LII_ISR); 853 if (status == 0) 854 return 0; 855 856 DPRINTF(("lii_intr (%x)\n", status)); 857 858 /* Clear the interrupt and disable them */ 859 LII_WRITE_4(sc, LII_ISR, status | ISR_DIS_INT); 860 861 if (status & (ISR_PHY | ISR_MANUAL)) { 862 /* Ack PHY interrupt. Magic register */ 863 if (status & ISR_PHY) 864 (void)lii_mii_readreg(&sc->sc_dev, 1, 19); 865 mii_mediachg(&sc->sc_mii); 866 } 867 868 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { 869 lii_init(&sc->sc_ac.ac_if); 870 return 1; 871 } 872 873 if (status & ISR_RX_EVENT) { 874 #ifdef LII_DEBUG 875 if (!(status & ISR_RS_UPDATE)) 876 printf("rxintr %08x\n", status); 877 #endif 878 lii_rxintr(sc); 879 } 880 881 if (status & ISR_TX_EVENT) 882 lii_txintr(sc); 883 884 /* Re-enable interrupts */ 885 LII_WRITE_4(sc, LII_ISR, 0); 886 887 return 1; 888 } 889 890 void 891 lii_rxintr(struct lii_softc *sc) 892 { 893 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 894 struct ifnet *ifp = &sc->sc_ac.ac_if; 895 struct rx_pkt *rxp; 896 struct mbuf *m; 897 uint16_t size; 898 899 DPRINTF(("lii_rxintr\n")); 900 901 for (;;) { 902 rxp = &sc->sc_rxp[sc->sc_rxcur]; 903 if (rxp->rxp_update == 0) 904 break; 905 906 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur, 907 rxp->rxp_size, rxp->rxp_flags)); 908 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; 909 rxp->rxp_update = 0; 910 if (!(rxp->rxp_flags & LII_RXF_SUCCESS)) { 911 ++ifp->if_ierrors; 912 continue; 913 } 914 915 MGETHDR(m, M_DONTWAIT, MT_DATA); 916 if (m == NULL) { 917 ++ifp->if_ierrors; 918 continue; 919 } 920 size = rxp->rxp_size - ETHER_CRC_LEN; 921 if (size > MHLEN) { 922 MCLGET(m, M_DONTWAIT); 923 if ((m->m_flags & M_EXT) == 0) { 924 m_freem(m); 925 ++ifp->if_ierrors; 926 continue; 927 } 928 } 929 930 /* Copy the packet without the FCS */ 931 m->m_pkthdr.len = m->m_len = size; 932 memcpy(mtod(m, void *), &rxp->rxp_data[0], size); 933 934 ml_enqueue(&ml, m); 935 } 936 937 if_input(ifp, &ml); 938 939 LII_WRITE_4(sc, LII_MB_RXD_RD_IDX, sc->sc_rxcur); 940 } 941 942 void 943 lii_txintr(struct lii_softc *sc) 944 { 945 struct ifnet *ifp = &sc->sc_ac.ac_if; 946 struct tx_pkt_status *txs; 947 struct tx_pkt_header *txph; 948 949 DPRINTF(("lii_txintr\n")); 950 951 for (;;) { 952 txs = &sc->sc_txs[sc->sc_txs_ack]; 953 if (txs->txps_update == 0) 954 break; 955 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack)); 956 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; 957 sc->sc_free_tx_slots = 1; 958 959 txs->txps_update = 0; 960 961 txph = (struct tx_pkt_header *) 962 (sc->sc_txdbase + sc->sc_txd_ack); 963 964 if (txph->txph_size != txs->txps_size) { 965 printf("%s: mismatched status and packet\n", 966 DEVNAME(sc)); 967 } 968 969 /* 970 * Move ack by the packet size, taking the packet header in 971 * account and round to the next 32-bit boundary 972 * (7 = sizeof(header) + 3) 973 */ 974 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; 975 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; 976 977 if (!ISSET(txs->txps_flags, LII_TXF_SUCCESS)) 978 ++ifp->if_oerrors; 979 ifq_clr_oactive(&ifp->if_snd); 980 } 981 982 if (sc->sc_free_tx_slots) 983 lii_start(ifp); 984 } 985 986 int 987 lii_alloc_rings(struct lii_softc *sc) 988 { 989 int nsegs; 990 bus_size_t bs; 991 992 /* 993 * We need a big chunk of DMA-friendly memory because descriptors 994 * are not separate from data on that crappy hardware, which means 995 * we'll have to copy data from and to that memory zone to and from 996 * the mbufs. 997 * 998 * How lame is that? Using the default values from the Linux driver, 999 * we allocate space for receiving up to 64 full-size Ethernet frames, 1000 * and only 8kb for transmitting up to 64 Ethernet frames. 1001 */ 1002 1003 sc->sc_ringsize = bs = AT_RXD_PADDING 1004 + AT_RXD_NUM * sizeof(struct rx_pkt) 1005 + AT_TXD_NUM * sizeof(struct tx_pkt_status) 1006 + AT_TXD_BUFFER_SIZE; 1007 1008 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), 1009 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { 1010 printf(": failed to create DMA map\n"); 1011 return 1; 1012 } 1013 1014 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), 1015 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { 1016 printf(": failed to allocate DMA memory\n"); 1017 goto destroy; 1018 } 1019 1020 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, 1021 (caddr_t *)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { 1022 printf(": failed to map DMA memory\n"); 1023 goto free; 1024 } 1025 1026 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, 1027 bs, NULL, BUS_DMA_NOWAIT) != 0) { 1028 printf(": failed to load DMA memory\n"); 1029 goto unmap; 1030 } 1031 1032 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); 1033 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING 1034 + AT_RXD_NUM * sizeof(struct rx_pkt)); 1035 sc->sc_txdbase = ((char *)sc->sc_txs) 1036 + AT_TXD_NUM * sizeof(struct tx_pkt_status); 1037 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr 1038 + ((char *)sc->sc_txs - (char *)sc->sc_ring); 1039 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr 1040 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); 1041 1042 return 0; 1043 1044 unmap: 1045 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); 1046 free: 1047 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); 1048 destroy: 1049 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); 1050 return 1; 1051 } 1052 1053 void 1054 lii_watchdog(struct ifnet *ifp) 1055 { 1056 struct lii_softc *sc = ifp->if_softc; 1057 1058 printf("%s: watchdog timeout\n", DEVNAME(sc)); 1059 ++ifp->if_oerrors; 1060 lii_init(ifp); 1061 } 1062 1063 int 1064 lii_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr) 1065 { 1066 struct lii_softc *sc = ifp->if_softc; 1067 struct ifreq *ifr = (struct ifreq *)addr; 1068 int s, error = 0; 1069 1070 s = splnet(); 1071 1072 switch(cmd) { 1073 case SIOCSIFADDR: 1074 SET(ifp->if_flags, IFF_UP); 1075 /* FALLTHROUGH */ 1076 1077 case SIOCSIFFLAGS: 1078 if (ISSET(ifp->if_flags, IFF_UP)) { 1079 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1080 error = ENETRESET; 1081 else 1082 lii_init(ifp); 1083 } else { 1084 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1085 lii_stop(ifp); 1086 } 1087 break; 1088 1089 case SIOCSIFMEDIA: 1090 case SIOCGIFMEDIA: 1091 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1092 break; 1093 1094 default: 1095 error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr); 1096 } 1097 1098 if (error == ENETRESET) { 1099 if (ifp->if_flags & IFF_RUNNING) 1100 lii_iff(sc); 1101 error = 0; 1102 } 1103 1104 splx(s); 1105 return error; 1106 } 1107 1108 void 1109 lii_iff(struct lii_softc *sc) 1110 { 1111 struct ifnet *ifp = &sc->sc_ac.ac_if; 1112 struct arpcom *ac = &sc->sc_ac; 1113 struct ether_multi *enm; 1114 struct ether_multistep step; 1115 uint32_t hashes[2]; 1116 uint32_t crc, val; 1117 1118 val = LII_READ_4(sc, LII_MACC); 1119 val &= ~(MACC_ALLMULTI_EN | MACC_BCAST_EN | MACC_PROMISC_EN); 1120 ifp->if_flags &= ~IFF_ALLMULTI; 1121 1122 /* 1123 * Always accept broadcast frames. 1124 */ 1125 val |= MACC_BCAST_EN; 1126 1127 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1128 ifp->if_flags |= IFF_ALLMULTI; 1129 if (ifp->if_flags & IFF_PROMISC) 1130 val |= MACC_PROMISC_EN; 1131 else 1132 val |= MACC_ALLMULTI_EN; 1133 hashes[0] = hashes[1] = 0xFFFFFFFF; 1134 } else { 1135 /* Program new filter. */ 1136 bzero(hashes, sizeof(hashes)); 1137 1138 ETHER_FIRST_MULTI(step, ac, enm); 1139 while (enm != NULL) { 1140 crc = ether_crc32_be(enm->enm_addrlo, 1141 ETHER_ADDR_LEN); 1142 1143 hashes[((crc >> 31) & 0x1)] |= 1144 (1 << ((crc >> 26) & 0x1f)); 1145 1146 ETHER_NEXT_MULTI(step, enm); 1147 } 1148 } 1149 1150 LII_WRITE_4(sc, LII_MHT, hashes[0]); 1151 LII_WRITE_4(sc, LII_MHT + 4, hashes[1]); 1152 LII_WRITE_4(sc, LII_MACC, val); 1153 } 1154 1155 void 1156 lii_tick(void *v) 1157 { 1158 struct lii_softc *sc = v; 1159 int s; 1160 1161 s = splnet(); 1162 mii_tick(&sc->sc_mii); 1163 splx(s); 1164 1165 timeout_add_sec(&sc->sc_tick, 1); 1166 } 1167