1 /* $OpenBSD: if_msk.c,v 1.136 2020/12/12 11:48:53 jan Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include "bpfilter.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/timeout.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <net/if.h> 103 104 #include <netinet/in.h> 105 #include <netinet/if_ether.h> 106 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/pci/if_skreg.h> 121 #include <dev/pci/if_mskvar.h> 122 123 int mskc_probe(struct device *, void *, void *); 124 void mskc_attach(struct device *, struct device *self, void *aux); 125 int mskc_detach(struct device *, int); 126 int mskc_activate(struct device *, int); 127 void mskc_reset(struct sk_softc *); 128 int msk_probe(struct device *, void *, void *); 129 void msk_attach(struct device *, struct device *self, void *aux); 130 int msk_detach(struct device *, int); 131 int msk_activate(struct device *, int); 132 void msk_reset(struct sk_if_softc *); 133 int mskcprint(void *, const char *); 134 int msk_intr(void *); 135 void msk_intr_yukon(struct sk_if_softc *); 136 static inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 137 void msk_rxeof(struct sk_if_softc *, struct mbuf_list *, uint16_t, uint32_t); 138 void msk_txeof(struct sk_if_softc *); 139 static unsigned int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t); 140 void msk_start(struct ifnet *); 141 int msk_ioctl(struct ifnet *, u_long, caddr_t); 142 void msk_init(void *); 143 void msk_init_yukon(struct sk_if_softc *); 144 void msk_stop(struct sk_if_softc *, int); 145 void msk_watchdog(struct ifnet *); 146 int msk_ifmedia_upd(struct ifnet *); 147 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148 static int msk_newbuf(struct sk_if_softc *); 149 int msk_init_rx_ring(struct sk_if_softc *); 150 int msk_init_tx_ring(struct sk_if_softc *); 151 void msk_fill_rx_ring(struct sk_if_softc *); 152 153 int msk_miibus_readreg(struct device *, int, int); 154 void msk_miibus_writereg(struct device *, int, int, int); 155 void msk_miibus_statchg(struct device *); 156 157 void msk_iff(struct sk_if_softc *); 158 void msk_tick(void *); 159 void msk_fill_rx_tick(void *); 160 161 #ifdef MSK_DEBUG 162 #define DPRINTF(x) if (mskdebug) printf x 163 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 164 int mskdebug = 0; 165 166 void msk_dump_txdesc(struct msk_tx_desc *, int); 167 void msk_dump_mbuf(struct mbuf *); 168 void msk_dump_bytes(const char *, int); 169 #else 170 #define DPRINTF(x) 171 #define DPRINTFN(n,x) 172 #endif 173 174 /* supported device vendors */ 175 const struct pci_matchid mskc_devices[] = { 176 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 177 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 178 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 179 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021CU }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8021X }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022CU }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8022X }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 200 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 201 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061CU }, 202 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8061X }, 203 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062CU }, 204 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8062X }, 205 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 206 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 207 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 208 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 209 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 210 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 211 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 212 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 213 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 214 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 215 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9EXX }, 216 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9SXX } 217 }; 218 219 static inline u_int32_t 220 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 221 { 222 return CSR_READ_4(sc, reg); 223 } 224 225 static inline u_int16_t 226 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 227 { 228 return CSR_READ_2(sc, reg); 229 } 230 231 static inline u_int8_t 232 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 233 { 234 return CSR_READ_1(sc, reg); 235 } 236 237 static inline void 238 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 239 { 240 CSR_WRITE_4(sc, reg, x); 241 } 242 243 static inline void 244 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 245 { 246 CSR_WRITE_2(sc, reg, x); 247 } 248 249 static inline void 250 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 251 { 252 CSR_WRITE_1(sc, reg, x); 253 } 254 255 int 256 msk_miibus_readreg(struct device *dev, int phy, int reg) 257 { 258 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 259 u_int16_t val; 260 int i; 261 262 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 263 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 264 265 for (i = 0; i < SK_TIMEOUT; i++) { 266 DELAY(1); 267 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 268 if (val & YU_SMICR_READ_VALID) 269 break; 270 } 271 272 if (i == SK_TIMEOUT) { 273 printf("%s: phy failed to come ready\n", 274 sc_if->sk_dev.dv_xname); 275 return (0); 276 } 277 278 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 279 SK_TIMEOUT)); 280 281 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 282 283 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 284 phy, reg, val)); 285 286 return (val); 287 } 288 289 void 290 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 291 { 292 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 293 int i; 294 295 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 296 phy, reg, val)); 297 298 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 299 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 300 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 301 302 for (i = 0; i < SK_TIMEOUT; i++) { 303 DELAY(1); 304 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 305 break; 306 } 307 308 if (i == SK_TIMEOUT) 309 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 310 } 311 312 void 313 msk_miibus_statchg(struct device *dev) 314 { 315 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 316 struct mii_data *mii = &sc_if->sk_mii; 317 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 318 int gpcr; 319 320 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 321 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 322 323 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 324 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 325 /* Set speed. */ 326 gpcr |= YU_GPCR_SPEED_DIS; 327 switch (IFM_SUBTYPE(mii->mii_media_active)) { 328 case IFM_1000_SX: 329 case IFM_1000_LX: 330 case IFM_1000_CX: 331 case IFM_1000_T: 332 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 333 break; 334 case IFM_100_TX: 335 gpcr |= YU_GPCR_SPEED; 336 break; 337 } 338 339 /* Set duplex. */ 340 gpcr |= YU_GPCR_DPLX_DIS; 341 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 342 gpcr |= YU_GPCR_DUPLEX; 343 344 /* Disable flow control. */ 345 gpcr |= YU_GPCR_FCTL_DIS; 346 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 347 } 348 349 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 350 351 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 352 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 353 } 354 355 void 356 msk_iff(struct sk_if_softc *sc_if) 357 { 358 struct ifnet *ifp = &sc_if->arpcom.ac_if; 359 struct arpcom *ac = &sc_if->arpcom; 360 struct ether_multi *enm; 361 struct ether_multistep step; 362 u_int32_t hashes[2]; 363 u_int16_t rcr; 364 int h; 365 366 rcr = SK_YU_READ_2(sc_if, YUKON_RCR); 367 rcr &= ~(YU_RCR_MUFLEN | YU_RCR_UFLEN); 368 ifp->if_flags &= ~IFF_ALLMULTI; 369 370 /* 371 * Always accept frames destined to our station address. 372 */ 373 rcr |= YU_RCR_UFLEN; 374 375 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 376 ifp->if_flags |= IFF_ALLMULTI; 377 if (ifp->if_flags & IFF_PROMISC) 378 rcr &= ~YU_RCR_UFLEN; 379 else 380 rcr |= YU_RCR_MUFLEN; 381 hashes[0] = hashes[1] = 0xFFFFFFFF; 382 } else { 383 rcr |= YU_RCR_MUFLEN; 384 /* Program new filter. */ 385 bzero(hashes, sizeof(hashes)); 386 387 ETHER_FIRST_MULTI(step, ac, enm); 388 while (enm != NULL) { 389 h = ether_crc32_be(enm->enm_addrlo, 390 ETHER_ADDR_LEN) & ((1 << SK_HASH_BITS) - 1); 391 392 if (h < 32) 393 hashes[0] |= (1 << h); 394 else 395 hashes[1] |= (1 << (h - 32)); 396 397 ETHER_NEXT_MULTI(step, enm); 398 } 399 } 400 401 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 402 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 403 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 404 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 405 SK_YU_WRITE_2(sc_if, YUKON_RCR, rcr); 406 } 407 408 int 409 msk_init_rx_ring(struct sk_if_softc *sc_if) 410 { 411 struct msk_ring_data *rd = sc_if->sk_rdata; 412 struct msk_rx_desc *r; 413 414 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 415 416 r = &rd->sk_rx_ring[0]; 417 r->sk_addr = htole32(0); 418 r->sk_opcode = SK_Y2_RXOPC_OWN | SK_Y2_RXOPC_ADDR64; 419 420 sc_if->sk_cdata.sk_rx_prod = 1; 421 sc_if->sk_cdata.sk_rx_cons = 0; 422 sc_if->sk_cdata.sk_rx_hiaddr = 0; 423 424 /* 425 * up to two ring entries per packet, so the effective ring size is 426 * halved 427 */ 428 if_rxr_init(&sc_if->sk_cdata.sk_rx_ring, 2, (MSK_RX_RING_CNT/2) - 1); 429 430 msk_fill_rx_ring(sc_if); 431 return (0); 432 } 433 434 int 435 msk_init_tx_ring(struct sk_if_softc *sc_if) 436 { 437 struct sk_softc *sc = sc_if->sk_softc; 438 struct msk_ring_data *rd = sc_if->sk_rdata; 439 struct msk_tx_desc *t; 440 int i; 441 442 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 443 444 for (i = 0; i < MSK_TX_RING_CNT; i++) { 445 if (bus_dmamap_create(sc->sc_dmatag, sc_if->sk_pktlen, 446 SK_NTXSEG, sc_if->sk_pktlen, 0, 447 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 448 &sc_if->sk_cdata.sk_tx_maps[i])) 449 return (ENOBUFS); 450 } 451 452 t = &rd->sk_tx_ring[0]; 453 t->sk_addr = htole32(0); 454 t->sk_opcode = SK_Y2_TXOPC_OWN | SK_Y2_TXOPC_ADDR64; 455 456 sc_if->sk_cdata.sk_tx_prod = 1; 457 sc_if->sk_cdata.sk_tx_cons = 0; 458 sc_if->sk_cdata.sk_tx_hiaddr = 0; 459 460 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, BUS_DMASYNC_PREWRITE); 461 462 return (0); 463 } 464 465 static int 466 msk_newbuf(struct sk_if_softc *sc_if) 467 { 468 struct msk_ring_data *rd = sc_if->sk_rdata; 469 struct msk_rx_desc *r; 470 struct mbuf *m; 471 bus_dmamap_t map; 472 uint64_t addr; 473 uint32_t prod, head; 474 uint32_t hiaddr; 475 unsigned int pktlen = sc_if->sk_pktlen + ETHER_ALIGN; 476 477 m = MCLGETL(NULL, M_DONTWAIT, pktlen); 478 if (m == NULL) 479 return (0); 480 m->m_len = m->m_pkthdr.len = pktlen; 481 m_adj(m, ETHER_ALIGN); 482 483 prod = sc_if->sk_cdata.sk_rx_prod; 484 map = sc_if->sk_cdata.sk_rx_maps[prod]; 485 486 if (bus_dmamap_load_mbuf(sc_if->sk_softc->sc_dmatag, map, m, 487 BUS_DMA_READ|BUS_DMA_NOWAIT) != 0) { 488 m_freem(m); 489 return (0); 490 } 491 492 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, map, 0, 493 map->dm_mapsize, BUS_DMASYNC_PREREAD); 494 495 head = prod; 496 497 /* high 32 bits of address */ 498 addr = map->dm_segs[0].ds_addr; 499 hiaddr = addr >> 32; 500 if (sc_if->sk_cdata.sk_rx_hiaddr != hiaddr) { 501 r = &rd->sk_rx_ring[prod]; 502 htolem32(&r->sk_addr, hiaddr); 503 r->sk_len = htole16(0); 504 r->sk_ctl = 0; 505 r->sk_opcode = SK_Y2_RXOPC_OWN | SK_Y2_RXOPC_ADDR64; 506 507 sc_if->sk_cdata.sk_rx_hiaddr = hiaddr; 508 509 SK_INC(prod, MSK_RX_RING_CNT); 510 } 511 512 r = &rd->sk_rx_ring[prod]; 513 htolem32(&r->sk_addr, addr); 514 htolem16(&r->sk_len, map->dm_segs[0].ds_len); 515 r->sk_ctl = 0; 516 r->sk_opcode = SK_Y2_RXOPC_OWN | SK_Y2_RXOPC_PACKET; 517 518 sc_if->sk_cdata.sk_rx_maps[head] = sc_if->sk_cdata.sk_rx_maps[prod]; 519 sc_if->sk_cdata.sk_rx_maps[prod] = map; 520 521 sc_if->sk_cdata.sk_rx_mbuf[prod] = m; 522 523 SK_INC(prod, MSK_RX_RING_CNT); 524 sc_if->sk_cdata.sk_rx_prod = prod; 525 526 return (1); 527 } 528 529 /* 530 * Set media options. 531 */ 532 int 533 msk_ifmedia_upd(struct ifnet *ifp) 534 { 535 struct sk_if_softc *sc_if = ifp->if_softc; 536 537 mii_mediachg(&sc_if->sk_mii); 538 return (0); 539 } 540 541 /* 542 * Report current media status. 543 */ 544 void 545 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 546 { 547 struct sk_if_softc *sc_if = ifp->if_softc; 548 549 mii_pollstat(&sc_if->sk_mii); 550 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 551 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 552 } 553 554 int 555 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 556 { 557 struct sk_if_softc *sc_if = ifp->if_softc; 558 struct ifreq *ifr = (struct ifreq *) data; 559 struct mii_data *mii; 560 int s, error = 0; 561 562 s = splnet(); 563 564 switch(command) { 565 case SIOCSIFADDR: 566 ifp->if_flags |= IFF_UP; 567 if (!(ifp->if_flags & IFF_RUNNING)) 568 msk_init(sc_if); 569 break; 570 571 case SIOCSIFFLAGS: 572 if (ifp->if_flags & IFF_UP) { 573 if (ifp->if_flags & IFF_RUNNING) 574 error = ENETRESET; 575 else 576 msk_init(sc_if); 577 } else { 578 if (ifp->if_flags & IFF_RUNNING) 579 msk_stop(sc_if, 0); 580 } 581 break; 582 583 case SIOCGIFMEDIA: 584 case SIOCSIFMEDIA: 585 mii = &sc_if->sk_mii; 586 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 587 break; 588 589 case SIOCGIFRXR: 590 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 591 NULL, sc_if->sk_pktlen, &sc_if->sk_cdata.sk_rx_ring); 592 break; 593 594 default: 595 error = ether_ioctl(ifp, &sc_if->arpcom, command, data); 596 } 597 598 if (error == ENETRESET) { 599 if (ifp->if_flags & IFF_RUNNING) 600 msk_iff(sc_if); 601 error = 0; 602 } 603 604 splx(s); 605 return (error); 606 } 607 608 /* 609 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 610 * IDs against our list and return a device name if we find a match. 611 */ 612 int 613 mskc_probe(struct device *parent, void *match, void *aux) 614 { 615 return (pci_matchbyid((struct pci_attach_args *)aux, mskc_devices, 616 nitems(mskc_devices))); 617 } 618 619 /* 620 * Force the GEnesis into reset, then bring it out of reset. 621 */ 622 void 623 mskc_reset(struct sk_softc *sc) 624 { 625 u_int32_t imtimer_ticks, reg1; 626 int reg; 627 628 DPRINTFN(2, ("mskc_reset\n")); 629 630 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 631 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 632 633 DELAY(1000); 634 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 635 DELAY(2); 636 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 637 638 sk_win_write_1(sc, SK_TESTCTL1, 2); 639 640 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 641 sc->sk_type >= SK_YUKON_FE_P) { 642 /* enable all clocks. */ 643 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 644 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 645 reg1 &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 646 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 647 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 648 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 649 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), reg1); 650 651 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5)); 652 reg1 &= SK_Y2_REG5_TIM_VMAIN_AV_MASK; 653 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), reg1); 654 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_CFGREG1), 0); 655 656 /* 657 * Disable status race, workaround for Yukon EC Ultra & 658 * Yukon EX. 659 */ 660 reg1 = sk_win_read_4(sc, SK_GPIO); 661 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 662 sk_win_write_4(sc, SK_GPIO, reg1); 663 sk_win_read_4(sc, SK_GPIO); 664 } 665 666 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 667 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 668 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 669 else 670 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 671 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 672 673 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 674 sk_win_write_1(sc, SK_Y2_CLKGATE, 675 SK_Y2_CLKGATE_LINK1_GATE_DIS | 676 SK_Y2_CLKGATE_LINK2_GATE_DIS | 677 SK_Y2_CLKGATE_LINK1_CORE_DIS | 678 SK_Y2_CLKGATE_LINK2_CORE_DIS | 679 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 680 else 681 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 682 683 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 684 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 685 DELAY(1000); 686 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 687 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 688 689 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 690 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 691 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 692 } 693 694 sk_win_write_1(sc, SK_TESTCTL1, 1); 695 696 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 697 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 698 CSR_READ_2(sc, SK_LINK_CTRL))); 699 700 /* Disable ASF */ 701 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 702 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 703 704 /* Clear I2C IRQ noise */ 705 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 706 707 /* Disable hardware timer */ 708 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 709 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 710 711 /* Disable descriptor polling */ 712 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 713 714 /* Disable time stamps */ 715 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 716 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 717 718 /* Enable RAM interface */ 719 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 720 for (reg = SK_TO0;reg <= SK_TO11; reg++) 721 sk_win_write_1(sc, reg, 36); 722 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 723 for (reg = SK_TO0;reg <= SK_TO11; reg++) 724 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 725 726 /* 727 * Configure interrupt moderation. The moderation timer 728 * defers interrupts specified in the interrupt moderation 729 * timer mask based on the timeout specified in the interrupt 730 * moderation timer init register. Each bit in the timer 731 * register represents one tick, so to specify a timeout in 732 * microseconds, we have to multiply by the correct number of 733 * ticks-per-microsecond. 734 */ 735 switch (sc->sk_type) { 736 case SK_YUKON_EC: 737 case SK_YUKON_EC_U: 738 case SK_YUKON_EX: 739 case SK_YUKON_SUPR: 740 case SK_YUKON_ULTRA2: 741 case SK_YUKON_OPTIMA: 742 case SK_YUKON_PRM: 743 case SK_YUKON_OPTIMA2: 744 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 745 break; 746 case SK_YUKON_FE: 747 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 748 break; 749 case SK_YUKON_FE_P: 750 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 751 break; 752 case SK_YUKON_XL: 753 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 754 break; 755 default: 756 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 757 break; 758 } 759 760 /* Reset status ring. */ 761 bzero(sc->sk_status_ring, 762 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 763 sc->sk_status_idx = 0; 764 765 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 766 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 767 768 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 769 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 770 sc->sk_status_map->dm_segs[0].ds_addr); 771 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 772 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 773 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10); 774 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16); 775 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16); 776 777 #if 0 778 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 779 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 780 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(20)); 781 #else 782 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4)); 783 #endif 784 785 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 786 787 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 788 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 789 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 790 } 791 792 int 793 msk_probe(struct device *parent, void *match, void *aux) 794 { 795 struct skc_attach_args *sa = aux; 796 797 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 798 return (0); 799 800 switch (sa->skc_type) { 801 case SK_YUKON_XL: 802 case SK_YUKON_EC_U: 803 case SK_YUKON_EX: 804 case SK_YUKON_EC: 805 case SK_YUKON_FE: 806 case SK_YUKON_FE_P: 807 case SK_YUKON_SUPR: 808 case SK_YUKON_ULTRA2: 809 case SK_YUKON_OPTIMA: 810 case SK_YUKON_PRM: 811 case SK_YUKON_OPTIMA2: 812 return (1); 813 } 814 815 return (0); 816 } 817 818 void 819 msk_reset(struct sk_if_softc *sc_if) 820 { 821 /* GMAC and GPHY Reset */ 822 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 823 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 824 DELAY(1000); 825 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 826 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 827 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 828 } 829 830 /* 831 * Each XMAC chip is attached as a separate logical IP interface. 832 * Single port cards will have only one logical interface of course. 833 */ 834 void 835 msk_attach(struct device *parent, struct device *self, void *aux) 836 { 837 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 838 struct sk_softc *sc = (struct sk_softc *)parent; 839 struct skc_attach_args *sa = aux; 840 struct ifnet *ifp; 841 caddr_t kva; 842 int i; 843 u_int32_t chunk; 844 int mii_flags; 845 int error; 846 847 sc_if->sk_port = sa->skc_port; 848 sc_if->sk_softc = sc; 849 sc->sk_if[sa->skc_port] = sc_if; 850 851 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 852 853 /* 854 * Get station address for this interface. Note that 855 * dual port cards actually come with three station 856 * addresses: one for each port, plus an extra. The 857 * extra one is used by the SysKonnect driver software 858 * as a 'virtual' station address for when both ports 859 * are operating in failover mode. Currently we don't 860 * use this extra address. 861 */ 862 for (i = 0; i < ETHER_ADDR_LEN; i++) 863 sc_if->arpcom.ac_enaddr[i] = 864 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 865 866 printf(": address %s\n", 867 ether_sprintf(sc_if->arpcom.ac_enaddr)); 868 869 /* 870 * Set up RAM buffer addresses. The Yukon2 has a small amount 871 * of SRAM on it, somewhere between 4K and 48K. We need to 872 * divide this up between the transmitter and receiver. We 873 * give the receiver 2/3 of the memory (rounded down), and the 874 * transmitter whatever remains. 875 */ 876 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 877 sc_if->sk_rx_ramstart = 0; 878 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 879 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 880 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 881 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 882 883 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 884 " tx_ramstart=%#x tx_ramend=%#x\n", 885 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 886 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 887 888 /* Allocate the descriptor queues. */ 889 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 890 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 891 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 892 printf(": can't alloc rx buffers\n"); 893 goto fail; 894 } 895 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 896 sc_if->sk_ring_nseg, 897 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 898 printf(": can't map dma buffers (%lu bytes)\n", 899 (ulong)sizeof(struct msk_ring_data)); 900 goto fail_1; 901 } 902 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 903 sizeof(struct msk_ring_data), 0, 904 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 905 &sc_if->sk_ring_map)) { 906 printf(": can't create dma map\n"); 907 goto fail_2; 908 } 909 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 910 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 911 printf(": can't load dma map\n"); 912 goto fail_3; 913 } 914 sc_if->sk_rdata = (struct msk_ring_data *)kva; 915 916 if (sc->sk_type != SK_YUKON_FE && 917 sc->sk_type != SK_YUKON_FE_P) 918 sc_if->sk_pktlen = SK_JLEN; 919 else 920 sc_if->sk_pktlen = MCLBYTES; 921 922 for (i = 0; i < MSK_RX_RING_CNT; i++) { 923 if ((error = bus_dmamap_create(sc->sc_dmatag, 924 sc_if->sk_pktlen, 1, sc_if->sk_pktlen, 0, 925 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 926 &sc_if->sk_cdata.sk_rx_maps[i])) != 0) { 927 printf("\n%s: unable to create rx DMA map %d, " 928 "error = %d\n", sc->sk_dev.dv_xname, i, error); 929 goto fail_4; 930 } 931 } 932 933 ifp = &sc_if->arpcom.ac_if; 934 ifp->if_softc = sc_if; 935 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 936 ifp->if_ioctl = msk_ioctl; 937 ifp->if_start = msk_start; 938 ifp->if_watchdog = msk_watchdog; 939 if (sc->sk_type != SK_YUKON_FE && 940 sc->sk_type != SK_YUKON_FE_P) 941 ifp->if_hardmtu = SK_JUMBO_MTU; 942 ifq_set_maxlen(&ifp->if_snd, MSK_TX_RING_CNT - 1); 943 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 944 945 ifp->if_capabilities = IFCAP_VLAN_MTU; 946 947 msk_reset(sc_if); 948 949 /* 950 * Do miibus setup. 951 */ 952 msk_init_yukon(sc_if); 953 954 DPRINTFN(2, ("msk_attach: 1\n")); 955 956 sc_if->sk_mii.mii_ifp = ifp; 957 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 958 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 959 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 960 961 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 962 msk_ifmedia_upd, msk_ifmedia_sts); 963 mii_flags = MIIF_DOPAUSE; 964 if (sc->sk_fibertype) 965 mii_flags |= MIIF_HAVEFIBER; 966 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 967 MII_OFFSET_ANY, mii_flags); 968 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 969 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 970 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 971 0, NULL); 972 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 973 } else 974 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 975 976 timeout_set(&sc_if->sk_tick_ch, msk_tick, sc_if); 977 timeout_set(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 978 979 /* 980 * Call MI attach routines. 981 */ 982 if_attach(ifp); 983 ether_ifattach(ifp); 984 985 DPRINTFN(2, ("msk_attach: end\n")); 986 return; 987 988 fail_4: 989 for (i = 0; i < MSK_RX_RING_CNT; i++) { 990 if (sc_if->sk_cdata.sk_rx_maps[i] != NULL) 991 bus_dmamap_destroy(sc->sc_dmatag, 992 sc_if->sk_cdata.sk_rx_maps[i]); 993 } 994 995 fail_3: 996 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 997 fail_2: 998 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 999 fail_1: 1000 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1001 fail: 1002 sc->sk_if[sa->skc_port] = NULL; 1003 } 1004 1005 int 1006 msk_detach(struct device *self, int flags) 1007 { 1008 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1009 struct sk_softc *sc = sc_if->sk_softc; 1010 struct ifnet *ifp= &sc_if->arpcom.ac_if; 1011 1012 if (sc->sk_if[sc_if->sk_port] == NULL) 1013 return (0); 1014 1015 msk_stop(sc_if, 1); 1016 1017 /* Detach any PHYs we might have. */ 1018 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1019 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1020 1021 /* Delete any remaining media. */ 1022 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1023 1024 ether_ifdetach(ifp); 1025 if_detach(ifp); 1026 1027 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata, 1028 sizeof(struct msk_ring_data)); 1029 bus_dmamem_free(sc->sc_dmatag, 1030 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1031 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1032 sc->sk_if[sc_if->sk_port] = NULL; 1033 1034 return (0); 1035 } 1036 1037 int 1038 msk_activate(struct device *self, int act) 1039 { 1040 struct sk_if_softc *sc_if = (void *)self; 1041 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1042 int rv = 0; 1043 1044 switch (act) { 1045 case DVACT_RESUME: 1046 msk_reset(sc_if); 1047 if (ifp->if_flags & IFF_RUNNING) 1048 msk_init(sc_if); 1049 break; 1050 default: 1051 rv = config_activate_children(self, act); 1052 break; 1053 } 1054 return (rv); 1055 } 1056 1057 int 1058 mskcprint(void *aux, const char *pnp) 1059 { 1060 struct skc_attach_args *sa = aux; 1061 1062 if (pnp) 1063 printf("msk port %c at %s", 1064 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1065 else 1066 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1067 return (UNCONF); 1068 } 1069 1070 /* 1071 * Attach the interface. Allocate softc structures, do ifmedia 1072 * setup and ethernet/BPF attach. 1073 */ 1074 void 1075 mskc_attach(struct device *parent, struct device *self, void *aux) 1076 { 1077 struct sk_softc *sc = (struct sk_softc *)self; 1078 struct pci_attach_args *pa = aux; 1079 struct skc_attach_args skca; 1080 pci_chipset_tag_t pc = pa->pa_pc; 1081 pcireg_t memtype; 1082 pci_intr_handle_t ih; 1083 const char *intrstr = NULL; 1084 u_int8_t hw, pmd; 1085 char *revstr = NULL; 1086 caddr_t kva; 1087 1088 DPRINTFN(2, ("begin mskc_attach\n")); 1089 1090 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 1091 1092 /* 1093 * Map control/status registers. 1094 */ 1095 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1096 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1097 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) { 1098 printf(": can't map mem space\n"); 1099 return; 1100 } 1101 1102 sc->sc_dmatag = pa->pa_dmat; 1103 1104 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1105 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1106 1107 /* bail out here if chip is not recognized */ 1108 if (!(SK_IS_YUKON2(sc))) { 1109 printf(": unknown chip type: %d\n", sc->sk_type); 1110 goto fail_1; 1111 } 1112 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1113 1114 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_MARVELL) { 1115 switch (PCI_PRODUCT(pa->pa_id)) { 1116 case PCI_PRODUCT_MARVELL_YUKON_8036: 1117 case PCI_PRODUCT_MARVELL_YUKON_8053: 1118 pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 1119 } 1120 } 1121 1122 /* Allocate interrupt */ 1123 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 1124 printf(": couldn't map interrupt\n"); 1125 goto fail_1; 1126 } 1127 1128 intrstr = pci_intr_string(pc, ih); 1129 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc, 1130 self->dv_xname); 1131 if (sc->sk_intrhand == NULL) { 1132 printf(": couldn't establish interrupt"); 1133 if (intrstr != NULL) 1134 printf(" at %s", intrstr); 1135 printf("\n"); 1136 goto fail_1; 1137 } 1138 sc->sk_pc = pc; 1139 1140 if (bus_dmamem_alloc(sc->sc_dmatag, 1141 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1142 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1143 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, 1144 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 1145 printf(": can't alloc status buffers\n"); 1146 goto fail_2; 1147 } 1148 1149 if (bus_dmamem_map(sc->sc_dmatag, 1150 &sc->sk_status_seg, sc->sk_status_nseg, 1151 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1152 &kva, BUS_DMA_NOWAIT)) { 1153 printf(": can't map dma buffers (%lu bytes)\n", 1154 (ulong)(MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc))); 1155 goto fail_3; 1156 } 1157 if (bus_dmamap_create(sc->sc_dmatag, 1158 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1159 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1160 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 1161 &sc->sk_status_map)) { 1162 printf(": can't create dma map\n"); 1163 goto fail_4; 1164 } 1165 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1166 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1167 NULL, BUS_DMA_NOWAIT)) { 1168 printf(": can't load dma map\n"); 1169 goto fail_5; 1170 } 1171 sc->sk_status_ring = (struct msk_status_desc *)kva; 1172 1173 /* Reset the adapter. */ 1174 mskc_reset(sc); 1175 1176 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1177 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1178 1179 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1180 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1181 sc->sk_fibertype = 1; 1182 1183 switch (sc->sk_type) { 1184 case SK_YUKON_XL: 1185 sc->sk_name = "Yukon-2 XL"; 1186 break; 1187 case SK_YUKON_EC_U: 1188 sc->sk_name = "Yukon-2 EC Ultra"; 1189 break; 1190 case SK_YUKON_EX: 1191 sc->sk_name = "Yukon-2 Extreme"; 1192 break; 1193 case SK_YUKON_EC: 1194 sc->sk_name = "Yukon-2 EC"; 1195 break; 1196 case SK_YUKON_FE: 1197 sc->sk_name = "Yukon-2 FE"; 1198 break; 1199 case SK_YUKON_FE_P: 1200 sc->sk_name = "Yukon-2 FE+"; 1201 break; 1202 case SK_YUKON_SUPR: 1203 sc->sk_name = "Yukon-2 Supreme"; 1204 break; 1205 case SK_YUKON_ULTRA2: 1206 sc->sk_name = "Yukon-2 Ultra 2"; 1207 break; 1208 case SK_YUKON_OPTIMA: 1209 sc->sk_name = "Yukon-2 Optima"; 1210 break; 1211 case SK_YUKON_PRM: 1212 sc->sk_name = "Yukon-2 Optima Prime"; 1213 break; 1214 case SK_YUKON_OPTIMA2: 1215 sc->sk_name = "Yukon-2 Optima 2"; 1216 break; 1217 default: 1218 sc->sk_name = "Yukon (Unknown)"; 1219 } 1220 1221 if (sc->sk_type == SK_YUKON_XL) { 1222 switch (sc->sk_rev) { 1223 case SK_YUKON_XL_REV_A0: 1224 revstr = "A0"; 1225 break; 1226 case SK_YUKON_XL_REV_A1: 1227 revstr = "A1"; 1228 break; 1229 case SK_YUKON_XL_REV_A2: 1230 revstr = "A2"; 1231 break; 1232 case SK_YUKON_XL_REV_A3: 1233 revstr = "A3"; 1234 break; 1235 default: 1236 ; 1237 } 1238 } 1239 1240 if (sc->sk_type == SK_YUKON_EC) { 1241 switch (sc->sk_rev) { 1242 case SK_YUKON_EC_REV_A1: 1243 revstr = "A1"; 1244 break; 1245 case SK_YUKON_EC_REV_A2: 1246 revstr = "A2"; 1247 break; 1248 case SK_YUKON_EC_REV_A3: 1249 revstr = "A3"; 1250 break; 1251 default: 1252 ; 1253 } 1254 } 1255 1256 if (sc->sk_type == SK_YUKON_EC_U) { 1257 switch (sc->sk_rev) { 1258 case SK_YUKON_EC_U_REV_A0: 1259 revstr = "A0"; 1260 break; 1261 case SK_YUKON_EC_U_REV_A1: 1262 revstr = "A1"; 1263 break; 1264 case SK_YUKON_EC_U_REV_B0: 1265 revstr = "B0"; 1266 break; 1267 case SK_YUKON_EC_U_REV_B1: 1268 revstr = "B1"; 1269 break; 1270 default: 1271 ; 1272 } 1273 } 1274 1275 if (sc->sk_type == SK_YUKON_FE) { 1276 switch (sc->sk_rev) { 1277 case SK_YUKON_FE_REV_A1: 1278 revstr = "A1"; 1279 break; 1280 case SK_YUKON_FE_REV_A2: 1281 revstr = "A2"; 1282 break; 1283 default: 1284 ; 1285 } 1286 } 1287 1288 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1289 revstr = "A0"; 1290 1291 if (sc->sk_type == SK_YUKON_EX) { 1292 switch (sc->sk_rev) { 1293 case SK_YUKON_EX_REV_A0: 1294 revstr = "A0"; 1295 break; 1296 case SK_YUKON_EX_REV_B0: 1297 revstr = "B0"; 1298 break; 1299 default: 1300 ; 1301 } 1302 } 1303 1304 if (sc->sk_type == SK_YUKON_SUPR) { 1305 switch (sc->sk_rev) { 1306 case SK_YUKON_SUPR_REV_A0: 1307 revstr = "A0"; 1308 break; 1309 case SK_YUKON_SUPR_REV_B0: 1310 revstr = "B0"; 1311 break; 1312 case SK_YUKON_SUPR_REV_B1: 1313 revstr = "B1"; 1314 break; 1315 default: 1316 ; 1317 } 1318 } 1319 1320 if (sc->sk_type == SK_YUKON_PRM) { 1321 switch (sc->sk_rev) { 1322 case SK_YUKON_PRM_REV_Z1: 1323 revstr = "Z1"; 1324 break; 1325 case SK_YUKON_PRM_REV_A0: 1326 revstr = "A0"; 1327 break; 1328 default: 1329 ; 1330 } 1331 } 1332 1333 /* Announce the product name. */ 1334 printf(", %s", sc->sk_name); 1335 if (revstr != NULL) 1336 printf(" rev. %s", revstr); 1337 printf(" (0x%x): %s\n", sc->sk_rev, intrstr); 1338 1339 sc->sk_macs = 1; 1340 1341 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1342 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1343 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1344 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1345 sc->sk_macs++; 1346 } 1347 1348 skca.skc_port = SK_PORT_A; 1349 skca.skc_type = sc->sk_type; 1350 skca.skc_rev = sc->sk_rev; 1351 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1352 1353 if (sc->sk_macs > 1) { 1354 skca.skc_port = SK_PORT_B; 1355 skca.skc_type = sc->sk_type; 1356 skca.skc_rev = sc->sk_rev; 1357 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1358 } 1359 1360 /* Turn on the 'driver is loaded' LED. */ 1361 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1362 1363 return; 1364 1365 fail_4: 1366 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1367 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1368 fail_3: 1369 bus_dmamem_free(sc->sc_dmatag, 1370 &sc->sk_status_seg, sc->sk_status_nseg); 1371 sc->sk_status_nseg = 0; 1372 fail_5: 1373 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1374 fail_2: 1375 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1376 sc->sk_intrhand = NULL; 1377 fail_1: 1378 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1379 sc->sk_bsize = 0; 1380 } 1381 1382 int 1383 mskc_detach(struct device *self, int flags) 1384 { 1385 struct sk_softc *sc = (struct sk_softc *)self; 1386 int rv; 1387 1388 if (sc->sk_intrhand) 1389 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1390 1391 rv = config_detach_children(self, flags); 1392 if (rv != 0) 1393 return (rv); 1394 1395 if (sc->sk_status_nseg > 0) { 1396 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1397 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sk_status_ring, 1398 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1399 bus_dmamem_free(sc->sc_dmatag, 1400 &sc->sk_status_seg, sc->sk_status_nseg); 1401 } 1402 1403 if (sc->sk_bsize > 0) 1404 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1405 1406 return(0); 1407 } 1408 1409 int 1410 mskc_activate(struct device *self, int act) 1411 { 1412 struct sk_softc *sc = (void *)self; 1413 int rv = 0; 1414 1415 switch (act) { 1416 case DVACT_RESUME: 1417 mskc_reset(sc); 1418 rv = config_activate_children(self, act); 1419 break; 1420 default: 1421 rv = config_activate_children(self, act); 1422 break; 1423 } 1424 return (rv); 1425 } 1426 1427 static unsigned int 1428 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m, uint32_t prod) 1429 { 1430 struct sk_softc *sc = sc_if->sk_softc; 1431 struct msk_ring_data *rd = sc_if->sk_rdata; 1432 struct msk_tx_desc *t; 1433 bus_dmamap_t map; 1434 uint64_t addr; 1435 uint32_t hiaddr; 1436 uint32_t next, last; 1437 uint8_t opcode; 1438 unsigned int entries = 0; 1439 int i; 1440 1441 map = sc_if->sk_cdata.sk_tx_maps[prod]; 1442 1443 switch (bus_dmamap_load_mbuf(sc->sc_dmatag, map, m, 1444 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)) { 1445 case 0: 1446 break; 1447 case EFBIG: /* mbuf chain is too fragmented */ 1448 if (m_defrag(m, M_DONTWAIT) == 0 && 1449 bus_dmamap_load_mbuf(sc->sc_dmatag, map, m, 1450 BUS_DMA_STREAMING | BUS_DMA_NOWAIT) == 0) 1451 break; 1452 /* FALLTHROUGH */ 1453 default: 1454 return (0); 1455 } 1456 1457 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1458 BUS_DMASYNC_PREWRITE); 1459 1460 opcode = SK_Y2_TXOPC_OWN | SK_Y2_TXOPC_PACKET; 1461 next = prod; 1462 for (i = 0; i < map->dm_nsegs; i++) { 1463 /* high 32 bits of address */ 1464 addr = map->dm_segs[i].ds_addr; 1465 hiaddr = addr >> 32; 1466 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1467 t = &rd->sk_tx_ring[next]; 1468 htolem32(&t->sk_addr, hiaddr); 1469 t->sk_opcode = SK_Y2_TXOPC_OWN | SK_Y2_TXOPC_ADDR64; 1470 1471 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1472 1473 SK_INC(next, MSK_TX_RING_CNT); 1474 entries++; 1475 } 1476 1477 /* low 32 bits of address + length */ 1478 t = &rd->sk_tx_ring[next]; 1479 htolem32(&t->sk_addr, addr); 1480 htolem16(&t->sk_len, map->dm_segs[i].ds_len); 1481 t->sk_ctl = 0; 1482 t->sk_opcode = opcode; 1483 1484 last = next; 1485 SK_INC(next, MSK_TX_RING_CNT); 1486 entries++; 1487 1488 opcode = SK_Y2_TXOPC_OWN | SK_Y2_TXOPC_BUFFER; 1489 } 1490 t->sk_ctl = SK_Y2_TXCTL_LASTFRAG; 1491 1492 sc_if->sk_cdata.sk_tx_maps[prod] = sc_if->sk_cdata.sk_tx_maps[last]; 1493 sc_if->sk_cdata.sk_tx_maps[last] = map; 1494 sc_if->sk_cdata.sk_tx_mbuf[last] = m; 1495 1496 return (entries); 1497 } 1498 1499 void 1500 msk_start(struct ifnet *ifp) 1501 { 1502 struct sk_if_softc *sc_if = ifp->if_softc; 1503 struct mbuf *m = NULL; 1504 uint32_t prod, free, used; 1505 int post = 0; 1506 1507 prod = sc_if->sk_cdata.sk_tx_prod; 1508 free = sc_if->sk_cdata.sk_tx_cons; 1509 if (free <= prod) 1510 free += MSK_TX_RING_CNT; 1511 free -= prod; 1512 1513 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, BUS_DMASYNC_POSTWRITE); 1514 1515 for (;;) { 1516 if (free <= SK_NTXSEG * 2) { 1517 ifq_set_oactive(&ifp->if_snd); 1518 break; 1519 } 1520 1521 m = ifq_dequeue(&ifp->if_snd); 1522 if (m == NULL) 1523 break; 1524 1525 used = msk_encap(sc_if, m, prod); 1526 if (used == 0) { 1527 m_freem(m); 1528 continue; 1529 } 1530 1531 free -= used; 1532 prod += used; 1533 prod &= MSK_TX_RING_CNT - 1; 1534 1535 #if NBPFILTER > 0 1536 if (ifp->if_bpf) 1537 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1538 #endif 1539 post = 1; 1540 } 1541 1542 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, BUS_DMASYNC_PREWRITE); 1543 1544 if (post == 0) 1545 return; 1546 1547 /* Transmit */ 1548 sc_if->sk_cdata.sk_tx_prod = prod; 1549 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, prod); 1550 1551 /* Set a timeout in case the chip goes out to lunch. */ 1552 ifp->if_timer = MSK_TX_TIMEOUT; 1553 } 1554 1555 void 1556 msk_watchdog(struct ifnet *ifp) 1557 { 1558 struct sk_if_softc *sc_if = ifp->if_softc; 1559 1560 /* 1561 * Reclaim first as there is a possibility of losing Tx completion 1562 * interrupts. 1563 */ 1564 msk_txeof(sc_if); 1565 if (sc_if->sk_cdata.sk_tx_prod != sc_if->sk_cdata.sk_tx_cons) { 1566 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1567 1568 ifp->if_oerrors++; 1569 1570 /* XXX Resets both ports; we shouldn't do that. */ 1571 mskc_reset(sc_if->sk_softc); 1572 msk_reset(sc_if); 1573 msk_init(sc_if); 1574 } 1575 } 1576 1577 static inline int 1578 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1579 { 1580 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1581 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1582 YU_RXSTAT_JABBER)) != 0 || 1583 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1584 YU_RXSTAT_BYTES(stat) != len) 1585 return (0); 1586 1587 return (1); 1588 } 1589 1590 void 1591 msk_rxeof(struct sk_if_softc *sc_if, struct mbuf_list *ml, 1592 uint16_t len, uint32_t rxstat) 1593 { 1594 struct sk_softc *sc = sc_if->sk_softc; 1595 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1596 struct mbuf *m = NULL; 1597 int prod, cons, tail; 1598 bus_dmamap_t map; 1599 1600 prod = sc_if->sk_cdata.sk_rx_prod; 1601 cons = sc_if->sk_cdata.sk_rx_cons; 1602 1603 while (cons != prod) { 1604 tail = cons; 1605 SK_INC(cons, MSK_RX_RING_CNT); 1606 1607 m = sc_if->sk_cdata.sk_rx_mbuf[tail]; 1608 if (m != NULL) { 1609 /* found it */ 1610 break; 1611 } 1612 } 1613 sc_if->sk_cdata.sk_rx_cons = cons; 1614 1615 if (m == NULL) { 1616 /* maybe if ADDR64 is consumed? */ 1617 return; 1618 } 1619 1620 sc_if->sk_cdata.sk_rx_mbuf[tail] = NULL; 1621 1622 map = sc_if->sk_cdata.sk_rx_maps[tail]; 1623 if_rxr_put(&sc_if->sk_cdata.sk_rx_ring, 1); 1624 1625 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, map, 0, map->dm_mapsize, 1626 BUS_DMASYNC_POSTREAD); 1627 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, map); 1628 1629 if (len < SK_MIN_FRAMELEN || len > SK_JUMBO_FRAMELEN || 1630 msk_rxvalid(sc, rxstat, len) == 0) { 1631 ifp->if_ierrors++; 1632 m_freem(m); 1633 return; 1634 } 1635 1636 m->m_pkthdr.len = m->m_len = len; 1637 1638 ml_enqueue(ml, m); 1639 } 1640 1641 void 1642 msk_txeof(struct sk_if_softc *sc_if) 1643 { 1644 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1645 struct sk_softc *sc = sc_if->sk_softc; 1646 uint32_t prod, cons; 1647 struct mbuf *m; 1648 bus_dmamap_t map; 1649 bus_size_t reg; 1650 1651 if (sc_if->sk_port == SK_PORT_A) 1652 reg = SK_STAT_BMU_TXA1_RIDX; 1653 else 1654 reg = SK_STAT_BMU_TXA2_RIDX; 1655 1656 /* 1657 * Go through our tx ring and free mbufs for those 1658 * frames that have been sent. 1659 */ 1660 cons = sc_if->sk_cdata.sk_tx_cons; 1661 prod = sk_win_read_2(sc, reg); 1662 1663 if (cons == prod) 1664 return; 1665 1666 while (cons != prod) { 1667 m = sc_if->sk_cdata.sk_tx_mbuf[cons]; 1668 if (m != NULL) { 1669 sc_if->sk_cdata.sk_tx_mbuf[cons] = NULL; 1670 1671 map = sc_if->sk_cdata.sk_tx_maps[cons]; 1672 bus_dmamap_sync(sc->sc_dmatag, map, 0, 1673 map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1674 bus_dmamap_unload(sc->sc_dmatag, map); 1675 1676 m_freem(m); 1677 } 1678 1679 SK_INC(cons, MSK_TX_RING_CNT); 1680 } 1681 if (cons == sc_if->sk_cdata.sk_tx_prod) 1682 ifp->if_timer = 0; 1683 1684 sc_if->sk_cdata.sk_tx_cons = cons; 1685 1686 if (ifq_is_oactive(&ifp->if_snd)) 1687 ifq_restart(&ifp->if_snd); 1688 } 1689 1690 void 1691 msk_fill_rx_ring(struct sk_if_softc *sc_if) 1692 { 1693 u_int slots, used; 1694 1695 slots = if_rxr_get(&sc_if->sk_cdata.sk_rx_ring, MSK_RX_RING_CNT/2); 1696 1697 MSK_CDRXSYNC(sc_if, 0, BUS_DMASYNC_POSTWRITE); /* XXX */ 1698 while (slots > 0) { 1699 used = msk_newbuf(sc_if); 1700 if (used == 0) 1701 break; 1702 1703 slots -= used; 1704 } 1705 MSK_CDRXSYNC(sc_if, 0, BUS_DMASYNC_PREWRITE); /* XXX */ 1706 1707 if_rxr_put(&sc_if->sk_cdata.sk_rx_ring, slots); 1708 if (if_rxr_inuse(&sc_if->sk_cdata.sk_rx_ring) == 0) 1709 timeout_add(&sc_if->sk_tick_rx, 1); 1710 } 1711 1712 void 1713 msk_fill_rx_tick(void *xsc_if) 1714 { 1715 struct sk_if_softc *sc_if = xsc_if; 1716 int s; 1717 1718 s = splnet(); 1719 if (if_rxr_inuse(&sc_if->sk_cdata.sk_rx_ring) == 0) { 1720 msk_fill_rx_ring(sc_if); 1721 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1722 sc_if->sk_cdata.sk_rx_prod); 1723 } 1724 splx(s); 1725 } 1726 1727 void 1728 msk_tick(void *xsc_if) 1729 { 1730 struct sk_if_softc *sc_if = xsc_if; 1731 struct mii_data *mii = &sc_if->sk_mii; 1732 int s; 1733 1734 s = splnet(); 1735 mii_tick(mii); 1736 splx(s); 1737 timeout_add_sec(&sc_if->sk_tick_ch, 1); 1738 } 1739 1740 void 1741 msk_intr_yukon(struct sk_if_softc *sc_if) 1742 { 1743 u_int8_t status; 1744 1745 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1746 /* RX overrun */ 1747 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1748 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1749 SK_RFCTL_RX_FIFO_OVER); 1750 } 1751 /* TX underrun */ 1752 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1753 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1754 SK_TFCTL_TX_FIFO_UNDER); 1755 } 1756 1757 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1758 } 1759 1760 int 1761 msk_intr(void *xsc) 1762 { 1763 struct sk_softc *sc = xsc; 1764 struct sk_if_softc *sc_if; 1765 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1766 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1767 struct mbuf_list ml[2] = { 1768 MBUF_LIST_INITIALIZER(), 1769 MBUF_LIST_INITIALIZER(), 1770 }; 1771 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1772 int claimed = 0; 1773 u_int32_t status; 1774 struct msk_status_desc *cur_st; 1775 1776 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1777 if (status == 0xffffffff) 1778 return (0); 1779 if (status == 0) { 1780 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1781 return (0); 1782 } 1783 1784 status = CSR_READ_4(sc, SK_ISR); 1785 1786 if (sc_if0 != NULL) 1787 ifp0 = &sc_if0->arpcom.ac_if; 1788 if (sc_if1 != NULL) 1789 ifp1 = &sc_if1->arpcom.ac_if; 1790 1791 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1792 (ifp0->if_flags & IFF_RUNNING)) { 1793 msk_intr_yukon(sc_if0); 1794 } 1795 1796 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1797 (ifp1->if_flags & IFF_RUNNING)) { 1798 msk_intr_yukon(sc_if1); 1799 } 1800 1801 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1802 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1803 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1804 1805 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1806 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1807 switch (cur_st->sk_opcode) { 1808 case SK_Y2_STOPC_RXSTAT: 1809 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 1810 msk_rxeof(sc_if, &ml[cur_st->sk_link & 0x01], 1811 lemtoh16(&cur_st->sk_len), 1812 lemtoh32(&cur_st->sk_status)); 1813 break; 1814 case SK_Y2_STOPC_TXSTAT: 1815 if (sc_if0) 1816 msk_txeof(sc_if0); 1817 if (sc_if1) 1818 msk_txeof(sc_if1); 1819 break; 1820 default: 1821 printf("opcode=0x%x\n", cur_st->sk_opcode); 1822 break; 1823 } 1824 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1825 1826 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1827 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1828 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1829 } 1830 1831 if (status & SK_Y2_IMR_BMU) { 1832 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1833 claimed = 1; 1834 } 1835 1836 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1837 1838 if (!ml_empty(&ml[0])) { 1839 if (ifiq_input(&ifp0->if_rcv, &ml[0])) 1840 if_rxr_livelocked(&sc_if0->sk_cdata.sk_rx_ring); 1841 msk_fill_rx_ring(sc_if0); 1842 SK_IF_WRITE_2(sc_if0, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1843 sc_if0->sk_cdata.sk_rx_prod); 1844 } 1845 if (!ml_empty(&ml[1])) { 1846 if (ifiq_input(&ifp1->if_rcv, &ml[1])) 1847 if_rxr_livelocked(&sc_if1->sk_cdata.sk_rx_ring); 1848 msk_fill_rx_ring(sc_if1); 1849 SK_IF_WRITE_2(sc_if1, 0, SK_RXQ1_Y2_PREF_PUTIDX, 1850 sc_if1->sk_cdata.sk_rx_prod); 1851 } 1852 1853 return (claimed); 1854 } 1855 1856 void 1857 msk_init_yukon(struct sk_if_softc *sc_if) 1858 { 1859 u_int32_t v; 1860 u_int16_t reg; 1861 struct sk_softc *sc; 1862 int i; 1863 1864 sc = sc_if->sk_softc; 1865 1866 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1867 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1868 1869 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1870 1871 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1872 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1873 1874 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1875 1876 /* unused read of the interrupt source register */ 1877 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1878 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1879 1880 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1881 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1882 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1883 1884 /* MIB Counter Clear Mode set */ 1885 reg |= YU_PAR_MIB_CLR; 1886 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1887 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1888 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1889 1890 /* MIB Counter Clear Mode clear */ 1891 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1892 reg &= ~YU_PAR_MIB_CLR; 1893 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1894 1895 /* receive control reg */ 1896 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1897 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1898 1899 /* transmit parameter register */ 1900 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1901 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1902 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 1903 1904 /* serial mode register */ 1905 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1906 reg = YU_SMR_DATA_BLIND(0x1c) | 1907 YU_SMR_MFL_VLAN | 1908 YU_SMR_IPG_DATA(0x1e); 1909 1910 if (sc->sk_type != SK_YUKON_FE && 1911 sc->sk_type != SK_YUKON_FE_P) 1912 reg |= YU_SMR_MFL_JUMBO; 1913 1914 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 1915 1916 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1917 /* Setup Yukon's address */ 1918 for (i = 0; i < 3; i++) { 1919 /* Write Source Address 1 (unicast filter) */ 1920 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1921 sc_if->arpcom.ac_enaddr[i * 2] | 1922 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 1923 } 1924 1925 for (i = 0; i < 3; i++) { 1926 reg = sk_win_read_2(sc_if->sk_softc, 1927 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1928 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1929 } 1930 1931 /* Program promiscuous mode and multicast filters */ 1932 DPRINTFN(6, ("msk_init_yukon: 11\n")); 1933 msk_iff(sc_if); 1934 1935 /* enable interrupt mask for counter overflows */ 1936 DPRINTFN(6, ("msk_init_yukon: 12\n")); 1937 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 1938 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 1939 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 1940 1941 /* Configure RX MAC FIFO Flush Mask */ 1942 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 1943 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 1944 YU_RXSTAT_JABBER; 1945 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 1946 1947 /* Configure RX MAC FIFO */ 1948 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 1949 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 1950 SK_RFCTL_FIFO_FLUSH_ON); 1951 1952 /* Increase flush threshould to 64 bytes */ 1953 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 1954 SK_RFCTL_FIFO_THRESHOLD + 1); 1955 1956 /* Configure TX MAC FIFO */ 1957 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 1958 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 1959 1960 #if 1 1961 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 1962 #endif 1963 DPRINTFN(6, ("msk_init_yukon: end\n")); 1964 } 1965 1966 /* 1967 * Note that to properly initialize any part of the GEnesis chip, 1968 * you first have to take it out of reset mode. 1969 */ 1970 void 1971 msk_init(void *xsc_if) 1972 { 1973 struct sk_if_softc *sc_if = xsc_if; 1974 struct sk_softc *sc = sc_if->sk_softc; 1975 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1976 struct mii_data *mii = &sc_if->sk_mii; 1977 int s; 1978 1979 DPRINTFN(2, ("msk_init\n")); 1980 1981 s = splnet(); 1982 1983 /* Cancel pending I/O and free all RX/TX buffers. */ 1984 msk_stop(sc_if, 0); 1985 1986 /* Configure I2C registers */ 1987 1988 /* Configure XMAC(s) */ 1989 msk_init_yukon(sc_if); 1990 mii_mediachg(mii); 1991 1992 /* Configure transmit arbiter(s) */ 1993 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 1994 #if 0 1995 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1996 #endif 1997 1998 /* Configure RAMbuffers */ 1999 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2000 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2001 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2002 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2003 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2004 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2005 2006 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2007 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2008 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2009 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2010 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2011 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2012 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2013 2014 /* Configure BMUs */ 2015 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2016 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2017 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2018 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600); 2019 2020 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2021 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2022 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2023 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600); 2024 2025 /* Make sure the sync transmit queue is disabled. */ 2026 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2027 2028 /* Init descriptors */ 2029 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2030 printf("%s: initialization failed: no " 2031 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2032 msk_stop(sc_if, 0); 2033 splx(s); 2034 return; 2035 } 2036 2037 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2038 printf("%s: initialization failed: no " 2039 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2040 msk_stop(sc_if, 0); 2041 splx(s); 2042 return; 2043 } 2044 2045 /* Initialize prefetch engine. */ 2046 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2047 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2048 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2049 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2050 MSK_RX_RING_ADDR(sc_if, 0)); 2051 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2052 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2053 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2054 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2055 2056 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2057 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2058 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2059 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2060 MSK_TX_RING_ADDR(sc_if, 0)); 2061 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2062 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2063 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2064 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2065 2066 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2067 sc_if->sk_cdata.sk_rx_prod); 2068 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, 2069 sc_if->sk_cdata.sk_tx_prod); 2070 2071 /* Configure interrupt handling */ 2072 if (sc_if->sk_port == SK_PORT_A) 2073 sc->sk_intrmask |= SK_Y2_INTRS1; 2074 else 2075 sc->sk_intrmask |= SK_Y2_INTRS2; 2076 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2077 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2078 2079 ifp->if_flags |= IFF_RUNNING; 2080 ifq_clr_oactive(&ifp->if_snd); 2081 2082 timeout_add_sec(&sc_if->sk_tick_ch, 1); 2083 2084 splx(s); 2085 } 2086 2087 void 2088 msk_stop(struct sk_if_softc *sc_if, int softonly) 2089 { 2090 struct sk_softc *sc = sc_if->sk_softc; 2091 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2092 struct mbuf *m; 2093 bus_dmamap_t map; 2094 int i; 2095 2096 DPRINTFN(2, ("msk_stop\n")); 2097 2098 timeout_del(&sc_if->sk_tick_ch); 2099 timeout_del(&sc_if->sk_tick_rx); 2100 2101 ifp->if_flags &= ~IFF_RUNNING; 2102 ifq_clr_oactive(&ifp->if_snd); 2103 2104 /* Stop transfer of Tx descriptors */ 2105 2106 /* Stop transfer of Rx descriptors */ 2107 2108 if (!softonly) { 2109 /* Turn off various components of this interface. */ 2110 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2111 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2112 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2113 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2114 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2115 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2116 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2117 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2118 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2119 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2120 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2121 2122 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2123 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2124 2125 /* Disable interrupts */ 2126 if (sc_if->sk_port == SK_PORT_A) 2127 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2128 else 2129 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2130 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2131 } 2132 2133 /* Free RX and TX mbufs still in the queues. */ 2134 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2135 m = sc_if->sk_cdata.sk_rx_mbuf[i]; 2136 if (m == NULL) 2137 continue; 2138 2139 map = sc_if->sk_cdata.sk_rx_maps[i]; 2140 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 2141 BUS_DMASYNC_POSTREAD); 2142 bus_dmamap_unload(sc->sc_dmatag, map); 2143 2144 m_freem(m); 2145 2146 sc_if->sk_cdata.sk_rx_mbuf[i] = NULL; 2147 } 2148 2149 sc_if->sk_cdata.sk_rx_prod = 0; 2150 sc_if->sk_cdata.sk_rx_cons = 0; 2151 2152 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2153 m = sc_if->sk_cdata.sk_tx_mbuf[i]; 2154 if (m == NULL) 2155 continue; 2156 2157 map = sc_if->sk_cdata.sk_tx_maps[i]; 2158 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 2159 BUS_DMASYNC_POSTREAD); 2160 bus_dmamap_unload(sc->sc_dmatag, map); 2161 2162 m_freem(m); 2163 2164 sc_if->sk_cdata.sk_tx_mbuf[i] = NULL; 2165 } 2166 } 2167 2168 struct cfattach mskc_ca = { 2169 sizeof(struct sk_softc), mskc_probe, mskc_attach, mskc_detach, 2170 mskc_activate 2171 }; 2172 2173 struct cfdriver mskc_cd = { 2174 NULL, "mskc", DV_DULL 2175 }; 2176 2177 struct cfattach msk_ca = { 2178 sizeof(struct sk_if_softc), msk_probe, msk_attach, msk_detach, 2179 msk_activate 2180 }; 2181 2182 struct cfdriver msk_cd = { 2183 NULL, "msk", DV_IFNET 2184 }; 2185 2186 #ifdef MSK_DEBUG 2187 void 2188 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2189 { 2190 #define DESC_PRINT(X) \ 2191 if (X) \ 2192 printf("txdesc[%d]." #X "=%#x\n", \ 2193 idx, X); 2194 2195 DESC_PRINT(letoh32(le->sk_addr)); 2196 DESC_PRINT(letoh16(le->sk_len)); 2197 DESC_PRINT(le->sk_ctl); 2198 DESC_PRINT(le->sk_opcode); 2199 #undef DESC_PRINT 2200 } 2201 2202 void 2203 msk_dump_bytes(const char *data, int len) 2204 { 2205 int c, i, j; 2206 2207 for (i = 0; i < len; i += 16) { 2208 printf("%08x ", i); 2209 c = len - i; 2210 if (c > 16) c = 16; 2211 2212 for (j = 0; j < c; j++) { 2213 printf("%02x ", data[i + j] & 0xff); 2214 if ((j & 0xf) == 7 && j > 0) 2215 printf(" "); 2216 } 2217 2218 for (; j < 16; j++) 2219 printf(" "); 2220 printf(" "); 2221 2222 for (j = 0; j < c; j++) { 2223 int ch = data[i + j] & 0xff; 2224 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2225 } 2226 2227 printf("\n"); 2228 2229 if (c < 16) 2230 break; 2231 } 2232 } 2233 2234 void 2235 msk_dump_mbuf(struct mbuf *m) 2236 { 2237 int count = m->m_pkthdr.len; 2238 2239 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len); 2240 2241 while (count > 0 && m) { 2242 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", 2243 m, m->m_data, m->m_len); 2244 msk_dump_bytes(mtod(m, char *), m->m_len); 2245 2246 count -= m->m_len; 2247 m = m->m_next; 2248 } 2249 } 2250 #endif 2251