1 /* 2 * Copyright (c) 2022 Claudio Jeker <claudio@openbsd.org> 3 * Copyright (C) 2021 MediaTek Inc. 4 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* MCU WFDMA1 */ 20 #define MT_MCU_WFDMA1_BASE 0x3000 21 22 #define MT_MDP_BASE 0x820cd000 23 #define MT_MDP_DCR0 0x820cd000 24 #define MT_MDP_DCR0_DAMSDU_EN (1U << 15) 25 #define MT_MDP_DCR0_RX_HDR_TRANS_EN (1U << 19) 26 27 #define MT_MDP_DCR1 0x820cd004 28 #define MT_MDP_DCR1_MAX_RX_LEN_MASK 0x0000fff8 29 #define MT_MDP_DCR1_MAX_RX_LEN_SHIFT 3 30 31 /* TMAC: band 0 (0x21000), band 1 (0xa1000) */ 32 #define MT_BAND_BASE0 0x820f0000 33 #define MT_BAND_BASE1 0x820e0000 34 #define MT_BAND_OFF (MT_BAND_BASE0 - MT_BAND_BASE1) 35 #define MT_BAND_ADDR(_band, ofs) \ 36 (MT_BAND_BASE0 - (_band) * MT_BAND_OFF + (ofs)) 37 38 #define MT_TMAC_TCR0(_band) MT_BAND_ADDR(_band, 0x4000) 39 #define MT_TMAC_TCR0_TBTT_STOP_CTRL (1U << 25) 40 41 #define MT_TMAC_CDTR(_band) MT_BAND_ADDR(_band, 0x4090) 42 #define MT_TMAC_ODTR(_band) MT_BAND_ADDR(_band, 0x4094) 43 #define MT_TIMEOUT_VAL_PLCP 0x0000ffff 44 #define MT_TIMEOUT_VAL_CCA 0xffff0000 45 #define MT_TIMEOUT_CCK_DEF_VAL (231 | (41 << 16)) 46 #define MT_TIMEOUT_OFDM_DEF_VAL (60 | (28 << 16)) 47 48 #define MT_TMAC_ICR0(_band) MT_BAND_ADDR(_band, 0x40a4) 49 #define MT_IFS_EIFS_MASK 0x0000001f 50 #define MT_IFS_EIFS_DEF 360 51 #define MT_IFS_RIFS_MASK 0x00007c00 52 #define MT_IFS_RIFS_DEF (2 << 10) 53 #define MT_IFS_SIFS_MASK 0x007f0000 54 #define MT_IFS_SIFS_SHIFT 16 55 #define MT_IFS_SLOT_MASK 0x7f000000 56 #define MT_IFS_SLOT_SHIFT 24 57 58 #define MT_TMAC_CTCR0(_band) MT_BAND_ADDR(_band, 0x40f4) 59 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME 0x0000003f 60 #define MT_TMAC_CTCR0_INS_DDLMT_EN (1U << 17) 61 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN (1U << 18) 62 63 #define MT_TMAC_TRCR0(_band) MT_BAND_ADDR(_band, 0x409c) 64 #define MT_TMAC_TFCR0(_band) MT_BAND_ADDR(_band, 0x41e0) 65 66 #define MT_DMA_DCR0(_band) MT_BAND_ADDR(_band, 0x7000) 67 #define MT_DMA_DCR0_MAX_RX_LEN_MASK 0x0000fff8 68 #define MT_DMA_DCR0_MAX_RX_LEN_SHIFT 3 69 #define MT_DMA_DCR0_RXD_G5_EN (1U << 23) 70 71 /* MIB: band 0(0x24800), band 1(0xa4800) */ 72 #define MT_MIB_SCR1(_band) MT_BAND_ADDR(_band, 0xd004) 73 #define MT_MIB_TXDUR_EN 0x0100 74 #define MT_MIB_RXDUR_EN 0x0200 75 76 #define MT_MIB_SDR9(_band) MT_BAND_ADDR(_band, 0xd02c) 77 #define MT_MIB_SDR9_BUSY_MASK 0x00ffffff 78 79 #define MT_MIB_SDR36(_band) MT_BAND_ADDR(_band, 0xd054) 80 #define MT_MIB_SDR36_TXTIME_MASK 0x00ffffff 81 #define MT_MIB_SDR37(_band) MT_BAND_ADDR(_band, 0xd058) 82 #define MT_MIB_SDR37_RXTIME_MASK 0x00ffffff 83 84 #define MT_TX_AGG_CNT(_band, n) MT_BAND_ADDR(_band, 0xd7dc + ((n) << 2)) 85 #define MT_TX_AGG_CNT2(_band, n) MT_BAND_ADDR(_band, 0xd7ec + ((n) << 2)) 86 87 #define MT_WTBLON_TOP_BASE 0x820d4000 88 #define MT_WTBLON_TOP_WDUCR 0x820d4200 89 #define MT_WTBLON_TOP_WDUCR_GROUP 0x0007 90 91 #define MT_WTBL_UPDATE 0x820d4230 92 #define MT_WTBL_UPDATE_WLAN_IDX 0x000003ff 93 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR (1U << 12) 94 #define MT_WTBL_UPDATE_BUSY (1U << 31) 95 96 #define MT_WTBL_BASE 0x820d8000 97 #define MT_WTBL_LMAC_ID GENMASK(14, 8) 98 #define MT_WTBL_LMAC_DW GENMASK(7, 2) 99 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 100 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 101 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 102 103 /* AGG: band 0(0x20800), band 1(0xa0800) */ 104 #define MT_AGG_ACR0(_band) MT_BAND_ADDR(_band, 0x2084) 105 #define MT_AGG_ACR_CFEND_RATE_MASK 0x00001fff 106 #define MT7921_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 107 #define MT7921_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 108 #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) 109 110 /* RMAC: band 0 (0x21400), band 1 (0xa1400) */ 111 #define MT_WF_RFCR(_base) MT_BAND_ADDR(_base, 0x5000) 112 #define MT_WF_RFCR_DROP_STBC_MULTI 0x00000001 113 #define MT_WF_RFCR_DROP_FCSFAIL 0x00000002 114 #define MT_WF_RFCR_DROP_VERSION 0x00000008 115 #define MT_WF_RFCR_DROP_PROBEREQ 0x00000010 116 #define MT_WF_RFCR_DROP_MCAST 0x00000020 117 #define MT_WF_RFCR_DROP_BCAST 0x00000040 118 #define MT_WF_RFCR_DROP_MCAST_FILTERED 0x00000080 119 #define MT_WF_RFCR_DROP_A3_MAC 0x00000100 120 #define MT_WF_RFCR_DROP_A3_BSSID 0x00000200 121 #define MT_WF_RFCR_DROP_A2_BSSID 0x00000400 122 #define MT_WF_RFCR_DROP_OTHER_BEACON 0x00000800 123 #define MT_WF_RFCR_DROP_FRAME_REPORT 0x00001000 124 #define MT_WF_RFCR_DROP_CTL_RSV 0x00002000 125 #define MT_WF_RFCR_DROP_CTS 0x00004000 126 #define MT_WF_RFCR_DROP_RTS 0x00008000 127 #define MT_WF_RFCR_DROP_DUPLICATE 0x00010000 128 #define MT_WF_RFCR_DROP_OTHER_BSS 0x00020000 129 #define MT_WF_RFCR_DROP_OTHER_UC 0x00040000 130 #define MT_WF_RFCR_DROP_OTHER_TIM 0x00080000 131 #define MT_WF_RFCR_DROP_NDPA 0x00100000 132 #define MT_WF_RFCR_DROP_UNWANTED_CTL 0x00200000 133 134 #define MT_WF_RFCR1(_band) MT_BAND_ADDR(_band, 0x5004) 135 #define MT_WF_RFCR1_DROP_ACK (1U << 4) 136 #define MT_WF_RFCR1_DROP_BF_POLL (1U << 5) 137 #define MT_WF_RFCR1_DROP_BA (1U << 6) 138 #define MT_WF_RFCR1_DROP_CFEND (1U << 7) 139 #define MT_WF_RFCR1_DROP_CFACK (1U << 8) 140 141 #define MT_WF_RMAC_MIB_TIME0(_band) MT_BAND_ADDR(_band, 0x53c4) 142 #define MT_WF_RMAC_MIB_RXTIME_CLR (1U << 31) 143 #define MT_WF_RMAC_MIB_RXTIME_EN (1U << 30) 144 145 #define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_BAND_ADDR(_band, 0x53b8) 146 #define MT_MIB_OBSSTIME_MASK 0x00ffffff 147 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_BAND_ADDR(_band, 0x5380) 148 149 /* ARB: band 0(0x20c00), band 1(0xa0c00) */ 150 #define MT_ARB_SCR(_band) MT_BAND_ADDR(_band, 0x3080) 151 #define MT_ARB_SCR_TX_DISABLE (1U << 8) 152 #define MT_ARB_SCR_RX_DISABLE (1U << 9) 153 154 /* WFDMA0 */ 155 #define MT_WFDMA0_BASE 0xd4000 156 157 #define MT_WFDMA0_RST 0xd4100 158 #define MT_WFDMA0_RST_LOGIC_RST (1U << 4) 159 #define MT_WFDMA0_RST_DMASHDL_ALL_RST (1U << 5) 160 161 #define MT_MCU_CMD 0xd41f0 162 #define MT_MCU_CMD_WAKE_RX_PCIE (1U << 0) 163 #define MT_MCU_CMD_STOP_DMA_FW_RELOAD (1U << 1) 164 #define MT_MCU_CMD_STOP_DMA (1U << 2) 165 #define MT_MCU_CMD_RESET_DONE (1U << 3) 166 #define MT_MCU_CMD_RECOVERY_DONE (1U << 4) 167 #define MT_MCU_CMD_NORMAL_STATE (1U << 5) 168 #define MT_MCU_CMD_ERROR_MASK 0x003e 169 170 #define MT_MCU2HOST_SW_INT_ENA 0xd41f4 171 172 #define MT_WFDMA0_HOST_INT_STA 0xd4200 173 #define HOST_RX_DONE_INT_STS0 (1U << 0) /* Rx mcu */ 174 #define HOST_RX_DONE_INT_STS2 (1U << 2) /* Rx data */ 175 #define HOST_RX_DONE_INT_STS4 (1U << 22) /* Rx mcu after fw downloaded */ 176 #define HOST_TX_DONE_INT_STS16 (1U << 26) 177 #define HOST_TX_DONE_INT_STS17 (1U << 27) /* MCU tx done*/ 178 179 #define MT_WFDMA0_HOST_INT_ENA 0xd4204 180 #define HOST_RX_DONE_INT_ENA0 (1U << 0) 181 #define HOST_RX_DONE_INT_ENA1 (1U << 1) 182 #define HOST_RX_DONE_INT_ENA2 (1U << 2) 183 #define HOST_RX_DONE_INT_ENA3 (1U << 3) 184 #define HOST_TX_DONE_INT_ENA0 (1U << 4) 185 #define HOST_TX_DONE_INT_ENA1 (1U << 5) 186 #define HOST_TX_DONE_INT_ENA2 (1U << 6) 187 #define HOST_TX_DONE_INT_ENA3 (1U << 7) 188 #define HOST_TX_DONE_INT_ENA4 (1U << 8) 189 #define HOST_TX_DONE_INT_ENA5 (1U << 9) 190 #define HOST_TX_DONE_INT_ENA6 (1U << 10) 191 #define HOST_TX_DONE_INT_ENA7 (1U << 11) 192 #define HOST_TX_DONE_INT_ENA8 (1U << 12) 193 #define HOST_TX_DONE_INT_ENA9 (1U << 13) 194 #define HOST_TX_DONE_INT_ENA10 (1U << 14) 195 #define HOST_TX_DONE_INT_ENA11 (1U << 15) 196 #define HOST_TX_DONE_INT_ENA12 (1U << 16) 197 #define HOST_TX_DONE_INT_ENA13 (1U << 17) 198 #define HOST_TX_DONE_INT_ENA14 (1U << 18) 199 #define HOST_RX_COHERENT_EN (1U << 20) 200 #define HOST_TX_COHERENT_EN (1U << 21) 201 #define HOST_RX_DONE_INT_ENA4 (1U << 22) 202 #define HOST_RX_DONE_INT_ENA5 (1U << 23) 203 #define HOST_TX_DONE_INT_ENA16 (1U << 26) 204 #define HOST_TX_DONE_INT_ENA17 (1U << 27) 205 #define MCU2HOST_SW_INT_ENA (1U << 29) 206 #define HOST_TX_DONE_INT_ENA18 (1U << 30) 207 208 #define MT_PCIE_MAC_BASE 0x10000 209 #define MT_PCIE_MAC_INT_ENABLE 0x10188 210 #define MT_PCIE_MAC_PM 0x10194 211 #define MT_PCIE_MAC_PM_L0S_DIS (1U << 8) 212 213 /* WFDMA interrupt */ 214 #define MT_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA2 215 #define MT_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA0 216 #define MT_INT_RX_DONE_WM2 HOST_RX_DONE_INT_ENA4 217 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_DATA | \ 218 MT_INT_RX_DONE_WM | \ 219 MT_INT_RX_DONE_WM2) 220 221 #define MT_INT_TX_DONE_MCU_WM HOST_TX_DONE_INT_ENA17 222 #define MT_INT_TX_DONE_FWDL HOST_TX_DONE_INT_ENA16 223 #define MT_INT_TX_DONE_BAND0 HOST_TX_DONE_INT_ENA0 224 #define MT_INT_MCU_CMD MCU2HOST_SW_INT_ENA 225 #define MT_INT_TX0_TO_TX14 0x7fff0 226 227 #define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WM | \ 228 MT_INT_TX_DONE_FWDL) 229 230 #define MT_INT_TX_DONE_ALL (MT_INT_TX_DONE_MCU | \ 231 MT_INT_TX0_TO_TX14) 232 233 #define MT_WFDMA0_GLO_CFG 0xd4208 234 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN (1U << 0) 235 #define MT_WFDMA0_GLO_CFG_TX_DMA_BUSY (1U << 1) 236 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN (1U << 2) 237 #define MT_WFDMA0_GLO_CFG_RX_DMA_BUSY (1U << 3) 238 #define MT_WFDMA0_GLO_CFG_TX_WB_DDONE (1U << 6) 239 #define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN (1U << 12) 240 #define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN (1U << 15) 241 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 (1U << 21) 242 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO (1U << 27) 243 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO (1U << 28) 244 #define MT_WFDMA0_GLO_CFG_CLK_GAT_DIS (1U << 30) 245 246 #define MT_WFDMA0_RST_DTX_PTR 0xd420c 247 #define MT_WFDMA0_GLO_CFG_EXT0 0xd42b0 248 #define MT_WFDMA0_CSR_TX_DMASHDL_ENABLE (1U << 6) 249 #define MT_WFDMA0_PRI_DLY_INT_CFG0 0xd42f0 250 251 #define MT_WFDMA0_TX_RING0_EXT_CTRL 0xd4600 252 #define MT_WFDMA0_TX_RING1_EXT_CTRL 0xd4604 253 #define MT_WFDMA0_TX_RING2_EXT_CTRL 0xd4608 254 #define MT_WFDMA0_TX_RING3_EXT_CTRL 0xd460c 255 #define MT_WFDMA0_TX_RING4_EXT_CTRL 0xd4610 256 #define MT_WFDMA0_TX_RING5_EXT_CTRL 0xd4614 257 #define MT_WFDMA0_TX_RING6_EXT_CTRL 0xd4618 258 #define MT_WFDMA0_TX_RING16_EXT_CTRL 0xd4640 259 #define MT_WFDMA0_TX_RING17_EXT_CTRL 0xd4644 260 261 #define MT_WFDMA0_RX_RING0_EXT_CTRL 0xd4680 262 #define MT_WFDMA0_RX_RING1_EXT_CTRL 0xd4684 263 #define MT_WFDMA0_RX_RING2_EXT_CTRL 0xd4688 264 #define MT_WFDMA0_RX_RING3_EXT_CTRL 0xd468c 265 #define MT_WFDMA0_RX_RING4_EXT_CTRL 0xd4690 266 #define MT_WFDMA0_RX_RING5_EXT_CTRL 0xd4694 267 268 #define MT_TX_DATA_RING_BASE 0xd4300 269 #define MT_TX_FWDL_RING_BASE 0xd4400 270 #define MT_TX_MCU_RING_BASE 0xd4410 271 #define MT_RX_DATA_RING_BASE 0xd4520 272 #define MT_RX_MCU_RING_BASE 0xd4540 273 #define MT_RX_FWDL_RING_BASE 0xd4500 274 275 #define MT_PCIE_MAC_BASE 0x10000 276 #define MT_PCIE_MAC_INT_ENABLE 0x10188 277 278 #define MT_INFRA_CFG_BASE 0xfe000 279 #define MT_HIF_REMAP_L1 0xfe24c 280 #define MT_HIF_REMAP_L1_MASK 0x0000ffff 281 #define MT_HIF_REMAP_L1_GET_OFFSET(x) ((x) & 0xffff) 282 #define MT_HIF_REMAP_L1_GET_BASE(x) ((x >> 16) & 0xffff) 283 #define MT_HIF_REMAP_BASE_L1 0x40000 284 285 #define MT_SWDEF_BASE 0x41f200 286 #define MT_SWDEF_MODE 0x41f23c 287 #define MT_SWDEF_NORMAL_MODE 0 288 #define MT_SWDEF_ICAP_MODE 1 289 #define MT_SWDEF_SPECTRUM_MODE 2 290 291 #define MT_DMASHDL_SW_CONTROL 0xd6004 292 #define MT_DMASHDL_DMASHDL_BYPASS (1U << 28) 293 #define MT_DMASHDL_OPTIONAL 0xd6008 294 #define MT_DMASHDL_PAGE 0xd600c 295 #define MT_DMASHDL_REFILL 0xd6010 296 #define MT_DMASHDL_PKT_MAX_SIZE 0xd601c 297 #define MT_DMASHDL_PKT_MAX_SIZE_PLE 0x00000fff 298 #define MT_DMASHDL_PKT_MAX_SIZE_PSE 0x0fff0000 299 300 #define MT_CONN_ON_MISC 0x7c0600f0 301 #define MT_TOP_MISC2_FW_N9_RDY 0x3 302 303 #define MT_CONN_ON_LPCTL 0x7c060010 304 #define PCIE_LPCR_HOST_SET_OWN (1U << 0) 305 #define PCIE_LPCR_HOST_CLR_OWN (1U << 1) 306 #define PCIE_LPCR_HOST_OWN_SYNC (1U << 2) 307 308 #define MT_WFSYS_SW_RST_B 0x18000140 309 #define WFSYS_SW_RST_B (1U << 0) 310 #define WFSYS_SW_INIT_DONE (1U << 4) 311 312 #define MT_TOP_BASE 0x18060000 313 #define MT_TOP_LPCR_HOST_BAND0 0x18060010 314 #define MT_TOP_LPCR_HOST_FW_OWN 0x0001 315 #define MT_TOP_LPCR_HOST_DRV_OWN 0x0002 316 317 #define MT_MCU_WPDMA0_BASE 0x54000000 318 #define MT_WFDMA_DUMMY_CR 0x54000120 319 #define MT_WFDMA_NEED_REINIT (1U << 1) 320 321 #define MT_HW_CHIPID 0x70010200 322 #define MT_HW_REV 0x70010204 323 324 #define MT_DMA_DESC_BASE 0 325 #define MT_DMA_RING_SIZE 4 326 #define MT_DMA_CPU_IDX 8 327 #define MT_DMA_DMA_IDX 12 328 329 #define MT_DMA_CTL_SD_LEN_MASK 0x00003fff 330 #define MT_DMA_CTL_SD_LEN0_SHIFT 16 331 #define MT_DMA_CTL_LAST_SEC1 (1U << 14) 332 #define MT_DMA_CTL_BURST (1U << 15) 333 #define MT_DMA_CTL_LAST_SEC0 (1U << 30) 334 #define MT_DMA_CTL_DMA_DONE (1U << 31) 335 #define MT_DMA_CTL_SD_LEN1(x) ((x) & MT_DMA_CTL_SD_LEN_MASK) 336 #define MT_DMA_CTL_SD_LEN0(x) \ 337 (((x) & MT_DMA_CTL_SD_LEN_MASK) << MT_DMA_CTL_SD_LEN0_SHIFT) 338 #define MT_DMA_CTL_SD_GET_LEN1(c) ((c) & MT_DMA_CTL_SD_LEN_MASK) 339 #define MT_DNA_CTL_SD_GET_LEN0(c) \ 340 (((c) >> MT_DMA_CTL_SD_LEN0_SHIFT) & MT_DMA_CTL_SD_LEN_MASK) 341 342 #define MT7921_MCU_INIT_RETRY_COUNT 10 343 344 enum mt76_txq_id { 345 MT_TXQ_VO, 346 MT_TXQ_VI, 347 MT_TXQ_BE, 348 MT_TXQ_BK, 349 MT_TXQ_PSD, 350 MT_TXQ_BEACON, 351 MT_TXQ_CAB, 352 __MT_TXQ_MAX 353 }; 354 355 enum mt76_mcuq_id { 356 MT_MCUQ_WM, 357 MT_MCUQ_WA, 358 MT_MCUQ_FWDL, 359 __MT_MCUQ_MAX 360 }; 361 362 enum mt76_rxq_id { 363 MT_RXQ_MAIN, 364 MT_RXQ_MCU, 365 MT_RXQ_MCU_WA, 366 MT_RXQ_BAND1, 367 MT_RXQ_BAND1_WA, 368 __MT_RXQ_MAX 369 }; 370 371 #define MT7921_MAX_INTERFACES 4 372 #define MT7921_MAX_WMM_SETS 4 373 #define MT7921_WTBL_SIZE 20 374 #define MT7921_WTBL_RESERVED (MT7921_WTBL_SIZE - 1) 375 #define MT7921_WTBL_STA (MT7921_WTBL_RESERVED - MT7921_MAX_INTERFACES) 376 377 #define MT_RX_BUF_SIZE 2048 378 #define MT_MAX_SCATTER 4 /* limit of MT_HW_TXP_MAX_BUF_NUM */ 379 #define MT_MAX_SIZE MT_DMA_CTL_SD_LEN_MASK 380 381 #define MWX_WCID_MAX 288 382 #define MWX_TXWI_MAX 512 /* HW limit is 8192 */ 383 384 #define MT_PACKET_ID_MASK 0x7f 385 #define MT_PACKET_ID_NO_ACK 0 386 #define MT_PACKET_ID_NO_SKB 1 387 #define MT_PACKET_ID_WED 2 388 #define MT_PACKET_ID_FIRST 3 389 #define MT_PACKET_ID_HAS_RATE (1U << 7) 390 391 struct mt76_desc { 392 volatile uint32_t buf0; 393 volatile uint32_t ctrl; 394 volatile uint32_t buf1; 395 volatile uint32_t info; 396 } __packed __aligned(4); 397 398 struct mt76_connac_txp_ptr { 399 uint32_t buf0; 400 uint16_t len0; 401 uint16_t len1; 402 uint32_t buf1; 403 } __packed __aligned(4); 404 405 #define MT_HW_TXP_MAX_MSDU_NUM 4 406 #define MT_HW_TXP_MAX_BUF_NUM 4 407 #define MT_TXD_SIZE (8 * sizeof(uint32_t)) 408 409 #define MT_TXD_LEN_LAST (1U << 15) 410 #define MT_TXD_LEN_MASK 0x00000fff 411 412 #define MT_MSDU_ID_VALID (1U << 15) 413 414 struct mt76_txwi { 415 uint32_t txwi[8]; 416 417 uint16_t msdu_id[MT_HW_TXP_MAX_MSDU_NUM]; 418 struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2]; 419 } __packed __aligned(4); 420 421 #define MCU_Q_QUERY 0 422 #define MCU_Q_SET 1 423 #define MCU_Q_RESERVED 2 424 #define MCU_Q_NA 3 425 426 #define CMD_S2D_IDX_H2N 0 427 #define CMD_S2D_IDX_C2N 1 428 #define CMD_S2D_IDX_H2C 2 429 #define CMD_S2D_IDX_H2N_AND_H2C 3 430 431 #define MCU_CMD_ACK 0x01 432 #define MCU_CMD_UNI 0x02 433 #define MCU_CMD_QUERY 0x04 434 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | MCU_CMD_QUERY) 435 436 #define MCU_CMD_FIELD_ID_MASK 0x000000ff 437 #define MCU_CMD_FIELD_EXT_ID_MASK 0x0000ff00 438 439 #define MCU_CMD_FIELD_QUERY (1U << 16) 440 #define MCU_CMD_FIELD_UNI (1U << 17) 441 #define MCU_CMD_FIELD_CE (1U << 18) 442 #define MCU_CMD_FIELD_WA (1U << 19) 443 444 #define MCU_CMD_TARGET_ADDRESS_LEN_REQ 0x00000001 445 #define MCU_CMD_FW_START_REQ 0x00000002 446 #define MCU_CMD_INIT_ACCESS_REG 0x00000003 447 #define MCU_CMD_NIC_POWER_CTRL 0x00000004 448 #define MCU_CMD_PATCH_START_REQ 0x00000005 449 #define MCU_CMD_PATCH_FINISH_REQ 0x00000007 450 #define MCU_CMD_PATCH_SEM_CONTROL 0x00000010 451 #define MCU_CMD_WA_PARAM 0x000000c4 452 #define MCU_CMD_EXT_CID 0x000000ed 453 #define MCU_CMD_FW_SCATTER 0x000000ee 454 #define MCU_CMD_RESTART_DL_REQ 0x000000ef 455 456 /* MCU_EXT_CMD use MCU_CMD_EXT_CID as FIELD_ID plus FIELD_EXT_ID */ 457 #define MCU_EXT_CMD_EFUSE_ACCESS 0x000001ed 458 #define MCU_EXT_CMD_RF_REG_ACCESS 0x000002ed 459 #define MCU_EXT_CMD_RF_TEST 0x000004ed 460 #define MCU_EXT_CMD_PM_STATE_CTRL 0x000007ed 461 #define MCU_EXT_CMD_CHANNEL_SWITCH 0x000008ed 462 #define MCU_EXT_CMD_SET_TX_POWER_CTRL 0x000011ed 463 #define MCU_EXT_CMD_FW_LOG_2_HOST 0x000013ed 464 #define MCU_EXT_CMD_TXBF_ACTION 0x00001eed 465 #define MCU_EXT_CMD_EFUSE_BUFFER_MODE 0x000021ed 466 #define MCU_EXT_CMD_THERMAL_PROT 0x000023ed 467 #define MCU_EXT_CMD_STA_REC_UPDATE 0x000025ed 468 #define MCU_EXT_CMD_BSS_INFO_UPDATE 0x000026ed 469 #define MCU_EXT_CMD_EDCA_UPDATE 0x000027ed 470 #define MCU_EXT_CMD_DEV_INFO_UPDATE 0x00002Aed 471 #define MCU_EXT_CMD_THERMAL_CTRL 0x00002ced 472 #define MCU_EXT_CMD_WTBL_UPDATE 0x000032ed 473 #define MCU_EXT_CMD_SET_DRR_CTRL 0x000036ed 474 #define MCU_EXT_CMD_SET_RDD_CTRL 0x00003aed 475 #define MCU_EXT_CMD_ATE_CTRL 0x00003ded 476 #define MCU_EXT_CMD_PROTECT_CTRL 0x00003eed 477 #define MCU_EXT_CMD_DBDC_CTRL 0x000045ed 478 #define MCU_EXT_CMD_MAC_INIT_CTRL 0x000046ed 479 #define MCU_EXT_CMD_RX_HDR_TRANS 0x000047ed 480 #define MCU_EXT_CMD_MUAR_UPDATE 0x000048ed 481 #define MCU_EXT_CMD_BCN_OFFLOAD 0x000049ed 482 #define MCU_EXT_CMD_RX_AIRTIME_CTRL 0x00004aed 483 #define MCU_EXT_CMD_SET_RX_PATH 0x00004eed 484 #define MCU_EXT_CMD_EFUSE_FREE_BLOCK 0x00004fed 485 #define MCU_EXT_CMD_TX_POWER_FEATURE_CTRL 0x000058ed 486 #define MCU_EXT_CMD_RXDCOC_CAL 0x000059ed 487 #define MCU_EXT_CMD_GET_MIB_INFO 0x00005aed 488 #define MCU_EXT_CMD_TXDPD_CAL 0x000060ed 489 #define MCU_EXT_CMD_CAL_CACHE 0x000067ed 490 #define MCU_EXT_CMD_SET_RADAR_TH 0x00007ced 491 #define MCU_EXT_CMD_SET_RDD_PATTERN 0x00007ded 492 #define MCU_EXT_CMD_MWDS_SUPPORT 0x000080ed 493 #define MCU_EXT_CMD_SET_SER_TRIGGER 0x000081ed 494 #define MCU_EXT_CMD_SCS_CTRL 0x000082ed 495 #define MCU_EXT_CMD_TWT_AGRT_UPDATE 0x000094ed 496 #define MCU_EXT_CMD_FW_DBG_CTRL 0x000095ed 497 #define MCU_EXT_CMD_SET_RDD_TH 0x00009ded 498 #define MCU_EXT_CMD_MURU_CTRL 0x00009fed 499 #define MCU_EXT_CMD_SET_SPR 0x0000a8ed 500 #define MCU_EXT_CMD_GROUP_PRE_CAL_INFO 0x0000abed 501 #define MCU_EXT_CMD_DPD_PRE_CAL_INFO 0x0000aced 502 #define MCU_EXT_CMD_PHY_STAT_INFO 0x0000aded 503 504 #define MCU_GET_EXT_CMD(x) (((x) & MCU_CMD_FIELD_EXT_ID_MASK) >> 8) 505 506 #define MCU_UNI_CMD_DEV_INFO_UPDATE 0x00020001 507 #define MCU_UNI_CMD_BSS_INFO_UPDATE 0x00020002 508 #define MCU_UNI_CMD_STA_REC_UPDATE 0x00020003 509 #define MCU_UNI_CMD_SUSPEND 0x00020005 510 #define MCU_UNI_CMD_OFFLOAD 0x00020006 511 #define MCU_UNI_CMD_HIF_CTRL 0x00020007 512 #define MCU_UNI_CMD_SNIFFER 0x00020024 513 514 #define UNI_BSS_INFO_BASIC 0 515 #define UNI_BSS_INFO_RLM 2 516 #define UNI_BSS_INFO_BSS_COLOR 4 517 #define UNI_BSS_INFO_HE_BASIC 5 518 #define UNI_BSS_INFO_BCN_CONTENT 7 519 #define UNI_BSS_INFO_QBSS 15 520 #define UNI_BSS_INFO_UAPSD 19 521 #define UNI_BSS_INFO_PS 21 522 #define UNI_BSS_INFO_BCNFT 22 523 524 /* offload mcu commands */ 525 #define MCU_CE_CMD_TEST_CTRL 0x00040001 526 #define MCU_CE_CMD_START_HW_SCAN 0x00040003 527 #define MCU_CE_CMD_SET_PS_PROFILE 0x00040005 528 #define MCU_CE_CMD_SET_CHAN_DOMAIN 0x0004000f 529 #define MCU_CE_CMD_SET_BSS_CONNECTED 0x00040016 530 #define MCU_CE_CMD_SET_BSS_ABORT 0x00040017 531 #define MCU_CE_CMD_CANCEL_HW_SCAN 0x0004001b 532 #define MCU_CE_CMD_SET_ROC 0x0004001c 533 #define MCU_CE_CMD_SET_EDCA_PARMS 0x0004001d 534 #define MCU_CE_CMD_SET_P2P_OPPPS 0x00040033 535 #define MCU_CE_CMD_SET_CLC 0x0004005c 536 #define MCU_CE_CMD_SET_RATE_TX_POWER 0x0004005d 537 #define MCU_CE_CMD_SCHED_SCAN_ENABLE 0x00040061 538 #define MCU_CE_CMD_SCHED_SCAN_REQ 0x00040062 539 #define MCU_CE_CMD_GET_NIC_CAPAB 0x0004008a 540 #define MCU_CE_CMD_SET_MU_EDCA_PARMS 0x000400b0 541 #define MCU_CE_CMD_REG_WRITE 0x000400c0 542 #define MCU_CE_CMD_REG_READ 0x000400c0 543 #define MCU_CE_CMD_CHIP_CONFIG 0x000400ca 544 #define MCU_CE_CMD_FWLOG_2_HOST 0x000400c5 545 #define MCU_CE_CMD_GET_WTBL 0x000400cd 546 #define MCU_CE_CMD_GET_TXPWR 0x000400d0 547 #define MCU_CE_QUERY_REG_READ (MCU_CE_CMD_REG_READ | MCU_CMD_FIELD_QUERY) 548 549 /* event commands */ 550 #define MCU_EVENT_TARGET_ADDRESS_LEN 0x01 551 #define MCU_EVENT_FW_START 0x01 552 #define MCU_EVENT_GENERIC 0x01 553 #define MCU_EVENT_ACCESS_REG 0x02 554 #define MCU_EVENT_MT_PATCH_SEM 0x04 555 #define MCU_EVENT_REG_ACCESS 0x05 556 #define MCU_EVENT_LP_INFO 0x07 557 #define MCU_EVENT_SCAN_DONE 0x0d 558 #define MCU_EVENT_TX_DONE 0x0f 559 #define MCU_EVENT_ROC 0x10 560 #define MCU_EVENT_BSS_ABSENCE 0x11 561 #define MCU_EVENT_BSS_BEACON_LOSS 0x13 562 #define MCU_EVENT_CH_PRIVILEGE 0x18 563 #define MCU_EVENT_SCHED_SCAN_DONE 0x23 564 #define MCU_EVENT_DBG_MSG 0x27 565 #define MCU_EVENT_TXPWR 0xd0 566 #define MCU_EVENT_EXT 0xed 567 #define MCU_EVENT_RESTART_DL 0xef 568 #define MCU_EVENT_COREDUMP 0xf0 569 570 /* extended event commands */ 571 #define MCU_EXT_EVENT_PS_SYNC 0x5 572 #define MCU_EXT_EVENT_FW_LOG_2_HOST 0x13 573 #define MCU_EXT_EVENT_THERMAL_PROTECT 0x22 574 #define MCU_EXT_EVENT_ASSERT_DUMP 0x23 575 #define MCU_EXT_EVENT_RDD_REPORT 0x3a 576 #define MCU_EXT_EVENT_CSA_NOTIFY 0x4f 577 #define MCU_EXT_EVENT_BCC_NOTIFY 0x75 578 #define MCU_EXT_EVENT_RATE_REPORT 0x87 579 #define MCU_EXT_EVENT_MURU_CTRL 0x9f 580 581 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 582 #define MCU_PKT_ID 0xa0 583 584 /* values for MT_TXD0_PKT_FMT */ 585 #define MT_TX_TYPE_CT (0 << 23) 586 #define MT_TX_TYPE_SF (1 << 23) 587 #define MT_TX_TYPE_CMD (2 << 23) 588 #define MT_TX_TYPE_FW (3 << 23) 589 590 /* values for port idx */ 591 #define MT_TX_PORT_IDX_LMAC 0 592 #define MT_TX_PORT_IDX_MCU 1 593 594 /* values for EEPROM command */ 595 #define EE_MODE_EFUSE 0 596 #define EE_MODE_BUFFER 1 597 598 #define EE_FORMAT_BIN 0 599 #define EE_FORMAT_WHOLE 1 600 #define EE_FORMAT_MULTIPLE 2 601 602 #define MT_CTX0 0x0 603 #define MT_HIF0 0x0 604 #define MT_LMAC_AC00 0x0 605 #define MT_LMAC_AC01 0x1 606 #define MT_LMAC_AC02 0x2 607 #define MT_LMAC_AC03 0x3 608 #define MT_LMAC_ALTX0 0x10 609 #define MT_LMAC_BMC0 0x11 610 #define MT_LMAC_BCN0 0x12 611 #define MT_LMAC_PSMP0 0x13 612 613 /* values for MT_TXD0_Q_IDX */ 614 #define MT_TX_MCU_PORT_RX_Q0 0x20 615 #define MT_TX_MCU_PORT_RX_Q1 0x21 616 #define MT_TX_MCU_PORT_RX_Q2 0x22 617 #define MT_TX_MCU_PORT_RX_Q3 0x23 618 #define MT_TX_MCU_PORT_RX_FWDL 0x3e 619 620 #define MT_TXD0_Q_IDX_MASK 0xfe000000 621 #define MT_TXD0_Q_IDX(x) (((x) << 25) & MT_TXD0_Q_IDX_MASK) 622 #define MT_TXD0_PKT_FMT 0x01800000 623 #define MT_TXD0_ETH_TYPE_OFFSET 0x007f0000 624 #define MT_TXD0_TX_BYTES_MASK 0x0000ffff 625 626 /* values for MT_TXD1_HDR_FORMAT */ 627 #define MT_HDR_FORMAT_802_3 (0 << 16) 628 #define MT_HDR_FORMAT_CMD (1 << 16) 629 #define MT_HDR_FORMAT_802_11 (2 << 16) 630 #define MT_HDR_FORMAT_802_11_EXT (3 << 16) 631 632 #define MT_TXD1_LONG_FORMAT (1U << 31) 633 #define MT_TXD1_TGID (1U << 30) 634 #define MT_TXD1_OWN_MAC_MASK 0x3f000000 635 #define MT_TXD1_OWN_MAC_SHIFT 24 636 #define MT_TXD1_AMSDU (1U << 23) 637 #define MT_TXD1_TID_MASK 0x00700000 638 #define MT_TXD1_TID(x) (((x) << 20) & MT_TXD1_TID_MASK) 639 #define MT_TXD1_HDR_PAD_MASK 0x000c0000 640 #define MT_TXD1_HDR_PAD_SHIFT 18 641 #define MT_TXD1_HDR_FORMAT_MASK 0x00030000 642 #define MT_TXD1_HDR_FORMAT_SHIFT 16 643 #define MT_TXD1_HDR_INFO_MASK 0x0000f800 644 #define MT_TXD1_HDR_INFO(x) (((x) << 11) & MT_TXD1_HDR_INFO_MASK) 645 #define MT_TXD1_ETH_802_3 (1U << 15) 646 #define MT_TXD1_VTA (1U << 10) 647 #define MT_TXD1_WLAN_IDX_MASK 0x000003ff 648 649 #define MT_TXD2_FIX_RATE (1U << 31) 650 #define MT_TXD2_FIXED_RATE (1U << 30) 651 #define MT_TXD2_POWER_OFFSET_MASK 0x3f000000 652 #define MT_TXD2_POWER_OFFSET_SHIFT 24 653 #define MT_TXD2_MAX_TX_TIME_MASK 0x00ff0000 654 #define MT_TXD2_MAX_TX_TIME_SHIFT 16 655 #define MT_TXD2_FRAG 0x0000c000 656 #define MT_TXD2_HTC_VLD (1U << 13) 657 #define MT_TXD2_DURATION (1U << 12) 658 #define MT_TXD2_BIP (1U << 11) 659 #define MT_TXD2_MULTICAST (1U << 10) 660 #define MT_TXD2_RTS (1U << 9) 661 #define MT_TXD2_SOUNDING (1U << 8) 662 #define MT_TXD2_NDPA (1U << 7) 663 #define MT_TXD2_NDP (1U << 6) 664 #define MT_TXD2_FRAME_TYPE_MASK 0x00000030 665 #define MT_TXD2_SUB_TYPE_MASK 0x0000000f 666 #define MT_TXD2_FRAME_TYPE(x) (((x) << 4) & MT_TXD2_FRAME_TYPE_MASK) 667 #define MT_TXD2_SUB_TYPE(x) ((x) & MT_TXD2_SUB_TYPE_MASK) 668 669 #define MT_TXD3_SN_VALID (1U << 31) 670 #define MT_TXD3_PN_VALID (1U << 30) 671 #define MT_TXD3_SW_POWER_MGMT (1U << 29) 672 #define MT_TXD3_BA_DISABLE (1U << 28) 673 #define MT_TXD3_SEQ GENMASK(27, 16) 674 #define MT_TXD3_REM_TX_COUNT_MASK 0x0000f800 675 #define MT_TXD3_REM_TX_COUNT_SHIFT 11 676 #define MT_TXD3_TX_COUNT GENMASK(10, 6) 677 #define MT_TXD3_TIMING_MEASURE (1U << 5) 678 #define MT_TXD3_DAS (1U << 4) 679 #define MT_TXD3_EEOSP (1U << 3) 680 #define MT_TXD3_EMRD (1U << 2) 681 #define MT_TXD3_PROTECT_FRAME (1U << 1) 682 #define MT_TXD3_NO_ACK (1U << 0) 683 684 #define MT_TXD4_PN_LOW_MASK 0xffffffff 685 686 #define MT_TXD5_PN_HIGH 0xffff0000 687 #define MT_TXD5_MD (1U << 15) 688 #define MT_TXD5_ADD_BA (1U << 14) 689 #define MT_TXD5_TX_STATUS_HOST (1U << 10) 690 #define MT_TXD5_TX_STATUS_MCU (1U << 9) 691 #define MT_TXD5_TX_STATUS_FMT (1U << 8) 692 #define MT_TXD5_PID 0x000000ff 693 694 #define MT_TXD6_TX_IBF (1U << 31) 695 #define MT_TXD6_TX_EBF (1U << 30) 696 #define MT_TXD6_TX_RATE_MASK 0x3fff0000 697 #define MT_TXD6_TX_RATE_SHIFT 16 698 #define MT_TXD6_SGI 0x0000c000 699 #define MT_TXD6_HELTF 0x00003000 700 #define MT_TXD6_LDPC (1U << 11) 701 #define MT_TXD6_SPE_ID_IDX (1U << 10) 702 #define MT_TXD6_ANT_ID 0x000000f0 703 #define MT_TXD6_DYN_BW (1U << 3) 704 #define MT_TXD6_FIXED_BW (1U << 2) 705 #define MT_TXD6_BW 0x00000003 706 707 #define MT_TXD7_TXD_LEN_MASK 0xc0000000 708 #define MT_TXD7_UDP_TCP_SUM (1U << 29) 709 #define MT_TXD7_IP_SUM (1U << 28) 710 #define MT_TXD7_TYPE_MASK 0x00300000 711 #define MT_TXD7_SUB_TYPE_MASK 0x000f0000 712 #define MT_TXD7_TYPE(x) (((x) << 20) & MT_TXD7_TYPE_MASK) 713 #define MT_TXD7_SUB_TYPE(x) (((x) << 16) & MT_TXD7_SUB_TYPE_MASK) 714 715 #define MT_TXD7_PSE_FID GENMASK(27, 16) 716 #define MT_TXD7_SPE_IDX GENMASK(15, 11) 717 #define MT_TXD7_HW_AMSDU (1U << 10) 718 #define MT_TXD7_TX_TIME 0x000003ff 719 720 #define MT_TX_RATE_STBC (1U << 13) 721 #define MT_TX_RATE_NSS_MASK 0x00001c00 722 #define MT_TX_RATE_NSS_SHIFT 10 723 #define MT_TX_RATE_MODE_MASK 0x000003c0 724 #define MT_TX_RATE_MODE_SHIFT 6 725 #define MT_TX_RATE_SU_EXT_TONE (1U << 5) 726 #define MT_TX_RATE_DCM (1U << 4) 727 /* VHT/HE only use bits 0-3 */ 728 #define MT_TX_RATE_IDX_MASK 0x0000003f 729 730 731 #define MT_RXD0_LENGTH_MASK 0x0000ffff 732 #define MT_RXD0_PKT_FLAG_MASK 0x000f0000 733 #define MT_RXD0_PKT_FLAG_SHIFT 16 734 #define MT_RXD0_NORMAL_ETH_TYPE_OFS 0x007f0000 735 #define MT_RXD0_NORMAL_IP_SUM (1U << 23) 736 #define MT_RXD0_NORMAL_UDP_TCP_SUM (1U << 24) 737 #define MT_RXD0_PKT_TYPE_MASK 0xf8000000 738 #define MT_RXD0_PKT_TYPE_SHIFT 27 739 #define MT_RXD0_PKT_TYPE_GET(x) \ 740 (((x) & MT_RXD0_PKT_TYPE_MASK) >> MT_RXD0_PKT_TYPE_SHIFT) 741 742 /* RXD DW1 */ 743 #define MT_RXD1_NORMAL_WLAN_IDX_MASK 0x000003ff 744 #define MT_RXD1_NORMAL_GROUP_1 (1U << 11) 745 #define MT_RXD1_NORMAL_GROUP_2 (1U << 12) 746 #define MT_RXD1_NORMAL_GROUP_3 (1U << 13) 747 #define MT_RXD1_NORMAL_GROUP_4 (1U << 14) 748 #define MT_RXD1_NORMAL_GROUP_5 (1U << 15) 749 #define MT_RXD1_NORMAL_SEC_MODE_MASK 0x001f0000 750 #define MT_RXD1_NORMAL_SEC_MODE_SHIFT 16 751 #define MT_RXD1_NORMAL_KEY_ID_MASK 0x00600000 752 #define MT_RXD1_NORMAL_CM (1U << 23) 753 #define MT_RXD1_NORMAL_CLM (1U << 24) 754 #define MT_RXD1_NORMAL_ICV_ERR (1U << 25) 755 #define MT_RXD1_NORMAL_TKIP_MIC_ERR (1U << 26) 756 #define MT_RXD1_NORMAL_FCS_ERR (1U << 27) 757 #define MT_RXD1_NORMAL_BAND_IDX (1U << 28) 758 #define MT_RXD1_NORMAL_SPP_EN (1U << 29) 759 #define MT_RXD1_NORMAL_ADD_OM (1U << 30) 760 #define MT_RXD1_NORMAL_SEC_DONE (1U << 31) 761 762 /* RXD DW2 */ 763 #define MT_RXD2_NORMAL_BSSID 0x0000003f 764 #define MT_RXD2_NORMAL_CO_ANT (1U << 6) 765 #define MT_RXD2_NORMAL_BF_CQI (1U << 7) 766 #define MT_RXD2_NORMAL_MAC_HDR_LEN 0x00001f00 767 #define MT_RXD2_NORMAL_HDR_TRANS (1U << 13) 768 #define MT_RXD2_NORMAL_HDR_OFFSET_MASK 0x0000c000 769 #define MT_RXD2_NORMAL_HDR_OFFSET_SHIFT 14 770 #define MT_RXD2_NORMAL_TID 0x000f0000 771 #define MT_RXD2_NORMAL_MU_BAR (1U << 21) 772 #define MT_RXD2_NORMAL_SW_BIT (1U << 22) 773 #define MT_RXD2_NORMAL_AMSDU_ERR (1U << 23) 774 #define MT_RXD2_NORMAL_MAX_LEN_ERROR (1U << 24) 775 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR (1U << 25) 776 #define MT_RXD2_NORMAL_INT_FRAME (1U << 26) 777 #define MT_RXD2_NORMAL_FRAG (1U << 27) 778 #define MT_RXD2_NORMAL_NULL_FRAME (1U << 28) 779 #define MT_RXD2_NORMAL_NDATA (1U << 29) 780 #define MT_RXD2_NORMAL_NON_AMPDU (1U << 30) 781 #define MT_RXD2_NORMAL_BF_REPORT (1U << 31) 782 783 /* RXD DW3 */ 784 #define MT_RXD3_NORMAL_RXV_SEQ_MASK 0x000000ff 785 #define MT_RXD3_NORMAL_CH_NUM_MASK 0x0000ff00 786 #define MT_RXD3_NORMAL_CH_NUM_SHIFT 8 787 #define MT_RXD3_NORMAL_ADDR_TYPE_MASK 0x00030000 788 #define MT_RXD3_NORMAL_U2M (1U << 16) 789 #define MT_RXD3_NORMAL_HTC_VLD (1U << 0) 790 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS (1U << 19) 791 #define MT_RXD3_NORMAL_BEACON_MC (1U << 20) 792 #define MT_RXD3_NORMAL_BEACON_UC (1U << 21) 793 #define MT_RXD3_NORMAL_AMSDU (1U << 22) 794 #define MT_RXD3_NORMAL_MESH (1U << 23) 795 #define MT_RXD3_NORMAL_MHCP (1U << 24) 796 #define MT_RXD3_NORMAL_NO_INFO_WB (1U << 25) 797 #define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS (1U << 26) 798 #define MT_RXD3_NORMAL_POWER_SAVE_STAT (1U << 27) 799 #define MT_RXD3_NORMAL_MORE (1U << 28) 800 #define MT_RXD3_NORMAL_UNWANT (1U << 29) 801 #define MT_RXD3_NORMAL_RX_DROP (1U << 30) 802 #define MT_RXD3_NORMAL_VLAN2ETH (1U << 31) 803 804 /* RXD DW4 */ 805 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT 0x00000003 806 #define MT_RXD4_FIRST_AMSDU_FRAME 0x3 807 #define MT_RXD4_MID_AMSDU_FRAME 0x2 808 #define MT_RXD4_LAST_AMSDU_FRAME 0x1 809 #define MT_RXD4_NORMAL_PATTERN_DROP (1U << 9) 810 #define MT_RXD4_NORMAL_CLS (1U << 10) 811 #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11) 812 #define MT_RXD4_NORMAL_MAGIC_PKT (1U << 13) 813 #define MT_RXD4_NORMAL_WOL GENMASK(18, 14) 814 #define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19) 815 #define MT_RXD3_NORMAL_PF_MODE (1U << 99) 816 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30) 817 818 #define PKT_TYPE_TXS 0 819 #define PKT_TYPE_TXRXV 1 820 #define PKT_TYPE_NORMAL 2 821 #define PKT_TYPE_RX_DUP_RFB 3 822 #define PKT_TYPE_RX_TMR 4 823 #define PKT_TYPE_RETRIEVE 5 824 #define PKT_TYPE_TXRX_NOTIFY 6 825 #define PKT_TYPE_RX_EVENT 7 826 #define PKT_TYPE_NORMAL_MCU 8 827 828 struct mt7921_mcu_txd { 829 uint32_t txd[8]; 830 831 uint16_t len; 832 uint16_t pq_id; 833 834 uint8_t cid; 835 uint8_t pkt_type; 836 uint8_t set_query; /* FW don't care */ 837 uint8_t seq; 838 839 uint8_t uc_d2b0_rev; 840 uint8_t ext_cid; 841 uint8_t s2d_index; 842 uint8_t ext_cid_ack; 843 844 uint32_t reserved[5]; 845 } __packed __aligned(4); 846 847 /** 848 * struct mt7921_uni_txd - mcu command descriptor for firmware v3 849 * @txd: hardware descriptor 850 * @len: total length not including txd 851 * @cid: command identifier 852 * @pkt_type: must be 0xa0 (cmd packet by long format) 853 * @frag_n: fragment number 854 * @seq: sequence number 855 * @checksum: 0 mean there is no checksum 856 * @s2d_index: index for command source and destination 857 * Definition | value | note 858 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 859 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 860 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 861 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 862 * 863 * @option: command option 864 * BIT[0]: UNI_CMD_OPT_BIT_ACK 865 * set to 1 to request a fw reply 866 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 867 * is set, mcu firmware will send response event EID = 0x01 868 * (UNI_EVENT_ID_CMD_RESULT) to the host. 869 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 870 * 0: original command 871 * 1: unified command 872 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 873 * 0: QUERY command 874 * 1: SET command 875 */ 876 struct mt7921_uni_txd { 877 uint32_t txd[8]; 878 879 /* DW1 */ 880 uint16_t len; 881 uint16_t cid; 882 883 /* DW2 */ 884 uint8_t reserved; 885 uint8_t pkt_type; 886 uint8_t frag_n; 887 uint8_t seq; 888 889 /* DW3 */ 890 uint16_t checksum; 891 uint8_t s2d_index; 892 uint8_t option; 893 894 /* DW4 */ 895 uint8_t reserved2[4]; 896 } __packed __aligned(4); 897 898 899 struct mt7921_mcu_rxd { 900 uint32_t rxd[6]; 901 uint16_t len; /* includes hdr but without rxd[6] */ 902 uint16_t pkt_type_id; 903 uint8_t eid; 904 uint8_t seq; 905 uint16_t pad0; 906 uint8_t ext_eid; 907 uint8_t pad1[2]; 908 uint8_t s2d_index; 909 } __packed; 910 911 struct mt7921_mcu_uni_event { 912 uint8_t cid; 913 uint8_t pad[3]; 914 uint32_t status; /* 0: success, others: fail */ 915 } __packed; 916 917 struct mt7921_mcu_reg_event { 918 uint32_t reg; 919 uint32_t val; 920 } __packed; 921 922 struct mt76_connac_config { 923 uint16_t id; 924 uint8_t type; 925 uint8_t resp_type; 926 uint16_t data_size; 927 uint16_t resv; 928 uint8_t data[320]; 929 }; 930 931 #define MT_SKU_POWER_LIMIT 161 932 933 struct mt76_connac_sku_tlv { 934 uint8_t channel; 935 int8_t pwr_limit[MT_SKU_POWER_LIMIT]; 936 } __packed; 937 938 struct mt76_power_limits { 939 int8_t cck[4]; 940 int8_t ofdm[8]; 941 int8_t mcs[4][10]; 942 int8_t ru[7][12]; 943 }; 944 945 #define MT_TX_PWR_BAND_2GHZ 1 946 #define MT_TX_PWR_BAND_5GHZ 2 947 #define MT_TX_PWR_BAND_6GHZ 3 948 949 struct mt76_connac_tx_power_limit_tlv { 950 /* DW0 - common info*/ 951 uint8_t ver; 952 uint8_t pad0; 953 uint16_t len; 954 /* DW1 - cmd hint */ 955 uint8_t n_chan; /* # channel */ 956 uint8_t band; /* 2.4GHz - 5GHz - 6GHz */ 957 uint8_t last_msg; 958 uint8_t pad1; 959 /* DW3 */ 960 uint8_t alpha2[4]; /* regulatory_request.alpha2 */ 961 uint8_t pad2[32]; 962 } __packed; 963 964 struct mt76_connac_bss_basic_tlv { 965 uint16_t tag; 966 uint16_t len; 967 uint8_t active; 968 uint8_t omac_idx; 969 uint8_t hw_bss_idx; 970 uint8_t band_idx; 971 uint32_t conn_type; 972 uint8_t conn_state; 973 uint8_t wmm_idx; 974 uint8_t bssid[IEEE80211_ADDR_LEN]; 975 uint16_t bmc_tx_wlan_idx; 976 uint16_t bcn_interval; 977 uint8_t dtim_period; 978 uint8_t phymode; /* bit(0): A 979 * bit(1): B 980 * bit(2): G 981 * bit(3): GN 982 * bit(4): AN 983 * bit(5): AC 984 * bit(6): AX2 985 * bit(7): AX5 986 * bit(8): AX6 987 */ 988 uint16_t sta_idx; 989 uint16_t nonht_basic_phy; 990 uint8_t phymode_ext; /* bit(0) AX_6G */ 991 uint8_t pad[1]; 992 } __packed; 993 994 struct mt76_connac_mcu_scan_ssid { 995 uint32_t ssid_len; 996 uint8_t ssid[IEEE80211_NWID_LEN]; 997 } __packed; 998 999 struct mt76_connac_mcu_scan_channel { 1000 uint8_t band; /* 1: 2.4GHz 1001 * 2: 5.0GHz 1002 * Others: Reserved 1003 */ 1004 uint8_t channel_num; 1005 } __packed; 1006 1007 struct mt76_connac_mcu_scan_match { 1008 uint32_t rssi_th; 1009 uint8_t ssid[IEEE80211_NWID_LEN]; 1010 uint8_t ssid_len; 1011 uint8_t rsv[3]; 1012 } __packed; 1013 1014 #define SCAN_FUNC_RANDOM_MAC 0x1 1015 #define SCAN_FUNC_SPLIT_SCAN 0x20 1016 #define MT76_HW_SCAN_IE_LEN 600 1017 1018 struct mt76_connac_hw_scan_req { 1019 uint8_t seq_num; 1020 uint8_t bss_idx; 1021 uint8_t scan_type; /* 0: PASSIVE SCAN 1022 * 1: ACTIVE SCAN 1023 */ 1024 uint8_t ssid_type; /* 0x1 wildcard SSID 1025 * 0x2 P2P wildcard SSID 1026 * 0x4 specified SSID + wildcard SSID 1027 * 0x4 + ssid_type_ext 0x1 1028 * specified SSID only 1029 */ 1030 uint8_t ssids_num; 1031 uint8_t probe_req_num; /* Number of probe request per SSID */ 1032 uint8_t scan_func; /* 0x1 Enable random MAC scan 1033 * 0x2 Disable DBDC scan type 1~3. 1034 * 0x4 Use DBDC scan type 3 1035 * (dedicated one RF to scan). 1036 */ 1037 uint8_t version; /* 0: Not support fields after ies. 1038 * 1: Support fields after ies. 1039 */ 1040 struct mt76_connac_mcu_scan_ssid ssids[4]; 1041 uint16_t probe_delay_time; 1042 uint16_t channel_dwell_time; /* channel Dwell interval */ 1043 uint16_t timeout_value; 1044 uint8_t channel_type; /* 0: Full channels 1045 * 1: Only 2.4GHz channels 1046 * 2: Only 5GHz channels 1047 * 3: P2P social channels only 1048 * (channel #1, #6 and #11) 1049 * 4: Specified channels 1050 * Others: Reserved 1051 */ 1052 uint8_t channels_num; /* valid when channel_type is 4 */ 1053 /* valid when channels_num is set */ 1054 struct mt76_connac_mcu_scan_channel channels[32]; 1055 uint16_t ies_len; 1056 uint8_t ies[MT76_HW_SCAN_IE_LEN]; 1057 /* following fields are valid if version > 0 */ 1058 uint8_t ext_channels_num; 1059 uint8_t ext_ssids_num; 1060 uint16_t channel_min_dwell_time; 1061 struct mt76_connac_mcu_scan_channel ext_channels[32]; 1062 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 1063 uint8_t bssid[IEEE80211_ADDR_LEN]; 1064 /* valid when BIT(1) in scan_func is set. */ 1065 uint8_t random_mac[IEEE80211_ADDR_LEN]; 1066 uint8_t pad[63]; 1067 uint8_t ssid_type_ext; 1068 } __packed; 1069 1070 #define MT76_HW_SCAN_DONE_MAX_CHANNEL_NUM 64 1071 1072 struct mt76_connac_hw_scan_done { 1073 uint8_t seq_num; 1074 uint8_t sparse_channel_num; 1075 struct mt76_connac_mcu_scan_channel sparse_channel; 1076 uint8_t complete_channel_num; 1077 uint8_t current_state; 1078 uint8_t version; 1079 uint8_t pad; 1080 uint32_t beacon_scan_num; 1081 uint8_t pno_enabled; 1082 uint8_t pad2[3]; 1083 uint8_t sparse_channel_valid_num; 1084 uint8_t pad3[3]; 1085 uint8_t channel_num[MT76_HW_SCAN_DONE_MAX_CHANNEL_NUM]; 1086 /* idle format for channel_idle_time 1087 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 1088 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 1089 * 2: dwell time (16us) 1090 */ 1091 uint16_t channel_idle_time[MT76_HW_SCAN_DONE_MAX_CHANNEL_NUM]; 1092 /* beacon and probe response count */ 1093 uint8_t beacon_probe_num[MT76_HW_SCAN_DONE_MAX_CHANNEL_NUM]; 1094 uint8_t mdrdy_count[MT76_HW_SCAN_DONE_MAX_CHANNEL_NUM]; 1095 uint32_t beacon_2g_num; 1096 uint32_t beacon_5g_num; 1097 } __packed; 1098 1099 struct mt7921_patch_hdr { 1100 char build_date[16]; 1101 char platform[4]; 1102 uint32_t hw_sw_ver; 1103 uint32_t patch_ver; 1104 uint16_t checksum; 1105 uint16_t reserved; 1106 struct { 1107 uint32_t patch_ver; 1108 uint32_t subsys; 1109 uint32_t feature; 1110 uint32_t n_region; 1111 uint32_t crc; 1112 uint32_t reserved[11]; 1113 } desc; 1114 } __packed; 1115 1116 struct mt7921_patch_sec { 1117 uint32_t type; 1118 uint32_t offs; 1119 uint32_t size; 1120 union { 1121 uint32_t spec[13]; 1122 struct { 1123 uint32_t addr; 1124 uint32_t len; 1125 uint32_t sec_key_idx; 1126 uint32_t align_len; 1127 uint32_t reserved[9]; 1128 } info; 1129 }; 1130 } __packed; 1131 1132 struct mt7921_fw_trailer { 1133 uint8_t chip_id; 1134 uint8_t eco_code; 1135 uint8_t n_region; 1136 uint8_t format_ver; 1137 uint8_t format_flag; 1138 uint8_t reserved[2]; 1139 char fw_ver[10]; 1140 char build_date[15]; 1141 uint32_t crc; 1142 } __packed; 1143 1144 struct mt7921_fw_region { 1145 uint32_t decomp_crc; 1146 uint32_t decomp_len; 1147 uint32_t decomp_blk_sz; 1148 uint8_t reserved[4]; 1149 uint32_t addr; 1150 uint32_t len; 1151 uint8_t feature_set; 1152 uint8_t reserved1[15]; 1153 } __packed; 1154 1155 /* STA_REC HEADER */ 1156 struct sta_req_hdr { 1157 uint8_t bss_idx; 1158 uint8_t wlan_idx_lo; 1159 uint16_t tlv_num; 1160 uint8_t is_tlv_append; 1161 uint8_t muar_idx; 1162 uint8_t wlan_idx_hi; 1163 uint8_t rsv; 1164 } __packed; 1165 1166 #define STA_REC_BASIC 0x00 1167 struct sta_rec_basic { 1168 uint16_t tag; 1169 uint16_t len; 1170 uint32_t conn_type; 1171 uint8_t conn_state; 1172 uint8_t qos; 1173 uint16_t aid; 1174 uint8_t peer_addr[IEEE80211_ADDR_LEN]; 1175 #define EXTRA_INFO_VER (1U << 0) 1176 #define EXTRA_INFO_NEW (1U << 1) 1177 uint16_t extra_info; 1178 } __packed; 1179 1180 #define STA_REC_RA 0x01 1181 #define HT_MCS_MASK_NUM 10 1182 struct sta_rec_ra_info { 1183 uint16_t tag; 1184 uint16_t len; 1185 uint16_t legacy; 1186 uint8_t rx_mcs_bitmask[HT_MCS_MASK_NUM]; 1187 } __packed; 1188 #define RA_LEGACY_OFDM 0x3fc0 1189 #define RA_LEGACY_CCK 0x000f 1190 1191 #define STA_REC_STATE 0x07 1192 struct sta_rec_state { 1193 uint16_t tag; 1194 uint16_t len; 1195 uint32_t flags; 1196 uint8_t state; 1197 uint8_t vht_opmode; 1198 uint8_t action; 1199 uint8_t rsv[1]; 1200 } __packed; 1201 1202 #define STA_REC_WTBL 0x0d 1203 struct sta_rec_wtbl { 1204 uint16_t tag; 1205 uint16_t len; 1206 uint8_t wlan_idx_lo; 1207 uint8_t operation; 1208 uint16_t tlv_num; 1209 uint8_t wlan_idx_hi; 1210 uint8_t rsv[3]; 1211 } __packed; 1212 1213 #define STA_REC_PHY 0x15 1214 struct sta_rec_phy { 1215 uint16_t tag; 1216 uint16_t len; 1217 uint16_t basic_rate; 1218 uint8_t phy_type; 1219 uint8_t ampdu; 1220 uint8_t rts_policy; 1221 uint8_t rcpi; 1222 uint8_t rsv[2]; 1223 } __packed; 1224 1225 /* WTBL REC */ 1226 #define WTBL_RESET_AND_SET 1 1227 #define WTBL_SET 2 1228 #define WTBL_QUERY 3 1229 #define WTBL_RESET_ALL 4 1230 1231 1232 #define WTBL_GENERIC 0x00 1233 struct wtbl_generic { 1234 uint16_t tag; 1235 uint16_t len; 1236 uint8_t peer_addr[IEEE80211_ADDR_LEN]; 1237 uint8_t muar_idx; 1238 uint8_t skip_tx; 1239 uint8_t cf_ack; 1240 uint8_t qos; 1241 uint8_t mesh; 1242 uint8_t adm; 1243 uint16_t partial_aid; 1244 uint8_t baf_en; 1245 uint8_t aad_om; 1246 } __packed; 1247 1248 #define WTBL_RX 0x01 1249 struct wtbl_rx { 1250 uint16_t tag; 1251 uint16_t len; 1252 uint8_t rcid; 1253 uint8_t rca1; 1254 uint8_t rca2; 1255 uint8_t rv; 1256 uint8_t rsv[4]; 1257 } __packed; 1258 1259 #define WTBL_HDR_TRANS 0x06 1260 struct wtbl_hdr_trans { 1261 uint16_t tag; 1262 uint16_t len; 1263 uint8_t to_ds; 1264 uint8_t from_ds; 1265 uint8_t no_rx_trans; 1266 uint8_t rsv; 1267 } __packed; 1268 1269 #define WTBL_SMPS 0x0d 1270 struct wtbl_smps { 1271 uint16_t tag; 1272 uint16_t len; 1273 uint8_t smps; 1274 uint8_t rsv[3]; 1275 } __packed; 1276 1277 1278 1279 #define FW_START_OVERRIDE 0x01 1280 #define FW_START_WORKING_PDA_CR4 0x02 1281 1282 #define FW_FEATURE_SET_ENCRYPT 0x1 1283 #define FW_FEATURE_SET_KEY_IDX_MASK 0x06 1284 #define FW_FEATURE_ENCRY_MODE 0x10 1285 #define FW_FEATURE_OVERRIDE_ADDR 0x20 1286 1287 #define PATCH_SEC_NOT_SUPPORT 0xffffffff 1288 #define PATCH_SEC_TYPE_MASK 0x0000ffff 1289 #define PATCH_SEC_TYPE_INFO 0x2 1290 1291 #define PATCH_SEC_ENC_TYPE_MASK 0xff000000 1292 #define PATCH_SEC_ENC_TYPE_SHIFT 24 1293 #define PATCH_SEC_ENC_TYPE_PLAIN (0x00 << PATCH_SEC_ENC_TYPE_SHIFT) 1294 #define PATCH_SEC_ENC_TYPE_AES (0x01 << PATCH_SEC_ENC_TYPE_SHIFT) 1295 #define PATCH_SEC_ENC_TYPE_SCRAMBLE (0x02 << PATCH_SEC_ENC_TYPE_SHIFT) 1296 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK 0xffff 1297 #define PATCH_SEC_ENC_AES_KEY_MASK 0xff 1298 1299 #define DL_MODE_ENCRYPT 0x01 1300 #define DL_MODE_KEY_IDX_MASK 0x06 1301 #define DL_MODE_KEY_IDX_SHIFT 1 1302 #define DL_MODE_RESET_SEC_IV 0x08 1303 #define DL_MODE_WORKING_PDA_CR4 0x10 1304 #define DL_CONFIG_ENCRY_MODE_SEL 0x40 1305 #define DL_MODE_NEED_RSP 0x80000000 1306 1307 /* defines for mt7921_mcu_get_nic_capability */ 1308 enum { 1309 MT_NIC_CAP_TX_RESOURCE, 1310 MT_NIC_CAP_TX_EFUSE_ADDR, 1311 MT_NIC_CAP_COEX, 1312 MT_NIC_CAP_SINGLE_SKU, 1313 MT_NIC_CAP_CSUM_OFFLOAD, 1314 MT_NIC_CAP_HW_VER, 1315 MT_NIC_CAP_SW_VER, 1316 MT_NIC_CAP_MAC_ADDR, 1317 MT_NIC_CAP_PHY, 1318 MT_NIC_CAP_MAC, 1319 MT_NIC_CAP_FRAME_BUF, 1320 MT_NIC_CAP_BEAM_FORM, 1321 MT_NIC_CAP_LOCATION, 1322 MT_NIC_CAP_MUMIMO, 1323 MT_NIC_CAP_BUFFER_MODE_INFO, 1324 MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 1325 MT_NIC_CAP_ANTSWP = 0x16, 1326 MT_NIC_CAP_WFDMA_REALLOC, 1327 MT_NIC_CAP_6G, 1328 }; 1329 1330 /* defines for channel bandwidth */ 1331 enum { 1332 CMD_CBW_20MHZ, 1333 CMD_CBW_40MHZ, 1334 CMD_CBW_80MHZ, 1335 CMD_CBW_160MHZ, 1336 CMD_CBW_10MHZ, 1337 CMD_CBW_5MHZ, 1338 CMD_CBW_8080MHZ, 1339 }; 1340 1341 /* defines for channel switch reason */ 1342 enum { 1343 CH_SWITCH_NORMAL = 0, 1344 CH_SWITCH_SCAN = 3, 1345 CH_SWITCH_MCC = 4, 1346 CH_SWITCH_DFS = 5, 1347 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1348 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1349 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1350 CH_SWITCH_SCAN_BYPASS_DPD = 9 1351 }; 1352 1353 enum { 1354 HW_BSSID_0 = 0x0, 1355 HW_BSSID_1, 1356 HW_BSSID_2, 1357 HW_BSSID_3, 1358 HW_BSSID_MAX = HW_BSSID_3, 1359 EXT_BSSID_START = 0x10, 1360 EXT_BSSID_1, 1361 EXT_BSSID_15 = 0x1f, 1362 EXT_BSSID_MAX = EXT_BSSID_15, 1363 REPEATER_BSSID_START = 0x20, 1364 REPEATER_BSSID_MAX = 0x3f, 1365 }; 1366 1367 enum mt76_phy_type { 1368 MT_PHY_TYPE_CCK, 1369 MT_PHY_TYPE_OFDM, 1370 MT_PHY_TYPE_HT, 1371 MT_PHY_TYPE_HT_GF, 1372 MT_PHY_TYPE_VHT, 1373 MT_PHY_TYPE_HE_SU = 8, 1374 MT_PHY_TYPE_HE_EXT_SU, 1375 MT_PHY_TYPE_HE_TB, 1376 MT_PHY_TYPE_HE_MU, 1377 __MT_PHY_TYPE_HE_MAX, 1378 }; 1379 1380 1381 #define STA_TYPE_STA (1U << 0) 1382 #define STA_TYPE_AP (1U << 1) 1383 #define STA_TYPE_ADHOC (1U << 2) 1384 #define STA_TYPE_WDS (1U << 4) 1385 #define STA_TYPE_BC (1U << 5) 1386 1387 #define NETWORK_INFRA (1U << 16) 1388 #define NETWORK_P2P (1U << 17) 1389 #define NETWORK_IBSS (1U << 18) 1390 #define NETWORK_WDS (1U << 21) 1391 1392 #define CONN_STATE_DISCONNECT 0 1393 #define CONN_STATE_CONNECT 1 1394 #define CONN_STATE_PORT_SECURE 2 1395 1396 #define DEV_INFO_ACTIVE 0 1397 1398 #define PHY_TYPE_BIT_HR_DSSS (1U << 0) 1399 #define PHY_TYPE_BIT_ERP (1U << 1) 1400 #define PHY_TYPE_BIT_OFDM (1U << 3) 1401 #define PHY_TYPE_BIT_HT (1U << 4) 1402 #define PHY_TYPE_BIT_VHT (1U << 5) 1403 #define PHY_TYPE_BIT_HE (1U << 6) 1404 1405 #define rssi_to_rcpi(rssi) (2 * (rssi) + 220) 1406 #define rcpi_to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) 1407