1 /* $OpenBSD: if_nge.c,v 1.73 2012/11/29 21:10:32 brad Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 5 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_nge.c,v 1.35 2002/08/08 18:33:28 ambrisko Exp $ 35 */ 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include "bpfilter.h" 92 #include "vlan.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/sockio.h> 97 #include <sys/mbuf.h> 98 #include <sys/malloc.h> 99 #include <sys/kernel.h> 100 #include <sys/device.h> 101 #include <sys/socket.h> 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #include <netinet/if_ether.h> 113 #endif 114 115 #if NVLAN > 0 116 #include <net/if_types.h> 117 #include <net/if_vlan_var.h> 118 #endif 119 120 #if NBPFILTER > 0 121 #include <net/bpf.h> 122 #endif 123 124 #include <uvm/uvm_extern.h> /* for vtophys */ 125 #define VTOPHYS(v) vtophys((vaddr_t)(v)) 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/mii/mii.h> 132 #include <dev/mii/miivar.h> 133 134 #define NGE_USEIOSPACE 135 136 #include <dev/pci/if_ngereg.h> 137 138 int nge_probe(struct device *, void *, void *); 139 void nge_attach(struct device *, struct device *, void *); 140 141 int nge_alloc_jumbo_mem(struct nge_softc *); 142 void *nge_jalloc(struct nge_softc *); 143 void nge_jfree(caddr_t, u_int, void *); 144 145 int nge_newbuf(struct nge_softc *, struct nge_desc *, 146 struct mbuf *); 147 int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *); 148 void nge_rxeof(struct nge_softc *); 149 void nge_txeof(struct nge_softc *); 150 int nge_intr(void *); 151 void nge_tick(void *); 152 void nge_start(struct ifnet *); 153 int nge_ioctl(struct ifnet *, u_long, caddr_t); 154 void nge_init(void *); 155 void nge_stop(struct nge_softc *); 156 void nge_watchdog(struct ifnet *); 157 int nge_ifmedia_mii_upd(struct ifnet *); 158 void nge_ifmedia_mii_sts(struct ifnet *, struct ifmediareq *); 159 int nge_ifmedia_tbi_upd(struct ifnet *); 160 void nge_ifmedia_tbi_sts(struct ifnet *, struct ifmediareq *); 161 162 void nge_delay(struct nge_softc *); 163 void nge_eeprom_idle(struct nge_softc *); 164 void nge_eeprom_putbyte(struct nge_softc *, int); 165 void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *); 166 void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int); 167 168 void nge_mii_sync(struct nge_softc *); 169 void nge_mii_send(struct nge_softc *, u_int32_t, int); 170 int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 171 int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 172 173 int nge_miibus_readreg(struct device *, int, int); 174 void nge_miibus_writereg(struct device *, int, int, int); 175 void nge_miibus_statchg(struct device *); 176 177 void nge_setmulti(struct nge_softc *); 178 void nge_reset(struct nge_softc *); 179 int nge_list_rx_init(struct nge_softc *); 180 int nge_list_tx_init(struct nge_softc *); 181 182 #ifdef NGE_USEIOSPACE 183 #define NGE_RES SYS_RES_IOPORT 184 #define NGE_RID NGE_PCI_LOIO 185 #else 186 #define NGE_RES SYS_RES_MEMORY 187 #define NGE_RID NGE_PCI_LOMEM 188 #endif 189 190 #ifdef NGE_DEBUG 191 #define DPRINTF(x) if (ngedebug) printf x 192 #define DPRINTFN(n,x) if (ngedebug >= (n)) printf x 193 int ngedebug = 0; 194 #else 195 #define DPRINTF(x) 196 #define DPRINTFN(n,x) 197 #endif 198 199 #define NGE_SETBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, \ 201 CSR_READ_4(sc, reg) | (x)) 202 203 #define NGE_CLRBIT(sc, reg, x) \ 204 CSR_WRITE_4(sc, reg, \ 205 CSR_READ_4(sc, reg) & ~(x)) 206 207 #define SIO_SET(x) \ 208 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 209 210 #define SIO_CLR(x) \ 211 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 212 213 void 214 nge_delay(sc) 215 struct nge_softc *sc; 216 { 217 int idx; 218 219 for (idx = (300 / 33) + 1; idx > 0; idx--) 220 CSR_READ_4(sc, NGE_CSR); 221 } 222 223 void 224 nge_eeprom_idle(sc) 225 struct nge_softc *sc; 226 { 227 int i; 228 229 SIO_SET(NGE_MEAR_EE_CSEL); 230 nge_delay(sc); 231 SIO_SET(NGE_MEAR_EE_CLK); 232 nge_delay(sc); 233 234 for (i = 0; i < 25; i++) { 235 SIO_CLR(NGE_MEAR_EE_CLK); 236 nge_delay(sc); 237 SIO_SET(NGE_MEAR_EE_CLK); 238 nge_delay(sc); 239 } 240 241 SIO_CLR(NGE_MEAR_EE_CLK); 242 nge_delay(sc); 243 SIO_CLR(NGE_MEAR_EE_CSEL); 244 nge_delay(sc); 245 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 246 } 247 248 /* 249 * Send a read command and address to the EEPROM, check for ACK. 250 */ 251 void 252 nge_eeprom_putbyte(sc, addr) 253 struct nge_softc *sc; 254 int addr; 255 { 256 int d, i; 257 258 d = addr | NGE_EECMD_READ; 259 260 /* 261 * Feed in each bit and strobe the clock. 262 */ 263 for (i = 0x400; i; i >>= 1) { 264 if (d & i) { 265 SIO_SET(NGE_MEAR_EE_DIN); 266 } else { 267 SIO_CLR(NGE_MEAR_EE_DIN); 268 } 269 nge_delay(sc); 270 SIO_SET(NGE_MEAR_EE_CLK); 271 nge_delay(sc); 272 SIO_CLR(NGE_MEAR_EE_CLK); 273 nge_delay(sc); 274 } 275 } 276 277 /* 278 * Read a word of data stored in the EEPROM at address 'addr.' 279 */ 280 void 281 nge_eeprom_getword(sc, addr, dest) 282 struct nge_softc *sc; 283 int addr; 284 u_int16_t *dest; 285 { 286 int i; 287 u_int16_t word = 0; 288 289 /* Force EEPROM to idle state. */ 290 nge_eeprom_idle(sc); 291 292 /* Enter EEPROM access mode. */ 293 nge_delay(sc); 294 SIO_CLR(NGE_MEAR_EE_CLK); 295 nge_delay(sc); 296 SIO_SET(NGE_MEAR_EE_CSEL); 297 nge_delay(sc); 298 299 /* 300 * Send address of word we want to read. 301 */ 302 nge_eeprom_putbyte(sc, addr); 303 304 /* 305 * Start reading bits from EEPROM. 306 */ 307 for (i = 0x8000; i; i >>= 1) { 308 SIO_SET(NGE_MEAR_EE_CLK); 309 nge_delay(sc); 310 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 311 word |= i; 312 nge_delay(sc); 313 SIO_CLR(NGE_MEAR_EE_CLK); 314 nge_delay(sc); 315 } 316 317 /* Turn off EEPROM access mode. */ 318 nge_eeprom_idle(sc); 319 320 *dest = word; 321 } 322 323 /* 324 * Read a sequence of words from the EEPROM. 325 */ 326 void 327 nge_read_eeprom(sc, dest, off, cnt, swap) 328 struct nge_softc *sc; 329 caddr_t dest; 330 int off; 331 int cnt; 332 int swap; 333 { 334 int i; 335 u_int16_t word = 0, *ptr; 336 337 for (i = 0; i < cnt; i++) { 338 nge_eeprom_getword(sc, off + i, &word); 339 ptr = (u_int16_t *)(dest + (i * 2)); 340 if (swap) 341 *ptr = ntohs(word); 342 else 343 *ptr = word; 344 } 345 } 346 347 /* 348 * Sync the PHYs by setting data bit and strobing the clock 32 times. 349 */ 350 void 351 nge_mii_sync(sc) 352 struct nge_softc *sc; 353 { 354 int i; 355 356 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 357 358 for (i = 0; i < 32; i++) { 359 SIO_SET(NGE_MEAR_MII_CLK); 360 DELAY(1); 361 SIO_CLR(NGE_MEAR_MII_CLK); 362 DELAY(1); 363 } 364 } 365 366 /* 367 * Clock a series of bits through the MII. 368 */ 369 void 370 nge_mii_send(sc, bits, cnt) 371 struct nge_softc *sc; 372 u_int32_t bits; 373 int cnt; 374 { 375 int i; 376 377 SIO_CLR(NGE_MEAR_MII_CLK); 378 379 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 380 if (bits & i) { 381 SIO_SET(NGE_MEAR_MII_DATA); 382 } else { 383 SIO_CLR(NGE_MEAR_MII_DATA); 384 } 385 DELAY(1); 386 SIO_CLR(NGE_MEAR_MII_CLK); 387 DELAY(1); 388 SIO_SET(NGE_MEAR_MII_CLK); 389 } 390 } 391 392 /* 393 * Read an PHY register through the MII. 394 */ 395 int 396 nge_mii_readreg(sc, frame) 397 struct nge_softc *sc; 398 struct nge_mii_frame *frame; 399 { 400 int i, ack, s; 401 402 s = splnet(); 403 404 /* 405 * Set up frame for RX. 406 */ 407 frame->mii_stdelim = NGE_MII_STARTDELIM; 408 frame->mii_opcode = NGE_MII_READOP; 409 frame->mii_turnaround = 0; 410 frame->mii_data = 0; 411 412 CSR_WRITE_4(sc, NGE_MEAR, 0); 413 414 /* 415 * Turn on data xmit. 416 */ 417 SIO_SET(NGE_MEAR_MII_DIR); 418 419 nge_mii_sync(sc); 420 421 /* 422 * Send command/address info. 423 */ 424 nge_mii_send(sc, frame->mii_stdelim, 2); 425 nge_mii_send(sc, frame->mii_opcode, 2); 426 nge_mii_send(sc, frame->mii_phyaddr, 5); 427 nge_mii_send(sc, frame->mii_regaddr, 5); 428 429 /* Idle bit */ 430 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 431 DELAY(1); 432 SIO_SET(NGE_MEAR_MII_CLK); 433 DELAY(1); 434 435 /* Turn off xmit. */ 436 SIO_CLR(NGE_MEAR_MII_DIR); 437 /* Check for ack */ 438 SIO_CLR(NGE_MEAR_MII_CLK); 439 DELAY(1); 440 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 441 SIO_SET(NGE_MEAR_MII_CLK); 442 DELAY(1); 443 444 /* 445 * Now try reading data bits. If the ack failed, we still 446 * need to clock through 16 cycles to keep the PHY(s) in sync. 447 */ 448 if (ack) { 449 for(i = 0; i < 16; i++) { 450 SIO_CLR(NGE_MEAR_MII_CLK); 451 DELAY(1); 452 SIO_SET(NGE_MEAR_MII_CLK); 453 DELAY(1); 454 } 455 goto fail; 456 } 457 458 for (i = 0x8000; i; i >>= 1) { 459 SIO_CLR(NGE_MEAR_MII_CLK); 460 DELAY(1); 461 if (!ack) { 462 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 463 frame->mii_data |= i; 464 DELAY(1); 465 } 466 SIO_SET(NGE_MEAR_MII_CLK); 467 DELAY(1); 468 } 469 470 fail: 471 472 SIO_CLR(NGE_MEAR_MII_CLK); 473 DELAY(1); 474 SIO_SET(NGE_MEAR_MII_CLK); 475 DELAY(1); 476 477 splx(s); 478 479 if (ack) 480 return(1); 481 return(0); 482 } 483 484 /* 485 * Write to a PHY register through the MII. 486 */ 487 int 488 nge_mii_writereg(sc, frame) 489 struct nge_softc *sc; 490 struct nge_mii_frame *frame; 491 { 492 int s; 493 494 s = splnet(); 495 /* 496 * Set up frame for TX. 497 */ 498 499 frame->mii_stdelim = NGE_MII_STARTDELIM; 500 frame->mii_opcode = NGE_MII_WRITEOP; 501 frame->mii_turnaround = NGE_MII_TURNAROUND; 502 503 /* 504 * Turn on data output. 505 */ 506 SIO_SET(NGE_MEAR_MII_DIR); 507 508 nge_mii_sync(sc); 509 510 nge_mii_send(sc, frame->mii_stdelim, 2); 511 nge_mii_send(sc, frame->mii_opcode, 2); 512 nge_mii_send(sc, frame->mii_phyaddr, 5); 513 nge_mii_send(sc, frame->mii_regaddr, 5); 514 nge_mii_send(sc, frame->mii_turnaround, 2); 515 nge_mii_send(sc, frame->mii_data, 16); 516 517 /* Idle bit. */ 518 SIO_SET(NGE_MEAR_MII_CLK); 519 DELAY(1); 520 SIO_CLR(NGE_MEAR_MII_CLK); 521 DELAY(1); 522 523 /* 524 * Turn off xmit. 525 */ 526 SIO_CLR(NGE_MEAR_MII_DIR); 527 528 splx(s); 529 530 return(0); 531 } 532 533 int 534 nge_miibus_readreg(dev, phy, reg) 535 struct device *dev; 536 int phy, reg; 537 { 538 struct nge_softc *sc = (struct nge_softc *)dev; 539 struct nge_mii_frame frame; 540 541 DPRINTFN(9, ("%s: nge_miibus_readreg\n", sc->sc_dv.dv_xname)); 542 543 bzero(&frame, sizeof(frame)); 544 545 frame.mii_phyaddr = phy; 546 frame.mii_regaddr = reg; 547 nge_mii_readreg(sc, &frame); 548 549 return(frame.mii_data); 550 } 551 552 void 553 nge_miibus_writereg(dev, phy, reg, data) 554 struct device *dev; 555 int phy, reg, data; 556 { 557 struct nge_softc *sc = (struct nge_softc *)dev; 558 struct nge_mii_frame frame; 559 560 561 DPRINTFN(9, ("%s: nge_miibus_writereg\n", sc->sc_dv.dv_xname)); 562 563 bzero(&frame, sizeof(frame)); 564 565 frame.mii_phyaddr = phy; 566 frame.mii_regaddr = reg; 567 frame.mii_data = data; 568 nge_mii_writereg(sc, &frame); 569 } 570 571 void 572 nge_miibus_statchg(dev) 573 struct device *dev; 574 { 575 struct nge_softc *sc = (struct nge_softc *)dev; 576 struct mii_data *mii = &sc->nge_mii; 577 u_int32_t txcfg, rxcfg; 578 579 txcfg = CSR_READ_4(sc, NGE_TX_CFG); 580 rxcfg = CSR_READ_4(sc, NGE_RX_CFG); 581 582 DPRINTFN(4, ("%s: nge_miibus_statchg txcfg=%#x, rxcfg=%#x\n", 583 sc->sc_dv.dv_xname, txcfg, rxcfg)); 584 585 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 586 txcfg |= (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR); 587 rxcfg |= (NGE_RXCFG_RX_FDX); 588 } else { 589 txcfg &= ~(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR); 590 rxcfg &= ~(NGE_RXCFG_RX_FDX); 591 } 592 593 txcfg |= NGE_TXCFG_AUTOPAD; 594 595 CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); 596 CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); 597 598 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 599 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 600 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 601 else 602 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 603 } 604 605 void 606 nge_setmulti(sc) 607 struct nge_softc *sc; 608 { 609 struct arpcom *ac = &sc->arpcom; 610 struct ifnet *ifp = &ac->ac_if; 611 struct ether_multi *enm; 612 struct ether_multistep step; 613 u_int32_t h = 0, i, filtsave; 614 int bit, index; 615 616 allmulti: 617 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 618 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 619 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 620 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 621 return; 622 } 623 624 /* 625 * We have to explicitly enable the multicast hash table 626 * on the NatSemi chip if we want to use it, which we do. 627 * We also have to tell it that we don't want to use the 628 * hash table for matching unicast addresses. 629 */ 630 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 631 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 632 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 633 634 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 635 636 /* first, zot all the existing hash bits */ 637 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 638 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 639 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 640 } 641 642 /* 643 * From the 11 bits returned by the crc routine, the top 7 644 * bits represent the 16-bit word in the mcast hash table 645 * that needs to be updated, and the lower 4 bits represent 646 * which bit within that byte needs to be set. 647 */ 648 ETHER_FIRST_MULTI(step, ac, enm); 649 while (enm != NULL) { 650 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 651 ifp->if_flags |= IFF_ALLMULTI; 652 goto allmulti; 653 } 654 h = (ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 21) & 655 0x00000FFF; 656 index = (h >> 4) & 0x7F; 657 bit = h & 0xF; 658 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 659 NGE_FILTADDR_MCAST_LO + (index * 2)); 660 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 661 ETHER_NEXT_MULTI(step, enm); 662 } 663 664 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 665 } 666 667 void 668 nge_reset(sc) 669 struct nge_softc *sc; 670 { 671 int i; 672 673 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 674 675 for (i = 0; i < NGE_TIMEOUT; i++) { 676 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 677 break; 678 } 679 680 if (i == NGE_TIMEOUT) 681 printf("%s: reset never completed\n", sc->sc_dv.dv_xname); 682 683 /* Wait a little while for the chip to get its brains in order. */ 684 DELAY(1000); 685 686 /* 687 * If this is a NetSemi chip, make sure to clear 688 * PME mode. 689 */ 690 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 691 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 692 } 693 694 /* 695 * Probe for an NatSemi chip. Check the PCI vendor and device 696 * IDs against our list and return a device name if we find a match. 697 */ 698 int 699 nge_probe(parent, match, aux) 700 struct device *parent; 701 void *match; 702 void *aux; 703 { 704 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 705 706 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 707 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_DP83820) 708 return (1); 709 710 return (0); 711 } 712 713 /* 714 * Attach the interface. Allocate softc structures, do ifmedia 715 * setup and ethernet/BPF attach. 716 */ 717 void 718 nge_attach(parent, self, aux) 719 struct device *parent, *self; 720 void *aux; 721 { 722 struct nge_softc *sc = (struct nge_softc *)self; 723 struct pci_attach_args *pa = aux; 724 pci_chipset_tag_t pc = pa->pa_pc; 725 pci_intr_handle_t ih; 726 const char *intrstr = NULL; 727 bus_size_t size; 728 bus_dma_segment_t seg; 729 bus_dmamap_t dmamap; 730 int rseg; 731 u_char eaddr[ETHER_ADDR_LEN]; 732 #ifndef NGE_USEIOSPACE 733 pcireg_t memtype; 734 #endif 735 struct ifnet *ifp; 736 caddr_t kva; 737 738 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 739 740 /* 741 * Map control/status registers. 742 */ 743 DPRINTFN(5, ("%s: map control/status regs\n", sc->sc_dv.dv_xname)); 744 745 #ifdef NGE_USEIOSPACE 746 DPRINTFN(5, ("%s: pci_mapreg_map\n", sc->sc_dv.dv_xname)); 747 if (pci_mapreg_map(pa, NGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 748 &sc->nge_btag, &sc->nge_bhandle, NULL, &size, 0)) { 749 printf(": can't map i/o space\n"); 750 return; 751 } 752 #else 753 DPRINTFN(5, ("%s: pci_mapreg_map\n", sc->sc_dv.dv_xname)); 754 memtype = pci_mapreg_type(pc, pa->pa_tag, NGE_PCI_LOMEM); 755 if (pci_mapreg_map(pa, NGE_PCI_LOMEM, memtype, 0, &sc->nge_btag, 756 &sc->nge_bhandle, NULL, &size, 0)) { 757 printf(": can't map mem space\n"); 758 return; 759 } 760 #endif 761 762 /* Disable all interrupts */ 763 CSR_WRITE_4(sc, NGE_IER, 0); 764 765 DPRINTFN(5, ("%s: pci_intr_map\n", sc->sc_dv.dv_xname)); 766 if (pci_intr_map(pa, &ih)) { 767 printf(": couldn't map interrupt\n"); 768 goto fail_1; 769 } 770 771 DPRINTFN(5, ("%s: pci_intr_string\n", sc->sc_dv.dv_xname)); 772 intrstr = pci_intr_string(pc, ih); 773 DPRINTFN(5, ("%s: pci_intr_establish\n", sc->sc_dv.dv_xname)); 774 sc->nge_intrhand = pci_intr_establish(pc, ih, IPL_NET, nge_intr, sc, 775 sc->sc_dv.dv_xname); 776 if (sc->nge_intrhand == NULL) { 777 printf(": couldn't establish interrupt"); 778 if (intrstr != NULL) 779 printf(" at %s", intrstr); 780 printf("\n"); 781 goto fail_1; 782 } 783 printf(": %s", intrstr); 784 785 /* Reset the adapter. */ 786 DPRINTFN(5, ("%s: nge_reset\n", sc->sc_dv.dv_xname)); 787 nge_reset(sc); 788 789 /* 790 * Get station address from the EEPROM. 791 */ 792 DPRINTFN(5, ("%s: nge_read_eeprom\n", sc->sc_dv.dv_xname)); 793 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 794 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 795 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 796 797 /* 798 * A NatSemi chip was detected. Inform the world. 799 */ 800 printf(", address %s\n", ether_sprintf(eaddr)); 801 802 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 803 804 sc->sc_dmatag = pa->pa_dmat; 805 DPRINTFN(5, ("%s: bus_dmamem_alloc\n", sc->sc_dv.dv_xname)); 806 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct nge_list_data), 807 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT | 808 BUS_DMA_ZERO)) { 809 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 810 goto fail_2; 811 } 812 DPRINTFN(5, ("%s: bus_dmamem_map\n", sc->sc_dv.dv_xname)); 813 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 814 sizeof(struct nge_list_data), &kva, 815 BUS_DMA_NOWAIT)) { 816 printf("%s: can't map dma buffers (%d bytes)\n", 817 sc->sc_dv.dv_xname, sizeof(struct nge_list_data)); 818 goto fail_3; 819 } 820 DPRINTFN(5, ("%s: bus_dmamem_create\n", sc->sc_dv.dv_xname)); 821 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct nge_list_data), 1, 822 sizeof(struct nge_list_data), 0, 823 BUS_DMA_NOWAIT, &dmamap)) { 824 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 825 goto fail_4; 826 } 827 DPRINTFN(5, ("%s: bus_dmamem_load\n", sc->sc_dv.dv_xname)); 828 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, 829 sizeof(struct nge_list_data), NULL, 830 BUS_DMA_NOWAIT)) { 831 goto fail_5; 832 } 833 834 DPRINTFN(5, ("%s: bzero\n", sc->sc_dv.dv_xname)); 835 sc->nge_ldata = (struct nge_list_data *)kva; 836 837 /* Try to allocate memory for jumbo buffers. */ 838 DPRINTFN(5, ("%s: nge_alloc_jumbo_mem\n", sc->sc_dv.dv_xname)); 839 if (nge_alloc_jumbo_mem(sc)) { 840 printf("%s: jumbo buffer allocation failed\n", 841 sc->sc_dv.dv_xname); 842 goto fail_5; 843 } 844 845 ifp = &sc->arpcom.ac_if; 846 ifp->if_softc = sc; 847 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 848 ifp->if_ioctl = nge_ioctl; 849 ifp->if_start = nge_start; 850 ifp->if_watchdog = nge_watchdog; 851 ifp->if_hardmtu = NGE_JUMBO_MTU; 852 IFQ_SET_MAXLEN(&ifp->if_snd, NGE_TX_LIST_CNT - 1); 853 IFQ_SET_READY(&ifp->if_snd); 854 DPRINTFN(5, ("%s: bcopy\n", sc->sc_dv.dv_xname)); 855 bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ); 856 857 ifp->if_capabilities = IFCAP_VLAN_MTU; 858 859 #if NVLAN > 0 860 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 861 #endif 862 863 /* 864 * Do MII setup. 865 */ 866 DPRINTFN(5, ("%s: mii setup\n", sc->sc_dv.dv_xname)); 867 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 868 DPRINTFN(5, ("%s: TBI mode\n", sc->sc_dv.dv_xname)); 869 sc->nge_tbi = 1; 870 871 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_tbi_upd, 872 nge_ifmedia_tbi_sts); 873 874 ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_NONE, 0, NULL), 875 ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 876 ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 877 0, NULL); 878 ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 879 880 ifmedia_set(&sc->nge_ifmedia, IFM_ETHER|IFM_AUTO); 881 882 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 883 | NGE_GPIO_GP4_OUT 884 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 885 | NGE_GPIO_GP3_OUTENB | NGE_GPIO_GP4_OUTENB 886 | NGE_GPIO_GP5_OUTENB); 887 888 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 889 } else { 890 sc->nge_mii.mii_ifp = ifp; 891 sc->nge_mii.mii_readreg = nge_miibus_readreg; 892 sc->nge_mii.mii_writereg = nge_miibus_writereg; 893 sc->nge_mii.mii_statchg = nge_miibus_statchg; 894 895 ifmedia_init(&sc->nge_mii.mii_media, 0, nge_ifmedia_mii_upd, 896 nge_ifmedia_mii_sts); 897 mii_attach(&sc->sc_dv, &sc->nge_mii, 0xffffffff, MII_PHY_ANY, 898 MII_OFFSET_ANY, 0); 899 900 if (LIST_FIRST(&sc->nge_mii.mii_phys) == NULL) { 901 902 printf("%s: no PHY found!\n", sc->sc_dv.dv_xname); 903 ifmedia_add(&sc->nge_mii.mii_media, 904 IFM_ETHER|IFM_MANUAL, 0, NULL); 905 ifmedia_set(&sc->nge_mii.mii_media, 906 IFM_ETHER|IFM_MANUAL); 907 } 908 else 909 ifmedia_set(&sc->nge_mii.mii_media, 910 IFM_ETHER|IFM_AUTO); 911 } 912 913 /* 914 * Call MI attach routine. 915 */ 916 DPRINTFN(5, ("%s: if_attach\n", sc->sc_dv.dv_xname)); 917 if_attach(ifp); 918 DPRINTFN(5, ("%s: ether_ifattach\n", sc->sc_dv.dv_xname)); 919 ether_ifattach(ifp); 920 DPRINTFN(5, ("%s: timeout_set\n", sc->sc_dv.dv_xname)); 921 timeout_set(&sc->nge_timeout, nge_tick, sc); 922 timeout_add_sec(&sc->nge_timeout, 1); 923 return; 924 925 fail_5: 926 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 927 928 fail_4: 929 bus_dmamem_unmap(sc->sc_dmatag, kva, 930 sizeof(struct nge_list_data)); 931 932 fail_3: 933 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 934 935 fail_2: 936 pci_intr_disestablish(pc, sc->nge_intrhand); 937 938 fail_1: 939 bus_space_unmap(sc->nge_btag, sc->nge_bhandle, size); 940 } 941 942 /* 943 * Initialize the transmit descriptors. 944 */ 945 int 946 nge_list_tx_init(sc) 947 struct nge_softc *sc; 948 { 949 struct nge_list_data *ld; 950 struct nge_ring_data *cd; 951 int i; 952 953 cd = &sc->nge_cdata; 954 ld = sc->nge_ldata; 955 956 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 957 if (i == (NGE_TX_LIST_CNT - 1)) { 958 ld->nge_tx_list[i].nge_nextdesc = 959 &ld->nge_tx_list[0]; 960 ld->nge_tx_list[i].nge_next = 961 VTOPHYS(&ld->nge_tx_list[0]); 962 } else { 963 ld->nge_tx_list[i].nge_nextdesc = 964 &ld->nge_tx_list[i + 1]; 965 ld->nge_tx_list[i].nge_next = 966 VTOPHYS(&ld->nge_tx_list[i + 1]); 967 } 968 ld->nge_tx_list[i].nge_mbuf = NULL; 969 ld->nge_tx_list[i].nge_ptr = 0; 970 ld->nge_tx_list[i].nge_ctl = 0; 971 } 972 973 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 974 975 return(0); 976 } 977 978 979 /* 980 * Initialize the RX descriptors and allocate mbufs for them. Note that 981 * we arrange the descriptors in a closed ring, so that the last descriptor 982 * points back to the first. 983 */ 984 int 985 nge_list_rx_init(sc) 986 struct nge_softc *sc; 987 { 988 struct nge_list_data *ld; 989 struct nge_ring_data *cd; 990 int i; 991 992 ld = sc->nge_ldata; 993 cd = &sc->nge_cdata; 994 995 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 996 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 997 return(ENOBUFS); 998 if (i == (NGE_RX_LIST_CNT - 1)) { 999 ld->nge_rx_list[i].nge_nextdesc = 1000 &ld->nge_rx_list[0]; 1001 ld->nge_rx_list[i].nge_next = 1002 VTOPHYS(&ld->nge_rx_list[0]); 1003 } else { 1004 ld->nge_rx_list[i].nge_nextdesc = 1005 &ld->nge_rx_list[i + 1]; 1006 ld->nge_rx_list[i].nge_next = 1007 VTOPHYS(&ld->nge_rx_list[i + 1]); 1008 } 1009 } 1010 1011 cd->nge_rx_prod = 0; 1012 1013 return(0); 1014 } 1015 1016 /* 1017 * Initialize an RX descriptor and attach an MBUF cluster. 1018 */ 1019 int 1020 nge_newbuf(sc, c, m) 1021 struct nge_softc *sc; 1022 struct nge_desc *c; 1023 struct mbuf *m; 1024 { 1025 struct mbuf *m_new = NULL; 1026 1027 if (m == NULL) { 1028 caddr_t buf = NULL; 1029 1030 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1031 if (m_new == NULL) 1032 return (ENOBUFS); 1033 1034 /* Allocate the jumbo buffer */ 1035 buf = nge_jalloc(sc); 1036 if (buf == NULL) { 1037 m_freem(m_new); 1038 return (ENOBUFS); 1039 } 1040 1041 /* Attach the buffer to the mbuf */ 1042 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1043 MEXTADD(m_new, buf, NGE_MCLBYTES, 0, nge_jfree, sc); 1044 } else { 1045 /* 1046 * We're re-using a previously allocated mbuf; 1047 * be sure to re-init pointers and lengths to 1048 * default values. 1049 */ 1050 m_new = m; 1051 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1052 m_new->m_data = m_new->m_ext.ext_buf; 1053 } 1054 1055 m_adj(m_new, sizeof(u_int64_t)); 1056 1057 c->nge_mbuf = m_new; 1058 c->nge_ptr = VTOPHYS(mtod(m_new, caddr_t)); 1059 DPRINTFN(7,("%s: c->nge_ptr=%#x\n", sc->sc_dv.dv_xname, 1060 c->nge_ptr)); 1061 c->nge_ctl = m_new->m_len; 1062 c->nge_extsts = 0; 1063 1064 return(0); 1065 } 1066 1067 int 1068 nge_alloc_jumbo_mem(sc) 1069 struct nge_softc *sc; 1070 { 1071 caddr_t ptr, kva; 1072 bus_dma_segment_t seg; 1073 bus_dmamap_t dmamap; 1074 int i, rseg, state, error; 1075 struct nge_jpool_entry *entry; 1076 1077 state = error = 0; 1078 1079 if (bus_dmamem_alloc(sc->sc_dmatag, NGE_JMEM, PAGE_SIZE, 0, 1080 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1081 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 1082 return (ENOBUFS); 1083 } 1084 1085 state = 1; 1086 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, NGE_JMEM, &kva, 1087 BUS_DMA_NOWAIT)) { 1088 printf("%s: can't map dma buffers (%d bytes)\n", 1089 sc->sc_dv.dv_xname, NGE_JMEM); 1090 error = ENOBUFS; 1091 goto out; 1092 } 1093 1094 state = 2; 1095 if (bus_dmamap_create(sc->sc_dmatag, NGE_JMEM, 1, 1096 NGE_JMEM, 0, BUS_DMA_NOWAIT, &dmamap)) { 1097 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 1098 error = ENOBUFS; 1099 goto out; 1100 } 1101 1102 state = 3; 1103 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, NGE_JMEM, 1104 NULL, BUS_DMA_NOWAIT)) { 1105 printf("%s: can't load dma map\n", sc->sc_dv.dv_xname); 1106 error = ENOBUFS; 1107 goto out; 1108 } 1109 1110 state = 4; 1111 sc->nge_cdata.nge_jumbo_buf = (caddr_t)kva; 1112 DPRINTFN(1,("%s: nge_jumbo_buf=%#x, NGE_MCLBYTES=%#x\n", 1113 sc->sc_dv.dv_xname , sc->nge_cdata.nge_jumbo_buf, 1114 NGE_MCLBYTES)); 1115 1116 LIST_INIT(&sc->nge_jfree_listhead); 1117 LIST_INIT(&sc->nge_jinuse_listhead); 1118 1119 /* 1120 * Now divide it up into 9K pieces and save the addresses 1121 * in an array. Note that we play an evil trick here by using 1122 * the first few bytes in the buffer to hold the address 1123 * of the softc structure for this interface. This is because 1124 * nge_jfree() needs it, but it is called by the mbuf management 1125 * code which will not pass it to us explicitly. 1126 */ 1127 ptr = sc->nge_cdata.nge_jumbo_buf; 1128 for (i = 0; i < NGE_JSLOTS; i++) { 1129 sc->nge_cdata.nge_jslots[i].nge_buf = ptr; 1130 sc->nge_cdata.nge_jslots[i].nge_inuse = 0; 1131 ptr += NGE_MCLBYTES; 1132 entry = malloc(sizeof(struct nge_jpool_entry), 1133 M_DEVBUF, M_NOWAIT); 1134 if (entry == NULL) { 1135 sc->nge_cdata.nge_jumbo_buf = NULL; 1136 printf("%s: no memory for jumbo buffer queue!\n", 1137 sc->sc_dv.dv_xname); 1138 error = ENOBUFS; 1139 goto out; 1140 } 1141 entry->slot = i; 1142 LIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, 1143 jpool_entries); 1144 } 1145 out: 1146 if (error != 0) { 1147 switch (state) { 1148 case 4: 1149 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1150 case 3: 1151 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1152 case 2: 1153 bus_dmamem_unmap(sc->sc_dmatag, kva, NGE_JMEM); 1154 case 1: 1155 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1156 break; 1157 default: 1158 break; 1159 } 1160 } 1161 1162 return (error); 1163 } 1164 1165 /* 1166 * Allocate a jumbo buffer. 1167 */ 1168 void * 1169 nge_jalloc(sc) 1170 struct nge_softc *sc; 1171 { 1172 struct nge_jpool_entry *entry; 1173 1174 entry = LIST_FIRST(&sc->nge_jfree_listhead); 1175 1176 if (entry == NULL) 1177 return (NULL); 1178 1179 LIST_REMOVE(entry, jpool_entries); 1180 LIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1181 sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1; 1182 return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf); 1183 } 1184 1185 /* 1186 * Release a jumbo buffer. 1187 */ 1188 void 1189 nge_jfree(buf, size, arg) 1190 caddr_t buf; 1191 u_int size; 1192 void *arg; 1193 { 1194 struct nge_softc *sc; 1195 int i; 1196 struct nge_jpool_entry *entry; 1197 1198 /* Extract the softc struct pointer. */ 1199 sc = (struct nge_softc *)arg; 1200 1201 if (sc == NULL) 1202 panic("nge_jfree: can't find softc pointer!"); 1203 1204 /* calculate the slot this buffer belongs to */ 1205 1206 i = ((vaddr_t)buf - (vaddr_t)sc->nge_cdata.nge_jumbo_buf) 1207 / NGE_MCLBYTES; 1208 1209 if ((i < 0) || (i >= NGE_JSLOTS)) 1210 panic("nge_jfree: asked to free buffer that we don't manage!"); 1211 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0) 1212 panic("nge_jfree: buffer already free!"); 1213 else { 1214 sc->nge_cdata.nge_jslots[i].nge_inuse--; 1215 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) { 1216 entry = LIST_FIRST(&sc->nge_jinuse_listhead); 1217 if (entry == NULL) 1218 panic("nge_jfree: buffer not in use!"); 1219 entry->slot = i; 1220 LIST_REMOVE(entry, jpool_entries); 1221 LIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1222 entry, jpool_entries); 1223 } 1224 } 1225 } 1226 1227 /* 1228 * A frame has been uploaded: pass the resulting mbuf chain up to 1229 * the higher level protocols. 1230 */ 1231 void 1232 nge_rxeof(sc) 1233 struct nge_softc *sc; 1234 { 1235 struct mbuf *m; 1236 struct ifnet *ifp; 1237 struct nge_desc *cur_rx; 1238 int i, total_len = 0; 1239 u_int32_t rxstat; 1240 1241 ifp = &sc->arpcom.ac_if; 1242 i = sc->nge_cdata.nge_rx_prod; 1243 1244 while (NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1245 struct mbuf *m0 = NULL; 1246 u_int32_t extsts; 1247 1248 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1249 rxstat = cur_rx->nge_rxstat; 1250 extsts = cur_rx->nge_extsts; 1251 m = cur_rx->nge_mbuf; 1252 cur_rx->nge_mbuf = NULL; 1253 total_len = NGE_RXBYTES(cur_rx); 1254 NGE_INC(i, NGE_RX_LIST_CNT); 1255 1256 /* 1257 * If an error occurs, update stats, clear the 1258 * status word and leave the mbuf cluster in place: 1259 * it should simply get re-used next time this descriptor 1260 * comes up in the ring. 1261 */ 1262 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1263 #if NVLAN > 0 1264 if ((rxstat & NGE_RXSTAT_RUNT) && 1265 total_len >= (ETHER_MIN_LEN - ETHER_CRC_LEN - 1266 ETHER_VLAN_ENCAP_LEN)) { 1267 /* 1268 * Workaround a hardware bug. Accept runt 1269 * frames if its length is larger than or 1270 * equal to 56. 1271 */ 1272 } else { 1273 #endif 1274 ifp->if_ierrors++; 1275 nge_newbuf(sc, cur_rx, m); 1276 continue; 1277 #if NVLAN > 0 1278 } 1279 #endif 1280 } 1281 1282 /* 1283 * Ok. NatSemi really screwed up here. This is the 1284 * only gigE chip I know of with alignment constraints 1285 * on receive buffers. RX buffers must be 64-bit aligned. 1286 */ 1287 #ifndef __STRICT_ALIGNMENT 1288 /* 1289 * By popular demand, ignore the alignment problems 1290 * on the Intel x86 platform. The performance hit 1291 * incurred due to unaligned accesses is much smaller 1292 * than the hit produced by forcing buffer copies all 1293 * the time, especially with jumbo frames. We still 1294 * need to fix up the alignment everywhere else though. 1295 */ 1296 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1297 #endif 1298 m0 = m_devget(mtod(m, char *), total_len, 1299 ETHER_ALIGN, ifp, NULL); 1300 nge_newbuf(sc, cur_rx, m); 1301 if (m0 == NULL) { 1302 ifp->if_ierrors++; 1303 continue; 1304 } 1305 m_adj(m0, ETHER_ALIGN); 1306 m = m0; 1307 #ifndef __STRICT_ALIGNMENT 1308 } else { 1309 m->m_pkthdr.rcvif = ifp; 1310 m->m_pkthdr.len = m->m_len = total_len; 1311 } 1312 #endif 1313 1314 ifp->if_ipackets++; 1315 1316 #if NVLAN > 0 1317 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1318 m->m_pkthdr.ether_vtag = 1319 ntohs(extsts & NGE_RXEXTSTS_VTCI); 1320 m->m_flags |= M_VLANTAG; 1321 } 1322 #endif 1323 1324 #if NBPFILTER > 0 1325 /* 1326 * Handle BPF listeners. Let the BPF user see the packet. 1327 */ 1328 if (ifp->if_bpf) 1329 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1330 #endif 1331 1332 /* Do IP checksum checking. */ 1333 if (extsts & NGE_RXEXTSTS_IPPKT) { 1334 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1335 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1336 if ((extsts & NGE_RXEXTSTS_TCPPKT) && 1337 (!(extsts & NGE_RXEXTSTS_TCPCSUMERR))) 1338 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 1339 else if ((extsts & NGE_RXEXTSTS_UDPPKT) && 1340 (!(extsts & NGE_RXEXTSTS_UDPCSUMERR))) 1341 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 1342 } 1343 1344 ether_input_mbuf(ifp, m); 1345 } 1346 1347 sc->nge_cdata.nge_rx_prod = i; 1348 } 1349 1350 /* 1351 * A frame was downloaded to the chip. It's safe for us to clean up 1352 * the list buffers. 1353 */ 1354 1355 void 1356 nge_txeof(sc) 1357 struct nge_softc *sc; 1358 { 1359 struct nge_desc *cur_tx; 1360 struct ifnet *ifp; 1361 u_int32_t idx; 1362 1363 ifp = &sc->arpcom.ac_if; 1364 1365 /* 1366 * Go through our tx list and free mbufs for those 1367 * frames that have been transmitted. 1368 */ 1369 idx = sc->nge_cdata.nge_tx_cons; 1370 while (idx != sc->nge_cdata.nge_tx_prod) { 1371 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1372 1373 if (NGE_OWNDESC(cur_tx)) 1374 break; 1375 1376 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1377 sc->nge_cdata.nge_tx_cnt--; 1378 NGE_INC(idx, NGE_TX_LIST_CNT); 1379 continue; 1380 } 1381 1382 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1383 ifp->if_oerrors++; 1384 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1385 ifp->if_collisions++; 1386 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1387 ifp->if_collisions++; 1388 } 1389 1390 ifp->if_collisions += 1391 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1392 1393 ifp->if_opackets++; 1394 if (cur_tx->nge_mbuf != NULL) { 1395 m_freem(cur_tx->nge_mbuf); 1396 cur_tx->nge_mbuf = NULL; 1397 ifp->if_flags &= ~IFF_OACTIVE; 1398 } 1399 1400 sc->nge_cdata.nge_tx_cnt--; 1401 NGE_INC(idx, NGE_TX_LIST_CNT); 1402 } 1403 1404 sc->nge_cdata.nge_tx_cons = idx; 1405 1406 if (idx == sc->nge_cdata.nge_tx_prod) 1407 ifp->if_timer = 0; 1408 } 1409 1410 void 1411 nge_tick(xsc) 1412 void *xsc; 1413 { 1414 struct nge_softc *sc = xsc; 1415 struct mii_data *mii = &sc->nge_mii; 1416 struct ifnet *ifp = &sc->arpcom.ac_if; 1417 int s; 1418 1419 s = splnet(); 1420 1421 DPRINTFN(10, ("%s: nge_tick: link=%d\n", sc->sc_dv.dv_xname, 1422 sc->nge_link)); 1423 1424 timeout_add_sec(&sc->nge_timeout, 1); 1425 if (sc->nge_link) { 1426 splx(s); 1427 return; 1428 } 1429 1430 if (sc->nge_tbi) { 1431 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1432 == IFM_AUTO) { 1433 u_int32_t bmsr, anlpar, txcfg, rxcfg; 1434 1435 bmsr = CSR_READ_4(sc, NGE_TBI_BMSR); 1436 DPRINTFN(2, ("%s: nge_tick: bmsr=%#x\n", 1437 sc->sc_dv.dv_xname, bmsr)); 1438 1439 if (!(bmsr & NGE_TBIBMSR_ANEG_DONE)) { 1440 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1441 1442 splx(s); 1443 return; 1444 } 1445 1446 anlpar = CSR_READ_4(sc, NGE_TBI_ANLPAR); 1447 txcfg = CSR_READ_4(sc, NGE_TX_CFG); 1448 rxcfg = CSR_READ_4(sc, NGE_RX_CFG); 1449 1450 DPRINTFN(2, ("%s: nge_tick: anlpar=%#x, txcfg=%#x, " 1451 "rxcfg=%#x\n", sc->sc_dv.dv_xname, anlpar, 1452 txcfg, rxcfg)); 1453 1454 if (anlpar == 0 || anlpar & NGE_TBIANAR_FDX) { 1455 txcfg |= (NGE_TXCFG_IGN_HBEAT| 1456 NGE_TXCFG_IGN_CARR); 1457 rxcfg |= NGE_RXCFG_RX_FDX; 1458 } else { 1459 txcfg &= ~(NGE_TXCFG_IGN_HBEAT| 1460 NGE_TXCFG_IGN_CARR); 1461 rxcfg &= ~(NGE_RXCFG_RX_FDX); 1462 } 1463 txcfg |= NGE_TXCFG_AUTOPAD; 1464 CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); 1465 CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); 1466 } 1467 1468 DPRINTF(("%s: gigabit link up\n", sc->sc_dv.dv_xname)); 1469 sc->nge_link++; 1470 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1471 nge_start(ifp); 1472 } else { 1473 mii_tick(mii); 1474 if (mii->mii_media_status & IFM_ACTIVE && 1475 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1476 sc->nge_link++; 1477 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1478 DPRINTF(("%s: gigabit link up\n", 1479 sc->sc_dv.dv_xname)); 1480 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1481 nge_start(ifp); 1482 } 1483 1484 } 1485 1486 splx(s); 1487 } 1488 1489 int 1490 nge_intr(arg) 1491 void *arg; 1492 { 1493 struct nge_softc *sc; 1494 struct ifnet *ifp; 1495 u_int32_t status; 1496 int claimed = 0; 1497 1498 sc = arg; 1499 ifp = &sc->arpcom.ac_if; 1500 1501 /* Suppress unwanted interrupts */ 1502 if (!(ifp->if_flags & IFF_UP)) { 1503 nge_stop(sc); 1504 return (0); 1505 } 1506 1507 /* Disable interrupts. */ 1508 CSR_WRITE_4(sc, NGE_IER, 0); 1509 1510 /* Data LED on for TBI mode */ 1511 if(sc->nge_tbi) 1512 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1513 | NGE_GPIO_GP3_OUT); 1514 1515 for (;;) { 1516 /* Reading the ISR register clears all interrupts. */ 1517 status = CSR_READ_4(sc, NGE_ISR); 1518 1519 if ((status & NGE_INTRS) == 0) 1520 break; 1521 1522 claimed = 1; 1523 1524 if ((status & NGE_ISR_TX_DESC_OK) || 1525 (status & NGE_ISR_TX_ERR) || 1526 (status & NGE_ISR_TX_OK) || 1527 (status & NGE_ISR_TX_IDLE)) 1528 nge_txeof(sc); 1529 1530 if ((status & NGE_ISR_RX_DESC_OK) || 1531 (status & NGE_ISR_RX_ERR) || 1532 (status & NGE_ISR_RX_OFLOW) || 1533 (status & NGE_ISR_RX_FIFO_OFLOW) || 1534 (status & NGE_ISR_RX_IDLE) || 1535 (status & NGE_ISR_RX_OK)) 1536 nge_rxeof(sc); 1537 1538 if ((status & NGE_ISR_RX_IDLE)) 1539 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1540 1541 if (status & NGE_ISR_SYSERR) { 1542 nge_reset(sc); 1543 ifp->if_flags &= ~IFF_RUNNING; 1544 nge_init(sc); 1545 } 1546 1547 #if 0 1548 /* 1549 * XXX: nge_tick() is not ready to be called this way 1550 * it screws up the aneg timeout because mii_tick() is 1551 * only to be called once per second. 1552 */ 1553 if (status & NGE_IMR_PHY_INTR) { 1554 sc->nge_link = 0; 1555 nge_tick(sc); 1556 } 1557 #endif 1558 } 1559 1560 /* Re-enable interrupts. */ 1561 CSR_WRITE_4(sc, NGE_IER, 1); 1562 1563 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1564 nge_start(ifp); 1565 1566 /* Data LED off for TBI mode */ 1567 if(sc->nge_tbi) 1568 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1569 & ~NGE_GPIO_GP3_OUT); 1570 1571 return claimed; 1572 } 1573 1574 /* 1575 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1576 * pointers to the fragment pointers. 1577 */ 1578 int 1579 nge_encap(sc, m_head, txidx) 1580 struct nge_softc *sc; 1581 struct mbuf *m_head; 1582 u_int32_t *txidx; 1583 { 1584 struct nge_desc *f = NULL; 1585 struct mbuf *m; 1586 int frag, cur, cnt = 0; 1587 1588 /* 1589 * Start packing the mbufs in this chain into 1590 * the fragment pointers. Stop when we run out 1591 * of fragments or hit the end of the mbuf chain. 1592 */ 1593 m = m_head; 1594 cur = frag = *txidx; 1595 1596 for (m = m_head; m != NULL; m = m->m_next) { 1597 if (m->m_len != 0) { 1598 if ((NGE_TX_LIST_CNT - 1599 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1600 return(ENOBUFS); 1601 f = &sc->nge_ldata->nge_tx_list[frag]; 1602 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1603 f->nge_ptr = VTOPHYS(mtod(m, vaddr_t)); 1604 DPRINTFN(7,("%s: f->nge_ptr=%#x\n", 1605 sc->sc_dv.dv_xname, f->nge_ptr)); 1606 if (cnt != 0) 1607 f->nge_ctl |= NGE_CMDSTS_OWN; 1608 cur = frag; 1609 NGE_INC(frag, NGE_TX_LIST_CNT); 1610 cnt++; 1611 } 1612 } 1613 1614 if (m != NULL) 1615 return(ENOBUFS); 1616 1617 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1618 1619 #if NVLAN > 0 1620 if (m_head->m_flags & M_VLANTAG) { 1621 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1622 (NGE_TXEXTSTS_VLANPKT|htons(m_head->m_pkthdr.ether_vtag)); 1623 } 1624 #endif 1625 1626 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1627 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1628 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1629 sc->nge_cdata.nge_tx_cnt += cnt; 1630 *txidx = frag; 1631 1632 return(0); 1633 } 1634 1635 /* 1636 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1637 * to the mbuf data regions directly in the transmit lists. We also save a 1638 * copy of the pointers since the transmit list fragment pointers are 1639 * physical addresses. 1640 */ 1641 1642 void 1643 nge_start(ifp) 1644 struct ifnet *ifp; 1645 { 1646 struct nge_softc *sc; 1647 struct mbuf *m_head = NULL; 1648 u_int32_t idx; 1649 int pkts = 0; 1650 1651 sc = ifp->if_softc; 1652 1653 if (!sc->nge_link) 1654 return; 1655 1656 idx = sc->nge_cdata.nge_tx_prod; 1657 1658 if (ifp->if_flags & IFF_OACTIVE) 1659 return; 1660 1661 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1662 IFQ_POLL(&ifp->if_snd, m_head); 1663 if (m_head == NULL) 1664 break; 1665 1666 if (nge_encap(sc, m_head, &idx)) { 1667 ifp->if_flags |= IFF_OACTIVE; 1668 break; 1669 } 1670 1671 /* now we are committed to transmit the packet */ 1672 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1673 pkts++; 1674 1675 #if NBPFILTER > 0 1676 /* 1677 * If there's a BPF listener, bounce a copy of this frame 1678 * to him. 1679 */ 1680 if (ifp->if_bpf) 1681 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1682 #endif 1683 } 1684 if (pkts == 0) 1685 return; 1686 1687 /* Transmit */ 1688 sc->nge_cdata.nge_tx_prod = idx; 1689 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1690 1691 /* 1692 * Set a timeout in case the chip goes out to lunch. 1693 */ 1694 ifp->if_timer = 5; 1695 } 1696 1697 void 1698 nge_init(xsc) 1699 void *xsc; 1700 { 1701 struct nge_softc *sc = xsc; 1702 struct ifnet *ifp = &sc->arpcom.ac_if; 1703 struct mii_data *mii; 1704 u_int32_t txcfg, rxcfg; 1705 int s, media; 1706 1707 if (ifp->if_flags & IFF_RUNNING) 1708 return; 1709 1710 s = splnet(); 1711 1712 /* 1713 * Cancel pending I/O and free all RX/TX buffers. 1714 */ 1715 nge_stop(sc); 1716 1717 mii = sc->nge_tbi ? NULL: &sc->nge_mii; 1718 1719 /* Set MAC address */ 1720 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1721 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1722 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1723 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1724 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1725 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1726 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1727 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1728 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1729 1730 /* Init circular RX list. */ 1731 if (nge_list_rx_init(sc) == ENOBUFS) { 1732 printf("%s: initialization failed: no " 1733 "memory for rx buffers\n", sc->sc_dv.dv_xname); 1734 nge_stop(sc); 1735 splx(s); 1736 return; 1737 } 1738 1739 /* 1740 * Init tx descriptors. 1741 */ 1742 nge_list_tx_init(sc); 1743 1744 /* 1745 * For the NatSemi chip, we have to explicitly enable the 1746 * reception of ARP frames, as well as turn on the 'perfect 1747 * match' filter where we store the station address, otherwise 1748 * we won't receive unicasts meant for this host. 1749 */ 1750 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1751 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1752 1753 /* If we want promiscuous mode, set the allframes bit. */ 1754 if (ifp->if_flags & IFF_PROMISC) 1755 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1756 else 1757 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1758 1759 /* 1760 * Set the capture broadcast bit to capture broadcast frames. 1761 */ 1762 if (ifp->if_flags & IFF_BROADCAST) 1763 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1764 else 1765 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1766 1767 /* 1768 * Load the multicast filter. 1769 */ 1770 nge_setmulti(sc); 1771 1772 /* Turn the receive filter on */ 1773 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1774 1775 /* 1776 * Load the address of the RX and TX lists. 1777 */ 1778 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1779 VTOPHYS(&sc->nge_ldata->nge_rx_list[0])); 1780 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1781 VTOPHYS(&sc->nge_ldata->nge_tx_list[0])); 1782 1783 /* Set RX configuration */ 1784 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1785 1786 /* 1787 * Enable hardware checksum validation for all IPv4 1788 * packets, do not reject packets with bad checksums. 1789 */ 1790 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1791 1792 /* 1793 * If VLAN support is enabled, tell the chip to detect 1794 * and strip VLAN tag info from received frames. The tag 1795 * will be provided in the extsts field in the RX descriptors. 1796 */ 1797 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1798 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1799 NGE_VIPRXCTL_TAG_DETECT_ENB | NGE_VIPRXCTL_TAG_STRIP_ENB); 1800 1801 /* Set TX configuration */ 1802 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1803 1804 /* 1805 * If VLAN support is enabled, tell the chip to insert 1806 * VLAN tags on a per-packet basis as dictated by the 1807 * code in the frame encapsulation routine. 1808 */ 1809 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1810 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1811 1812 /* Set full/half duplex mode. */ 1813 if (sc->nge_tbi) 1814 media = sc->nge_ifmedia.ifm_cur->ifm_media; 1815 else 1816 media = mii->mii_media_active; 1817 1818 txcfg = CSR_READ_4(sc, NGE_TX_CFG); 1819 rxcfg = CSR_READ_4(sc, NGE_RX_CFG); 1820 1821 DPRINTFN(4, ("%s: nge_init txcfg=%#x, rxcfg=%#x\n", 1822 sc->sc_dv.dv_xname, txcfg, rxcfg)); 1823 1824 if ((media & IFM_GMASK) == IFM_FDX) { 1825 txcfg |= (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR); 1826 rxcfg |= (NGE_RXCFG_RX_FDX); 1827 } else { 1828 txcfg &= ~(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR); 1829 rxcfg &= ~(NGE_RXCFG_RX_FDX); 1830 } 1831 1832 txcfg |= NGE_TXCFG_AUTOPAD; 1833 1834 CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); 1835 CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); 1836 1837 nge_tick(sc); 1838 1839 /* 1840 * Enable the delivery of PHY interrupts based on 1841 * link/speed/duplex status changes and enable return 1842 * of extended status information in the DMA descriptors, 1843 * required for checksum offloading. 1844 */ 1845 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|NGE_CFG_PHYINTR_LNK| 1846 NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1847 1848 DPRINTFN(1, ("%s: nge_init: config=%#x\n", sc->sc_dv.dv_xname, 1849 CSR_READ_4(sc, NGE_CFG))); 1850 1851 /* 1852 * Configure interrupt holdoff (moderation). We can 1853 * have the chip delay interrupt delivery for a certain 1854 * period. Units are in 100us, and the max setting 1855 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1856 */ 1857 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1858 1859 /* 1860 * Enable interrupts. 1861 */ 1862 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1863 CSR_WRITE_4(sc, NGE_IER, 1); 1864 1865 /* Enable receiver and transmitter. */ 1866 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1867 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1868 1869 if (sc->nge_tbi) 1870 nge_ifmedia_tbi_upd(ifp); 1871 else 1872 nge_ifmedia_mii_upd(ifp); 1873 1874 ifp->if_flags |= IFF_RUNNING; 1875 ifp->if_flags &= ~IFF_OACTIVE; 1876 1877 splx(s); 1878 } 1879 1880 /* 1881 * Set mii media options. 1882 */ 1883 int 1884 nge_ifmedia_mii_upd(ifp) 1885 struct ifnet *ifp; 1886 { 1887 struct nge_softc *sc = ifp->if_softc; 1888 struct mii_data *mii = &sc->nge_mii; 1889 1890 DPRINTFN(2, ("%s: nge_ifmedia_mii_upd\n", sc->sc_dv.dv_xname)); 1891 1892 sc->nge_link = 0; 1893 1894 if (mii->mii_instance) { 1895 struct mii_softc *miisc; 1896 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1897 mii_phy_reset(miisc); 1898 } 1899 mii_mediachg(mii); 1900 1901 return(0); 1902 } 1903 1904 /* 1905 * Report current mii media status. 1906 */ 1907 void 1908 nge_ifmedia_mii_sts(ifp, ifmr) 1909 struct ifnet *ifp; 1910 struct ifmediareq *ifmr; 1911 { 1912 struct nge_softc *sc = ifp->if_softc; 1913 struct mii_data *mii = &sc->nge_mii; 1914 1915 DPRINTFN(2, ("%s: nge_ifmedia_mii_sts\n", sc->sc_dv.dv_xname)); 1916 1917 mii_pollstat(mii); 1918 ifmr->ifm_active = mii->mii_media_active; 1919 ifmr->ifm_status = mii->mii_media_status; 1920 } 1921 1922 /* 1923 * Set mii media options. 1924 */ 1925 int 1926 nge_ifmedia_tbi_upd(ifp) 1927 struct ifnet *ifp; 1928 { 1929 struct nge_softc *sc = ifp->if_softc; 1930 1931 DPRINTFN(2, ("%s: nge_ifmedia_tbi_upd\n", sc->sc_dv.dv_xname)); 1932 1933 sc->nge_link = 0; 1934 1935 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1936 == IFM_AUTO) { 1937 u_int32_t anar, bmcr; 1938 anar = CSR_READ_4(sc, NGE_TBI_ANAR); 1939 anar |= (NGE_TBIANAR_HDX | NGE_TBIANAR_FDX); 1940 CSR_WRITE_4(sc, NGE_TBI_ANAR, anar); 1941 1942 bmcr = CSR_READ_4(sc, NGE_TBI_BMCR); 1943 bmcr |= (NGE_TBIBMCR_ENABLE_ANEG|NGE_TBIBMCR_RESTART_ANEG); 1944 CSR_WRITE_4(sc, NGE_TBI_BMCR, bmcr); 1945 1946 bmcr &= ~(NGE_TBIBMCR_RESTART_ANEG); 1947 CSR_WRITE_4(sc, NGE_TBI_BMCR, bmcr); 1948 } else { 1949 u_int32_t txcfg, rxcfg; 1950 txcfg = CSR_READ_4(sc, NGE_TX_CFG); 1951 rxcfg = CSR_READ_4(sc, NGE_RX_CFG); 1952 1953 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1954 == IFM_FDX) { 1955 txcfg |= NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR; 1956 rxcfg |= NGE_RXCFG_RX_FDX; 1957 } else { 1958 txcfg &= ~(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR); 1959 rxcfg &= ~(NGE_RXCFG_RX_FDX); 1960 } 1961 1962 txcfg |= NGE_TXCFG_AUTOPAD; 1963 CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); 1964 CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); 1965 } 1966 1967 NGE_CLRBIT(sc, NGE_GPIO, NGE_GPIO_GP3_OUT); 1968 1969 return(0); 1970 } 1971 1972 /* 1973 * Report current tbi media status. 1974 */ 1975 void 1976 nge_ifmedia_tbi_sts(ifp, ifmr) 1977 struct ifnet *ifp; 1978 struct ifmediareq *ifmr; 1979 { 1980 struct nge_softc *sc = ifp->if_softc; 1981 u_int32_t bmcr; 1982 1983 bmcr = CSR_READ_4(sc, NGE_TBI_BMCR); 1984 1985 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) == IFM_AUTO) { 1986 u_int32_t bmsr = CSR_READ_4(sc, NGE_TBI_BMSR); 1987 DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts bmsr=%#x, bmcr=%#x\n", 1988 sc->sc_dv.dv_xname, bmsr, bmcr)); 1989 1990 if (!(bmsr & NGE_TBIBMSR_ANEG_DONE)) { 1991 ifmr->ifm_active = IFM_ETHER|IFM_NONE; 1992 ifmr->ifm_status = IFM_AVALID; 1993 return; 1994 } 1995 } else { 1996 DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts bmcr=%#x\n", 1997 sc->sc_dv.dv_xname, bmcr)); 1998 } 1999 2000 ifmr->ifm_status = IFM_AVALID|IFM_ACTIVE; 2001 ifmr->ifm_active = IFM_ETHER|IFM_1000_SX; 2002 2003 if (bmcr & NGE_TBIBMCR_LOOPBACK) 2004 ifmr->ifm_active |= IFM_LOOP; 2005 2006 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) == IFM_AUTO) { 2007 u_int32_t anlpar = CSR_READ_4(sc, NGE_TBI_ANLPAR); 2008 DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts anlpar=%#x\n", 2009 sc->sc_dv.dv_xname, anlpar)); 2010 2011 ifmr->ifm_active |= IFM_AUTO; 2012 if (anlpar & NGE_TBIANLPAR_FDX) { 2013 ifmr->ifm_active |= IFM_FDX; 2014 } else if (anlpar & NGE_TBIANLPAR_HDX) { 2015 ifmr->ifm_active |= IFM_HDX; 2016 } else 2017 ifmr->ifm_active |= IFM_FDX; 2018 2019 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) == IFM_FDX) 2020 ifmr->ifm_active |= IFM_FDX; 2021 else 2022 ifmr->ifm_active |= IFM_HDX; 2023 2024 } 2025 2026 int 2027 nge_ioctl(ifp, command, data) 2028 struct ifnet *ifp; 2029 u_long command; 2030 caddr_t data; 2031 { 2032 struct nge_softc *sc = ifp->if_softc; 2033 struct ifaddr *ifa = (struct ifaddr *) data; 2034 struct ifreq *ifr = (struct ifreq *) data; 2035 struct mii_data *mii; 2036 int s, error = 0; 2037 2038 s = splnet(); 2039 2040 switch(command) { 2041 case SIOCSIFADDR: 2042 ifp->if_flags |= IFF_UP; 2043 switch (ifa->ifa_addr->sa_family) { 2044 #ifdef INET 2045 case AF_INET: 2046 nge_init(sc); 2047 arp_ifinit(&sc->arpcom, ifa); 2048 break; 2049 #endif /* INET */ 2050 default: 2051 nge_init(sc); 2052 break; 2053 } 2054 break; 2055 2056 case SIOCSIFFLAGS: 2057 if (ifp->if_flags & IFF_UP) { 2058 if (ifp->if_flags & IFF_RUNNING && 2059 ifp->if_flags & IFF_PROMISC && 2060 !(sc->nge_if_flags & IFF_PROMISC)) { 2061 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2062 NGE_RXFILTCTL_ALLPHYS| 2063 NGE_RXFILTCTL_ALLMULTI); 2064 } else if (ifp->if_flags & IFF_RUNNING && 2065 !(ifp->if_flags & IFF_PROMISC) && 2066 sc->nge_if_flags & IFF_PROMISC) { 2067 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2068 NGE_RXFILTCTL_ALLPHYS); 2069 if (!(ifp->if_flags & IFF_ALLMULTI)) 2070 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2071 NGE_RXFILTCTL_ALLMULTI); 2072 } else { 2073 ifp->if_flags &= ~IFF_RUNNING; 2074 nge_init(sc); 2075 } 2076 } else { 2077 if (ifp->if_flags & IFF_RUNNING) 2078 nge_stop(sc); 2079 } 2080 sc->nge_if_flags = ifp->if_flags; 2081 error = 0; 2082 break; 2083 2084 case SIOCGIFMEDIA: 2085 case SIOCSIFMEDIA: 2086 if (sc->nge_tbi) { 2087 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2088 command); 2089 } else { 2090 mii = &sc->nge_mii; 2091 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2092 command); 2093 } 2094 break; 2095 2096 default: 2097 error = ether_ioctl(ifp, &sc->arpcom, command, data); 2098 } 2099 2100 if (error == ENETRESET) { 2101 if (ifp->if_flags & IFF_RUNNING) 2102 nge_setmulti(sc); 2103 error = 0; 2104 } 2105 2106 splx(s); 2107 return(error); 2108 } 2109 2110 void 2111 nge_watchdog(ifp) 2112 struct ifnet *ifp; 2113 { 2114 struct nge_softc *sc; 2115 2116 sc = ifp->if_softc; 2117 2118 ifp->if_oerrors++; 2119 printf("%s: watchdog timeout\n", sc->sc_dv.dv_xname); 2120 2121 nge_stop(sc); 2122 nge_reset(sc); 2123 ifp->if_flags &= ~IFF_RUNNING; 2124 nge_init(sc); 2125 2126 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2127 nge_start(ifp); 2128 } 2129 2130 /* 2131 * Stop the adapter and free any mbufs allocated to the 2132 * RX and TX lists. 2133 */ 2134 void 2135 nge_stop(sc) 2136 struct nge_softc *sc; 2137 { 2138 int i; 2139 struct ifnet *ifp; 2140 struct mii_data *mii; 2141 2142 ifp = &sc->arpcom.ac_if; 2143 ifp->if_timer = 0; 2144 if (sc->nge_tbi) { 2145 mii = NULL; 2146 } else { 2147 mii = &sc->nge_mii; 2148 } 2149 2150 timeout_del(&sc->nge_timeout); 2151 2152 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2153 2154 CSR_WRITE_4(sc, NGE_IER, 0); 2155 CSR_WRITE_4(sc, NGE_IMR, 0); 2156 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2157 DELAY(1000); 2158 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2159 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2160 2161 if (!sc->nge_tbi) 2162 mii_down(mii); 2163 2164 sc->nge_link = 0; 2165 2166 /* 2167 * Free data in the RX lists. 2168 */ 2169 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2170 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2171 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2172 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2173 } 2174 } 2175 bzero(&sc->nge_ldata->nge_rx_list, 2176 sizeof(sc->nge_ldata->nge_rx_list)); 2177 2178 /* 2179 * Free the TX list buffers. 2180 */ 2181 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2182 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2183 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2184 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2185 } 2186 } 2187 2188 bzero(&sc->nge_ldata->nge_tx_list, 2189 sizeof(sc->nge_ldata->nge_tx_list)); 2190 } 2191 2192 struct cfattach nge_ca = { 2193 sizeof(struct nge_softc), nge_probe, nge_attach 2194 }; 2195 2196 struct cfdriver nge_cd = { 2197 NULL, "nge", DV_IFNET 2198 }; 2199