1 /* $OpenBSD: if_stge.c,v 1.55 2013/08/07 01:06:38 bluhm Exp $ */ 2 /* $NetBSD: if_stge.c,v 1.27 2005/05/16 21:35:32 bouyer Exp $ */ 3 4 /*- 5 * Copyright (c) 2001 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Sundance Tech. TC9021 10/100/1000 35 * Ethernet controller. 36 */ 37 38 #include "bpfilter.h" 39 #include "vlan.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/timeout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_ether.h> 61 #endif 62 63 #include <net/if_media.h> 64 65 #if NVLAN > 0 66 #include <net/if_types.h> 67 #include <net/if_vlan_var.h> 68 #endif 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <machine/bus.h> 75 #include <machine/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/pci/pcireg.h> 82 #include <dev/pci/pcivar.h> 83 #include <dev/pci/pcidevs.h> 84 85 #include <dev/pci/if_stgereg.h> 86 87 void stge_start(struct ifnet *); 88 void stge_watchdog(struct ifnet *); 89 int stge_ioctl(struct ifnet *, u_long, caddr_t); 90 int stge_init(struct ifnet *); 91 void stge_stop(struct ifnet *, int); 92 93 void stge_reset(struct stge_softc *); 94 void stge_rxdrain(struct stge_softc *); 95 int stge_add_rxbuf(struct stge_softc *, int); 96 void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 97 void stge_tick(void *); 98 99 void stge_stats_update(struct stge_softc *); 100 101 void stge_iff(struct stge_softc *); 102 103 int stge_intr(void *); 104 void stge_txintr(struct stge_softc *); 105 void stge_rxintr(struct stge_softc *); 106 107 int stge_mii_readreg(struct device *, int, int); 108 void stge_mii_writereg(struct device *, int, int, int); 109 void stge_mii_statchg(struct device *); 110 111 int stge_mediachange(struct ifnet *); 112 void stge_mediastatus(struct ifnet *, struct ifmediareq *); 113 114 int stge_match(struct device *, void *, void *); 115 void stge_attach(struct device *, struct device *, void *); 116 117 int stge_copy_small = 0; 118 119 struct cfattach stge_ca = { 120 sizeof(struct stge_softc), stge_match, stge_attach, 121 }; 122 123 struct cfdriver stge_cd = { 124 NULL, "stge", DV_IFNET 125 }; 126 127 uint32_t stge_mii_bitbang_read(struct device *); 128 void stge_mii_bitbang_write(struct device *, uint32_t); 129 130 const struct mii_bitbang_ops stge_mii_bitbang_ops = { 131 stge_mii_bitbang_read, 132 stge_mii_bitbang_write, 133 { 134 PC_MgmtData, /* MII_BIT_MDO */ 135 PC_MgmtData, /* MII_BIT_MDI */ 136 PC_MgmtClk, /* MII_BIT_MDC */ 137 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 138 0, /* MII_BIT_DIR_PHY_HOST */ 139 } 140 }; 141 142 /* 143 * Devices supported by this driver. 144 */ 145 const struct pci_matchid stge_devices[] = { 146 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021 }, 147 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T }, 148 { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_ST1023 }, 149 { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_ST2021 }, 150 { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_TC9021 }, 151 { PCI_VENDOR_SUNDANCE, PCI_PRODUCT_SUNDANCE_TC9021_ALT }, 152 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021 }, 153 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT } 154 }; 155 156 int 157 stge_match(struct device *parent, void *match, void *aux) 158 { 159 return (pci_matchbyid((struct pci_attach_args *)aux, stge_devices, 160 sizeof(stge_devices) / sizeof(stge_devices[0]))); 161 } 162 163 void 164 stge_attach(struct device *parent, struct device *self, void *aux) 165 { 166 struct stge_softc *sc = (struct stge_softc *) self; 167 struct pci_attach_args *pa = aux; 168 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 169 pci_chipset_tag_t pc = pa->pa_pc; 170 pci_intr_handle_t ih; 171 const char *intrstr = NULL; 172 bus_space_tag_t iot, memt; 173 bus_space_handle_t ioh, memh; 174 bus_dma_segment_t seg; 175 bus_size_t iosize; 176 int ioh_valid, memh_valid; 177 int i, rseg, error; 178 179 timeout_set(&sc->sc_timeout, stge_tick, sc); 180 181 sc->sc_rev = PCI_REVISION(pa->pa_class); 182 183 /* 184 * Map the device. 185 */ 186 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 187 PCI_MAPREG_TYPE_IO, 0, 188 &iot, &ioh, NULL, &iosize, 0) == 0); 189 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 190 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 191 &memt, &memh, NULL, &iosize, 0) == 0); 192 193 if (memh_valid) { 194 sc->sc_st = memt; 195 sc->sc_sh = memh; 196 } else if (ioh_valid) { 197 sc->sc_st = iot; 198 sc->sc_sh = ioh; 199 } else { 200 printf(": unable to map device registers\n"); 201 return; 202 } 203 204 sc->sc_dmat = pa->pa_dmat; 205 206 /* Get it out of power save mode if needed. */ 207 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 208 209 /* 210 * Map and establish our interrupt. 211 */ 212 if (pci_intr_map(pa, &ih)) { 213 printf(": unable to map interrupt\n"); 214 goto fail_0; 215 } 216 intrstr = pci_intr_string(pc, ih); 217 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc, 218 sc->sc_dev.dv_xname); 219 if (sc->sc_ih == NULL) { 220 printf(": unable to establish interrupt"); 221 if (intrstr != NULL) 222 printf(" at %s", intrstr); 223 printf("\n"); 224 goto fail_0; 225 } 226 printf(": %s", intrstr); 227 228 /* 229 * Allocate the control data structures, and create and load the 230 * DMA map for it. 231 */ 232 if ((error = bus_dmamem_alloc(sc->sc_dmat, 233 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 234 0)) != 0) { 235 printf("%s: unable to allocate control data, error = %d\n", 236 sc->sc_dev.dv_xname, error); 237 goto fail_0; 238 } 239 240 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 241 sizeof(struct stge_control_data), (caddr_t *)&sc->sc_control_data, 242 BUS_DMA_COHERENT)) != 0) { 243 printf("%s: unable to map control data, error = %d\n", 244 sc->sc_dev.dv_xname, error); 245 goto fail_1; 246 } 247 248 if ((error = bus_dmamap_create(sc->sc_dmat, 249 sizeof(struct stge_control_data), 1, 250 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 251 printf("%s: unable to create control data DMA map, " 252 "error = %d\n", sc->sc_dev.dv_xname, error); 253 goto fail_2; 254 } 255 256 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 257 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 258 0)) != 0) { 259 printf("%s: unable to load control data DMA map, error = %d\n", 260 sc->sc_dev.dv_xname, error); 261 goto fail_3; 262 } 263 264 /* 265 * Create the transmit buffer DMA maps. Note that rev B.3 266 * and earlier seem to have a bug regarding multi-fragment 267 * packets. We need to limit the number of Tx segments on 268 * such chips to 1. 269 */ 270 for (i = 0; i < STGE_NTXDESC; i++) { 271 if ((error = bus_dmamap_create(sc->sc_dmat, 272 STGE_JUMBO_FRAMELEN, STGE_NTXFRAGS, MCLBYTES, 0, 0, 273 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 274 printf("%s: unable to create tx DMA map %d, " 275 "error = %d\n", sc->sc_dev.dv_xname, i, error); 276 goto fail_4; 277 } 278 } 279 280 /* 281 * Create the receive buffer DMA maps. 282 */ 283 for (i = 0; i < STGE_NRXDESC; i++) { 284 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 285 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 286 printf("%s: unable to create rx DMA map %d, " 287 "error = %d\n", sc->sc_dev.dv_xname, i, error); 288 goto fail_5; 289 } 290 sc->sc_rxsoft[i].ds_mbuf = NULL; 291 } 292 293 /* 294 * Determine if we're copper or fiber. It affects how we 295 * reset the card. 296 */ 297 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 298 sc->sc_usefiber = 1; 299 else 300 sc->sc_usefiber = 0; 301 302 /* 303 * Reset the chip to a known state. 304 */ 305 stge_reset(sc); 306 307 /* 308 * Reading the station address from the EEPROM doesn't seem 309 * to work, at least on my sample boards. Instead, since 310 * the reset sequence does AutoInit, read it from the station 311 * address registers. For Sundance 1023 you can only read it 312 * from EEPROM. 313 */ 314 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_SUNDANCE_ST1023) { 315 sc->sc_arpcom.ac_enaddr[0] = CSR_READ_2(sc, 316 STGE_StationAddress0) & 0xff; 317 sc->sc_arpcom.ac_enaddr[1] = CSR_READ_2(sc, 318 STGE_StationAddress0) >> 8; 319 sc->sc_arpcom.ac_enaddr[2] = CSR_READ_2(sc, 320 STGE_StationAddress1) & 0xff; 321 sc->sc_arpcom.ac_enaddr[3] = CSR_READ_2(sc, 322 STGE_StationAddress1) >> 8; 323 sc->sc_arpcom.ac_enaddr[4] = CSR_READ_2(sc, 324 STGE_StationAddress2) & 0xff; 325 sc->sc_arpcom.ac_enaddr[5] = CSR_READ_2(sc, 326 STGE_StationAddress2) >> 8; 327 sc->sc_stge1023 = 0; 328 } else { 329 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 330 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 331 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 332 &myaddr[i]); 333 myaddr[i] = letoh16(myaddr[i]); 334 } 335 (void)memcpy(sc->sc_arpcom.ac_enaddr, myaddr, 336 sizeof(sc->sc_arpcom.ac_enaddr)); 337 sc->sc_stge1023 = 1; 338 } 339 340 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 341 342 /* 343 * Read some important bits from the PhyCtrl register. 344 */ 345 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 346 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 347 348 /* 349 * Initialize our media structures and probe the MII. 350 */ 351 sc->sc_mii.mii_ifp = ifp; 352 sc->sc_mii.mii_readreg = stge_mii_readreg; 353 sc->sc_mii.mii_writereg = stge_mii_writereg; 354 sc->sc_mii.mii_statchg = stge_mii_statchg; 355 ifmedia_init(&sc->sc_mii.mii_media, 0, stge_mediachange, 356 stge_mediastatus); 357 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 358 MII_OFFSET_ANY, MIIF_DOPAUSE); 359 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 360 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 361 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 362 } else 363 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 364 365 ifp = &sc->sc_arpcom.ac_if; 366 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = stge_ioctl; 370 ifp->if_start = stge_start; 371 ifp->if_watchdog = stge_watchdog; 372 #ifdef STGE_JUMBO 373 ifp->if_hardmtu = STGE_JUMBO_MTU; 374 #endif 375 IFQ_SET_MAXLEN(&ifp->if_snd, STGE_NTXDESC - 1); 376 IFQ_SET_READY(&ifp->if_snd); 377 378 ifp->if_capabilities = IFCAP_VLAN_MTU; 379 380 #if NVLAN > 0 381 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 382 #endif 383 384 /* 385 * The manual recommends disabling early transmit, so we 386 * do. It's disabled anyway, if using IP checksumming, 387 * since the entire packet must be in the FIFO in order 388 * for the chip to perform the checksum. 389 */ 390 sc->sc_txthresh = 0x0fff; 391 392 /* 393 * Disable MWI if the PCI layer tells us to. 394 */ 395 sc->sc_DMACtrl = 0; 396 #ifdef fake 397 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 398 sc->sc_DMACtrl |= DMAC_MWIDisable; 399 #endif 400 401 #ifdef STGE_CHECKSUM 402 /* 403 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 404 */ 405 sc->sc_arpcom.ac_if.if_capabilities |= IFCAP_CSUM_IPv4 | 406 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 407 #endif 408 409 /* 410 * Attach the interface. 411 */ 412 if_attach(ifp); 413 ether_ifattach(ifp); 414 return; 415 416 /* 417 * Free any resources we've allocated during the failed attach 418 * attempt. Do this in reverse order and fall through. 419 */ 420 fail_5: 421 for (i = 0; i < STGE_NRXDESC; i++) { 422 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 423 bus_dmamap_destroy(sc->sc_dmat, 424 sc->sc_rxsoft[i].ds_dmamap); 425 } 426 fail_4: 427 for (i = 0; i < STGE_NTXDESC; i++) { 428 if (sc->sc_txsoft[i].ds_dmamap != NULL) 429 bus_dmamap_destroy(sc->sc_dmat, 430 sc->sc_txsoft[i].ds_dmamap); 431 } 432 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 433 fail_3: 434 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 435 fail_2: 436 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 437 sizeof(struct stge_control_data)); 438 fail_1: 439 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 440 fail_0: 441 bus_space_unmap(sc->sc_st, sc->sc_sh, iosize); 442 return; 443 } 444 445 static void 446 stge_dma_wait(struct stge_softc *sc) 447 { 448 int i; 449 450 for (i = 0; i < STGE_TIMEOUT; i++) { 451 delay(2); 452 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 453 break; 454 } 455 456 if (i == STGE_TIMEOUT) 457 printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname); 458 } 459 460 /* 461 * stge_start: [ifnet interface function] 462 * 463 * Start packet transmission on the interface. 464 */ 465 void 466 stge_start(struct ifnet *ifp) 467 { 468 struct stge_softc *sc = ifp->if_softc; 469 struct mbuf *m0; 470 struct stge_descsoft *ds; 471 struct stge_tfd *tfd; 472 bus_dmamap_t dmamap; 473 int error, firsttx, nexttx, opending, seg, totlen; 474 uint64_t csum_flags = 0, tfc; 475 476 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 477 return; 478 479 /* 480 * Remember the previous number of pending transmissions 481 * and the first descriptor we will use. 482 */ 483 opending = sc->sc_txpending; 484 firsttx = STGE_NEXTTX(sc->sc_txlast); 485 486 /* 487 * Loop through the send queue, setting up transmit descriptors 488 * until we drain the queue, or use up all available transmit 489 * descriptors. 490 */ 491 for (;;) { 492 /* 493 * Grab a packet off the queue. 494 */ 495 IFQ_POLL(&ifp->if_snd, m0); 496 if (m0 == NULL) 497 break; 498 499 /* 500 * Leave one unused descriptor at the end of the 501 * list to prevent wrapping completely around. 502 */ 503 if (sc->sc_txpending == (STGE_NTXDESC - 1)) 504 break; 505 506 /* 507 * Get the last and next available transmit descriptor. 508 */ 509 nexttx = STGE_NEXTTX(sc->sc_txlast); 510 tfd = &sc->sc_txdescs[nexttx]; 511 ds = &sc->sc_txsoft[nexttx]; 512 513 dmamap = ds->ds_dmamap; 514 515 /* 516 * Load the DMA map. If this fails, the packet either 517 * didn't fit in the alloted number of segments, or we 518 * were short on resources. For the too-many-segments 519 * case, we simply report an error and drop the packet, 520 * since we can't sanely copy a jumbo packet to a single 521 * buffer. 522 */ 523 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 524 BUS_DMA_NOWAIT); 525 if (error) { 526 if (error == EFBIG) { 527 printf("%s: Tx packet consumes too many " 528 "DMA segments (%u), dropping...\n", 529 sc->sc_dev.dv_xname, dmamap->dm_nsegs); 530 IFQ_DEQUEUE(&ifp->if_snd, m0); 531 m_freem(m0); 532 continue; 533 } 534 /* 535 * Short on resources, just stop for now. 536 */ 537 break; 538 } 539 540 IFQ_DEQUEUE(&ifp->if_snd, m0); 541 542 /* 543 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 544 */ 545 546 /* Sync the DMA map. */ 547 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 548 BUS_DMASYNC_PREWRITE); 549 550 /* Initialize the fragment list. */ 551 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 552 tfd->tfd_frags[seg].frag_word0 = 553 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 554 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 555 totlen += dmamap->dm_segs[seg].ds_len; 556 } 557 558 #ifdef STGE_CHECKSUM 559 /* 560 * Initialize checksumming flags in the descriptor. 561 * Byte-swap constants so the compiler can optimize. 562 */ 563 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 564 csum_flags |= TFD_IPChecksumEnable; 565 566 if (m0->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 567 csum_flags |= TFD_TCPChecksumEnable; 568 else if (m0->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 569 csum_flags |= TFD_UDPChecksumEnable; 570 #endif 571 572 /* 573 * Initialize the descriptor and give it to the chip. 574 */ 575 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 576 TFD_FragCount(seg) | csum_flags; 577 if ((nexttx & STGE_TXINTR_SPACING_MASK) == 0) 578 tfc |= TFD_TxDMAIndicate; 579 580 #if NVLAN > 0 581 /* Check if we have a VLAN tag to insert. */ 582 if (m0->m_flags & M_VLANTAG) 583 tfc |= (TFD_VLANTagInsert | 584 TFD_VID(m0->m_pkthdr.ether_vtag)); 585 #endif 586 587 tfd->tfd_control = htole64(tfc); 588 589 /* Sync the descriptor. */ 590 STGE_CDTXSYNC(sc, nexttx, 591 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 592 593 /* 594 * Kick the transmit DMA logic. 595 */ 596 CSR_WRITE_4(sc, STGE_DMACtrl, 597 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 598 599 /* 600 * Store a pointer to the packet so we can free it later. 601 */ 602 ds->ds_mbuf = m0; 603 604 /* Advance the tx pointer. */ 605 sc->sc_txpending++; 606 sc->sc_txlast = nexttx; 607 608 #if NBPFILTER > 0 609 /* 610 * Pass the packet to any BPF listeners. 611 */ 612 if (ifp->if_bpf) 613 bpf_mtap_ether(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 614 #endif /* NBPFILTER > 0 */ 615 } 616 617 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 618 /* No more slots left; notify upper layer. */ 619 ifp->if_flags |= IFF_OACTIVE; 620 } 621 622 if (sc->sc_txpending != opending) { 623 /* 624 * We enqueued packets. If the transmitter was idle, 625 * reset the txdirty pointer. 626 */ 627 if (opending == 0) 628 sc->sc_txdirty = firsttx; 629 630 /* Set a watchdog timer in case the chip flakes out. */ 631 ifp->if_timer = 5; 632 } 633 } 634 635 /* 636 * stge_watchdog: [ifnet interface function] 637 * 638 * Watchdog timer handler. 639 */ 640 void 641 stge_watchdog(struct ifnet *ifp) 642 { 643 struct stge_softc *sc = ifp->if_softc; 644 645 /* 646 * Sweep up first, since we don't interrupt every frame. 647 */ 648 stge_txintr(sc); 649 if (sc->sc_txpending != 0) { 650 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 651 ifp->if_oerrors++; 652 653 (void) stge_init(ifp); 654 655 /* Try to get more packets going. */ 656 stge_start(ifp); 657 } 658 } 659 660 /* 661 * stge_ioctl: [ifnet interface function] 662 * 663 * Handle control requests from the operator. 664 */ 665 int 666 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 667 { 668 struct stge_softc *sc = ifp->if_softc; 669 struct ifaddr *ifa = (struct ifaddr *)data; 670 struct ifreq *ifr = (struct ifreq *)data; 671 int s, error = 0; 672 673 s = splnet(); 674 675 switch (cmd) { 676 case SIOCSIFADDR: 677 ifp->if_flags |= IFF_UP; 678 if (!(ifp->if_flags & IFF_RUNNING)) 679 stge_init(ifp); 680 681 #ifdef INET 682 if (ifa->ifa_addr->sa_family == AF_INET) 683 arp_ifinit(&sc->sc_arpcom, ifa); 684 #endif 685 break; 686 687 case SIOCSIFFLAGS: 688 if (ifp->if_flags & IFF_UP) { 689 if (ifp->if_flags & IFF_RUNNING) 690 error = ENETRESET; 691 else 692 stge_init(ifp); 693 } else { 694 if (ifp->if_flags & IFF_RUNNING) 695 stge_stop(ifp, 1); 696 } 697 break; 698 699 case SIOCSIFMEDIA: 700 case SIOCGIFMEDIA: 701 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 702 break; 703 704 default: 705 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 706 } 707 708 if (error == ENETRESET) { 709 if (ifp->if_flags & IFF_RUNNING) 710 stge_iff(sc); 711 error = 0; 712 } 713 714 /* Try to get more packets going. */ 715 stge_start(ifp); 716 717 splx(s); 718 return (error); 719 } 720 721 /* 722 * stge_intr: 723 * 724 * Interrupt service routine. 725 */ 726 int 727 stge_intr(void *arg) 728 { 729 struct stge_softc *sc = arg; 730 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 731 uint32_t txstat; 732 int wantinit; 733 uint16_t isr; 734 735 if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0) 736 return (0); 737 738 for (wantinit = 0; wantinit == 0;) { 739 isr = CSR_READ_2(sc, STGE_IntStatusAck); 740 if ((isr & sc->sc_IntEnable) == 0) 741 break; 742 743 /* Host interface errors. */ 744 if (isr & IS_HostError) { 745 printf("%s: Host interface error\n", 746 sc->sc_dev.dv_xname); 747 wantinit = 1; 748 continue; 749 } 750 751 /* Receive interrupts. */ 752 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 753 stge_rxintr(sc); 754 if (isr & IS_RFDListEnd) { 755 printf("%s: receive ring overflow\n", 756 sc->sc_dev.dv_xname); 757 /* 758 * XXX Should try to recover from this 759 * XXX more gracefully. 760 */ 761 wantinit = 1; 762 } 763 } 764 765 /* Transmit interrupts. */ 766 if (isr & (IS_TxDMAComplete|IS_TxComplete)) 767 stge_txintr(sc); 768 769 /* Statistics overflow. */ 770 if (isr & IS_UpdateStats) 771 stge_stats_update(sc); 772 773 /* Transmission errors. */ 774 if (isr & IS_TxComplete) { 775 for (;;) { 776 txstat = CSR_READ_4(sc, STGE_TxStatus); 777 if ((txstat & TS_TxComplete) == 0) 778 break; 779 if (txstat & TS_TxUnderrun) { 780 sc->sc_txthresh++; 781 if (sc->sc_txthresh > 0x0fff) 782 sc->sc_txthresh = 0x0fff; 783 printf("%s: transmit underrun, new " 784 "threshold: %d bytes\n", 785 sc->sc_dev.dv_xname, 786 sc->sc_txthresh << 5); 787 } 788 if (txstat & TS_MaxCollisions) 789 printf("%s: excessive collisions\n", 790 sc->sc_dev.dv_xname); 791 } 792 wantinit = 1; 793 } 794 795 } 796 797 if (wantinit) 798 stge_init(ifp); 799 800 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 801 802 /* Try to get more packets going. */ 803 stge_start(ifp); 804 805 return (1); 806 } 807 808 /* 809 * stge_txintr: 810 * 811 * Helper; handle transmit interrupts. 812 */ 813 void 814 stge_txintr(struct stge_softc *sc) 815 { 816 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 817 struct stge_descsoft *ds; 818 uint64_t control; 819 int i; 820 821 ifp->if_flags &= ~IFF_OACTIVE; 822 823 /* 824 * Go through our Tx list and free mbufs for those 825 * frames which have been transmitted. 826 */ 827 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 828 i = STGE_NEXTTX(i), sc->sc_txpending--) { 829 ds = &sc->sc_txsoft[i]; 830 831 STGE_CDTXSYNC(sc, i, 832 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 833 834 control = letoh64(sc->sc_txdescs[i].tfd_control); 835 if ((control & TFD_TFDDone) == 0) 836 break; 837 838 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 839 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 840 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 841 m_freem(ds->ds_mbuf); 842 ds->ds_mbuf = NULL; 843 } 844 845 /* Update the dirty transmit buffer pointer. */ 846 sc->sc_txdirty = i; 847 848 /* 849 * If there are no more pending transmissions, cancel the watchdog 850 * timer. 851 */ 852 if (sc->sc_txpending == 0) 853 ifp->if_timer = 0; 854 } 855 856 /* 857 * stge_rxintr: 858 * 859 * Helper; handle receive interrupts. 860 */ 861 void 862 stge_rxintr(struct stge_softc *sc) 863 { 864 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 865 struct stge_descsoft *ds; 866 struct mbuf *m, *tailm; 867 uint64_t status; 868 int i, len; 869 870 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 871 ds = &sc->sc_rxsoft[i]; 872 873 STGE_CDRXSYNC(sc, i, 874 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 875 876 status = letoh64(sc->sc_rxdescs[i].rfd_status); 877 878 if ((status & RFD_RFDDone) == 0) 879 break; 880 881 if (__predict_false(sc->sc_rxdiscard)) { 882 STGE_INIT_RXDESC(sc, i); 883 if (status & RFD_FrameEnd) { 884 /* Reset our state. */ 885 sc->sc_rxdiscard = 0; 886 } 887 continue; 888 } 889 890 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 891 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 892 893 m = ds->ds_mbuf; 894 895 /* 896 * Add a new receive buffer to the ring. 897 */ 898 if (stge_add_rxbuf(sc, i) != 0) { 899 /* 900 * Failed, throw away what we've done so 901 * far, and discard the rest of the packet. 902 */ 903 ifp->if_ierrors++; 904 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 905 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 906 STGE_INIT_RXDESC(sc, i); 907 if ((status & RFD_FrameEnd) == 0) 908 sc->sc_rxdiscard = 1; 909 if (sc->sc_rxhead != NULL) 910 m_freem(sc->sc_rxhead); 911 STGE_RXCHAIN_RESET(sc); 912 continue; 913 } 914 915 #ifdef DIAGNOSTIC 916 if (status & RFD_FrameStart) { 917 KASSERT(sc->sc_rxhead == NULL); 918 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 919 } 920 #endif 921 922 STGE_RXCHAIN_LINK(sc, m); 923 924 /* 925 * If this is not the end of the packet, keep 926 * looking. 927 */ 928 if ((status & RFD_FrameEnd) == 0) { 929 sc->sc_rxlen += m->m_len; 930 continue; 931 } 932 933 /* 934 * Okay, we have the entire packet now... 935 */ 936 *sc->sc_rxtailp = NULL; 937 m = sc->sc_rxhead; 938 tailm = sc->sc_rxtail; 939 940 STGE_RXCHAIN_RESET(sc); 941 942 /* 943 * If the packet had an error, drop it. Note we 944 * count the error later in the periodic stats update. 945 */ 946 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 947 RFD_RxAlignmentError | RFD_RxFCSError | 948 RFD_RxLengthError)) { 949 m_freem(m); 950 continue; 951 } 952 953 /* 954 * No errors. 955 * 956 * Note we have configured the chip to not include 957 * the CRC at the end of the packet. 958 */ 959 len = RFD_RxDMAFrameLen(status); 960 tailm->m_len = len - sc->sc_rxlen; 961 962 /* 963 * If the packet is small enough to fit in a 964 * single header mbuf, allocate one and copy 965 * the data into it. This greatly reduces 966 * memory consumption when we receive lots 967 * of small packets. 968 */ 969 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 970 struct mbuf *nm; 971 MGETHDR(nm, M_DONTWAIT, MT_DATA); 972 if (nm == NULL) { 973 ifp->if_ierrors++; 974 m_freem(m); 975 continue; 976 } 977 nm->m_data += 2; 978 nm->m_pkthdr.len = nm->m_len = len; 979 m_copydata(m, 0, len, mtod(nm, caddr_t)); 980 m_freem(m); 981 m = nm; 982 } 983 984 /* 985 * Set the incoming checksum information for the packet. 986 */ 987 if ((status & RFD_IPDetected) && 988 (!(status & RFD_IPError))) 989 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 990 if ((status & RFD_TCPDetected) && 991 (!(status & RFD_TCPError))) 992 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 993 else if ((status & RFD_UDPDetected) && 994 (!(status & RFD_UDPError))) 995 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 996 997 #if NVLAN > 0 998 /* Check for VLAN tagged packets. */ 999 if (status & RFD_VLANDetected) { 1000 m->m_pkthdr.ether_vtag = RFD_TCI(status); 1001 m->m_flags |= M_VLANTAG; 1002 } 1003 #endif 1004 1005 m->m_pkthdr.rcvif = ifp; 1006 m->m_pkthdr.len = len; 1007 1008 #if NBPFILTER > 0 1009 /* 1010 * Pass this up to any BPF listeners, but only 1011 * pass if up the stack if it's for us. 1012 */ 1013 if (ifp->if_bpf) 1014 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1015 #endif /* NBPFILTER > 0 */ 1016 1017 /* Pass it on. */ 1018 ether_input_mbuf(ifp, m); 1019 } 1020 1021 /* Update the receive pointer. */ 1022 sc->sc_rxptr = i; 1023 } 1024 1025 /* 1026 * stge_tick: 1027 * 1028 * One second timer, used to tick the MII. 1029 */ 1030 void 1031 stge_tick(void *arg) 1032 { 1033 struct stge_softc *sc = arg; 1034 int s; 1035 1036 s = splnet(); 1037 mii_tick(&sc->sc_mii); 1038 stge_stats_update(sc); 1039 splx(s); 1040 1041 timeout_add_sec(&sc->sc_timeout, 1); 1042 } 1043 1044 /* 1045 * stge_stats_update: 1046 * 1047 * Read the TC9021 statistics counters. 1048 */ 1049 void 1050 stge_stats_update(struct stge_softc *sc) 1051 { 1052 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1053 1054 (void) CSR_READ_4(sc, STGE_OctetRcvOk); 1055 1056 ifp->if_ipackets += 1057 CSR_READ_4(sc, STGE_FramesRcvdOk); 1058 1059 ifp->if_ierrors += 1060 (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors); 1061 1062 (void) CSR_READ_4(sc, STGE_OctetXmtdOk); 1063 1064 ifp->if_opackets += 1065 CSR_READ_4(sc, STGE_FramesXmtdOk); 1066 1067 ifp->if_collisions += 1068 CSR_READ_4(sc, STGE_LateCollisions) + 1069 CSR_READ_4(sc, STGE_MultiColFrames) + 1070 CSR_READ_4(sc, STGE_SingleColFrames); 1071 1072 ifp->if_oerrors += 1073 (u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1074 (u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal); 1075 } 1076 1077 /* 1078 * stge_reset: 1079 * 1080 * Perform a soft reset on the TC9021. 1081 */ 1082 void 1083 stge_reset(struct stge_softc *sc) 1084 { 1085 uint32_t ac; 1086 int i; 1087 1088 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1089 1090 /* 1091 * Only assert RstOut if we're fiber. We need GMII clocks 1092 * to be present in order for the reset to complete on fiber 1093 * cards. 1094 */ 1095 CSR_WRITE_4(sc, STGE_AsicCtrl, 1096 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1097 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1098 (sc->sc_usefiber ? AC_RstOut : 0)); 1099 1100 delay(50000); 1101 1102 for (i = 0; i < STGE_TIMEOUT; i++) { 1103 delay(5000); 1104 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1105 break; 1106 } 1107 1108 if (i == STGE_TIMEOUT) 1109 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1110 1111 delay(1000); 1112 } 1113 1114 /* 1115 * stge_init: [ ifnet interface function ] 1116 * 1117 * Initialize the interface. Must be called at splnet(). 1118 */ 1119 int 1120 stge_init(struct ifnet *ifp) 1121 { 1122 struct stge_softc *sc = ifp->if_softc; 1123 struct stge_descsoft *ds; 1124 int i, error = 0; 1125 1126 /* 1127 * Cancel any pending I/O. 1128 */ 1129 stge_stop(ifp, 0); 1130 1131 /* 1132 * Reset the chip to a known state. 1133 */ 1134 stge_reset(sc); 1135 1136 /* 1137 * Initialize the transmit descriptor ring. 1138 */ 1139 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1140 for (i = 0; i < STGE_NTXDESC; i++) { 1141 sc->sc_txdescs[i].tfd_next = htole64( 1142 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1143 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1144 } 1145 sc->sc_txpending = 0; 1146 sc->sc_txdirty = 0; 1147 sc->sc_txlast = STGE_NTXDESC - 1; 1148 1149 /* 1150 * Initialize the receive descriptor and receive job 1151 * descriptor rings. 1152 */ 1153 for (i = 0; i < STGE_NRXDESC; i++) { 1154 ds = &sc->sc_rxsoft[i]; 1155 if (ds->ds_mbuf == NULL) { 1156 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1157 printf("%s: unable to allocate or map rx " 1158 "buffer %d, error = %d\n", 1159 sc->sc_dev.dv_xname, i, error); 1160 /* 1161 * XXX Should attempt to run with fewer receive 1162 * XXX buffers instead of just failing. 1163 */ 1164 stge_rxdrain(sc); 1165 goto out; 1166 } 1167 } else 1168 STGE_INIT_RXDESC(sc, i); 1169 } 1170 sc->sc_rxptr = 0; 1171 sc->sc_rxdiscard = 0; 1172 STGE_RXCHAIN_RESET(sc); 1173 1174 /* Set the station address. */ 1175 if (sc->sc_stge1023) { 1176 CSR_WRITE_2(sc, STGE_StationAddress0, 1177 sc->sc_arpcom.ac_enaddr[0] | sc->sc_arpcom.ac_enaddr[1] << 8); 1178 CSR_WRITE_2(sc, STGE_StationAddress1, 1179 sc->sc_arpcom.ac_enaddr[2] | sc->sc_arpcom.ac_enaddr[3] << 8); 1180 CSR_WRITE_2(sc, STGE_StationAddress2, 1181 sc->sc_arpcom.ac_enaddr[4] | sc->sc_arpcom.ac_enaddr[5] << 8); 1182 } else { 1183 for (i = 0; i < ETHER_ADDR_LEN; i++) 1184 CSR_WRITE_1(sc, STGE_StationAddress0 + i, 1185 sc->sc_arpcom.ac_enaddr[i]); 1186 } 1187 1188 /* 1189 * Set the statistics masks. Disable all the RMON stats, 1190 * and disable selected stats in the non-RMON stats registers. 1191 */ 1192 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 1193 CSR_WRITE_4(sc, STGE_StatisticsMask, 1194 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1195 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1196 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1197 (1U << 21)); 1198 1199 /* Program promiscuous mode and multicast filters. */ 1200 stge_iff(sc); 1201 1202 /* 1203 * Give the transmit and receive ring to the chip. 1204 */ 1205 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1206 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 1207 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1208 1209 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1210 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 1211 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1212 1213 /* 1214 * Initialize the Tx auto-poll period. It's OK to make this number 1215 * large (255 is the max, but we use 127) -- we explicitly kick the 1216 * transmit engine when there's actually a packet. 1217 */ 1218 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 1219 1220 /* ..and the Rx auto-poll period. */ 1221 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64); 1222 1223 /* Initialize the Tx start threshold. */ 1224 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 1225 1226 /* RX DMA thresholds, from linux */ 1227 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 1228 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 1229 1230 /* Rx early threhold, from Linux */ 1231 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 1232 1233 /* Tx DMA thresholds, from Linux */ 1234 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 1235 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 1236 1237 /* 1238 * Initialize the Rx DMA interrupt control register. We 1239 * request an interrupt after every incoming packet, but 1240 * defer it for 32us (64 * 512 ns). When the number of 1241 * interrupts pending reaches 8, we stop deferring the 1242 * interrupt, and signal it immediately. 1243 */ 1244 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 1245 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1246 1247 /* 1248 * Initialize the interrupt mask. 1249 */ 1250 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1251 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1252 CSR_WRITE_2(sc, STGE_IntStatus, 0xffff); 1253 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1254 1255 /* 1256 * Configure the DMA engine. 1257 * XXX Should auto-tune TxBurstLimit. 1258 */ 1259 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | 1260 DMAC_TxBurstLimit(3)); 1261 1262 /* 1263 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1264 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 1265 * in the Rx FIFO. 1266 */ 1267 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 1268 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 1269 1270 /* 1271 * Set the maximum frame size. 1272 */ 1273 #ifdef STGE_JUMBO 1274 CSR_WRITE_2(sc, STGE_MaxFrameSize, STGE_JUMBO_FRAMELEN); 1275 #else 1276 CSR_WRITE_2(sc, STGE_MaxFrameSize, ETHER_MAX_LEN); 1277 #endif 1278 1279 /* 1280 * Initialize MacCtrl -- do it before setting the media, 1281 * as setting the media will actually program the register. 1282 * 1283 * Note: We have to poke the IFS value before poking 1284 * anything else. 1285 */ 1286 sc->sc_MACCtrl = MC_IFSSelect(0); 1287 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); 1288 1289 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1290 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1291 1292 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1293 1294 if (sc->sc_rev >= 6) { /* >= B.2 */ 1295 /* Multi-frag frame bug work-around. */ 1296 CSR_WRITE_2(sc, STGE_DebugCtrl, 1297 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 1298 1299 /* Tx Poll Now bug work-around. */ 1300 CSR_WRITE_2(sc, STGE_DebugCtrl, 1301 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 1302 1303 /* Rx Poll Now bug work-around. */ 1304 CSR_WRITE_2(sc, STGE_DebugCtrl, 1305 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 1306 } 1307 1308 /* 1309 * Set the current media. 1310 */ 1311 mii_mediachg(&sc->sc_mii); 1312 1313 /* 1314 * Start the one second MII clock. 1315 */ 1316 timeout_add_sec(&sc->sc_timeout, 1); 1317 1318 /* 1319 * ...all done! 1320 */ 1321 ifp->if_flags |= IFF_RUNNING; 1322 ifp->if_flags &= ~IFF_OACTIVE; 1323 1324 out: 1325 if (error) 1326 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1327 return (error); 1328 } 1329 1330 /* 1331 * stge_drain: 1332 * 1333 * Drain the receive queue. 1334 */ 1335 void 1336 stge_rxdrain(struct stge_softc *sc) 1337 { 1338 struct stge_descsoft *ds; 1339 int i; 1340 1341 for (i = 0; i < STGE_NRXDESC; i++) { 1342 ds = &sc->sc_rxsoft[i]; 1343 if (ds->ds_mbuf != NULL) { 1344 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1345 ds->ds_mbuf->m_next = NULL; 1346 m_freem(ds->ds_mbuf); 1347 ds->ds_mbuf = NULL; 1348 } 1349 } 1350 } 1351 1352 /* 1353 * stge_stop: [ ifnet interface function ] 1354 * 1355 * Stop transmission on the interface. 1356 */ 1357 void 1358 stge_stop(struct ifnet *ifp, int disable) 1359 { 1360 struct stge_softc *sc = ifp->if_softc; 1361 struct stge_descsoft *ds; 1362 int i; 1363 1364 /* 1365 * Stop the one second clock. 1366 */ 1367 timeout_del(&sc->sc_timeout); 1368 1369 /* 1370 * Mark the interface down and cancel the watchdog timer. 1371 */ 1372 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1373 ifp->if_timer = 0; 1374 1375 /* Down the MII. */ 1376 mii_down(&sc->sc_mii); 1377 1378 /* 1379 * Disable interrupts. 1380 */ 1381 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1382 1383 /* 1384 * Stop receiver, transmitter, and stats update. 1385 */ 1386 CSR_WRITE_4(sc, STGE_MACCtrl, 1387 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1388 1389 /* 1390 * Stop the transmit and receive DMA. 1391 */ 1392 stge_dma_wait(sc); 1393 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 1394 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 1395 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 1396 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 1397 1398 /* 1399 * Release any queued transmit buffers. 1400 */ 1401 for (i = 0; i < STGE_NTXDESC; i++) { 1402 ds = &sc->sc_txsoft[i]; 1403 if (ds->ds_mbuf != NULL) { 1404 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1405 m_freem(ds->ds_mbuf); 1406 ds->ds_mbuf = NULL; 1407 } 1408 } 1409 1410 if (disable) 1411 stge_rxdrain(sc); 1412 } 1413 1414 static int 1415 stge_eeprom_wait(struct stge_softc *sc) 1416 { 1417 int i; 1418 1419 for (i = 0; i < STGE_TIMEOUT; i++) { 1420 delay(1000); 1421 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 1422 return (0); 1423 } 1424 return (1); 1425 } 1426 1427 /* 1428 * stge_read_eeprom: 1429 * 1430 * Read data from the serial EEPROM. 1431 */ 1432 void 1433 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1434 { 1435 1436 if (stge_eeprom_wait(sc)) 1437 printf("%s: EEPROM failed to come ready\n", 1438 sc->sc_dev.dv_xname); 1439 1440 CSR_WRITE_2(sc, STGE_EepromCtrl, 1441 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1442 if (stge_eeprom_wait(sc)) 1443 printf("%s: EEPROM read timed out\n", 1444 sc->sc_dev.dv_xname); 1445 *data = CSR_READ_2(sc, STGE_EepromData); 1446 } 1447 1448 /* 1449 * stge_add_rxbuf: 1450 * 1451 * Add a receive buffer to the indicated descriptor. 1452 */ 1453 int 1454 stge_add_rxbuf(struct stge_softc *sc, int idx) 1455 { 1456 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1457 struct mbuf *m; 1458 int error; 1459 1460 MGETHDR(m, M_DONTWAIT, MT_DATA); 1461 if (m == NULL) 1462 return (ENOBUFS); 1463 1464 MCLGET(m, M_DONTWAIT); 1465 if ((m->m_flags & M_EXT) == 0) { 1466 m_freem(m); 1467 return (ENOBUFS); 1468 } 1469 1470 m->m_data = m->m_ext.ext_buf + 2; 1471 m->m_len = MCLBYTES - 2; 1472 1473 if (ds->ds_mbuf != NULL) 1474 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1475 1476 ds->ds_mbuf = m; 1477 1478 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1479 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1480 if (error) { 1481 printf("%s: can't load rx DMA map %d, error = %d\n", 1482 sc->sc_dev.dv_xname, idx, error); 1483 panic("stge_add_rxbuf"); /* XXX */ 1484 } 1485 1486 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1487 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1488 1489 STGE_INIT_RXDESC(sc, idx); 1490 1491 return (0); 1492 } 1493 1494 /* 1495 * stge_iff: 1496 * 1497 * Set up the receive filter. 1498 */ 1499 void 1500 stge_iff(struct stge_softc *sc) 1501 { 1502 struct arpcom *ac = &sc->sc_arpcom; 1503 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1504 struct ether_multi *enm; 1505 struct ether_multistep step; 1506 uint32_t crc; 1507 uint32_t mchash[2]; 1508 1509 memset(mchash, 0, sizeof(mchash)); 1510 ifp->if_flags &= ~IFF_ALLMULTI; 1511 1512 /* 1513 * Always accept broadcast packets. 1514 * Always accept frames destined to our station address. 1515 */ 1516 sc->sc_ReceiveMode = RM_ReceiveBroadcast | RM_ReceiveUnicast; 1517 1518 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1519 ifp->if_flags |= IFF_ALLMULTI; 1520 if (ifp->if_flags & IFF_PROMISC) 1521 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1522 else 1523 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1524 } else { 1525 /* 1526 * Set up the multicast address filter by passing all 1527 * multicast addresses through a CRC generator, and then 1528 * using the low-order 6 bits as an index into the 64 bit 1529 * multicast hash table. The high order bits select the 1530 * register, while the rest of the bits select the bit 1531 * within the register. 1532 */ 1533 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1534 1535 ETHER_FIRST_MULTI(step, ac, enm); 1536 while (enm != NULL) { 1537 crc = ether_crc32_be(enm->enm_addrlo, 1538 ETHER_ADDR_LEN); 1539 1540 /* Just want the 6 least significant bits. */ 1541 crc &= 0x3f; 1542 1543 /* Set the corresponding bit in the hash table. */ 1544 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1545 1546 ETHER_NEXT_MULTI(step, enm); 1547 } 1548 } 1549 1550 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 1551 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 1552 CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode); 1553 } 1554 1555 /* 1556 * stge_mii_readreg: [mii interface function] 1557 * 1558 * Read a PHY register on the MII of the TC9021. 1559 */ 1560 int 1561 stge_mii_readreg(struct device *self, int phy, int reg) 1562 { 1563 1564 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1565 } 1566 1567 /* 1568 * stge_mii_writereg: [mii interface function] 1569 * 1570 * Write a PHY register on the MII of the TC9021. 1571 */ 1572 void 1573 stge_mii_writereg(struct device *self, int phy, int reg, int val) 1574 { 1575 1576 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1577 } 1578 1579 /* 1580 * stge_mii_statchg: [mii interface function] 1581 * 1582 * Callback from MII layer when media changes. 1583 */ 1584 void 1585 stge_mii_statchg(struct device *self) 1586 { 1587 struct stge_softc *sc = (struct stge_softc *) self; 1588 struct mii_data *mii = &sc->sc_mii; 1589 1590 sc->sc_MACCtrl &= ~(MC_DuplexSelect | MC_RxFlowControlEnable | 1591 MC_TxFlowControlEnable); 1592 1593 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 1594 sc->sc_MACCtrl |= MC_DuplexSelect; 1595 1596 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0) 1597 sc->sc_MACCtrl |= MC_RxFlowControlEnable; 1598 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0) 1599 sc->sc_MACCtrl |= MC_TxFlowControlEnable; 1600 1601 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); 1602 } 1603 1604 /* 1605 * sste_mii_bitbang_read: [mii bit-bang interface function] 1606 * 1607 * Read the MII serial port for the MII bit-bang module. 1608 */ 1609 uint32_t 1610 stge_mii_bitbang_read(struct device *self) 1611 { 1612 struct stge_softc *sc = (void *) self; 1613 1614 return (CSR_READ_1(sc, STGE_PhyCtrl)); 1615 } 1616 1617 /* 1618 * stge_mii_bitbang_write: [mii big-bang interface function] 1619 * 1620 * Write the MII serial port for the MII bit-bang module. 1621 */ 1622 void 1623 stge_mii_bitbang_write(struct device *self, uint32_t val) 1624 { 1625 struct stge_softc *sc = (void *) self; 1626 1627 CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl); 1628 } 1629 1630 /* 1631 * stge_mediastatus: [ifmedia interface function] 1632 * 1633 * Get the current interface media status. 1634 */ 1635 void 1636 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1637 { 1638 struct stge_softc *sc = ifp->if_softc; 1639 1640 mii_pollstat(&sc->sc_mii); 1641 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1642 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1643 } 1644 1645 /* 1646 * stge_mediachange: [ifmedia interface function] 1647 * 1648 * Set hardware to newly-selected media. 1649 */ 1650 int 1651 stge_mediachange(struct ifnet *ifp) 1652 { 1653 struct stge_softc *sc = ifp->if_softc; 1654 1655 if (ifp->if_flags & IFF_UP) 1656 mii_mediachg(&sc->sc_mii); 1657 return (0); 1658 } 1659