1 /* $OpenBSD: if_tht.c,v 1.126 2013/04/02 13:43:40 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2007 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for the Tehuti TN30xx multi port 10Gb Ethernet chipsets, 21 * see http://www.tehutinetworks.net/. 22 * 23 * This driver was made possible because Tehuti networks provided 24 * hardware and documentation. Thanks! 25 */ 26 27 #include "bpfilter.h" 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/sockio.h> 32 #include <sys/mbuf.h> 33 #include <sys/kernel.h> 34 #include <sys/socket.h> 35 #include <sys/malloc.h> 36 #include <sys/device.h> 37 #include <sys/timeout.h> 38 #include <sys/queue.h> 39 #include <sys/rwlock.h> 40 #include <sys/time.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #if NBPFILTER > 0 54 #include <net/bpf.h> 55 #endif 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/if_ether.h> 60 #endif 61 62 #ifdef THT_DEBUG 63 #define THT_D_FIFO (1<<0) 64 #define THT_D_TX (1<<1) 65 #define THT_D_RX (1<<2) 66 #define THT_D_INTR (1<<3) 67 68 int thtdebug = THT_D_TX | THT_D_RX | THT_D_INTR; 69 70 #define DPRINTF(l, f...) do { if (thtdebug & (l)) printf(f); } while (0) 71 #else 72 #define DPRINTF(l, f...) 73 #endif 74 75 /* registers */ 76 77 #define THT_PCI_BAR 0x10 78 79 #define _Q(_q) ((_q) * 4) 80 81 /* General Configuration */ 82 #define THT_REG_END_SEL 0x5448 /* PCI Endian Select */ 83 #define THT_REG_CLKPLL 0x5000 84 #define THT_REG_CLKPLL_PLLLK (1<<9) /* PLL is locked */ 85 #define THT_REG_CLKPLL_RSTEND (1<<8) /* Reset ended */ 86 #define THT_REG_CLKPLL_TXF_DIS (1<<3) /* TX Free disabled */ 87 #define THT_REG_CLKPLL_VNT_STOP (1<<2) /* VENETO Stop */ 88 #define THT_REG_CLKPLL_PLLRST (1<<1) /* PLL Reset */ 89 #define THT_REG_CLKPLL_SFTRST (1<<0) /* Software Reset */ 90 /* Descriptors and FIFO Registers */ 91 #define THT_REG_TXT_CFG0(_q) (0x4040 + _Q(_q)) /* CFG0 TX Task queues */ 92 #define THT_REG_RXF_CFG0(_q) (0x4050 + _Q(_q)) /* CFG0 RX Free queues */ 93 #define THT_REG_RXD_CFG0(_q) (0x4060 + _Q(_q)) /* CFG0 RX DSC queues */ 94 #define THT_REG_TXF_CFG0(_q) (0x4070 + _Q(_q)) /* CFG0 TX Free queues */ 95 #define THT_REG_TXT_CFG1(_q) (0x4000 + _Q(_q)) /* CFG1 TX Task queues */ 96 #define THT_REG_RXF_CFG1(_q) (0x4010 + _Q(_q)) /* CFG1 RX Free queues */ 97 #define THT_REG_RXD_CFG1(_q) (0x4020 + _Q(_q)) /* CFG1 RX DSC queues */ 98 #define THT_REG_TXF_CFG1(_q) (0x4030 + _Q(_q)) /* CFG1 TX Free queues */ 99 #define THT_REG_TXT_RPTR(_q) (0x40c0 + _Q(_q)) /* TX Task read ptr */ 100 #define THT_REG_RXF_RPTR(_q) (0x40d0 + _Q(_q)) /* RX Free read ptr */ 101 #define THT_REG_RXD_RPTR(_q) (0x40e0 + _Q(_q)) /* RX DSC read ptr */ 102 #define THT_REG_TXF_RPTR(_q) (0x40f0 + _Q(_q)) /* TX Free read ptr */ 103 #define THT_REG_TXT_WPTR(_q) (0x4080 + _Q(_q)) /* TX Task write ptr */ 104 #define THT_REG_RXF_WPTR(_q) (0x4090 + _Q(_q)) /* RX Free write ptr */ 105 #define THT_REG_RXD_WPTR(_q) (0x40a0 + _Q(_q)) /* RX DSC write ptr */ 106 #define THT_REG_TXF_WPTR(_q) (0x40b0 + _Q(_q)) /* TX Free write ptr */ 107 #define THT_REG_HTB_ADDR 0x4100 /* HTB Addressing Mechanism enable */ 108 #define THT_REG_HTB_ADDR_HI 0x4110 /* High HTB Address */ 109 #define THT_REG_HTB_ST_TMR 0x3290 /* HTB Timer */ 110 #define THT_REG_RDINTCM(_q) (0x5120 + _Q(_q)) /* RX DSC Intr Coalescing */ 111 #define THT_REG_RDINTCM_PKT_TH(_c) ((_c)<<20) /* pkt count threshold */ 112 #define THT_REG_RDINTCM_RXF_TH(_c) ((_c)<<16) /* rxf intr req thresh */ 113 #define THT_REG_RDINTCM_COAL_RC (1<<15) /* coalescing timer recharge */ 114 #define THT_REG_RDINTCM_COAL(_c) (_c) /* coalescing timer */ 115 #define THT_REG_TDINTCM(_q) (0x5130 + _Q(_q)) /* TX DSC Intr Coalescing */ 116 #define THT_REG_TDINTCM_PKT_TH(_c) ((_c)<<20) /* pkt count threshold */ 117 #define THT_REG_TDINTCM_COAL_RC (1<<15) /* coalescing timer recharge */ 118 #define THT_REG_TDINTCM_COAL(_c) (_c) /* coalescing timer */ 119 /* 10G Ethernet MAC */ 120 #define THT_REG_10G_REV 0x6000 /* Revision */ 121 #define THT_REG_10G_SCR 0x6004 /* Scratch */ 122 #define THT_REG_10G_CTL 0x6008 /* Control/Status */ 123 #define THT_REG_10G_CTL_CMD_FRAME_EN (1<<13) /* cmd frame enable */ 124 #define THT_REG_10G_CTL_SW_RESET (1<<12) /* sw reset */ 125 #define THT_REG_10G_CTL_STATS_AUTO_CLR (1<<11) /* auto clear statistics */ 126 #define THT_REG_10G_CTL_LOOPBACK (1<<10) /* enable loopback */ 127 #define THT_REG_10G_CTL_TX_ADDR_INS (1<<9) /* set mac on tx */ 128 #define THT_REG_10G_CTL_PAUSE_IGNORE (1<<8) /* ignore pause */ 129 #define THT_REG_10G_CTL_PAUSE_FWD (1<<7) /* forward pause */ 130 #define THT_REG_10G_CTL_CRC_FWD (1<<6) /* crc forward */ 131 #define THT_REG_10G_CTL_PAD (1<<5) /* frame padding */ 132 #define THT_REG_10G_CTL_PROMISC (1<<4) /* promiscuous mode */ 133 #define THT_REG_10G_CTL_WAN_MODE (1<<3) /* WAN mode */ 134 #define THT_REG_10G_CTL_RX_EN (1<<1) /* RX enable */ 135 #define THT_REG_10G_CTL_TX_EN (1<<0) /* TX enable */ 136 #define THT_REG_10G_FRM_LEN 0x6014 /* Frame Length */ 137 #define THT_REG_10G_PAUSE 0x6018 /* Pause Quanta */ 138 #define THT_REG_10G_RX_SEC 0x601c /* RX Section */ 139 #define THT_REG_10G_TX_SEC 0x6020 /* TX Section */ 140 #define THT_REG_10G_SEC_AVAIL(_t) (_t) /* section available thresh*/ 141 #define THT_REG_10G_SEC_EMPTY(_t) ((_t)<<16) /* section empty avail */ 142 #define THT_REG_10G_RFIFO_AEF 0x6024 /* RX FIFO Almost Empty/Full */ 143 #define THT_REG_10G_TFIFO_AEF 0x6028 /* TX FIFO Almost Empty/Full */ 144 #define THT_REG_10G_FIFO_AE(_t) (_t) /* almost empty */ 145 #define THT_REG_10G_FIFO_AF(_t) ((_t)<<16) /* almost full */ 146 #define THT_REG_10G_SM_STAT 0x6030 /* MDIO Status */ 147 #define THT_REG_10G_SM_CMD 0x6034 /* MDIO Command */ 148 #define THT_REG_10G_SM_DAT 0x6038 /* MDIO Data */ 149 #define THT_REG_10G_SM_ADD 0x603c /* MDIO Address */ 150 #define THT_REG_10G_STAT 0x6040 /* Status */ 151 /* Statistic Counters */ 152 /* XXX todo */ 153 /* Status Registers */ 154 #define THT_REG_MAC_LNK_STAT 0x0200 /* Link Status */ 155 #define THT_REG_MAC_LNK_STAT_DIS (1<<4) /* Mac Stats read disable */ 156 #define THT_REG_MAC_LNK_STAT_LINK (1<<2) /* Link State */ 157 #define THT_REG_MAC_LNK_STAT_REM_FAULT (1<<1) /* Remote Fault */ 158 #define THT_REG_MAC_LNK_STAT_LOC_FAULT (1<<0) /* Local Fault */ 159 /* Interrupt Registers */ 160 #define THT_REG_ISR 0x5100 /* Interrupt Status */ 161 #define THT_REG_ISR_LINKCHG(_p) (1<<(27+(_p))) /* link changed */ 162 #define THT_REG_ISR_GPIO (1<<26) /* GPIO */ 163 #define THT_REG_ISR_RFRSH (1<<25) /* DDR Refresh */ 164 #define THT_REG_ISR_SWI (1<<23) /* software interrupt */ 165 #define THT_REG_ISR_RXF(_q) (1<<(19+(_q))) /* rx free fifo */ 166 #define THT_REG_ISR_TXF(_q) (1<<(15+(_q))) /* tx free fifo */ 167 #define THT_REG_ISR_RXD(_q) (1<<(11+(_q))) /* rx desc fifo */ 168 #define THT_REG_ISR_TMR(_t) (1<<(6+(_t))) /* timer */ 169 #define THT_REG_ISR_VNT (1<<5) /* optistrata */ 170 #define THT_REG_ISR_RxFL (1<<4) /* RX Full */ 171 #define THT_REG_ISR_TR (1<<2) /* table read */ 172 #define THT_REG_ISR_PCIE_LNK_INT (1<<1) /* pcie link fail */ 173 #define THT_REG_ISR_GPLE_CLR (1<<0) /* pcie timeout */ 174 #define THT_FMT_ISR "\020" "\035LINKCHG1" "\034LINKCHG0" \ 175 "\033GPIO" "\032RFRSH" "\030SWI" \ 176 "\027RXF3" "\026RXF2" "\025RXF1" \ 177 "\024RXF0" "\023TXF3" "\022TXF2" \ 178 "\021TXF1" "\020TXF0" "\017RXD3" \ 179 "\016RXD2" "\015RXD1" "\014RXD0" \ 180 "\012TMR3" "\011TMR2" "\010TMR1" \ 181 "\007TMR0" "\006VNT" "\005RxFL" \ 182 "\003TR" "\002PCI_LNK_INT" \ 183 "\001GPLE_CLR" 184 #define THT_REG_ISR_GTI 0x5080 /* GTI Interrupt Status */ 185 #define THT_REG_IMR 0x5110 /* Interrupt Mask */ 186 #define THT_REG_IMR_LINKCHG(_p) (1<<(27+(_p))) /* link changed */ 187 #define THT_REG_IMR_GPIO (1<<26) /* GPIO */ 188 #define THT_REG_IMR_RFRSH (1<<25) /* DDR Refresh */ 189 #define THT_REG_IMR_SWI (1<<23) /* software interrupt */ 190 #define THT_REG_IMR_RXF(_q) (1<<(19+(_q))) /* rx free fifo */ 191 #define THT_REG_IMR_TXF(_q) (1<<(15+(_q))) /* tx free fifo */ 192 #define THT_REG_IMR_RXD(_q) (1<<(11+(_q))) /* rx desc fifo */ 193 #define THT_REG_IMR_TMR(_t) (1<<(6+(_t))) /* timer */ 194 #define THT_REG_IMR_VNT (1<<5) /* optistrata */ 195 #define THT_REG_IMR_RxFL (1<<4) /* RX Full */ 196 #define THT_REG_IMR_TR (1<<2) /* table read */ 197 #define THT_REG_IMR_PCIE_LNK_INT (1<<1) /* pcie link fail */ 198 #define THT_REG_IMR_GPLE_CLR (1<<0) /* pcie timeout */ 199 #define THT_REG_IMR_GTI 0x5090 /* GTI Interrupt Mask */ 200 #define THT_REG_ISR_MSK 0x5140 /* ISR Masked */ 201 /* Global Counters */ 202 /* XXX todo */ 203 /* DDR2 SDRAM Controller Registers */ 204 /* XXX TBD */ 205 /* EEPROM Registers */ 206 /* XXX todo */ 207 /* Init arbitration and status registers */ 208 #define THT_REG_INIT_SEMAPHORE 0x5170 /* Init Semaphore */ 209 #define THT_REG_INIT_STATUS 0x5180 /* Init Status */ 210 /* PCI Credits Registers */ 211 /* XXX todo */ 212 /* TX Arbitration Registers */ 213 #define THT_REG_TXTSK_PR(_q) (0x41b0 + _Q(_q)) /* TX Queue Priority */ 214 /* RX Part Registers */ 215 #define THT_REG_RX_FLT 0x1240 /* RX Filter Configuration */ 216 #define THT_REG_RX_FLT_ATXER (1<<15) /* accept with xfer err */ 217 #define THT_REG_RX_FLT_ATRM (1<<14) /* accept with term err */ 218 #define THT_REG_RX_FLT_AFTSQ (1<<13) /* accept with fault seq */ 219 #define THT_REG_RX_FLT_OSEN (1<<12) /* enable pkts */ 220 #define THT_REG_RX_FLT_APHER (1<<11) /* accept with phy err */ 221 #define THT_REG_RX_FLT_TXFC (1<<10) /* TX flow control */ 222 #define THT_REG_RX_FLT_FDA (1<<8) /* filter direct address */ 223 #define THT_REG_RX_FLT_AOF (1<<7) /* accept overflow frame */ 224 #define THT_REG_RX_FLT_ACF (1<<6) /* accept control frame */ 225 #define THT_REG_RX_FLT_ARUNT (1<<5) /* accept runt */ 226 #define THT_REG_RX_FLT_ACRC (1<<4) /* accept crc error */ 227 #define THT_REG_RX_FLT_AM (1<<3) /* accept multicast */ 228 #define THT_REG_RX_FLT_AB (1<<2) /* accept broadcast */ 229 #define THT_REG_RX_FLT_PRM_MASK 0x3 /* promiscuous mode */ 230 #define THT_REG_RX_FLT_PRM_NORMAL 0x0 /* normal mode */ 231 #define THT_REG_RX_FLT_PRM_ALL 0x1 /* pass all incoming frames */ 232 #define THT_REG_RX_MAX_FRAME 0x12c0 /* Max Frame Size */ 233 #define THT_REG_RX_UNC_MAC0 0x1250 /* MAC Address low word */ 234 #define THT_REG_RX_UNC_MAC1 0x1260 /* MAC Address mid word */ 235 #define THT_REG_RX_UNC_MAC2 0x1270 /* MAC Address high word */ 236 #define THT_REG_RX_MAC_MCST0(_m) (0x1a80 + (_m)*8) 237 #define THT_REG_RX_MAC_MCST1(_m) (0x1a84 + (_m)*8) 238 #define THT_REG_RX_MAC_MCST_CNT 15 239 #define THT_REG_RX_MCST_HASH 0x1a00 /* imperfect multicast filter hash */ 240 #define THT_REG_RX_MCST_HASH_SIZE (256 / NBBY) 241 /* OptiStrata Debug Registers */ 242 #define THT_REG_VPC 0x2300 /* Program Counter */ 243 #define THT_REG_VLI 0x2310 /* Last Interrupt */ 244 #define THT_REG_VIC 0x2320 /* Interrupts Count */ 245 #define THT_REG_VTMR 0x2330 /* Timer */ 246 #define THT_REG_VGLB 0x2340 /* Global */ 247 /* SW Reset Registers */ 248 #define THT_REG_RST_PRT 0x7000 /* Reset Port */ 249 #define THT_REG_RST_PRT_ACTIVE 0x1 /* port reset is active */ 250 #define THT_REG_DIS_PRT 0x7010 /* Disable Port */ 251 #define THT_REG_RST_QU_0 0x7020 /* Reset Queue 0 */ 252 #define THT_REG_RST_QU_1 0x7028 /* Reset Queue 1 */ 253 #define THT_REG_DIS_QU_0 0x7030 /* Disable Queue 0 */ 254 #define THT_REG_DIS_QU_1 0x7038 /* Disable Queue 1 */ 255 256 #define THT_PORT_SIZE 0x8000 257 #define THT_PORT_REGION(_p) ((_p) * THT_PORT_SIZE) 258 #define THT_NQUEUES 4 259 260 #define THT_FIFO_ALIGN 4096 261 #define THT_FIFO_SIZE_4k 0x0 262 #define THT_FIFO_SIZE_8k 0x1 263 #define THT_FIFO_SIZE_16k 0x2 264 #define THT_FIFO_SIZE_32k 0x3 265 #define THT_FIFO_SIZE(_r) (4096 * (1<<(_r))) 266 #define THT_FIFO_GAP 8 /* keep 8 bytes between ptrs */ 267 #define THT_FIFO_PTR_MASK 0x00007ff8 /* rptr/wptr mask */ 268 269 #define THT_FIFO_DESC_LEN 208 /* a descriptor cant be bigger than this */ 270 271 #define THT_IMR_DOWN(_p) (THT_REG_IMR_LINKCHG(_p)) 272 #define THT_IMR_UP(_p) (THT_REG_IMR_LINKCHG(_p) | \ 273 THT_REG_IMR_RXF(0) | THT_REG_IMR_TXF(0) | \ 274 THT_REG_IMR_RXD(0)) 275 276 /* hardware structures (we're using the 64 bit variants) */ 277 278 /* physical buffer descriptor */ 279 struct tht_pbd { 280 u_int32_t addr_lo; 281 u_int32_t addr_hi; 282 u_int32_t len; 283 } __packed; 284 #define THT_PBD_PKTLEN (64 * 1024) 285 286 /* rx free fifo */ 287 struct tht_rx_free { 288 u_int16_t bc; /* buffer count (0:4) */ 289 u_int16_t type; 290 291 u_int64_t uid; 292 293 /* followed by a pdb list */ 294 } __packed; 295 #define THT_RXF_TYPE 1 296 #define THT_RXF_1ST_PDB_LEN 128 297 #define THT_RXF_SGL_LEN ((THT_FIFO_DESC_LEN - \ 298 sizeof(struct tht_rx_free)) / \ 299 sizeof(struct tht_pbd)) 300 #define THT_RXF_PKT_NUM 128 301 302 /* rx descriptor */ 303 struct tht_rx_desc { 304 u_int32_t flags; 305 #define THT_RXD_FLAGS_BC(_f) ((_f) & 0x1f) /* buffer count */ 306 #define THT_RXD_FLAGS_RXFQ(_f) (((_f)>>8) & 0x3) /* rxf queue id */ 307 #define THT_RXD_FLAGS_TO (1<<15) 308 #define THT_RXD_FLAGS_TYPE(_f) (((_f)>>16) & 0xf) /* desc type */ 309 #define THT_RXD_FLAGS_OVF (1<<21) /* overflow error */ 310 #define THT_RXD_FLAGS_RUNT (1<<22) /* runt error */ 311 #define THT_RXD_FLAGS_CRC (1<<23) /* crc error */ 312 #define THT_RXD_FLAGS_UDPCS (1<<24) /* udp checksum error */ 313 #define THT_RXD_FLAGS_TCPCS (1<<25) /* tcp checksum error */ 314 #define THT_RXD_FLAGS_IPCS (1<<26) /* ip checksum error */ 315 #define THT_RXD_FLAGS_PKT_ID 0x70000000 316 #define THT_RXD_FLAGS_PKT_ID_NONIP 0x00000000 317 #define THT_RXD_FLAGS_PKT_ID_TCP4 0x10000000 318 #define THT_RXD_FLAGS_PKT_ID_UDP4 0x20000000 319 #define THT_RXD_FLAGS_PKT_ID_IPV4 0x30000000 320 #define THT_RXD_FLAGS_PKT_ID_TCP6 0x50000000 321 #define THT_RXD_FLAGS_PKT_ID_UDP6 0x60000000 322 #define THT_RXD_FLAGS_PKT_ID_IPV6 0x70000000 323 #define THT_RXD_FLAGS_VTAG (1<<31) 324 u_int16_t len; 325 u_int16_t vlan; 326 #define THT_RXD_VLAN_ID(_v) ((_v) & 0xfff) 327 #define THT_RXD_VLAN_CFI (1<<12) 328 #define THT_RXD_VLAN_PRI(_v) ((_v) & 0x7) >> 13) 329 330 u_int64_t uid; 331 } __packed; 332 #define THT_RXD_TYPE 2 333 334 /* rx decriptor type 3: data chain instruction */ 335 struct tht_rx_desc_dc { 336 /* preceded by tht_rx_desc */ 337 338 u_int16_t cd_offset; 339 u_int16_t flags; 340 341 u_int8_t data[4]; 342 } __packed; 343 #define THT_RXD_TYPE_DC 3 344 345 /* rx descriptor type 4: rss (recv side scaling) information */ 346 struct tht_rx_desc_rss { 347 /* preceded by tht_rx_desc */ 348 349 u_int8_t rss_hft; 350 u_int8_t rss_type; 351 u_int8_t rss_tcpu; 352 u_int8_t reserved; 353 354 u_int32_t rss_hash; 355 } __packed; 356 #define THT_RXD_TYPE_RSS 4 357 358 /* tx task fifo */ 359 struct tht_tx_task { 360 u_int32_t flags; 361 #define THT_TXT_FLAGS_BC(_f) (_f) /* buffer count */ 362 #define THT_TXT_FLAGS_UDPCS (1<<5) /* udp checksum */ 363 #define THT_TXT_FLAGS_TCPCS (1<<6) /* tcp checksum */ 364 #define THT_TXT_FLAGS_IPCS (1<<7) /* ip checksum */ 365 #define THT_TXT_FLAGS_VTAG (1<<8) /* insert vlan tag */ 366 #define THT_TXT_FLAGS_LGSND (1<<9) /* tcp large send enabled */ 367 #define THT_TXT_FLAGS_FRAG (1<<10) /* ip fragmentation enabled */ 368 #define THT_TXT_FLAGS_CFI (1<<12) /* canonical format indicator */ 369 #define THT_TXT_FLAGS_PRIO(_f) ((_f)<<13) /* vlan priority */ 370 #define THT_TXT_FLAGS_VLAN(_f) ((_f)<<20) /* vlan id */ 371 u_int16_t mss_mtu; 372 u_int16_t len; 373 374 u_int64_t uid; 375 376 /* followed by a pbd list */ 377 } __packed; 378 #define THT_TXT_TYPE (3<<16) 379 #define THT_TXT_SGL_LEN ((THT_FIFO_DESC_LEN - \ 380 sizeof(struct tht_tx_task)) / \ 381 sizeof(struct tht_pbd)) 382 #define THT_TXT_PKT_NUM 128 383 384 /* tx free fifo */ 385 struct tht_tx_free { 386 u_int32_t status; 387 388 u_int64_t uid; 389 390 u_int32_t pad; 391 } __packed; 392 393 /* pci controller autoconf glue */ 394 395 struct thtc_softc { 396 struct device sc_dev; 397 398 bus_dma_tag_t sc_dmat; 399 400 bus_space_tag_t sc_memt; 401 bus_space_handle_t sc_memh; 402 bus_size_t sc_mems; 403 void *sc_ih; 404 }; 405 406 int thtc_match(struct device *, void *, void *); 407 void thtc_attach(struct device *, struct device *, void *); 408 int thtc_print(void *, const char *); 409 410 struct cfattach thtc_ca = { 411 sizeof(struct thtc_softc), thtc_match, thtc_attach 412 }; 413 414 struct cfdriver thtc_cd = { 415 NULL, "thtc", DV_DULL 416 }; 417 418 /* glue between the controller and the port */ 419 420 struct tht_attach_args { 421 int taa_port; 422 423 struct pci_attach_args *taa_pa; 424 }; 425 426 /* tht itself */ 427 428 struct tht_dmamem { 429 bus_dmamap_t tdm_map; 430 bus_dma_segment_t tdm_seg; 431 size_t tdm_size; 432 caddr_t tdm_kva; 433 }; 434 #define THT_DMA_MAP(_tdm) ((_tdm)->tdm_map) 435 #define THT_DMA_DVA(_tdm) ((_tdm)->tdm_map->dm_segs[0].ds_addr) 436 #define THT_DMA_KVA(_tdm) ((void *)(_tdm)->tdm_kva) 437 438 struct tht_fifo_desc { 439 bus_size_t tfd_cfg0; 440 bus_size_t tfd_cfg1; 441 bus_size_t tfd_rptr; 442 bus_size_t tfd_wptr; 443 u_int32_t tfd_size; 444 int tfd_write; 445 }; 446 #define THT_FIFO_PRE_SYNC(_d) ((_d)->tfd_write ? \ 447 BUS_DMASYNC_PREWRITE : \ 448 BUS_DMASYNC_PREREAD) 449 #define THT_FIFO_POST_SYNC(_d) ((_d)->tfd_write ? \ 450 BUS_DMASYNC_POSTWRITE : \ 451 BUS_DMASYNC_POSTREAD) 452 453 struct tht_fifo { 454 struct tht_fifo_desc *tf_desc; 455 struct tht_dmamem *tf_mem; 456 int tf_len; 457 int tf_rptr; 458 int tf_wptr; 459 int tf_ready; 460 }; 461 462 struct tht_pkt { 463 u_int64_t tp_id; 464 465 bus_dmamap_t tp_dmap; 466 struct mbuf *tp_m; 467 468 TAILQ_ENTRY(tht_pkt) tp_link; 469 }; 470 471 struct tht_pkt_list { 472 struct tht_pkt *tpl_pkts; 473 TAILQ_HEAD(, tht_pkt) tpl_free; 474 TAILQ_HEAD(, tht_pkt) tpl_used; 475 }; 476 477 struct tht_softc { 478 struct device sc_dev; 479 struct thtc_softc *sc_thtc; 480 int sc_port; 481 482 bus_space_handle_t sc_memh; 483 484 struct arpcom sc_ac; 485 struct ifmedia sc_media; 486 struct timeval sc_mediacheck; 487 488 u_int16_t sc_lladdr[3]; 489 490 struct tht_pkt_list sc_tx_list; 491 struct tht_pkt_list sc_rx_list; 492 493 struct tht_fifo sc_txt; 494 struct tht_fifo sc_rxf; 495 struct tht_fifo sc_rxd; 496 struct tht_fifo sc_txf; 497 498 u_int32_t sc_imr; 499 500 struct rwlock sc_lock; 501 }; 502 503 int tht_match(struct device *, void *, void *); 504 void tht_attach(struct device *, struct device *, void *); 505 void tht_mountroot(void *); 506 int tht_intr(void *); 507 508 struct cfattach tht_ca = { 509 sizeof(struct tht_softc), tht_match, tht_attach 510 }; 511 512 struct cfdriver tht_cd = { 513 NULL, "tht", DV_IFNET 514 }; 515 516 /* pkts */ 517 int tht_pkt_alloc(struct tht_softc *, 518 struct tht_pkt_list *, int, int); 519 void tht_pkt_free(struct tht_softc *, 520 struct tht_pkt_list *); 521 void tht_pkt_put(struct tht_pkt_list *, struct tht_pkt *); 522 struct tht_pkt *tht_pkt_get(struct tht_pkt_list *); 523 struct tht_pkt *tht_pkt_used(struct tht_pkt_list *); 524 525 /* fifos */ 526 527 struct tht_fifo_desc tht_txt_desc = { 528 THT_REG_TXT_CFG0(0), 529 THT_REG_TXT_CFG1(0), 530 THT_REG_TXT_RPTR(0), 531 THT_REG_TXT_WPTR(0), 532 THT_FIFO_SIZE_16k, 533 1 534 }; 535 536 struct tht_fifo_desc tht_rxf_desc = { 537 THT_REG_RXF_CFG0(0), 538 THT_REG_RXF_CFG1(0), 539 THT_REG_RXF_RPTR(0), 540 THT_REG_RXF_WPTR(0), 541 THT_FIFO_SIZE_16k, 542 1 543 }; 544 545 struct tht_fifo_desc tht_rxd_desc = { 546 THT_REG_RXD_CFG0(0), 547 THT_REG_RXD_CFG1(0), 548 THT_REG_RXD_RPTR(0), 549 THT_REG_RXD_WPTR(0), 550 THT_FIFO_SIZE_16k, 551 0 552 }; 553 554 struct tht_fifo_desc tht_txf_desc = { 555 THT_REG_TXF_CFG0(0), 556 THT_REG_TXF_CFG1(0), 557 THT_REG_TXF_RPTR(0), 558 THT_REG_TXF_WPTR(0), 559 THT_FIFO_SIZE_4k, 560 0 561 }; 562 563 int tht_fifo_alloc(struct tht_softc *, struct tht_fifo *, 564 struct tht_fifo_desc *); 565 void tht_fifo_free(struct tht_softc *, struct tht_fifo *); 566 567 size_t tht_fifo_readable(struct tht_softc *, 568 struct tht_fifo *); 569 size_t tht_fifo_writable(struct tht_softc *, 570 struct tht_fifo *); 571 void tht_fifo_pre(struct tht_softc *, 572 struct tht_fifo *); 573 void tht_fifo_read(struct tht_softc *, struct tht_fifo *, 574 void *, size_t); 575 void tht_fifo_write(struct tht_softc *, struct tht_fifo *, 576 void *, size_t); 577 void tht_fifo_write_dmap(struct tht_softc *, 578 struct tht_fifo *, bus_dmamap_t); 579 void tht_fifo_write_pad(struct tht_softc *, 580 struct tht_fifo *, int); 581 void tht_fifo_post(struct tht_softc *, 582 struct tht_fifo *); 583 584 /* port operations */ 585 void tht_lladdr_read(struct tht_softc *); 586 void tht_lladdr_write(struct tht_softc *); 587 int tht_sw_reset(struct tht_softc *); 588 int tht_fw_load(struct tht_softc *); 589 void tht_fw_tick(void *arg); 590 void tht_link_state(struct tht_softc *); 591 592 /* interface operations */ 593 int tht_ioctl(struct ifnet *, u_long, caddr_t); 594 void tht_watchdog(struct ifnet *); 595 void tht_start(struct ifnet *); 596 int tht_load_pkt(struct tht_softc *, struct tht_pkt *, 597 struct mbuf *); 598 void tht_txf(struct tht_softc *sc); 599 600 void tht_rxf_fill(struct tht_softc *, int); 601 void tht_rxf_drain(struct tht_softc *); 602 void tht_rxd(struct tht_softc *); 603 604 void tht_up(struct tht_softc *); 605 void tht_iff(struct tht_softc *); 606 void tht_down(struct tht_softc *); 607 608 /* ifmedia operations */ 609 int tht_media_change(struct ifnet *); 610 void tht_media_status(struct ifnet *, struct ifmediareq *); 611 612 /* wrapper around dma memory */ 613 struct tht_dmamem *tht_dmamem_alloc(struct tht_softc *, bus_size_t, 614 bus_size_t); 615 void tht_dmamem_free(struct tht_softc *, 616 struct tht_dmamem *); 617 618 /* bus space operations */ 619 u_int32_t tht_read(struct tht_softc *, bus_size_t); 620 void tht_write(struct tht_softc *, bus_size_t, u_int32_t); 621 void tht_write_region(struct tht_softc *, bus_size_t, 622 void *, size_t); 623 int tht_wait_eq(struct tht_softc *, bus_size_t, u_int32_t, 624 u_int32_t, int); 625 int tht_wait_ne(struct tht_softc *, bus_size_t, u_int32_t, 626 u_int32_t, int); 627 628 #define tht_set(_s, _r, _b) tht_write((_s), (_r), \ 629 tht_read((_s), (_r)) | (_b)) 630 #define tht_clr(_s, _r, _b) tht_write((_s), (_r), \ 631 tht_read((_s), (_r)) & ~(_b)) 632 #define tht_wait_set(_s, _r, _b, _t) tht_wait_eq((_s), (_r), \ 633 (_b), (_b), (_t)) 634 635 636 /* misc */ 637 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 638 #define LWORDS(_b) (((_b) + 7) >> 3) 639 640 641 struct thtc_device { 642 pci_vendor_id_t td_vendor; 643 pci_vendor_id_t td_product; 644 u_int td_nports; 645 }; 646 647 const struct thtc_device *thtc_lookup(struct pci_attach_args *); 648 649 static const struct thtc_device thtc_devices[] = { 650 { PCI_VENDOR_TEHUTI, PCI_PRODUCT_TEHUTI_TN3009, 1 }, 651 { PCI_VENDOR_TEHUTI, PCI_PRODUCT_TEHUTI_TN3010, 1 }, 652 { PCI_VENDOR_TEHUTI, PCI_PRODUCT_TEHUTI_TN3014, 2 } 653 }; 654 655 const struct thtc_device * 656 thtc_lookup(struct pci_attach_args *pa) 657 { 658 int i; 659 const struct thtc_device *td; 660 661 for (i = 0; i < nitems(thtc_devices); i++) { 662 td = &thtc_devices[i]; 663 if (td->td_vendor == PCI_VENDOR(pa->pa_id) && 664 td->td_product == PCI_PRODUCT(pa->pa_id)) 665 return (td); 666 } 667 668 return (NULL); 669 } 670 671 int 672 thtc_match(struct device *parent, void *match, void *aux) 673 { 674 struct pci_attach_args *pa = aux; 675 676 if (thtc_lookup(pa) != NULL) 677 return (1); 678 679 return (0); 680 } 681 682 void 683 thtc_attach(struct device *parent, struct device *self, void *aux) 684 { 685 struct thtc_softc *sc = (struct thtc_softc *)self; 686 struct pci_attach_args *pa = aux; 687 pcireg_t memtype; 688 const struct thtc_device *td; 689 struct tht_attach_args taa; 690 pci_intr_handle_t ih; 691 int i; 692 693 bzero(&taa, sizeof(taa)); 694 td = thtc_lookup(pa); 695 696 sc->sc_dmat = pa->pa_dmat; 697 698 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, THT_PCI_BAR); 699 if (pci_mapreg_map(pa, THT_PCI_BAR, memtype, 0, &sc->sc_memt, 700 &sc->sc_memh, NULL, &sc->sc_mems, 0) != 0) { 701 printf(": unable to map host registers\n"); 702 return; 703 } 704 705 if (pci_intr_map(pa, &ih) != 0) { 706 printf(": unable to map interrupt\n"); 707 goto unmap; 708 } 709 710 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, 711 IPL_NET, tht_intr, sc, DEVNAME(sc)); 712 if (sc->sc_ih == NULL) { 713 printf(": unable to establish interrupt\n"); 714 return; 715 } 716 printf(": %s\n", pci_intr_string(pa->pa_pc, ih)); 717 718 taa.taa_pa = pa; 719 for (i = 0; i < td->td_nports; i++) { 720 taa.taa_port = i; 721 722 config_found(self, &taa, thtc_print); 723 } 724 725 return; 726 727 unmap: 728 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 729 sc->sc_mems = 0; 730 } 731 732 int 733 thtc_print(void *aux, const char *pnp) 734 { 735 struct tht_attach_args *taa = aux; 736 737 if (pnp != NULL) 738 printf("\"%s\" at %s", tht_cd.cd_name, pnp); 739 740 printf(" port %d", taa->taa_port); 741 742 return (UNCONF); 743 } 744 745 int 746 tht_match(struct device *parent, void *match, void *aux) 747 { 748 return (1); 749 } 750 751 void 752 tht_attach(struct device *parent, struct device *self, void *aux) 753 { 754 struct thtc_softc *csc = (struct thtc_softc *)parent; 755 struct tht_softc *sc = (struct tht_softc *)self; 756 struct tht_attach_args *taa = aux; 757 struct ifnet *ifp; 758 759 sc->sc_thtc = csc; 760 sc->sc_port = taa->taa_port; 761 sc->sc_imr = THT_IMR_DOWN(sc->sc_port); 762 rw_init(&sc->sc_lock, "thtioc"); 763 764 if (bus_space_subregion(csc->sc_memt, csc->sc_memh, 765 THT_PORT_REGION(sc->sc_port), THT_PORT_SIZE, 766 &sc->sc_memh) != 0) { 767 printf(": unable to map port registers\n"); 768 return; 769 } 770 771 if (tht_sw_reset(sc) != 0) { 772 printf(": unable to reset port\n"); 773 /* bus_space(9) says we dont have to free subregions */ 774 return; 775 } 776 777 tht_lladdr_read(sc); 778 bcopy(sc->sc_lladdr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 779 780 ifp = &sc->sc_ac.ac_if; 781 ifp->if_softc = sc; 782 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 783 ifp->if_capabilities = IFCAP_VLAN_MTU; 784 ifp->if_ioctl = tht_ioctl; 785 ifp->if_start = tht_start; 786 ifp->if_watchdog = tht_watchdog; 787 ifp->if_hardmtu = MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN; /* XXX */ 788 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 789 IFQ_SET_MAXLEN(&ifp->if_snd, 400); 790 IFQ_SET_READY(&ifp->if_snd); 791 792 ifmedia_init(&sc->sc_media, 0, tht_media_change, tht_media_status); 793 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_AUTO, 0, NULL); 794 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 795 796 if_attach(ifp); 797 ether_ifattach(ifp); 798 799 printf(": address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr)); 800 801 mountroothook_establish(tht_mountroot, sc); 802 } 803 804 void 805 tht_mountroot(void *arg) 806 { 807 struct tht_softc *sc = arg; 808 809 if (tht_fifo_alloc(sc, &sc->sc_txt, &tht_txt_desc) != 0) 810 return; 811 812 if (tht_fw_load(sc) != 0) 813 printf("%s: firmware load failed\n", DEVNAME(sc)); 814 815 tht_sw_reset(sc); 816 817 tht_fifo_free(sc, &sc->sc_txt); 818 819 tht_link_state(sc); 820 tht_write(sc, THT_REG_IMR, sc->sc_imr); 821 } 822 823 int 824 tht_intr(void *arg) 825 { 826 struct thtc_softc *thtc = arg; 827 struct tht_softc *sc = arg; 828 struct device *d; 829 struct ifnet *ifp; 830 u_int32_t isr; 831 int rv = 0; 832 833 for (d = TAILQ_NEXT(&thtc->sc_dev, dv_list); d != NULL; 834 d = TAILQ_NEXT(d, dv_list)) { 835 sc = (struct tht_softc *)d; 836 837 isr = tht_read(sc, THT_REG_ISR); 838 if (isr == 0x0) { 839 tht_write(sc, THT_REG_IMR, sc->sc_imr); 840 continue; 841 } 842 rv = 1; 843 844 DPRINTF(THT_D_INTR, "%s: isr: 0x%b\n", DEVNAME(sc), isr, THT_FMT_ISR); 845 846 if (ISSET(isr, THT_REG_ISR_LINKCHG(0) | THT_REG_ISR_LINKCHG(1))) 847 tht_link_state(sc); 848 849 ifp = &sc->sc_ac.ac_if; 850 if (ifp->if_flags & IFF_RUNNING) { 851 if (ISSET(isr, THT_REG_ISR_RXD(0))) 852 tht_rxd(sc); 853 854 if (ISSET(isr, THT_REG_ISR_RXF(0))) 855 tht_rxf_fill(sc, 0); 856 857 if (ISSET(isr, THT_REG_ISR_TXF(0))) 858 tht_txf(sc); 859 860 tht_start(ifp); 861 } 862 tht_write(sc, THT_REG_IMR, sc->sc_imr); 863 } 864 return (rv); 865 } 866 867 int 868 tht_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr) 869 { 870 struct tht_softc *sc = ifp->if_softc; 871 struct ifaddr *ifa = (struct ifaddr *)addr; 872 struct ifreq *ifr = (struct ifreq *)addr; 873 int s, error = 0; 874 875 rw_enter_write(&sc->sc_lock); 876 s = splnet(); 877 878 switch (cmd) { 879 case SIOCSIFADDR: 880 ifp->if_flags |= IFF_UP; 881 882 #ifdef INET 883 if (ifa->ifa_addr->sa_family == AF_INET) 884 arp_ifinit(&sc->sc_ac, ifa); 885 #endif 886 /* FALLTHROUGH */ 887 888 case SIOCSIFFLAGS: 889 if (ifp->if_flags & IFF_UP) { 890 if (ifp->if_flags & IFF_RUNNING) 891 error = ENETRESET; 892 else 893 tht_up(sc); 894 } else { 895 if (ifp->if_flags & IFF_RUNNING) 896 tht_down(sc); 897 } 898 break; 899 900 case SIOCGIFMEDIA: 901 case SIOCSIFMEDIA: 902 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 903 break; 904 905 default: 906 error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr); 907 } 908 909 if (error == ENETRESET) { 910 if (ifp->if_flags & IFF_RUNNING) 911 tht_iff(sc); 912 error = 0; 913 } 914 915 splx(s); 916 rw_exit_write(&sc->sc_lock); 917 918 return (error); 919 } 920 921 void 922 tht_up(struct tht_softc *sc) 923 { 924 struct ifnet *ifp = &sc->sc_ac.ac_if; 925 926 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 927 return; 928 } 929 930 if (tht_pkt_alloc(sc, &sc->sc_tx_list, THT_TXT_PKT_NUM, 931 THT_TXT_SGL_LEN) != 0) 932 return; 933 if (tht_pkt_alloc(sc, &sc->sc_rx_list, THT_RXF_PKT_NUM, 934 THT_RXF_SGL_LEN) != 0) 935 goto free_tx_list; 936 937 if (tht_fifo_alloc(sc, &sc->sc_txt, &tht_txt_desc) != 0) 938 goto free_rx_list; 939 if (tht_fifo_alloc(sc, &sc->sc_rxf, &tht_rxf_desc) != 0) 940 goto free_txt; 941 if (tht_fifo_alloc(sc, &sc->sc_rxd, &tht_rxd_desc) != 0) 942 goto free_rxf; 943 if (tht_fifo_alloc(sc, &sc->sc_txf, &tht_txf_desc) != 0) 944 goto free_rxd; 945 946 tht_write(sc, THT_REG_10G_FRM_LEN, MCLBYTES - ETHER_ALIGN); 947 tht_write(sc, THT_REG_10G_PAUSE, 0x96); 948 tht_write(sc, THT_REG_10G_RX_SEC, THT_REG_10G_SEC_AVAIL(0x10) | 949 THT_REG_10G_SEC_EMPTY(0x80)); 950 tht_write(sc, THT_REG_10G_TX_SEC, THT_REG_10G_SEC_AVAIL(0x10) | 951 THT_REG_10G_SEC_EMPTY(0xe0)); 952 tht_write(sc, THT_REG_10G_RFIFO_AEF, THT_REG_10G_FIFO_AE(0x0) | 953 THT_REG_10G_FIFO_AF(0x0)); 954 tht_write(sc, THT_REG_10G_TFIFO_AEF, THT_REG_10G_FIFO_AE(0x0) | 955 THT_REG_10G_FIFO_AF(0x0)); 956 tht_write(sc, THT_REG_10G_CTL, THT_REG_10G_CTL_TX_EN | 957 THT_REG_10G_CTL_RX_EN | THT_REG_10G_CTL_PAD | 958 THT_REG_10G_CTL_PROMISC); 959 960 tht_write(sc, THT_REG_VGLB, 0); 961 962 tht_write(sc, THT_REG_RX_MAX_FRAME, MCLBYTES - ETHER_ALIGN); 963 964 tht_write(sc, THT_REG_RDINTCM(0), THT_REG_RDINTCM_PKT_TH(12) | 965 THT_REG_RDINTCM_RXF_TH(4) | THT_REG_RDINTCM_COAL_RC | 966 THT_REG_RDINTCM_COAL(0x20)); 967 tht_write(sc, THT_REG_TDINTCM(0), THT_REG_TDINTCM_PKT_TH(12) | 968 THT_REG_TDINTCM_COAL_RC | THT_REG_TDINTCM_COAL(0x20)); 969 970 bcopy(sc->sc_ac.ac_enaddr, sc->sc_lladdr, ETHER_ADDR_LEN); 971 tht_lladdr_write(sc); 972 973 /* populate rxf fifo */ 974 tht_rxf_fill(sc, 1); 975 976 /* program promiscuous mode and multicast filters */ 977 tht_iff(sc); 978 979 ifp->if_flags |= IFF_RUNNING; 980 ifp->if_flags &= ~IFF_OACTIVE; 981 982 /* enable interrupts */ 983 sc->sc_imr = THT_IMR_UP(sc->sc_port); 984 tht_write(sc, THT_REG_IMR, sc->sc_imr); 985 986 return; 987 988 free_rxd: 989 tht_fifo_free(sc, &sc->sc_rxd); 990 free_rxf: 991 tht_fifo_free(sc, &sc->sc_rxf); 992 free_txt: 993 tht_fifo_free(sc, &sc->sc_txt); 994 995 tht_sw_reset(sc); 996 997 free_rx_list: 998 tht_pkt_free(sc, &sc->sc_rx_list); 999 free_tx_list: 1000 tht_pkt_free(sc, &sc->sc_tx_list); 1001 } 1002 1003 void 1004 tht_iff(struct tht_softc *sc) 1005 { 1006 struct ifnet *ifp = &sc->sc_ac.ac_if; 1007 struct ether_multi *enm; 1008 struct ether_multistep step; 1009 u_int32_t rxf; 1010 u_int8_t imf[THT_REG_RX_MCST_HASH_SIZE]; 1011 u_int8_t hash; 1012 int i; 1013 1014 ifp->if_flags &= ~IFF_ALLMULTI; 1015 1016 rxf = THT_REG_RX_FLT_OSEN | THT_REG_RX_FLT_AM | THT_REG_RX_FLT_AB; 1017 for (i = 0; i < THT_REG_RX_MAC_MCST_CNT; i++) { 1018 tht_write(sc, THT_REG_RX_MAC_MCST0(i), 0); 1019 tht_write(sc, THT_REG_RX_MAC_MCST1(i), 0); 1020 } 1021 memset(imf, 0x00, sizeof(imf)); 1022 1023 if (ifp->if_flags & IFF_PROMISC) { 1024 ifp->if_flags |= IFF_ALLMULTI; 1025 rxf |= THT_REG_RX_FLT_PRM_ALL; 1026 } else if (sc->sc_ac.ac_multirangecnt > 0) { 1027 ifp->if_flags |= IFF_ALLMULTI; 1028 memset(imf, 0xff, sizeof(imf)); 1029 } else { 1030 ETHER_FIRST_MULTI(step, &sc->sc_ac, enm); 1031 1032 #if 0 1033 /* fill the perfect multicast filters */ 1034 for (i = 0; i < THT_REG_RX_MAC_MCST_CNT; i++) { 1035 if (enm == NULL) 1036 break; 1037 1038 tht_write(sc, THT_REG_RX_MAC_MCST0(i), 1039 (enm->enm_addrlo[0] << 0) | 1040 (enm->enm_addrlo[1] << 8) | 1041 (enm->enm_addrlo[2] << 16) | 1042 (enm->enm_addrlo[3] << 24)); 1043 tht_write(sc, THT_REG_RX_MAC_MCST1(i), 1044 (enm->enm_addrlo[4] << 0) | 1045 (enm->enm_addrlo[5] << 8)); 1046 1047 ETHER_NEXT_MULTI(step, enm); 1048 } 1049 #endif 1050 1051 /* fill the imperfect multicast filter with whats left */ 1052 while (enm != NULL) { 1053 hash = 0x00; 1054 for (i = 0; i < ETHER_ADDR_LEN; i++) 1055 hash ^= enm->enm_addrlo[i]; 1056 setbit(imf, hash); 1057 1058 ETHER_NEXT_MULTI(step, enm); 1059 } 1060 } 1061 1062 tht_write_region(sc, THT_REG_RX_MCST_HASH, imf, sizeof(imf)); 1063 tht_write(sc, THT_REG_RX_FLT, rxf); 1064 } 1065 1066 void 1067 tht_down(struct tht_softc *sc) 1068 { 1069 struct ifnet *ifp = &sc->sc_ac.ac_if; 1070 1071 if (!ISSET(ifp->if_flags, IFF_RUNNING)) { 1072 return; 1073 } 1074 1075 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE | IFF_ALLMULTI); 1076 1077 while (tht_fifo_writable(sc, &sc->sc_txt) < sc->sc_txt.tf_len && 1078 tht_fifo_readable(sc, &sc->sc_txf) > 0) 1079 tsleep(sc, 0, "thtdown", hz); 1080 1081 sc->sc_imr = THT_IMR_DOWN(sc->sc_port); 1082 tht_write(sc, THT_REG_IMR, sc->sc_imr); 1083 1084 tht_sw_reset(sc); 1085 1086 tht_fifo_free(sc, &sc->sc_txf); 1087 tht_fifo_free(sc, &sc->sc_rxd); 1088 tht_fifo_free(sc, &sc->sc_rxf); 1089 tht_fifo_free(sc, &sc->sc_txt); 1090 1091 /* free mbufs that were on the rxf fifo */ 1092 tht_rxf_drain(sc); 1093 1094 tht_pkt_free(sc, &sc->sc_rx_list); 1095 tht_pkt_free(sc, &sc->sc_tx_list); 1096 } 1097 1098 void 1099 tht_start(struct ifnet *ifp) 1100 { 1101 struct tht_softc *sc = ifp->if_softc; 1102 struct tht_pkt *pkt; 1103 struct tht_tx_task txt; 1104 u_int32_t flags; 1105 struct mbuf *m; 1106 int bc; 1107 1108 if (!(ifp->if_flags & IFF_RUNNING)) 1109 return; 1110 if (ifp->if_flags & IFF_OACTIVE) 1111 return; 1112 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1113 return; 1114 1115 if (tht_fifo_writable(sc, &sc->sc_txt) <= THT_FIFO_DESC_LEN) 1116 return; 1117 1118 bzero(&txt, sizeof(txt)); 1119 1120 tht_fifo_pre(sc, &sc->sc_txt); 1121 1122 do { 1123 IFQ_POLL(&ifp->if_snd, m); 1124 if (m == NULL) 1125 break; 1126 1127 pkt = tht_pkt_get(&sc->sc_tx_list); 1128 if (pkt == NULL) { 1129 ifp->if_flags |= IFF_OACTIVE; 1130 break; 1131 } 1132 1133 IFQ_DEQUEUE(&ifp->if_snd, m); 1134 if (tht_load_pkt(sc, pkt, m) != 0) { 1135 m_freem(m); 1136 tht_pkt_put(&sc->sc_tx_list, pkt); 1137 ifp->if_oerrors++; 1138 break; 1139 } 1140 /* thou shalt not use m after this point, only pkt->tp_m */ 1141 1142 #if NBPFILTER > 0 1143 if (ifp->if_bpf) 1144 bpf_mtap(ifp->if_bpf, pkt->tp_m, BPF_DIRECTION_OUT); 1145 #endif 1146 1147 bc = sizeof(txt) + 1148 sizeof(struct tht_pbd) * pkt->tp_dmap->dm_nsegs; 1149 1150 flags = THT_TXT_TYPE | LWORDS(bc); 1151 txt.flags = htole32(flags); 1152 txt.len = htole16(pkt->tp_m->m_pkthdr.len); 1153 txt.uid = pkt->tp_id; 1154 1155 DPRINTF(THT_D_TX, "%s: txt uid 0x%llx flags 0x%08x len %d\n", 1156 DEVNAME(sc), pkt->tp_id, flags, pkt->tp_m->m_pkthdr.len); 1157 1158 tht_fifo_write(sc, &sc->sc_txt, &txt, sizeof(txt)); 1159 tht_fifo_write_dmap(sc, &sc->sc_txt, pkt->tp_dmap); 1160 tht_fifo_write_pad(sc, &sc->sc_txt, bc); 1161 1162 bus_dmamap_sync(sc->sc_thtc->sc_dmat, pkt->tp_dmap, 0, 1163 pkt->tp_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1164 1165 ifp->if_opackets++; 1166 1167 } while (sc->sc_txt.tf_ready > THT_FIFO_DESC_LEN); 1168 1169 tht_fifo_post(sc, &sc->sc_txt); 1170 } 1171 1172 int 1173 tht_load_pkt(struct tht_softc *sc, struct tht_pkt *pkt, struct mbuf *m) 1174 { 1175 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1176 bus_dmamap_t dmap = pkt->tp_dmap; 1177 struct mbuf *m0 = NULL; 1178 1179 switch(bus_dmamap_load_mbuf(dmat, dmap, m, BUS_DMA_NOWAIT)) { 1180 case 0: 1181 pkt->tp_m = m; 1182 break; 1183 1184 case EFBIG: /* mbuf chain is too fragmented */ 1185 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1186 if (m0 == NULL) 1187 return (ENOBUFS); 1188 if (m->m_pkthdr.len > MHLEN) { 1189 MCLGET(m0, M_DONTWAIT); 1190 if (!(m0->m_flags & M_EXT)) { 1191 m_freem(m0); 1192 return (ENOBUFS); 1193 } 1194 } 1195 m_copydata(m, 0, m->m_pkthdr.len, mtod(m0, caddr_t)); 1196 m0->m_pkthdr.len = m0->m_len = m->m_pkthdr.len; 1197 if (bus_dmamap_load_mbuf(dmat, dmap, m0, BUS_DMA_NOWAIT)) { 1198 m_freem(m0); 1199 return (ENOBUFS); 1200 } 1201 1202 m_freem(m); 1203 pkt->tp_m = m0; 1204 break; 1205 1206 default: 1207 return (ENOBUFS); 1208 } 1209 1210 return (0); 1211 } 1212 1213 void 1214 tht_txf(struct tht_softc *sc) 1215 { 1216 struct ifnet *ifp = &sc->sc_ac.ac_if; 1217 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1218 bus_dmamap_t dmap; 1219 struct tht_tx_free txf; 1220 struct tht_pkt *pkt; 1221 1222 if (tht_fifo_readable(sc, &sc->sc_txf) < sizeof(txf)) 1223 return; 1224 1225 tht_fifo_pre(sc, &sc->sc_txf); 1226 1227 do { 1228 tht_fifo_read(sc, &sc->sc_txf, &txf, sizeof(txf)); 1229 1230 DPRINTF(THT_D_TX, "%s: txf uid 0x%llx\n", DEVNAME(sc), txf.uid); 1231 1232 pkt = &sc->sc_tx_list.tpl_pkts[txf.uid]; 1233 dmap = pkt->tp_dmap; 1234 1235 bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize, 1236 BUS_DMASYNC_POSTWRITE); 1237 bus_dmamap_unload(dmat, dmap); 1238 1239 m_freem(pkt->tp_m); 1240 1241 tht_pkt_put(&sc->sc_tx_list, pkt); 1242 1243 } while (sc->sc_txf.tf_ready >= sizeof(txf)); 1244 1245 ifp->if_flags &= ~IFF_OACTIVE; 1246 1247 tht_fifo_post(sc, &sc->sc_txf); 1248 } 1249 1250 void 1251 tht_rxf_fill(struct tht_softc *sc, int wait) 1252 { 1253 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1254 bus_dmamap_t dmap; 1255 struct tht_rx_free rxf; 1256 struct tht_pkt *pkt; 1257 struct mbuf *m; 1258 int bc; 1259 1260 if (tht_fifo_writable(sc, &sc->sc_rxf) <= THT_FIFO_DESC_LEN) 1261 return; 1262 1263 tht_fifo_pre(sc, &sc->sc_rxf); 1264 1265 for (;;) { 1266 if ((pkt = tht_pkt_get(&sc->sc_rx_list)) == NULL) 1267 goto done; 1268 1269 MGETHDR(m, wait ? M_WAIT : M_DONTWAIT, MT_DATA); 1270 if (m == NULL) 1271 goto put_pkt; 1272 1273 MCLGET(m, wait ? M_WAIT : M_DONTWAIT); 1274 if (!ISSET(m->m_flags, M_EXT)) 1275 goto free_m; 1276 1277 m->m_data += ETHER_ALIGN; 1278 m->m_len = m->m_pkthdr.len = MCLBYTES - ETHER_ALIGN; 1279 1280 dmap = pkt->tp_dmap; 1281 if (bus_dmamap_load_mbuf(dmat, dmap, m, 1282 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT) != 0) 1283 goto free_m; 1284 1285 pkt->tp_m = m; 1286 1287 bc = sizeof(rxf) + sizeof(struct tht_pbd) * dmap->dm_nsegs; 1288 1289 rxf.bc = htole16(LWORDS(bc)); 1290 rxf.type = htole16(THT_RXF_TYPE); 1291 rxf.uid = pkt->tp_id; 1292 1293 tht_fifo_write(sc, &sc->sc_rxf, &rxf, sizeof(rxf)); 1294 tht_fifo_write_dmap(sc, &sc->sc_rxf, dmap); 1295 tht_fifo_write_pad(sc, &sc->sc_rxf, bc); 1296 1297 bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize, 1298 BUS_DMASYNC_PREREAD); 1299 1300 if (sc->sc_rxf.tf_ready <= THT_FIFO_DESC_LEN) 1301 goto done; 1302 } 1303 1304 free_m: 1305 m_freem(m); 1306 put_pkt: 1307 tht_pkt_put(&sc->sc_rx_list, pkt); 1308 done: 1309 tht_fifo_post(sc, &sc->sc_rxf); 1310 } 1311 1312 void 1313 tht_rxf_drain(struct tht_softc *sc) 1314 { 1315 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1316 bus_dmamap_t dmap; 1317 struct tht_pkt *pkt; 1318 1319 while ((pkt = tht_pkt_used(&sc->sc_rx_list)) != NULL) { 1320 dmap = pkt->tp_dmap; 1321 1322 bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize, 1323 BUS_DMASYNC_POSTREAD); 1324 bus_dmamap_unload(dmat, dmap); 1325 1326 m_freem(pkt->tp_m); 1327 1328 tht_pkt_put(&sc->sc_rx_list, pkt); 1329 } 1330 } 1331 1332 void 1333 tht_rxd(struct tht_softc *sc) 1334 { 1335 struct ifnet *ifp = &sc->sc_ac.ac_if; 1336 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1337 bus_dmamap_t dmap; 1338 struct tht_rx_desc rxd; 1339 struct tht_pkt *pkt; 1340 struct mbuf *m; 1341 int bc; 1342 u_int32_t flags; 1343 1344 if (tht_fifo_readable(sc, &sc->sc_rxd) < sizeof(rxd)) 1345 return; 1346 1347 tht_fifo_pre(sc, &sc->sc_rxd); 1348 1349 do { 1350 tht_fifo_read(sc, &sc->sc_rxd, &rxd, sizeof(rxd)); 1351 1352 flags = letoh32(rxd.flags); 1353 bc = THT_RXD_FLAGS_BC(flags) * 8; 1354 bc -= sizeof(rxd); 1355 pkt = &sc->sc_rx_list.tpl_pkts[rxd.uid]; 1356 1357 dmap = pkt->tp_dmap; 1358 1359 bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize, 1360 BUS_DMASYNC_POSTREAD); 1361 bus_dmamap_unload(dmat, dmap); 1362 1363 m = pkt->tp_m; 1364 m->m_pkthdr.rcvif = ifp; 1365 m->m_pkthdr.len = m->m_len = letoh16(rxd.len); 1366 1367 /* XXX process type 3 rx descriptors */ 1368 1369 #if NBPFILTER > 0 1370 if (ifp->if_bpf) 1371 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1372 #endif 1373 1374 ether_input_mbuf(ifp, m); 1375 1376 tht_pkt_put(&sc->sc_rx_list, pkt); 1377 1378 while (bc > 0) { 1379 static u_int32_t pad; 1380 1381 tht_fifo_read(sc, &sc->sc_rxd, &pad, sizeof(pad)); 1382 bc -= sizeof(pad); 1383 } 1384 1385 ifp->if_ipackets++; 1386 1387 } while (sc->sc_rxd.tf_ready >= sizeof(rxd)); 1388 1389 tht_fifo_post(sc, &sc->sc_rxd); 1390 1391 /* put more pkts on the fifo */ 1392 tht_rxf_fill(sc, 0); 1393 } 1394 1395 void 1396 tht_watchdog(struct ifnet *ifp) 1397 { 1398 /* do nothing */ 1399 } 1400 1401 int 1402 tht_media_change(struct ifnet *ifp) 1403 { 1404 /* ignore */ 1405 return (0); 1406 } 1407 1408 void 1409 tht_media_status(struct ifnet *ifp, struct ifmediareq *imr) 1410 { 1411 struct tht_softc *sc = ifp->if_softc; 1412 1413 imr->ifm_active = IFM_ETHER | IFM_AUTO; 1414 imr->ifm_status = IFM_AVALID; 1415 1416 tht_link_state(sc); 1417 1418 if (LINK_STATE_IS_UP(ifp->if_link_state)) 1419 imr->ifm_status |= IFM_ACTIVE; 1420 } 1421 1422 int 1423 tht_fifo_alloc(struct tht_softc *sc, struct tht_fifo *tf, 1424 struct tht_fifo_desc *tfd) 1425 { 1426 u_int64_t dva; 1427 1428 tf->tf_len = THT_FIFO_SIZE(tfd->tfd_size); 1429 tf->tf_mem = tht_dmamem_alloc(sc, tf->tf_len, THT_FIFO_ALIGN); 1430 if (tf->tf_mem == NULL) 1431 return (1); 1432 1433 tf->tf_desc = tfd; 1434 tf->tf_rptr = tf->tf_wptr = 0; 1435 1436 bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem), 1437 0, tf->tf_len, THT_FIFO_PRE_SYNC(tfd)); 1438 1439 dva = THT_DMA_DVA(tf->tf_mem); 1440 tht_write(sc, tfd->tfd_cfg0, (u_int32_t)dva | tfd->tfd_size); 1441 tht_write(sc, tfd->tfd_cfg1, (u_int32_t)(dva >> 32)); 1442 1443 return (0); 1444 } 1445 1446 void 1447 tht_fifo_free(struct tht_softc *sc, struct tht_fifo *tf) 1448 { 1449 bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem), 1450 0, tf->tf_len, THT_FIFO_POST_SYNC(tf->tf_desc)); 1451 tht_dmamem_free(sc, tf->tf_mem); 1452 } 1453 1454 size_t 1455 tht_fifo_readable(struct tht_softc *sc, struct tht_fifo *tf) 1456 { 1457 tf->tf_wptr = tht_read(sc, tf->tf_desc->tfd_wptr); 1458 tf->tf_wptr &= THT_FIFO_PTR_MASK; 1459 tf->tf_ready = tf->tf_wptr - tf->tf_rptr; 1460 if (tf->tf_ready < 0) 1461 tf->tf_ready += tf->tf_len; 1462 1463 DPRINTF(THT_D_FIFO, "%s: fifo rdable wptr: %d rptr: %d ready: %d\n", 1464 DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready); 1465 1466 return (tf->tf_ready); 1467 } 1468 1469 size_t 1470 tht_fifo_writable(struct tht_softc *sc, struct tht_fifo *tf) 1471 { 1472 tf->tf_rptr = tht_read(sc, tf->tf_desc->tfd_rptr); 1473 tf->tf_rptr &= THT_FIFO_PTR_MASK; 1474 tf->tf_ready = tf->tf_rptr - tf->tf_wptr; 1475 if (tf->tf_ready <= 0) 1476 tf->tf_ready += tf->tf_len; 1477 1478 DPRINTF(THT_D_FIFO, "%s: fifo wrable wptr: %d rptr: %d ready: %d\n", 1479 DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready); 1480 1481 return (tf->tf_ready); 1482 } 1483 1484 void 1485 tht_fifo_pre(struct tht_softc *sc, struct tht_fifo *tf) 1486 { 1487 bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem), 1488 0, tf->tf_len, THT_FIFO_POST_SYNC(tf->tf_desc)); 1489 } 1490 1491 void 1492 tht_fifo_read(struct tht_softc *sc, struct tht_fifo *tf, 1493 void *buf, size_t buflen) 1494 { 1495 u_int8_t *fifo = THT_DMA_KVA(tf->tf_mem); 1496 u_int8_t *desc = buf; 1497 size_t len; 1498 1499 tf->tf_ready -= buflen; 1500 1501 len = tf->tf_len - tf->tf_rptr; 1502 1503 if (len < buflen) { 1504 memcpy(desc, fifo + tf->tf_rptr, len); 1505 1506 buflen -= len; 1507 desc += len; 1508 1509 tf->tf_rptr = 0; 1510 } 1511 1512 memcpy(desc, fifo + tf->tf_rptr, buflen); 1513 tf->tf_rptr += buflen; 1514 1515 DPRINTF(THT_D_FIFO, "%s: fifo rd wptr: %d rptr: %d ready: %d\n", 1516 DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready); 1517 } 1518 1519 void 1520 tht_fifo_write(struct tht_softc *sc, struct tht_fifo *tf, 1521 void *buf, size_t buflen) 1522 { 1523 u_int8_t *fifo = THT_DMA_KVA(tf->tf_mem); 1524 u_int8_t *desc = buf; 1525 size_t len; 1526 1527 tf->tf_ready -= buflen; 1528 1529 len = tf->tf_len - tf->tf_wptr; 1530 1531 if (len < buflen) { 1532 memcpy(fifo + tf->tf_wptr, desc, len); 1533 1534 buflen -= len; 1535 desc += len; 1536 1537 tf->tf_wptr = 0; 1538 } 1539 1540 memcpy(fifo + tf->tf_wptr, desc, buflen); 1541 tf->tf_wptr += buflen; 1542 tf->tf_wptr %= tf->tf_len; 1543 1544 DPRINTF(THT_D_FIFO, "%s: fifo wr wptr: %d rptr: %d ready: %d\n", 1545 DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready); 1546 } 1547 1548 void 1549 tht_fifo_write_dmap(struct tht_softc *sc, struct tht_fifo *tf, 1550 bus_dmamap_t dmap) 1551 { 1552 struct tht_pbd pbd; 1553 u_int64_t dva; 1554 int i; 1555 1556 for (i = 0; i < dmap->dm_nsegs; i++) { 1557 dva = dmap->dm_segs[i].ds_addr; 1558 1559 pbd.addr_lo = htole32(dva); 1560 pbd.addr_hi = htole32(dva >> 32); 1561 pbd.len = htole32(dmap->dm_segs[i].ds_len); 1562 1563 tht_fifo_write(sc, tf, &pbd, sizeof(pbd)); 1564 } 1565 } 1566 1567 void 1568 tht_fifo_write_pad(struct tht_softc *sc, struct tht_fifo *tf, int bc) 1569 { 1570 const static u_int32_t pad = 0x0; 1571 1572 /* this assumes you'll only ever be writing multiples of 4 bytes */ 1573 if (bc % 8) 1574 tht_fifo_write(sc, tf, (void *)&pad, sizeof(pad)); 1575 } 1576 1577 void 1578 tht_fifo_post(struct tht_softc *sc, struct tht_fifo *tf) 1579 { 1580 bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem), 1581 0, tf->tf_len, THT_FIFO_PRE_SYNC(tf->tf_desc)); 1582 if (tf->tf_desc->tfd_write) 1583 tht_write(sc, tf->tf_desc->tfd_wptr, tf->tf_wptr); 1584 else 1585 tht_write(sc, tf->tf_desc->tfd_rptr, tf->tf_rptr); 1586 1587 DPRINTF(THT_D_FIFO, "%s: fifo post wptr: %d rptr: %d\n", DEVNAME(sc), 1588 tf->tf_wptr, tf->tf_rptr); 1589 } 1590 1591 const static bus_size_t tht_mac_regs[3] = { 1592 THT_REG_RX_UNC_MAC2, THT_REG_RX_UNC_MAC1, THT_REG_RX_UNC_MAC0 1593 }; 1594 1595 void 1596 tht_lladdr_read(struct tht_softc *sc) 1597 { 1598 int i; 1599 1600 for (i = 0; i < nitems(tht_mac_regs); i++) 1601 sc->sc_lladdr[i] = betoh16(tht_read(sc, tht_mac_regs[i])); 1602 } 1603 1604 void 1605 tht_lladdr_write(struct tht_softc *sc) 1606 { 1607 int i; 1608 1609 for (i = 0; i < nitems(tht_mac_regs); i++) 1610 tht_write(sc, tht_mac_regs[i], htobe16(sc->sc_lladdr[i])); 1611 } 1612 1613 #define tht_swrst_set(_s, _r) tht_write((_s), (_r), 0x1) 1614 #define tht_swrst_clr(_s, _r) tht_write((_s), (_r), 0x0) 1615 int 1616 tht_sw_reset(struct tht_softc *sc) 1617 { 1618 int i; 1619 1620 /* this follows SW Reset process in 8.8 of the doco */ 1621 1622 /* 1. disable rx */ 1623 tht_clr(sc, THT_REG_RX_FLT, THT_REG_RX_FLT_OSEN); 1624 1625 /* 2. initiate port disable */ 1626 tht_swrst_set(sc, THT_REG_DIS_PRT); 1627 1628 /* 3. initiate queue disable */ 1629 tht_swrst_set(sc, THT_REG_DIS_QU_0); 1630 tht_swrst_set(sc, THT_REG_DIS_QU_1); 1631 1632 /* 4. wait for successful finish of previous tasks */ 1633 if (!tht_wait_set(sc, THT_REG_RST_PRT, THT_REG_RST_PRT_ACTIVE, 1000)) 1634 return (1); 1635 1636 /* 5. Reset interrupt registers */ 1637 tht_write(sc, THT_REG_IMR, 0x0); /* 5.a */ 1638 tht_read(sc, THT_REG_ISR); /* 5.b */ 1639 for (i = 0; i < THT_NQUEUES; i++) { 1640 tht_write(sc, THT_REG_RDINTCM(i), 0x0); /* 5.c/5.d */ 1641 tht_write(sc, THT_REG_TDINTCM(i), 0x0); /* 5.e */ 1642 } 1643 1644 /* 6. initiate queue reset */ 1645 tht_swrst_set(sc, THT_REG_RST_QU_0); 1646 tht_swrst_set(sc, THT_REG_RST_QU_1); 1647 1648 /* 7. initiate port reset */ 1649 tht_swrst_set(sc, THT_REG_RST_PRT); 1650 1651 /* 8. clear txt/rxf/rxd/txf read and write ptrs */ 1652 for (i = 0; i < THT_NQUEUES; i++) { 1653 tht_write(sc, THT_REG_TXT_RPTR(i), 0); 1654 tht_write(sc, THT_REG_RXF_RPTR(i), 0); 1655 tht_write(sc, THT_REG_RXD_RPTR(i), 0); 1656 tht_write(sc, THT_REG_TXF_RPTR(i), 0); 1657 1658 tht_write(sc, THT_REG_TXT_WPTR(i), 0); 1659 tht_write(sc, THT_REG_RXF_WPTR(i), 0); 1660 tht_write(sc, THT_REG_RXD_WPTR(i), 0); 1661 tht_write(sc, THT_REG_TXF_WPTR(i), 0); 1662 } 1663 1664 /* 9. unset port disable */ 1665 tht_swrst_clr(sc, THT_REG_DIS_PRT); 1666 1667 /* 10. unset queue disable */ 1668 tht_swrst_clr(sc, THT_REG_DIS_QU_0); 1669 tht_swrst_clr(sc, THT_REG_DIS_QU_1); 1670 1671 /* 11. unset queue reset */ 1672 tht_swrst_clr(sc, THT_REG_RST_QU_0); 1673 tht_swrst_clr(sc, THT_REG_RST_QU_1); 1674 1675 /* 12. unset port reset */ 1676 tht_swrst_clr(sc, THT_REG_RST_PRT); 1677 1678 /* 13. enable rx */ 1679 tht_set(sc, THT_REG_RX_FLT, THT_REG_RX_FLT_OSEN); 1680 1681 return (0); 1682 } 1683 1684 int 1685 tht_fw_load(struct tht_softc *sc) 1686 { 1687 struct timeout ticker; 1688 volatile int ok = 1; 1689 u_int8_t *fw, *buf; 1690 size_t fwlen, wrlen; 1691 int error = 1; 1692 1693 if (loadfirmware("tht", &fw, &fwlen) != 0) 1694 return (1); 1695 1696 if ((fwlen % 8) != 0) 1697 goto err; 1698 1699 buf = fw; 1700 while (fwlen > 0) { 1701 while (tht_fifo_writable(sc, &sc->sc_txt) <= THT_FIFO_GAP) { 1702 if (tsleep(sc, PCATCH, "thtfw", 1) == EINTR) 1703 goto err; 1704 } 1705 1706 wrlen = MIN(sc->sc_txt.tf_ready - THT_FIFO_GAP, fwlen); 1707 tht_fifo_pre(sc, &sc->sc_txt); 1708 tht_fifo_write(sc, &sc->sc_txt, buf, wrlen); 1709 tht_fifo_post(sc, &sc->sc_txt); 1710 1711 fwlen -= wrlen; 1712 buf += wrlen; 1713 } 1714 1715 timeout_set(&ticker, tht_fw_tick, (void *)&ok); 1716 timeout_add_sec(&ticker, 2); 1717 while (ok) { 1718 if (tht_read(sc, THT_REG_INIT_STATUS) != 0) { 1719 error = 0; 1720 break; 1721 } 1722 1723 if (tsleep(sc, PCATCH, "thtinit", 1) == EINTR) 1724 goto err; 1725 } 1726 timeout_del(&ticker); 1727 1728 tht_write(sc, THT_REG_INIT_SEMAPHORE, 0x1); 1729 1730 err: 1731 free(fw, M_DEVBUF); 1732 return (error); 1733 } 1734 1735 void 1736 tht_fw_tick(void *arg) 1737 { 1738 volatile int *ok = arg; 1739 1740 *ok = 0; 1741 } 1742 1743 void 1744 tht_link_state(struct tht_softc *sc) 1745 { 1746 static const struct timeval interval = { 0, 10000 }; 1747 struct ifnet *ifp = &sc->sc_ac.ac_if; 1748 int link_state = LINK_STATE_DOWN; 1749 1750 if (!ratecheck(&sc->sc_mediacheck, &interval)) 1751 return; 1752 1753 if (tht_read(sc, THT_REG_MAC_LNK_STAT) & THT_REG_MAC_LNK_STAT_LINK) 1754 link_state = LINK_STATE_FULL_DUPLEX; 1755 1756 if (ifp->if_link_state != link_state) { 1757 ifp->if_link_state = link_state; 1758 if_link_state_change(ifp); 1759 } 1760 1761 if (LINK_STATE_IS_UP(ifp->if_link_state)) 1762 ifp->if_baudrate = IF_Gbps(10); 1763 else 1764 ifp->if_baudrate = 0; 1765 } 1766 1767 u_int32_t 1768 tht_read(struct tht_softc *sc, bus_size_t r) 1769 { 1770 bus_space_barrier(sc->sc_thtc->sc_memt, sc->sc_memh, r, 4, 1771 BUS_SPACE_BARRIER_READ); 1772 return (bus_space_read_4(sc->sc_thtc->sc_memt, sc->sc_memh, r)); 1773 } 1774 1775 void 1776 tht_write(struct tht_softc *sc, bus_size_t r, u_int32_t v) 1777 { 1778 bus_space_write_4(sc->sc_thtc->sc_memt, sc->sc_memh, r, v); 1779 bus_space_barrier(sc->sc_thtc->sc_memt, sc->sc_memh, r, 4, 1780 BUS_SPACE_BARRIER_WRITE); 1781 } 1782 1783 void 1784 tht_write_region(struct tht_softc *sc, bus_size_t r, void *buf, size_t len) 1785 { 1786 bus_space_write_raw_region_4(sc->sc_thtc->sc_memt, sc->sc_memh, r, 1787 buf, len); 1788 bus_space_barrier(sc->sc_thtc->sc_memt, sc->sc_memh, r, len, 1789 BUS_SPACE_BARRIER_WRITE); 1790 } 1791 1792 int 1793 tht_wait_eq(struct tht_softc *sc, bus_size_t r, u_int32_t m, u_int32_t v, 1794 int timeout) 1795 { 1796 while ((tht_read(sc, r) & m) != v) { 1797 if (timeout == 0) 1798 return (0); 1799 1800 delay(1000); 1801 timeout--; 1802 } 1803 1804 return (1); 1805 } 1806 1807 int 1808 tht_wait_ne(struct tht_softc *sc, bus_size_t r, u_int32_t m, u_int32_t v, 1809 int timeout) 1810 { 1811 while ((tht_read(sc, r) & m) == v) { 1812 if (timeout == 0) 1813 return (0); 1814 1815 delay(1000); 1816 timeout--; 1817 } 1818 1819 return (1); 1820 } 1821 1822 struct tht_dmamem * 1823 tht_dmamem_alloc(struct tht_softc *sc, bus_size_t size, bus_size_t align) 1824 { 1825 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1826 struct tht_dmamem *tdm; 1827 int nsegs; 1828 1829 tdm = malloc(sizeof(struct tht_dmamem), M_DEVBUF, M_WAITOK | M_ZERO); 1830 tdm->tdm_size = size; 1831 1832 if (bus_dmamap_create(dmat, size, 1, size, 0, 1833 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &tdm->tdm_map) != 0) 1834 goto tdmfree; 1835 1836 if (bus_dmamem_alloc(dmat, size, align, 0, &tdm->tdm_seg, 1, &nsegs, 1837 BUS_DMA_WAITOK | BUS_DMA_ZERO) != 0) 1838 goto destroy; 1839 1840 if (bus_dmamem_map(dmat, &tdm->tdm_seg, nsegs, size, &tdm->tdm_kva, 1841 BUS_DMA_WAITOK) != 0) 1842 goto free; 1843 1844 if (bus_dmamap_load(dmat, tdm->tdm_map, tdm->tdm_kva, size, 1845 NULL, BUS_DMA_WAITOK) != 0) 1846 goto unmap; 1847 1848 return (tdm); 1849 1850 unmap: 1851 bus_dmamem_unmap(dmat, tdm->tdm_kva, size); 1852 free: 1853 bus_dmamem_free(dmat, &tdm->tdm_seg, 1); 1854 destroy: 1855 bus_dmamap_destroy(dmat, tdm->tdm_map); 1856 tdmfree: 1857 free(tdm, M_DEVBUF); 1858 1859 return (NULL); 1860 } 1861 1862 void 1863 tht_dmamem_free(struct tht_softc *sc, struct tht_dmamem *tdm) 1864 { 1865 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1866 1867 bus_dmamap_unload(dmat, tdm->tdm_map); 1868 bus_dmamem_unmap(dmat, tdm->tdm_kva, tdm->tdm_size); 1869 bus_dmamem_free(dmat, &tdm->tdm_seg, 1); 1870 bus_dmamap_destroy(dmat, tdm->tdm_map); 1871 free(tdm, M_DEVBUF); 1872 } 1873 1874 int 1875 tht_pkt_alloc(struct tht_softc *sc, struct tht_pkt_list *tpl, int npkts, 1876 int nsegs) 1877 { 1878 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1879 struct tht_pkt *pkt; 1880 int i; 1881 1882 tpl->tpl_pkts = malloc(sizeof(struct tht_pkt) * npkts, M_DEVBUF, 1883 M_WAITOK | M_ZERO); 1884 1885 TAILQ_INIT(&tpl->tpl_free); 1886 TAILQ_INIT(&tpl->tpl_used); 1887 for (i = 0; i < npkts; i++) { 1888 pkt = &tpl->tpl_pkts[i]; 1889 1890 pkt->tp_id = i; 1891 if (bus_dmamap_create(dmat, THT_PBD_PKTLEN, nsegs, 1892 THT_PBD_PKTLEN, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1893 &pkt->tp_dmap) != 0) { 1894 tht_pkt_free(sc, tpl); 1895 return (1); 1896 } 1897 1898 TAILQ_INSERT_TAIL(&tpl->tpl_free, pkt, tp_link); 1899 } 1900 1901 return (0); 1902 } 1903 1904 void 1905 tht_pkt_free(struct tht_softc *sc, struct tht_pkt_list *tpl) 1906 { 1907 bus_dma_tag_t dmat = sc->sc_thtc->sc_dmat; 1908 struct tht_pkt *pkt; 1909 1910 while ((pkt = tht_pkt_get(tpl)) != NULL) 1911 bus_dmamap_destroy(dmat, pkt->tp_dmap); 1912 free(tpl->tpl_pkts, M_DEVBUF); 1913 tpl->tpl_pkts = NULL; 1914 } 1915 1916 void 1917 tht_pkt_put(struct tht_pkt_list *tpl, struct tht_pkt *pkt) 1918 { 1919 TAILQ_REMOVE(&tpl->tpl_used, pkt, tp_link); 1920 TAILQ_INSERT_TAIL(&tpl->tpl_free, pkt, tp_link); 1921 } 1922 1923 struct tht_pkt * 1924 tht_pkt_get(struct tht_pkt_list *tpl) 1925 { 1926 struct tht_pkt *pkt; 1927 1928 pkt = TAILQ_FIRST(&tpl->tpl_free); 1929 if (pkt != NULL) { 1930 TAILQ_REMOVE(&tpl->tpl_free, pkt, tp_link); 1931 TAILQ_INSERT_TAIL(&tpl->tpl_used, pkt, tp_link); 1932 1933 } 1934 1935 return (pkt); 1936 } 1937 1938 struct tht_pkt * 1939 tht_pkt_used(struct tht_pkt_list *tpl) 1940 { 1941 return (TAILQ_FIRST(&tpl->tpl_used)); 1942 } 1943