1 /* $OpenBSD: if_xl_pci.c,v 1.48 2022/03/11 18:00:50 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_xl.c,v 1.72 2000/01/09 21:12:59 wpaul Exp $ 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/socket.h> 43 #include <sys/ioctl.h> 44 #include <sys/errno.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <dev/mii/miivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pcidevs.h> 59 60 #if NBPFILTER > 0 61 #include <net/bpf.h> 62 #endif 63 64 /* 65 * The following #define causes the code to use PIO to access the 66 * chip's registers instead of memory mapped mode. The reason PIO mode 67 * is on by default is that the Etherlink XL manual seems to indicate 68 * that only the newer revision chips (3c905B) support both PIO and 69 * memory mapped access. Since we want to be compatible with the older 70 * bus master chips, we use PIO here. If you comment this out, the 71 * driver will use memory mapped I/O, which may be faster but which 72 * might not work on some devices. 73 */ 74 #define XL_USEIOSPACE 75 76 #define XL_PCI_FUNCMEM 0x0018 77 #define XL_PCI_INTR 0x0004 78 #define XL_PCI_INTRACK 0x8000 79 80 #include <dev/ic/xlreg.h> 81 82 int xl_pci_match(struct device *, void *, void *); 83 void xl_pci_attach(struct device *, struct device *, void *); 84 int xl_pci_detach(struct device *, int); 85 void xl_pci_intr_ack(struct xl_softc *); 86 #ifndef SMALL_KERNEL 87 void xl_pci_wol_power(void *); 88 #endif 89 90 struct xl_pci_softc { 91 struct xl_softc psc_softc; 92 pci_chipset_tag_t psc_pc; 93 pcitag_t psc_tag; 94 bus_size_t psc_iosize; 95 bus_size_t psc_funsize; 96 }; 97 98 const struct cfattach xl_pci_ca = { 99 sizeof(struct xl_pci_softc), xl_pci_match, xl_pci_attach, 100 xl_pci_detach, xl_activate 101 }; 102 103 const struct pci_matchid xl_pci_devices[] = { 104 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CSOHO100TX }, 105 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900TPO }, 106 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900COMBO }, 107 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900B }, 108 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900BCOMBO }, 109 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900BTPC }, 110 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C900BFL }, 111 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905TX }, 112 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905T4 }, 113 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BTX }, 114 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BT4 }, 115 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BCOMBO }, 116 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905BFX }, 117 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C980TX }, 118 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C980CTX }, 119 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C905CTX }, 120 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C450 }, 121 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C555 }, 122 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C556 }, 123 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C556B }, 124 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C9201 }, 125 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C920BEMBW }, 126 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C575 }, 127 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFE575BT }, 128 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFE575CT }, 129 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFEM656 }, 130 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFEM656B }, 131 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CCFEM656C }, 132 }; 133 134 int 135 xl_pci_match(struct device *parent, void *match, void *aux) 136 { 137 return (pci_matchbyid((struct pci_attach_args *)aux, xl_pci_devices, 138 nitems(xl_pci_devices))); 139 } 140 141 void 142 xl_pci_attach(struct device *parent, struct device *self, void *aux) 143 { 144 struct xl_pci_softc *psc = (void *)self; 145 struct xl_softc *sc = &psc->psc_softc; 146 struct pci_attach_args *pa = aux; 147 pci_chipset_tag_t pc = pa->pa_pc; 148 pci_intr_handle_t ih; 149 const char *intrstr = NULL; 150 bus_size_t iosize, funsize; 151 #ifndef SMALL_KERNEL 152 u_int32_t command; 153 #endif 154 155 psc->psc_pc = pc; 156 psc->psc_tag = pa->pa_tag; 157 sc->sc_dmat = pa->pa_dmat; 158 159 sc->xl_flags = 0; 160 sc->wol_power = sc->wol_power_arg = NULL; 161 162 /* set required flags */ 163 switch (PCI_PRODUCT(pa->pa_id)) { 164 case TC_DEVICEID_HURRICANE_555: 165 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 166 break; 167 case TC_DEVICEID_HURRICANE_556: 168 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 169 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET; 170 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR|XL_FLAG_INVERT_MII_PWR; 171 sc->xl_flags |= XL_FLAG_8BITROM; 172 break; 173 case TC_DEVICEID_HURRICANE_556B: 174 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 175 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET; 176 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR|XL_FLAG_INVERT_MII_PWR; 177 break; 178 case PCI_PRODUCT_3COM_3C9201: 179 case PCI_PRODUCT_3COM_3C920BEMBW: 180 sc->xl_flags |= XL_FLAG_PHYOK; 181 break; 182 case TC_DEVICEID_BOOMERANG_10_100BT: 183 sc->xl_flags |= XL_FLAG_NO_MMIO; 184 break; 185 case PCI_PRODUCT_3COM_3C575: 186 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 187 XL_FLAG_8BITROM; 188 break; 189 case PCI_PRODUCT_3COM_3CCFE575BT: 190 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 191 XL_FLAG_8BITROM | XL_FLAG_INVERT_LED_PWR; 192 sc->xl_flags |= XL_FLAG_FUNCREG; 193 break; 194 case PCI_PRODUCT_3COM_3CCFE575CT: 195 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 196 XL_FLAG_8BITROM | XL_FLAG_INVERT_MII_PWR; 197 sc->xl_flags |= XL_FLAG_FUNCREG; 198 break; 199 case PCI_PRODUCT_3COM_3CCFEM656: 200 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 201 XL_FLAG_8BITROM | XL_FLAG_INVERT_LED_PWR | 202 XL_FLAG_INVERT_MII_PWR; 203 sc->xl_flags |= XL_FLAG_FUNCREG; 204 break; 205 case PCI_PRODUCT_3COM_3CCFEM656B: 206 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 207 XL_FLAG_8BITROM | XL_FLAG_INVERT_LED_PWR | 208 XL_FLAG_INVERT_MII_PWR; 209 sc->xl_flags |= XL_FLAG_FUNCREG; 210 break; 211 case PCI_PRODUCT_3COM_3CCFEM656C: 212 sc->xl_flags = XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 213 XL_FLAG_8BITROM | XL_FLAG_INVERT_MII_PWR; 214 sc->xl_flags |= XL_FLAG_FUNCREG; 215 break; 216 default: 217 break; 218 } 219 220 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 221 222 #ifndef SMALL_KERNEL 223 /* 224 * The card is WOL-capable if it supports PME# assertion 225 * from D3hot power state. Install a callback to configure 226 * PCI power state for WOL. It will be invoked when the 227 * interface stops and WOL was enabled. 228 */ 229 command = pci_conf_read(pc, pa->pa_tag, XL_PCI_CAPID); 230 if ((command >> 16) & XL_PME_CAP_D3_HOT) { 231 sc->wol_power = xl_pci_wol_power; 232 sc->wol_power_arg = psc; 233 } 234 #endif 235 236 /* 237 * Map control/status registers. 238 */ 239 #ifdef XL_USEIOSPACE 240 if (pci_mapreg_map(pa, XL_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 241 &sc->xl_btag, &sc->xl_bhandle, NULL, &iosize, 0)) { 242 printf(": can't map i/o space\n"); 243 return; 244 } 245 #else 246 if (pci_mapreg_map(pa, XL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 247 &sc->xl_btag, &sc->xl_bhandle, NULL, &iosize, 0)) { 248 printf(": can't map i/o space\n"); 249 return; 250 } 251 #endif 252 psc->psc_iosize = iosize; 253 254 if (sc->xl_flags & XL_FLAG_FUNCREG) { 255 if (pci_mapreg_map(pa, XL_PCI_FUNCMEM, PCI_MAPREG_TYPE_MEM, 0, 256 &sc->xl_funct, &sc->xl_funch, NULL, &funsize, 0)) { 257 printf(": can't map i/o space\n"); 258 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, iosize); 259 return; 260 } 261 psc->psc_funsize = funsize; 262 sc->intr_ack = xl_pci_intr_ack; 263 } 264 265 /* 266 * Allocate our interrupt. 267 */ 268 if (pci_intr_map(pa, &ih)) { 269 printf(": couldn't map interrupt\n"); 270 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, iosize); 271 if (sc->xl_flags & XL_FLAG_FUNCREG) 272 bus_space_unmap(sc->xl_funct, sc->xl_funch, funsize); 273 return; 274 } 275 276 intrstr = pci_intr_string(pc, ih); 277 sc->xl_intrhand = pci_intr_establish(pc, ih, IPL_NET, xl_intr, sc, 278 self->dv_xname); 279 if (sc->xl_intrhand == NULL) { 280 printf(": couldn't establish interrupt"); 281 if (intrstr != NULL) 282 printf(" at %s", intrstr); 283 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, iosize); 284 if (sc->xl_flags & XL_FLAG_FUNCREG) 285 bus_space_unmap(sc->xl_funct, sc->xl_funch, funsize); 286 return; 287 } 288 printf(": %s", intrstr); 289 290 xl_attach(sc); 291 } 292 293 int 294 xl_pci_detach(struct device *self, int flags) 295 { 296 struct xl_pci_softc *psc = (void *)self; 297 struct xl_softc *sc = &psc->psc_softc; 298 299 if (sc->xl_intrhand != NULL) { 300 pci_intr_disestablish(psc->psc_pc, sc->xl_intrhand); 301 xl_detach(sc); 302 } 303 if (psc->psc_iosize > 0) 304 bus_space_unmap(sc->xl_btag, sc->xl_bhandle, psc->psc_iosize); 305 if (psc->psc_funsize > 0) 306 bus_space_unmap(sc->xl_funct, sc->xl_funch, psc->psc_funsize); 307 return (0); 308 } 309 310 void 311 xl_pci_intr_ack(struct xl_softc *sc) 312 { 313 bus_space_write_4(sc->xl_funct, sc->xl_funch, XL_PCI_INTR, 314 XL_PCI_INTRACK); 315 } 316 317 #ifndef SMALL_KERNEL 318 void 319 xl_pci_wol_power(void *ppsc) 320 { 321 struct xl_pci_softc *psc = (struct xl_pci_softc*)ppsc; 322 u_int32_t command; 323 324 /* Make sure wake-up generation is enabled. */ 325 command = pci_conf_read(psc->psc_pc, psc->psc_tag, XL_PCI_PWRMGMTCTRL); 326 command |= XL_PME_EN; 327 pci_conf_write(psc->psc_pc, psc->psc_tag, XL_PCI_PWRMGMTCTRL, command); 328 } 329 #endif 330