1 /* $OpenBSD: igc_defines.h,v 1.2 2024/09/06 10:54:08 jsg Exp $ */ 2 3 /*- 4 * Copyright 2021 Intel Corp 5 * Copyright 2021 Rubicon Communications, LLC (Netgate) 6 * SPDX-License-Identifier: BSD-3-Clause 7 * 8 * $FreeBSD$ 9 */ 10 11 #ifndef _IGC_DEFINES_H_ 12 #define _IGC_DEFINES_H_ 13 14 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 15 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 16 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 17 18 /* Definitions for power management and wakeup registers */ 19 /* Wake Up Control */ 20 #define IGC_WUC_APME 0x00000001 /* APM Enable */ 21 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */ 22 #define IGC_WUC_PME_STATUS 0x00000004 /* PME Status */ 23 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 24 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 25 26 /* Wake Up Filter Control */ 27 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 28 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 29 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 30 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 31 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 32 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 33 #define IGC_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 34 35 /* Wake Up Status */ 36 #define IGC_WUS_LNKC IGC_WUFC_LNKC 37 #define IGC_WUS_MAG IGC_WUFC_MAG 38 #define IGC_WUS_EX IGC_WUFC_EX 39 #define IGC_WUS_MC IGC_WUFC_MC 40 #define IGC_WUS_BC IGC_WUFC_BC 41 42 /* Packet types that are enabled for wake packet delivery */ 43 #define WAKE_PKT_WUS ( \ 44 IGC_WUS_EX | \ 45 IGC_WUS_ARPD | \ 46 IGC_WUS_IPV4 | \ 47 IGC_WUS_IPV6 | \ 48 IGC_WUS_NSD) 49 50 /* Wake Up Packet Length */ 51 #define IGC_WUPL_MASK 0x00000FFF 52 53 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */ 54 #define IGC_WUPM_BYTES 128 55 56 #define IGC_WUS_ARPD 0x00000020 /* Directed ARP Request */ 57 #define IGC_WUS_IPV4 0x00000040 /* Directed IPv4 */ 58 #define IGC_WUS_IPV6 0x00000080 /* Directed IPv6 */ 59 #define IGC_WUS_NSD 0x00000400 /* Directed IPv6 Neighbor Solicitation */ 60 61 /* Extended Device Control */ 62 #define IGC_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 63 #define IGC_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ 64 #define IGC_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ 65 #define IGC_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ 66 #define IGC_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 67 #define IGC_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ 68 #define IGC_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 69 #define IGC_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 70 #define IGC_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 71 #define IGC_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ 72 #define IGC_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 73 #define IGC_CTRL_EXT_EIAME 0x01000000 74 #define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 75 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 76 #define IGC_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 77 #define IGC_CTRL_EXT_PHYPDEN 0x00100000 78 #define IGC_IVAR_VALID 0x80 79 #define IGC_GPIE_NSICR 0x00000001 80 #define IGC_GPIE_MSIX_MODE 0x00000010 81 #define IGC_GPIE_EIAME 0x40000000 82 #define IGC_GPIE_PBA 0x80000000 83 84 /* Receive Descriptor bit definitions */ 85 #define IGC_RXD_STAT_DD 0x01 /* Descriptor Done */ 86 #define IGC_RXD_STAT_EOP 0x02 /* End of Packet */ 87 #define IGC_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 88 #define IGC_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 89 #define IGC_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 90 #define IGC_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 91 #define IGC_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 92 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 93 #define IGC_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 94 #define IGC_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 95 #define IGC_RXD_ERR_CE 0x01 /* CRC Error */ 96 #define IGC_RXD_ERR_SE 0x02 /* Symbol Error */ 97 #define IGC_RXD_ERR_SEQ 0x04 /* Sequence Error */ 98 #define IGC_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 99 #define IGC_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 100 #define IGC_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 101 #define IGC_RXD_ERR_RXE 0x80 /* Rx Data Error */ 102 #define IGC_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 103 104 #define IGC_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 105 #define IGC_RXDEXT_STATERR_LB 0x00040000 106 #define IGC_RXDEXT_STATERR_L4E 0x20000000 107 #define IGC_RXDEXT_STATERR_IPE 0x40000000 108 #define IGC_RXDEXT_STATERR_RXE 0x80000000 109 110 /* Same mask, but for extended and packet split descriptors */ 111 #define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \ 112 IGC_RXDEXT_STATERR_CE | \ 113 IGC_RXDEXT_STATERR_SE | \ 114 IGC_RXDEXT_STATERR_SEQ | \ 115 IGC_RXDEXT_STATERR_CXE | \ 116 IGC_RXDEXT_STATERR_RXE) 117 118 #define IGC_MRQC_RSS_FIELD_MASK 0xFFFF0000 119 #define IGC_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 120 #define IGC_MRQC_RSS_FIELD_IPV4 0x00020000 121 #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 122 #define IGC_MRQC_RSS_FIELD_IPV6 0x00100000 123 #define IGC_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 124 125 #define IGC_RXDPS_HDRSTAT_HDRSP 0x00008000 126 127 /* Management Control */ 128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 130 #define IGC_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 131 #define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 132 #define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 133 /* Enable MAC address filtering */ 134 #define IGC_MANC_EN_MAC_ADDR_FILTER 0x00100000 135 /* Enable MNG packets to host memory */ 136 #define IGC_MANC_EN_MNG2HOST 0x00200000 137 138 #define IGC_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 139 #define IGC_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 140 #define IGC_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 141 #define IGC_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 142 143 /* Receive Control */ 144 #define IGC_RCTL_RST 0x00000001 /* Software reset */ 145 #define IGC_RCTL_EN 0x00000002 /* enable */ 146 #define IGC_RCTL_SBP 0x00000004 /* store bad packet */ 147 #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */ 148 #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */ 149 #define IGC_RCTL_LPE 0x00000020 /* long packet enable */ 150 #define IGC_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 151 #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 152 #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 153 #define IGC_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 154 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 155 #define IGC_RCTL_RDMTS_HEX 0x00010000 156 #define IGC_RCTL_RDMTS1_HEX IGC_RCTL_RDMTS_HEX 157 #define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */ 158 #define IGC_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 159 #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */ 160 /* these buffer sizes are valid if IGC_RCTL_BSEX is 0 */ 161 #define IGC_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 162 #define IGC_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 163 #define IGC_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 164 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 165 /* these buffer sizes are valid if IGC_RCTL_BSEX is 1 */ 166 #define IGC_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 167 #define IGC_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 168 #define IGC_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 169 #define IGC_RCTL_VFE 0x00040000 /* vlan filter enable */ 170 #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */ 171 #define IGC_RCTL_CFI 0x00100000 /* canonical form indicator */ 172 #define IGC_RCTL_DPF 0x00400000 /* discard pause frames */ 173 #define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 174 #define IGC_RCTL_BSEX 0x02000000 /* Buffer size extension */ 175 #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 176 177 /* Use byte values for the following shift parameters 178 * Usage: 179 * psrctl |= (((ROUNDUP(value0, 128) >> IGC_PSRCTL_BSIZE0_SHIFT) & 180 * IGC_PSRCTL_BSIZE0_MASK) | 181 * ((ROUNDUP(value1, 1024) >> IGC_PSRCTL_BSIZE1_SHIFT) & 182 * IGC_PSRCTL_BSIZE1_MASK) | 183 * ((ROUNDUP(value2, 1024) << IGC_PSRCTL_BSIZE2_SHIFT) & 184 * IGC_PSRCTL_BSIZE2_MASK) | 185 * ((ROUNDUP(value3, 1024) << IGC_PSRCTL_BSIZE3_SHIFT) |; 186 * IGC_PSRCTL_BSIZE3_MASK)) 187 * where value0 = [128..16256], default=256 188 * value1 = [1024..64512], default=4096 189 * value2 = [0..64512], default=4096 190 * value3 = [0..64512], default=0 191 */ 192 193 #define IGC_PSRCTL_BSIZE0_MASK 0x0000007F 194 #define IGC_PSRCTL_BSIZE1_MASK 0x00003F00 195 #define IGC_PSRCTL_BSIZE2_MASK 0x003F0000 196 #define IGC_PSRCTL_BSIZE3_MASK 0x3F000000 197 198 #define IGC_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 199 #define IGC_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 200 #define IGC_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 201 #define IGC_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 202 203 /* SWFW_SYNC Definitions */ 204 #define IGC_SWFW_EEP_SM 0x01 205 #define IGC_SWFW_PHY0_SM 0x02 206 #define IGC_SWFW_PHY1_SM 0x04 207 #define IGC_SWFW_CSR_SM 0x08 208 #define IGC_SWFW_SW_MNG_SM 0x400 209 210 /* Device Control */ 211 #define IGC_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 212 #define IGC_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 213 #define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ 214 #define IGC_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 216 #define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 218 #define IGC_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 219 #define IGC_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 220 #define IGC_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 221 #define IGC_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 222 #define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */ 223 #define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 224 #define IGC_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 225 #define IGC_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 226 #define IGC_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 227 #define IGC_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 228 #define IGC_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 229 #define IGC_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 230 #define IGC_CTRL_DEV_RST 0x20000000 /* Device reset */ 231 #define IGC_CTRL_RST 0x04000000 /* Global reset */ 232 #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 233 #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 234 #define IGC_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 235 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 236 237 238 #define IGC_CONNSW_AUTOSENSE_EN 0x01 239 #define IGC_PCS_LCTL_FORCE_FCTRL 0x80 240 241 #define IGC_PCS_LSTS_AN_COMPLETE 0x10000 242 243 /* Device Status */ 244 #define IGC_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ 245 #define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 246 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 247 #define IGC_STATUS_FUNC_SHIFT 2 248 #define IGC_STATUS_FUNC_1 0x00000004 /* Function 1 */ 249 #define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */ 250 #define IGC_STATUS_SPEED_MASK 0x000000C0 251 #define IGC_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 252 #define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 253 #define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 254 #define IGC_STATUS_SPEED_2500 0x00400000 /* Speed 2.5Gb/s */ 255 #define IGC_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ 256 #define IGC_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 257 #define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ 258 #define IGC_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 259 #define IGC_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 260 #define IGC_STATUS_PCIM_STATE 0x40000000 /* PCIm function state */ 261 262 #define SPEED_10 10 263 #define SPEED_100 100 264 #define SPEED_1000 1000 265 #define SPEED_2500 2500 266 #define HALF_DUPLEX 1 267 #define FULL_DUPLEX 2 268 269 #define ADVERTISE_10_HALF 0x0001 270 #define ADVERTISE_10_FULL 0x0002 271 #define ADVERTISE_100_HALF 0x0004 272 #define ADVERTISE_100_FULL 0x0008 273 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 274 #define ADVERTISE_1000_FULL 0x0020 275 #define ADVERTISE_2500_HALF 0x0040 /* NOT used, just FYI */ 276 #define ADVERTISE_2500_FULL 0x0080 277 278 /* 1000/H is not supported, nor spec-compliant. */ 279 #define IGC_ALL_SPEED_DUPLEX ( \ 280 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 281 ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 282 #define IGC_ALL_SPEED_DUPLEX_2500 ( \ 283 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 284 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 285 #define IGC_ALL_NOT_GIG ( \ 286 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 287 ADVERTISE_100_FULL) 288 #define IGC_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 289 #define IGC_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 290 #define IGC_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 291 292 #define AUTONEG_ADVERTISE_SPEED_DEFAULT IGC_ALL_SPEED_DUPLEX 293 #define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 IGC_ALL_SPEED_DUPLEX_2500 294 295 /* LED Control */ 296 #define IGC_LEDCTL_LED0_MODE_MASK 0x0000000F 297 #define IGC_LEDCTL_LED0_MODE_SHIFT 0 298 #define IGC_LEDCTL_LED0_IVRT 0x00000040 299 #define IGC_LEDCTL_LED0_BLINK 0x00000080 300 301 #define IGC_LEDCTL_MODE_LED_ON 0x0E 302 #define IGC_LEDCTL_MODE_LED_OFF 0x0F 303 304 /* Transmit Descriptor bit definitions */ 305 #define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 306 #define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 307 #define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 308 #define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 309 #define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */ 310 #define IGC_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 311 #define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 312 #define IGC_TXD_CMD_RS 0x08000000 /* Report Status */ 313 #define IGC_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 314 #define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 315 #define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 316 #define IGC_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 317 #define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 318 #define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */ 319 #define IGC_TXD_CMD_IP 0x02000000 /* IP packet */ 320 #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 321 #define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 322 323 /* Transmit Control */ 324 #define IGC_TCTL_EN 0x00000002 /* enable Tx */ 325 #define IGC_TCTL_PSP 0x00000008 /* pad short packets */ 326 #define IGC_TCTL_CT 0x00000ff0 /* collision threshold */ 327 #define IGC_TCTL_COLD 0x003ff000 /* collision distance */ 328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 329 #define IGC_TCTL_MULR 0x10000000 /* Multiple request support */ 330 331 /* Transmit Arbitration Count */ 332 #define IGC_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 333 334 /* SerDes Control */ 335 #define IGC_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 336 #define IGC_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 337 338 /* Receive Checksum Control */ 339 #define IGC_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 340 #define IGC_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 341 #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 342 #define IGC_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 343 #define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 344 345 /* GPY211 - I225 defines */ 346 #define GPY_MMD_MASK 0xFFFF0000 347 #define GPY_MMD_SHIFT 16 348 #define GPY_REG_MASK 0x0000FFFF 349 /* Header split receive */ 350 #define IGC_RFCTL_NFSW_DIS 0x00000040 351 #define IGC_RFCTL_NFSR_DIS 0x00000080 352 #define IGC_RFCTL_ACK_DIS 0x00001000 353 #define IGC_RFCTL_EXTEN 0x00008000 354 #define IGC_RFCTL_IPV6_EX_DIS 0x00010000 355 #define IGC_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 356 #define IGC_RFCTL_LEF 0x00040000 357 358 /* Collision related configuration parameters */ 359 #define IGC_CT_SHIFT 4 360 #define IGC_COLLISION_THRESHOLD 15 361 #define IGC_COLLISION_DISTANCE 63 362 #define IGC_COLD_SHIFT 12 363 364 /* Default values for the transmit IPG register */ 365 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 366 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 367 368 #define IGC_TIPG_IPGT_MASK 0x000003FF 369 370 #define DEFAULT_82543_TIPG_IPGR1 8 371 #define IGC_TIPG_IPGR1_SHIFT 10 372 373 #define DEFAULT_82543_TIPG_IPGR2 6 374 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 375 #define IGC_TIPG_IPGR2_SHIFT 20 376 377 /* Ethertype field values */ 378 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 379 380 #define ETHERNET_FCS_SIZE 4 381 #define MAX_JUMBO_FRAME_SIZE 9216 382 #define IGC_TX_PTR_GAP 0x1F 383 384 /* Extended Configuration Control and Size */ 385 #define IGC_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 386 #define IGC_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 387 #define IGC_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 388 #define IGC_EXTCNF_CTRL_SWFLAG 0x00000020 389 #define IGC_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 390 #define IGC_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 391 #define IGC_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 392 #define IGC_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 393 #define IGC_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 394 395 #define IGC_PHY_CTRL_D0A_LPLU 0x00000002 396 #define IGC_PHY_CTRL_NOND0A_LPLU 0x00000004 397 #define IGC_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 398 #define IGC_PHY_CTRL_GBE_DISABLE 0x00000040 399 400 #define IGC_KABGTXD_BGSQLBIAS 0x00050000 401 402 /* PBA constants */ 403 #define IGC_PBA_8K 0x0008 /* 8KB */ 404 #define IGC_PBA_10K 0x000A /* 10KB */ 405 #define IGC_PBA_12K 0x000C /* 12KB */ 406 #define IGC_PBA_14K 0x000E /* 14KB */ 407 #define IGC_PBA_16K 0x0010 /* 16KB */ 408 #define IGC_PBA_18K 0x0012 409 #define IGC_PBA_20K 0x0014 410 #define IGC_PBA_22K 0x0016 411 #define IGC_PBA_24K 0x0018 412 #define IGC_PBA_26K 0x001A 413 #define IGC_PBA_30K 0x001E 414 #define IGC_PBA_32K 0x0020 415 #define IGC_PBA_34K 0x0022 416 #define IGC_PBA_35K 0x0023 417 #define IGC_PBA_38K 0x0026 418 #define IGC_PBA_40K 0x0028 419 #define IGC_PBA_48K 0x0030 /* 48KB */ 420 #define IGC_PBA_64K 0x0040 /* 64KB */ 421 422 #define IGC_PBA_RXA_MASK 0xFFFF 423 424 #define IGC_PBS_16K IGC_PBA_16K 425 426 /* Uncorrectable/correctable ECC Error counts and enable bits */ 427 #define IGC_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 428 #define IGC_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 429 #define IGC_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 430 #define IGC_PBECCSTS_ECC_ENABLE 0x00010000 431 432 #define IFS_MAX 80 433 #define IFS_MIN 40 434 #define IFS_RATIO 4 435 #define IFS_STEP 10 436 #define MIN_NUM_XMITS 1000 437 438 /* SW Semaphore Register */ 439 #define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 440 #define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 441 #define IGC_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 442 443 #define IGC_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 444 445 /* Interrupt Cause Read */ 446 #define IGC_ICR_TXDW 0x00000001 /* Transmit desc written back */ 447 #define IGC_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 448 #define IGC_ICR_LSC 0x00000004 /* Link Status Change */ 449 #define IGC_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 450 #define IGC_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 451 #define IGC_ICR_RXO 0x00000040 /* Rx overrun */ 452 #define IGC_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 453 #define IGC_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 454 #define IGC_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 455 #define IGC_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 456 #define IGC_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 457 #define IGC_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 458 #define IGC_ICR_TXD_LOW 0x00008000 459 #define IGC_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 460 #define IGC_ICR_TS 0x00080000 /* Time Sync Interrupt */ 461 #define IGC_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 462 /* If this bit asserted, the driver should claim the interrupt */ 463 #define IGC_ICR_INT_ASSERTED 0x80000000 464 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 465 #define IGC_ICR_FER 0x00400000 /* Fatal Error */ 466 467 468 469 /* Extended Interrupt Cause Read */ 470 #define IGC_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 471 #define IGC_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 472 #define IGC_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 473 #define IGC_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 474 #define IGC_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 475 #define IGC_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 476 #define IGC_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 477 #define IGC_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 478 #define IGC_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 479 #define IGC_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 480 /* TCP Timer */ 481 #define IGC_TCPTIMER_KS 0x00000100 /* KickStart */ 482 #define IGC_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 483 #define IGC_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 484 #define IGC_TCPTIMER_LOOP 0x00000800 /* Loop */ 485 486 /* This defines the bits that are set in the Interrupt Mask 487 * Set/Read Register. Each bit is documented below: 488 * o RXT0 = Receiver Timer Interrupt (ring 0) 489 * o TXDW = Transmit Descriptor Written Back 490 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 491 * o RXSEQ = Receive Sequence Error 492 * o LSC = Link Status Change 493 */ 494 #define IMS_ENABLE_MASK ( \ 495 IGC_IMS_RXT0 | \ 496 IGC_IMS_TXDW | \ 497 IGC_IMS_RXDMT0 | \ 498 IGC_IMS_RXSEQ | \ 499 IGC_IMS_LSC) 500 501 /* Interrupt Mask Set */ 502 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */ 503 #define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */ 504 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */ 505 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */ 506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */ 507 #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */ 508 #define IGC_IMS_RXO IGC_ICR_RXO /* Rx overrun */ 509 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */ 510 #define IGC_IMS_TXD_LOW IGC_ICR_TXD_LOW 511 #define IGC_IMS_ECCER IGC_ICR_ECCER /* Uncorrectable ECC Error */ 512 #define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */ 513 #define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */ 514 #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */ 515 #define IGC_IMS_FER IGC_ICR_FER /* Fatal Error */ 516 517 #define IGC_IMS_THS IGC_ICR_THS /* ICR.TS: Thermal Sensor Event*/ 518 #define IGC_IMS_MDDET IGC_ICR_MDDET /* Malicious Driver Detect */ 519 /* Extended Interrupt Mask Set */ 520 #define IGC_EIMS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 521 #define IGC_EIMS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 522 #define IGC_EIMS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 523 #define IGC_EIMS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 524 #define IGC_EIMS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 525 #define IGC_EIMS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 526 #define IGC_EIMS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 527 #define IGC_EIMS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 528 #define IGC_EIMS_TCP_TIMER IGC_EICR_TCP_TIMER /* TCP Timer */ 529 #define IGC_EIMS_OTHER IGC_EICR_OTHER /* Interrupt Cause Active */ 530 531 /* Interrupt Cause Set */ 532 #define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */ 533 #define IGC_ICS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */ 534 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */ 535 536 /* Extended Interrupt Cause Set */ 537 #define IGC_EICS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 538 #define IGC_EICS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 539 #define IGC_EICS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 540 #define IGC_EICS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 541 #define IGC_EICS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 542 #define IGC_EICS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 543 #define IGC_EICS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 544 #define IGC_EICS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 545 #define IGC_EICS_TCP_TIMER IGC_EICR_TCP_TIMER /* TCP Timer */ 546 #define IGC_EICS_OTHER IGC_EICR_OTHER /* Interrupt Cause Active */ 547 548 #define IGC_EITR_ITR_INT_MASK 0x0000FFFF 549 #define IGC_EITR_INTERVAL 0x00007FFC 550 /* IGC_EITR_CNT_IGNR is only for 82576 and newer */ 551 #define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 552 553 /* Transmit Descriptor Control */ 554 #define IGC_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 555 #define IGC_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 556 #define IGC_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 557 #define IGC_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 558 #define IGC_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 559 #define IGC_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 560 /* Enable the counting of descriptors still to be processed. */ 561 #define IGC_TXDCTL_COUNT_DESC 0x00400000 562 563 /* Flow Control Constants */ 564 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 565 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 566 #define FLOW_CONTROL_TYPE 0x8808 567 568 /* 802.1q VLAN Packet Size */ 569 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 570 #define IGC_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 571 572 /* Receive Address 573 * Number of high/low register pairs in the RAR. The RAR (Receive Address 574 * Registers) holds the directed and multicast addresses that we monitor. 575 * Technically, we have 16 spots. However, we reserve one of these spots 576 * (RAR[15]) for our directed address used by controllers with 577 * manageability enabled, allowing us room for 15 multicast addresses. 578 */ 579 #define IGC_RAR_ENTRIES 15 580 #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */ 581 #define IGC_RAL_MAC_ADDR_LEN 4 582 #define IGC_RAH_MAC_ADDR_LEN 2 583 584 /* Error Codes */ 585 #define IGC_SUCCESS 0 586 #define IGC_ERR_NVM 1 587 #define IGC_ERR_PHY 2 588 #define IGC_ERR_CONFIG 3 589 #define IGC_ERR_PARAM 4 590 #define IGC_ERR_MAC_INIT 5 591 #define IGC_ERR_PHY_TYPE 6 592 #define IGC_ERR_RESET 9 593 #define IGC_ERR_MASTER_REQUESTS_PENDING 10 594 #define IGC_ERR_HOST_INTERFACE_COMMAND 11 595 #define IGC_BLK_PHY_RESET 12 596 #define IGC_ERR_SWFW_SYNC 13 597 #define IGC_NOT_IMPLEMENTED 14 598 #define IGC_ERR_MBX 15 599 #define IGC_ERR_INVALID_ARGUMENT 16 600 #define IGC_ERR_NO_SPACE 17 601 #define IGC_ERR_NVM_PBA_SECTION 18 602 #define IGC_ERR_INVM_VALUE_NOT_FOUND 20 603 604 /* Loop limit on how long we wait for auto-negotiation to complete */ 605 #define COPPER_LINK_UP_LIMIT 10 606 #define PHY_AUTO_NEG_LIMIT 45 607 /* Number of 100 microseconds we wait for PCI Express master disable */ 608 #define MASTER_DISABLE_TIMEOUT 800 609 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 610 #define PHY_CFG_TIMEOUT 100 611 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 612 #define MDIO_OWNERSHIP_TIMEOUT 10 613 /* Number of milliseconds for NVM auto read done after MAC reset. */ 614 #define AUTO_READ_DONE_TIMEOUT 10 615 616 /* Flow Control */ 617 #define IGC_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 618 #define IGC_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 619 #define IGC_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 620 621 /* Transmit Configuration Word */ 622 #define IGC_TXCW_FD 0x00000020 /* TXCW full duplex */ 623 #define IGC_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 624 #define IGC_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 625 #define IGC_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */ 627 628 /* Receive Configuration Word */ 629 #define IGC_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 630 #define IGC_RXCW_IV 0x08000000 /* Receive config invalid */ 631 #define IGC_RXCW_C 0x20000000 /* Receive config */ 632 #define IGC_RXCW_SYNCH 0x40000000 /* Receive config synch */ 633 634 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */ 635 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 636 637 #define IGC_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 638 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 639 #define IGC_TSYNCRXCTL_TYPE_L2_V2 0x00 640 #define IGC_TSYNCRXCTL_TYPE_L4_V1 0x02 641 #define IGC_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 642 #define IGC_TSYNCRXCTL_TYPE_ALL 0x08 643 #define IGC_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 644 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 645 #define IGC_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 646 647 #define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 648 #define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 649 #define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 650 #define IGC_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 651 #define IGC_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 652 #define IGC_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 653 654 #define IGC_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 655 #define IGC_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 656 #define IGC_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 657 #define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 658 #define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 659 #define IGC_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 660 #define IGC_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 661 #define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 662 #define IGC_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 663 #define IGC_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 664 #define IGC_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 665 666 #define IGC_TIMINCA_16NS_SHIFT 24 667 #define IGC_TIMINCA_INCPERIOD_SHIFT 24 668 #define IGC_TIMINCA_INCVALUE_MASK 0x00FFFFFF 669 670 /* Time Sync Interrupt Cause/Mask Register Bits */ 671 #define TSINTR_SYS_WRAP (1 << 0) /* SYSTIM Wrap around. */ 672 #define TSINTR_TXTS (1 << 1) /* Transmit Timestamp. */ 673 #define TSINTR_TT0 (1 << 3) /* Target Time 0 Trigger. */ 674 #define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */ 675 #define TSINTR_AUTT0 (1 << 5) /* Auxiliary Timestamp 0 Taken. */ 676 #define TSINTR_AUTT1 (1 << 6) /* Auxiliary Timestamp 1 Taken. */ 677 678 #define TSYNC_INTERRUPTS TSINTR_TXTS 679 680 /* TSAUXC Configuration Bits */ 681 #define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */ 682 #define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */ 683 #define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */ 684 #define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */ 685 #define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */ 686 #define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */ 687 #define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */ 688 #define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */ 689 690 /* SDP Configuration Bits */ 691 #define AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */ 692 #define AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */ 693 #define AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */ 694 #define AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */ 695 #define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */ 696 #define AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */ 697 #define AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */ 698 #define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */ 699 #define AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */ 700 #define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */ 701 #define TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */ 702 #define TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */ 703 #define TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */ 704 #define TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */ 705 #define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */ 706 #define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */ 707 #define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */ 708 #define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */ 709 #define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */ 710 #define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */ 711 #define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */ 712 #define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */ 713 #define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */ 714 #define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */ 715 #define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */ 716 #define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */ 717 #define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */ 718 #define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */ 719 #define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */ 720 #define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */ 721 722 #define IGC_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */ 723 #define IGC_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */ 724 725 /* Extended Device Control */ 726 #define IGC_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */ 727 728 /* ETQF register bit definitions */ 729 #define IGC_ETQF_1588 (1 << 30) 730 #define IGC_FTQF_VF_BP 0x00008000 731 #define IGC_FTQF_1588_TIME_STAMP 0x08000000 732 #define IGC_FTQF_MASK 0xF0000000 733 #define IGC_FTQF_MASK_PROTO_BP 0x10000000 734 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 735 #define IGC_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 736 #define IGC_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 737 738 #define IGC_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 739 #define IGC_TSICR_TXTS 0x00000002 740 #define IGC_TSIM_TXTS 0x00000002 741 /* TUPLE Filtering Configuration */ 742 #define IGC_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ 743 #define IGC_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ 744 #define IGC_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ 745 /* TTQF TCP Bit, shift with IGC_TTQF_PROTOCOL SHIFT */ 746 #define IGC_TTQF_PROTOCOL_TCP 0x0 747 /* TTQF UDP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */ 748 #define IGC_TTQF_PROTOCOL_UDP 0x1 749 /* TTQF SCTP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */ 750 #define IGC_TTQF_PROTOCOL_SCTP 0x2 751 #define IGC_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ 752 #define IGC_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shift */ 753 #define IGC_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ 754 #define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ 755 #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 756 #define IGC_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 757 #define IGC_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 758 #define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 759 760 #define IGC_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 761 #define IGC_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 762 #define IGC_MDICNFG_PHY_MASK 0x03E00000 763 #define IGC_MDICNFG_PHY_SHIFT 21 764 765 #define IGC_MEDIA_PORT_COPPER 1 766 #define IGC_MEDIA_PORT_OTHER 2 767 #define IGC_M88E1112_AUTO_COPPER_SGMII 0x2 768 #define IGC_M88E1112_AUTO_COPPER_BASEX 0x3 769 #define IGC_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ 770 #define IGC_M88E1112_MAC_CTRL_1 0x10 771 #define IGC_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ 772 #define IGC_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 773 #define IGC_M88E1112_PAGE_ADDR 0x16 774 #define IGC_M88E1112_STATUS 0x01 775 776 #define IGC_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */ 777 #define IGC_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */ 778 #define IGC_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */ 779 #define IGC_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 780 #define IGC_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ 781 782 /* EEE defines */ 783 #define IGC_IPCNFG_EEE_2_5G_AN 0x00000010 /* IPCNFG EEE Ena 2.5G AN */ 784 #define IGC_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 785 #define IGC_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 786 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 787 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 788 #define IGC_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 789 /* EEE status */ 790 #define IGC_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 791 #define IGC_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 792 #define IGC_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 793 #define IGC_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 794 #define IGC_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 795 #define IGC_M88E1543_EEE_CTRL_1 0x0 796 #define IGC_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 797 #define IGC_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */ 798 #define IGC_EEE_ADV_DEV_I354 7 799 #define IGC_EEE_ADV_ADDR_I354 60 800 #define IGC_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 801 #define IGC_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 802 #define IGC_PCS_STATUS_DEV_I354 3 803 #define IGC_PCS_STATUS_ADDR_I354 1 804 #define IGC_PCS_STATUS_RX_LPI_RCVD 0x0400 805 #define IGC_PCS_STATUS_TX_LPI_RCVD 0x0800 806 #define IGC_M88E1512_CFG_REG_1 0x0010 807 #define IGC_M88E1512_CFG_REG_2 0x0011 808 #define IGC_M88E1512_CFG_REG_3 0x0007 809 #define IGC_M88E1512_MODE 0x0014 810 #define IGC_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ 811 #define IGC_EEE_LP_ADV_DEV_I225 7 /* EEE LP Adv Device */ 812 #define IGC_EEE_LP_ADV_ADDR_I225 61 /* EEE LP Adv Register */ 813 814 #define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 815 816 /* PHY Control Register */ 817 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 818 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 819 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 820 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 821 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 822 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 823 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 824 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 825 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 826 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 827 #define MII_CR_SPEED_1000 0x0040 828 #define MII_CR_SPEED_100 0x2000 829 #define MII_CR_SPEED_10 0x0000 830 831 /* PHY Status Register */ 832 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 833 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 834 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 835 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 836 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 837 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 838 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 839 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 840 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 841 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 842 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 843 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 844 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 845 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 846 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 847 848 /* Autoneg Advertisement Register */ 849 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 850 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 851 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 852 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 853 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 854 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 855 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 856 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 857 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 858 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 859 860 /* Link Partner Ability Register (Base Page) */ 861 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 862 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */ 863 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */ 864 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */ 865 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 866 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 867 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 868 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */ 869 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */ 870 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */ 871 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 872 873 /* Autoneg Expansion Register */ 874 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 875 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */ 876 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */ 877 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */ 878 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */ 879 880 /* 1000BASE-T Control Register */ 881 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 882 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 883 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 884 /* 1=Repeater/switch device port 0=DTE device */ 885 #define CR_1000T_REPEATER_DTE 0x0400 886 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 887 #define CR_1000T_MS_VALUE 0x0800 888 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 889 #define CR_1000T_MS_ENABLE 0x1000 890 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 891 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 892 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 893 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 894 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 895 896 /* 1000BASE-T Status Register */ 897 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */ 898 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */ 899 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 900 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 901 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 902 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 903 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */ 904 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 905 906 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 907 908 /* PHY 1000 MII Register/Bit Definitions */ 909 /* PHY Registers defined by IEEE */ 910 #define PHY_CONTROL 0x00 /* Control Register */ 911 #define PHY_STATUS 0x01 /* Status Register */ 912 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 913 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 914 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 915 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 916 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 917 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ 918 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 921 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 922 923 /* PHY GPY 211 registers */ 924 #define STANDARD_AN_REG_MASK 0x0007 /* MMD */ 925 #define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */ 926 #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */ 927 #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */ 928 929 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 930 931 /* NVM Control */ 932 #define IGC_EECD_SK 0x00000001 /* NVM Clock */ 933 #define IGC_EECD_CS 0x00000002 /* NVM Chip Select */ 934 #define IGC_EECD_DI 0x00000004 /* NVM Data In */ 935 #define IGC_EECD_DO 0x00000008 /* NVM Data Out */ 936 #define IGC_EECD_REQ 0x00000040 /* NVM Access Request */ 937 #define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */ 938 #define IGC_EECD_PRES 0x00000100 /* NVM Present */ 939 #define IGC_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 940 /* NVM Addressing bits based on type 0=small, 1=large */ 941 #define IGC_EECD_ADDR_BITS 0x00000400 942 #define IGC_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 943 #define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 944 #define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 945 #define IGC_EECD_SIZE_EX_SHIFT 11 946 #define IGC_EECD_FLUPD 0x00080000 /* Update FLASH */ 947 #define IGC_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 948 #define IGC_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 949 #define IGC_EECD_SEC1VAL_VALID_MASK (IGC_EECD_AUTO_RD | IGC_EECD_PRES) 950 951 #define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */ 952 #define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done */ 953 #define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */ 954 #define IGC_FLUDONE_ATTEMPTS 20000 955 #define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 956 #define IGC_EECD_SEC1VAL_I225 0x02000000 /* Sector One Valid */ 957 #define IGC_FLSECU_BLK_SW_ACCESS_I225 0x00000004 /* Block SW access */ 958 #define IGC_FWSM_FW_VALID_I225 0x8000 /* FW valid bit */ 959 960 #define IGC_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 961 #define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 962 #define IGC_NVM_RW_REG_START 1 /* Start operation */ 963 #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 964 #define IGC_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 965 #define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */ 966 #define IGC_FLASH_UPDATES 2000 967 968 /* NVM Word Offsets */ 969 #define NVM_COMPAT 0x0003 970 #define NVM_ID_LED_SETTINGS 0x0004 971 #define NVM_FUTURE_INIT_WORD1 0x0019 972 #define NVM_COMPAT_VALID_CSUM 0x0001 973 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 974 975 #define NVM_INIT_CONTROL2_REG 0x000F 976 #define NVM_INIT_CONTROL3_PORT_B 0x0014 977 #define NVM_INIT_3GIO_3 0x001A 978 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 979 #define NVM_INIT_CONTROL3_PORT_A 0x0024 980 #define NVM_CFG 0x0012 981 #define NVM_ALT_MAC_ADDR_PTR 0x0037 982 #define NVM_CHECKSUM_REG 0x003F 983 984 #define IGC_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 985 #define IGC_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 986 987 /* Mask bits for fields in Word 0x0f of the NVM */ 988 #define NVM_WORD0F_PAUSE_MASK 0x3000 989 #define NVM_WORD0F_PAUSE 0x1000 990 #define NVM_WORD0F_ASM_DIR 0x2000 991 992 /* Mask bits for fields in Word 0x1a of the NVM */ 993 #define NVM_WORD1A_ASPM_MASK 0x000C 994 995 /* Mask bits for fields in Word 0x03 of the EEPROM */ 996 #define NVM_COMPAT_LOM 0x0800 997 998 /* length of string needed to store PBA number */ 999 #define IGC_PBANUM_LENGTH 11 1000 1001 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 1002 #define NVM_SUM 0xBABA 1003 1004 /* PBA (printed board assembly) number words */ 1005 #define NVM_PBA_OFFSET_0 8 1006 #define NVM_PBA_OFFSET_1 9 1007 #define NVM_PBA_PTR_GUARD 0xFAFA 1008 #define NVM_WORD_SIZE_BASE_SHIFT 6 1009 1010 /* NVM Commands - Microwire */ 1011 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 1012 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 1013 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 1014 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 1015 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ 1016 1017 /* NVM Commands - SPI */ 1018 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1019 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 1020 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 1021 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1022 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 1023 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 1024 1025 /* SPI NVM Status Register */ 1026 #define NVM_STATUS_RDY_SPI 0x01 1027 1028 /* Word definitions for ID LED Settings */ 1029 #define ID_LED_RESERVED_0000 0x0000 1030 #define ID_LED_RESERVED_FFFF 0xFFFF 1031 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1032 (ID_LED_OFF1_OFF2 << 8) | \ 1033 (ID_LED_DEF1_DEF2 << 4) | \ 1034 (ID_LED_DEF1_DEF2)) 1035 #define ID_LED_DEF1_DEF2 0x1 1036 #define ID_LED_DEF1_ON2 0x2 1037 #define ID_LED_DEF1_OFF2 0x3 1038 #define ID_LED_ON1_DEF2 0x4 1039 #define ID_LED_ON1_ON2 0x5 1040 #define ID_LED_ON1_OFF2 0x6 1041 #define ID_LED_OFF1_DEF2 0x7 1042 #define ID_LED_OFF1_ON2 0x8 1043 #define ID_LED_OFF1_OFF2 0x9 1044 1045 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1046 #define IGP_ACTIVITY_LED_ENABLE 0x0300 1047 #define IGP_LED3_MODE 0x07000000 1048 1049 /* PCI/PCI-X/PCI-EX Config space */ 1050 #define PCIX_COMMAND_REGISTER 0xE6 1051 #define PCIX_STATUS_REGISTER_LO 0xE8 1052 #define PCIX_STATUS_REGISTER_HI 0xEA 1053 #define PCI_HEADER_TYPE_REGISTER 0x0E 1054 #define PCIE_LINK_STATUS 0x12 1055 1056 #define PCIX_COMMAND_MMRBC_MASK 0x000C 1057 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1058 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1059 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1060 #define PCIX_STATUS_HI_MMRBC_4K 0x3 1061 #define PCIX_STATUS_HI_MMRBC_2K 0x2 1062 #define PCIX_STATUS_LO_FUNC_MASK 0x7 1063 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 1064 #define PCIE_LINK_WIDTH_MASK 0x3F0 1065 #define PCIE_LINK_WIDTH_SHIFT 4 1066 #define PCIE_LINK_SPEED_MASK 0x0F 1067 #define PCIE_LINK_SPEED_2500 0x01 1068 #define PCIE_LINK_SPEED_5000 0x02 1069 1070 #define PHY_REVISION_MASK 0xFFFFFFF0 1071 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1072 #define MAX_PHY_MULTI_PAGE_REG 0xF 1073 1074 /* Bit definitions for valid PHY IDs. 1075 * I = Integrated 1076 * E = External 1077 */ 1078 #define M88IGC_E_PHY_ID 0x01410C50 1079 #define M88IGC_I_PHY_ID 0x01410C30 1080 #define M88E1011_I_PHY_ID 0x01410C20 1081 #define IGP01IGC_I_PHY_ID 0x02A80380 1082 #define M88E1111_I_PHY_ID 0x01410CC0 1083 #define GG82563_E_PHY_ID 0x01410CA0 1084 #define IGP03IGC_E_PHY_ID 0x02A80390 1085 #define IFE_E_PHY_ID 0x02A80330 1086 #define IFE_PLUS_E_PHY_ID 0x02A80320 1087 #define IFE_C_E_PHY_ID 0x02A80310 1088 #define I225_I_PHY_ID 0x67C9DC00 1089 1090 /* M88IGC Specific Registers */ 1091 #define M88IGC_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ 1092 #define M88IGC_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ 1093 #define M88IGC_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ 1094 #define M88IGC_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1095 1096 #define M88IGC_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */ 1097 #define M88IGC_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ 1098 1099 /* M88IGC PHY Specific Control Register */ 1100 #define M88IGC_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ 1101 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ 1102 #define M88IGC_PSCR_MDI_MANUAL_MODE 0x0000 1103 #define M88IGC_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1104 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 1105 #define M88IGC_PSCR_AUTO_X_1000T 0x0040 1106 /* Auto crossover enabled all speeds */ 1107 #define M88IGC_PSCR_AUTO_X_MODE 0x0060 1108 #define M88IGC_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ 1109 1110 /* M88IGC PHY Specific Status Register */ 1111 #define M88IGC_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1112 #define M88IGC_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1113 #define M88IGC_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1114 /* 0 = <50M 1115 * 1 = 50-80M 1116 * 2 = 80-110M 1117 * 3 = 110-140M 1118 * 4 = >140M 1119 */ 1120 #define M88IGC_PSSR_CABLE_LENGTH 0x0380 1121 #define M88IGC_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1122 #define M88IGC_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1123 #define M88IGC_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1124 #define M88IGC_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1125 1126 #define M88IGC_PSSR_CABLE_LENGTH_SHIFT 7 1127 1128 /* Number of times we will attempt to autonegotiate before downshifting if we 1129 * are the master 1130 */ 1131 #define M88IGC_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1132 #define M88IGC_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1133 /* Number of times we will attempt to autonegotiate before downshifting if we 1134 * are the slave 1135 */ 1136 #define M88IGC_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1137 #define M88IGC_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1138 #define M88IGC_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1139 1140 1141 /* M88EC018 Rev 2 specific DownShift settings */ 1142 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1143 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1144 1145 /* Bits... 1146 * 15-5: page 1147 * 4-0: register offset 1148 */ 1149 #define GG82563_PAGE_SHIFT 5 1150 #define GG82563_REG(page, reg) \ 1151 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1152 #define GG82563_MIN_ALT_REG 30 1153 1154 /* GG82563 Specific Registers */ 1155 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ 1156 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ 1157 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ 1158 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ 1159 1160 /* MAC Specific Control Register */ 1161 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) 1162 1163 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ 1164 1165 /* Page 193 - Port Control Registers */ 1166 /* Kumeran Mode Control */ 1167 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) 1168 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ 1169 1170 /* Page 194 - KMRN Registers */ 1171 #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ 1172 1173 /* MDI Control */ 1174 #define IGC_MDIC_DATA_MASK 0x0000FFFF 1175 #define IGC_MDIC_INT_EN 0x20000000 1176 #define IGC_MDIC_REG_MASK 0x001F0000 1177 #define IGC_MDIC_REG_SHIFT 16 1178 #define IGC_MDIC_PHY_SHIFT 21 1179 #define IGC_MDIC_OP_WRITE 0x04000000 1180 #define IGC_MDIC_OP_READ 0x08000000 1181 #define IGC_MDIC_READY 0x10000000 1182 #define IGC_MDIC_ERROR 0x40000000 1183 1184 #define IGC_N0_QUEUE -1 1185 1186 #define IGC_MAX_MAC_HDR_LEN 127 1187 #define IGC_MAX_NETWORK_HDR_LEN 511 1188 1189 #define IGC_VLANPQF_QUEUE_SEL(_n, q_idx) ((q_idx) << ((_n) * 4)) 1190 #define IGC_VLANPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4)) 1191 #define IGC_VLANPQF_QUEUE_MASK 0x03 1192 #define IGC_VFTA_BLOCK_SIZE 8 1193 /* SerDes Control */ 1194 #define IGC_GEN_POLL_TIMEOUT 640 1195 1196 /* DMA Coalescing register fields */ 1197 /* DMA Coalescing Watchdog Timer */ 1198 #define IGC_DMACR_DMACWT_MASK 0x00003FFF 1199 /* DMA Coalescing Rx Threshold */ 1200 #define IGC_DMACR_DMACTHR_MASK 0x00FF0000 1201 #define IGC_DMACR_DMACTHR_SHIFT 16 1202 /* Lx when no PCIe transactions */ 1203 #define IGC_DMACR_DMAC_LX_MASK 0x30000000 1204 #define IGC_DMACR_DMAC_LX_SHIFT 28 1205 #define IGC_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 1206 /* DMA Coalescing BMC-to-OS Watchdog Enable */ 1207 #define IGC_DMACR_DC_BMC2OSW_EN 0x00008000 1208 1209 /* DMA Coalescing Transmit Threshold */ 1210 #define IGC_DMCTXTH_DMCTTHR_MASK 0x00000FFF 1211 1212 #define IGC_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1213 1214 /* Rx Traffic Rate Threshold */ 1215 #define IGC_DMCRTRH_UTRESH_MASK 0x0007FFFF 1216 /* Rx packet rate in current window */ 1217 #define IGC_DMCRTRH_LRPRCW 0x80000000 1218 1219 /* DMA Coal Rx Traffic Current Count */ 1220 #define IGC_DMCCNT_CCOUNT_MASK 0x01FFFFFF 1221 1222 /* Flow ctrl Rx Threshold High val */ 1223 #define IGC_FCRTC_RTH_COAL_MASK 0x0003FFF0 1224 #define IGC_FCRTC_RTH_COAL_SHIFT 4 1225 /* Lx power decision based on DMA coal */ 1226 #define IGC_PCIEMISC_LX_DECISION 0x00000080 1227 1228 #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ 1229 #define IGC_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ 1230 #define IGC_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ 1231 #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 1232 #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 1233 1234 #define IGC_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */ 1235 /* Minimum time for 1000BASE-T where no data will be transmit following move out 1236 * of EEE LPI Tx state 1237 */ 1238 #define IGC_TW_SYSTEM_1000_MASK 0x000000FF 1239 /* Minimum time for 100BASE-T where no data will be transmit following move out 1240 * of EEE LPI Tx state 1241 */ 1242 #define IGC_TW_SYSTEM_100_MASK 0x0000FF00 1243 #define IGC_TW_SYSTEM_100_SHIFT 8 1244 #define IGC_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */ 1245 #define IGC_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */ 1246 #define IGC_LTRMINV_SCALE_MASK 0x00001C00 /* LTR minimum scale */ 1247 #define IGC_LTRMINV_SCALE_SHIFT 10 1248 /* Reg val to set scale to 1024 nsec */ 1249 #define IGC_LTRMINV_SCALE_1024 2 1250 /* Reg val to set scale to 32768 nsec */ 1251 #define IGC_LTRMINV_SCALE_32768 3 1252 #define IGC_LTRMINV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ 1253 #define IGC_LTRMAXV_SCALE_MASK 0x00001C00 /* LTR maximum scale */ 1254 #define IGC_LTRMAXV_SCALE_SHIFT 10 1255 /* Reg val to set scale to 1024 nsec */ 1256 #define IGC_LTRMAXV_SCALE_1024 2 1257 /* Reg val to set scale to 32768 nsec */ 1258 #define IGC_LTRMAXV_SCALE_32768 3 1259 #define IGC_LTRMAXV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ 1260 1261 #define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 1262 #define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 1263 #define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */ 1264 #define IGC_TXPB0S_SIZE_I225_MASK 0x0000003F /* Tx packet buffer 0 size */ 1265 #define IGC_STM_OPCODE 0xDB00 1266 #define IGC_EEPROM_FLASH_SIZE_WORD 0x11 1267 #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \ 1268 (u8)((invm_dword) & 0x7) 1269 #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \ 1270 (u8)(((invm_dword) & 0x0000FE00) >> 9) 1271 #define INVM_DWORD_TO_WORD_DATA(invm_dword) \ 1272 (u16)(((invm_dword) & 0xFFFF0000) >> 16) 1273 #define IGC_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 1274 #define IGC_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 1275 #define IGC_INVM_ULT_BYTES_SIZE 8 1276 #define IGC_INVM_RECORD_SIZE_IN_BYTES 4 1277 #define IGC_INVM_VER_FIELD_ONE 0x1FF8 1278 #define IGC_INVM_VER_FIELD_TWO 0x7FE000 1279 #define IGC_INVM_IMGTYPE_FIELD 0x1F800000 1280 1281 #define IGC_INVM_MAJOR_MASK 0x3F0 1282 #define IGC_INVM_MINOR_MASK 0xF 1283 #define IGC_INVM_MAJOR_SHIFT 4 1284 1285 /* PLL Defines */ 1286 #define IGC_PCI_PMCSR 0x44 1287 #define IGC_PCI_PMCSR_D3 0x03 1288 #define IGC_MAX_PLL_TRIES 5 1289 #define IGC_PHY_PLL_UNCONF 0xFF 1290 #define IGC_PHY_PLL_FREQ_PAGE 0xFC0000 1291 #define IGC_PHY_PLL_FREQ_REG 0x000E 1292 #define IGC_INVM_DEFAULT_AL 0x202F 1293 #define IGC_INVM_AUTOLOAD 0x0A 1294 #define IGC_INVM_PLL_WO_VAL 0x0010 1295 1296 /* Proxy Filter Control Extended */ 1297 #define IGC_PROXYFCEX_MDNS 0x00000001 /* mDNS */ 1298 #define IGC_PROXYFCEX_MDNS_M 0x00000002 /* mDNS Multicast */ 1299 #define IGC_PROXYFCEX_MDNS_U 0x00000004 /* mDNS Unicast */ 1300 #define IGC_PROXYFCEX_IPV4_M 0x00000008 /* IPv4 Multicast */ 1301 #define IGC_PROXYFCEX_IPV6_M 0x00000010 /* IPv6 Multicast */ 1302 #define IGC_PROXYFCEX_IGMP 0x00000020 /* IGMP */ 1303 #define IGC_PROXYFCEX_IGMP_M 0x00000040 /* IGMP Multicast */ 1304 #define IGC_PROXYFCEX_ARPRES 0x00000080 /* ARP Response */ 1305 #define IGC_PROXYFCEX_ARPRES_D 0x00000100 /* ARP Response Directed */ 1306 #define IGC_PROXYFCEX_ICMPV4 0x00000200 /* ICMPv4 */ 1307 #define IGC_PROXYFCEX_ICMPV4_D 0x00000400 /* ICMPv4 Directed */ 1308 #define IGC_PROXYFCEX_ICMPV6 0x00000800 /* ICMPv6 */ 1309 #define IGC_PROXYFCEX_ICMPV6_D 0x00001000 /* ICMPv6 Directed */ 1310 #define IGC_PROXYFCEX_DNS 0x00002000 /* DNS */ 1311 1312 /* Proxy Filter Control */ 1313 #define IGC_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ 1314 #define IGC_PROXYFC_EX 0x00000004 /* Directed exact proxy */ 1315 #define IGC_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ 1316 #define IGC_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ 1317 #define IGC_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ 1318 #define IGC_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ 1319 #define IGC_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ 1320 #define IGC_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 1321 #define IGC_PROXYFC_NS_DIRECTED 0x00000400 /* Directed NS Proxy Ena */ 1322 #define IGC_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ 1323 /* Proxy Status */ 1324 #define IGC_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ 1325 1326 /* Firmware Status */ 1327 #define IGC_FWSTS_FWRI 0x80000000 /* FW Reset Indication */ 1328 /* VF Control */ 1329 #define IGC_VTCTRL_RST 0x04000000 /* Reset VF */ 1330 1331 #define IGC_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */ 1332 /* Lan ID bit field offset in status register */ 1333 #define IGC_STATUS_LAN_ID_OFFSET 2 1334 #define IGC_VFTA_ENTRIES 128 1335 1336 #define IGC_UNUSEDARG 1337 1338 #endif /* _IGC_DEFINES_H_ */ 1339