1 /* $OpenBSD: ixgbe_82599.c,v 1.7 2012/11/06 17:29:39 mikeb Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2009, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.3 2009/12/07 21:30:54 jfv Exp $*/ 36 37 #include <dev/pci/ixgbe.h> 38 #include <dev/pci/ixgbe_type.h> 39 40 int32_t ixgbe_init_ops_82599(struct ixgbe_hw *hw); 41 int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 42 ixgbe_link_speed *speed, 43 int *autoneg); 44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); 45 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 47 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 48 int32_t ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 49 ixgbe_link_speed speed, int autoneg, 50 int autoneg_wait_to_complete); 51 int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 52 ixgbe_link_speed speed, int autoneg, 53 int autoneg_wait_to_complete); 54 int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 55 int autoneg_wait_to_complete); 56 int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 57 ixgbe_link_speed speed, 58 int autoneg, 59 int autoneg_wait_to_complete); 60 int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 61 ixgbe_link_speed speed, 62 int autoneg, 63 int autoneg_wait_to_complete); 64 int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); 65 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); 66 int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw); 67 int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val); 68 int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, uint8_t val); 69 int32_t ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw); 70 int32_t ixgbe_identify_phy_82599(struct ixgbe_hw *hw); 71 int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); 72 uint32_t ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); 73 int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval); 74 int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 75 int ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 76 77 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 78 { 79 struct ixgbe_mac_info *mac = &hw->mac; 80 81 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 82 83 /* enable the laser control functions for SFP+ fiber */ 84 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { 85 mac->ops.disable_tx_laser = 86 &ixgbe_disable_tx_laser_multispeed_fiber; 87 mac->ops.enable_tx_laser = 88 &ixgbe_enable_tx_laser_multispeed_fiber; 89 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 90 91 } else { 92 mac->ops.disable_tx_laser = NULL; 93 mac->ops.enable_tx_laser = NULL; 94 mac->ops.flap_tx_laser = NULL; 95 } 96 97 if (hw->phy.multispeed_fiber) { 98 /* Set up dual speed SFP+ support */ 99 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 100 } else { 101 if ((ixgbe_hw0(hw, get_media_type) == ixgbe_media_type_backplane) && 102 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 103 hw->phy.smart_speed == ixgbe_smart_speed_on) && 104 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 105 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 106 } else { 107 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 108 } 109 } 110 } 111 112 /** 113 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 114 * @hw: pointer to hardware structure 115 * 116 * Initialize any function pointers that were not able to be 117 * set during init_shared_code because the PHY/SFP type was 118 * not known. Perform the SFP init if necessary. 119 * 120 **/ 121 int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 122 { 123 struct ixgbe_mac_info *mac = &hw->mac; 124 struct ixgbe_phy_info *phy = &hw->phy; 125 int32_t ret_val = IXGBE_SUCCESS; 126 127 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 128 129 /* Identify the PHY or SFP module */ 130 ret_val = phy->ops.identify(hw); 131 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 132 goto init_phy_ops_out; 133 134 /* Setup function pointers based on detected SFP module and speeds */ 135 ixgbe_init_mac_link_ops_82599(hw); 136 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 137 hw->phy.ops.reset = NULL; 138 139 /* If copper media, overwrite with copper function pointers */ 140 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 141 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 142 mac->ops.get_link_capabilities = 143 &ixgbe_get_copper_link_capabilities_generic; 144 } 145 146 /* Set necessary function pointers based on phy type */ 147 switch (hw->phy.type) { 148 case ixgbe_phy_tn: 149 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 150 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 151 phy->ops.get_firmware_version = 152 &ixgbe_get_phy_firmware_version_tnx; 153 break; 154 case ixgbe_phy_aq: 155 phy->ops.get_firmware_version = 156 &ixgbe_get_phy_firmware_version_generic; 157 break; 158 default: 159 break; 160 } 161 init_phy_ops_out: 162 return ret_val; 163 } 164 165 int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 166 { 167 int32_t ret_val = IXGBE_SUCCESS; 168 uint32_t reg_anlp1 = 0; 169 uint32_t i = 0; 170 uint16_t list_offset, data_offset, data_value; 171 172 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 173 174 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 175 ixgbe_init_mac_link_ops_82599(hw); 176 177 hw->phy.ops.reset = NULL; 178 179 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 180 &data_offset); 181 if (ret_val != IXGBE_SUCCESS) 182 goto setup_sfp_out; 183 184 /* PHY config will finish before releasing the semaphore */ 185 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 186 IXGBE_GSSR_MAC_CSR_SM); 187 if (ret_val != IXGBE_SUCCESS) { 188 ret_val = IXGBE_ERR_SWFW_SYNC; 189 goto setup_sfp_out; 190 } 191 192 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 193 while (data_value != 0xffff) { 194 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 195 IXGBE_WRITE_FLUSH(hw); 196 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 197 } 198 199 /* Release the semaphore */ 200 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 201 /* Delay obtaining semaphore again to allow FW access */ 202 msec_delay(hw->eeprom.semaphore_delay); 203 204 /* Now restart DSP by setting Restart_AN and clearing LMS */ 205 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw, 206 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) | 207 IXGBE_AUTOC_AN_RESTART)); 208 209 /* Wait for AN to leave state 0 */ 210 for (i = 0; i < 10; i++) { 211 msec_delay(4); 212 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1); 213 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK) 214 break; 215 } 216 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) { 217 DEBUGOUT("sfp module setup not complete\n"); 218 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 219 goto setup_sfp_out; 220 } 221 222 /* Restart DSP by setting Restart_AN and return to SFI mode */ 223 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw, 224 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL | 225 IXGBE_AUTOC_AN_RESTART)); 226 } 227 228 setup_sfp_out: 229 return ret_val; 230 } 231 232 /** 233 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 234 * @hw: pointer to hardware structure 235 * 236 * Initialize the function pointers and assign the MAC type for 82599. 237 * Does not touch the hardware. 238 **/ 239 240 int32_t ixgbe_init_ops_82599(struct ixgbe_hw *hw) 241 { 242 struct ixgbe_mac_info *mac = &hw->mac; 243 struct ixgbe_phy_info *phy = &hw->phy; 244 int32_t ret_val; 245 246 DEBUGFUNC("ixgbe_init_ops_82599"); 247 248 ret_val = ixgbe_init_phy_ops_generic(hw); 249 ret_val = ixgbe_init_ops_generic(hw); 250 251 /* PHY */ 252 phy->ops.identify = &ixgbe_identify_phy_82599; 253 phy->ops.init = &ixgbe_init_phy_ops_82599; 254 255 /* MAC */ 256 mac->ops.reset_hw = &ixgbe_reset_hw_82599; 257 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 258 mac->ops.get_media_type = &ixgbe_get_media_type_82599; 259 mac->ops.get_supported_physical_layer = 260 &ixgbe_get_supported_physical_layer_82599; 261 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; 262 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; 263 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; 264 mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599; 265 266 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 267 #if 0 268 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 269 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 270 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 271 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; 272 #endif 273 274 /* RAR, Multicast, VLAN */ 275 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 276 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 277 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 278 mac->rar_highwater = 1; 279 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 280 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 281 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 282 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; 283 #if 0 284 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; 285 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; 286 #endif 287 288 /* Link */ 289 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; 290 mac->ops.check_link = &ixgbe_check_mac_link_generic; 291 ixgbe_init_mac_link_ops_82599(hw); 292 293 mac->mcft_size = 128; 294 mac->vft_size = 128; 295 mac->num_rar_entries = 128; 296 mac->rx_pb_size = 512; 297 mac->max_tx_queues = 128; 298 mac->max_rx_queues = 128; 299 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 300 301 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 302 303 return ret_val; 304 } 305 306 /** 307 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 308 * @hw: pointer to hardware structure 309 * @speed: pointer to link speed 310 * @negotiation: TRUE when autoneg or autotry is enabled 311 * 312 * Determines the link capabilities by reading the AUTOC register. 313 **/ 314 int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 315 ixgbe_link_speed *speed, 316 int *negotiation) 317 { 318 int32_t status = IXGBE_SUCCESS; 319 uint32_t autoc = 0; 320 321 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 322 323 /* Check if 1G SFP module. */ 324 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 325 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) { 326 *speed = IXGBE_LINK_SPEED_1GB_FULL; 327 *negotiation = TRUE; 328 goto out; 329 } 330 331 /* 332 * Determine link capabilities based on the stored value of AUTOC, 333 * which represents EEPROM defaults. If AUTOC value has not 334 * been stored, use the current register values. 335 */ 336 if (hw->mac.orig_link_settings_stored) 337 autoc = hw->mac.orig_autoc; 338 else 339 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 340 341 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 342 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 343 *speed = IXGBE_LINK_SPEED_1GB_FULL; 344 *negotiation = FALSE; 345 break; 346 347 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 348 *speed = IXGBE_LINK_SPEED_10GB_FULL; 349 *negotiation = FALSE; 350 break; 351 352 case IXGBE_AUTOC_LMS_1G_AN: 353 *speed = IXGBE_LINK_SPEED_1GB_FULL; 354 *negotiation = TRUE; 355 break; 356 357 case IXGBE_AUTOC_LMS_10G_SERIAL: 358 *speed = IXGBE_LINK_SPEED_10GB_FULL; 359 *negotiation = FALSE; 360 break; 361 362 case IXGBE_AUTOC_LMS_KX4_KX_KR: 363 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 364 *speed = IXGBE_LINK_SPEED_UNKNOWN; 365 if (autoc & IXGBE_AUTOC_KR_SUPP) 366 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 367 if (autoc & IXGBE_AUTOC_KX4_SUPP) 368 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 369 if (autoc & IXGBE_AUTOC_KX_SUPP) 370 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 371 *negotiation = TRUE; 372 break; 373 374 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 375 *speed = IXGBE_LINK_SPEED_100_FULL; 376 if (autoc & IXGBE_AUTOC_KR_SUPP) 377 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 378 if (autoc & IXGBE_AUTOC_KX4_SUPP) 379 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 380 if (autoc & IXGBE_AUTOC_KX_SUPP) 381 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 382 *negotiation = TRUE; 383 break; 384 385 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 386 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 387 *negotiation = FALSE; 388 break; 389 390 default: 391 status = IXGBE_ERR_LINK_SETUP; 392 goto out; 393 break; 394 } 395 396 if (hw->phy.multispeed_fiber) { 397 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 398 IXGBE_LINK_SPEED_1GB_FULL; 399 *negotiation = TRUE; 400 } 401 402 out: 403 return status; 404 } 405 406 /** 407 * ixgbe_get_media_type_82599 - Get media type 408 * @hw: pointer to hardware structure 409 * 410 * Returns the media type (fiber, copper, backplane) 411 **/ 412 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 413 { 414 enum ixgbe_media_type media_type; 415 416 DEBUGFUNC("ixgbe_get_media_type_82599"); 417 418 /* Detect if there is a copper PHY attached. */ 419 switch (hw->phy.type) { 420 case ixgbe_phy_cu_unknown: 421 case ixgbe_phy_tn: 422 case ixgbe_phy_aq: 423 media_type = ixgbe_media_type_copper; 424 goto out; 425 default: 426 break; 427 } 428 429 switch (hw->device_id) { 430 case IXGBE_DEV_ID_82599_KX4: 431 case IXGBE_DEV_ID_82599_KX4_MEZZ: 432 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 433 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 434 case IXGBE_DEV_ID_82599_XAUI_LOM: 435 /* Default device ID is mezzanine card KX/KX4 */ 436 media_type = ixgbe_media_type_backplane; 437 break; 438 case IXGBE_DEV_ID_82599_SFP: 439 case IXGBE_DEV_ID_82599_SFP_FCOE: 440 case IXGBE_DEV_ID_82599_SFP_SF2: 441 media_type = ixgbe_media_type_fiber; 442 break; 443 case IXGBE_DEV_ID_82599_CX4: 444 media_type = ixgbe_media_type_cx4; 445 break; 446 case IXGBE_DEV_ID_82599_T3_LOM: 447 media_type = ixgbe_media_type_copper; 448 break; 449 default: 450 media_type = ixgbe_media_type_unknown; 451 break; 452 } 453 out: 454 return media_type; 455 } 456 457 /** 458 * ixgbe_start_mac_link_82599 - Setup MAC link settings 459 * @hw: pointer to hardware structure 460 * 461 * Configures link settings based on values in the ixgbe_hw struct. 462 * Restarts the link. Performs autonegotiation if needed. 463 **/ 464 int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 465 int autoneg_wait_to_complete) 466 { 467 uint32_t autoc_reg; 468 uint32_t links_reg; 469 uint32_t i; 470 int32_t status = IXGBE_SUCCESS; 471 472 DEBUGFUNC("ixgbe_start_mac_link_82599"); 473 474 475 /* Restart link */ 476 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 477 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 478 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 479 480 /* Only poll for autoneg to complete if specified to do so */ 481 if (autoneg_wait_to_complete) { 482 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 483 IXGBE_AUTOC_LMS_KX4_KX_KR || 484 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 485 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 486 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 487 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 488 links_reg = 0; /* Just in case Autoneg time = 0 */ 489 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 490 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 491 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 492 break; 493 msec_delay(100); 494 } 495 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 496 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 497 DEBUGOUT("Autoneg did not complete.\n"); 498 } 499 } 500 } 501 502 /* Add delay to filter out noises during initial link setup */ 503 msec_delay(50); 504 505 return status; 506 } 507 508 /** 509 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 510 * @hw: pointer to hardware structure 511 * 512 * The base drivers may require better control over SFP+ module 513 * PHY states. This includes selectively shutting down the Tx 514 * laser on the PHY, effectively halting physical link. 515 **/ 516 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 517 { 518 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 519 520 /* Disable tx laser; allow 100us to go dark per spec */ 521 esdp_reg |= IXGBE_ESDP_SDP3; 522 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 523 IXGBE_WRITE_FLUSH(hw); 524 usec_delay(100); 525 } 526 527 /** 528 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 529 * @hw: pointer to hardware structure 530 * 531 * The base drivers may require better control over SFP+ module 532 * PHY states. This includes selectively turning on the Tx 533 * laser on the PHY, effectively starting physical link. 534 **/ 535 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 536 { 537 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 538 539 /* Enable tx laser; allow 100ms to light up */ 540 esdp_reg &= ~IXGBE_ESDP_SDP3; 541 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 542 IXGBE_WRITE_FLUSH(hw); 543 msec_delay(100); 544 } 545 546 /** 547 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 548 * @hw: pointer to hardware structure 549 * 550 * When the driver changes the link speeds that it can support, 551 * it sets autotry_restart to TRUE to indicate that we need to 552 * initiate a new autotry session with the link partner. To do 553 * so, we set the speed then disable and re-enable the tx laser, to 554 * alert the link partner that it also needs to restart autotry on its 555 * end. This is consistent with TRUE clause 37 autoneg, which also 556 * involves a loss of signal. 557 **/ 558 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 559 { 560 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 561 562 if (hw->mac.autotry_restart) { 563 ixgbe_disable_tx_laser_multispeed_fiber(hw); 564 ixgbe_enable_tx_laser_multispeed_fiber(hw); 565 hw->mac.autotry_restart = FALSE; 566 } 567 } 568 569 /** 570 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 571 * @hw: pointer to hardware structure 572 * @speed: new link speed 573 * @autoneg: TRUE if autonegotiation enabled 574 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 575 * 576 * Set the link speed in the AUTOC register and restarts link. 577 **/ 578 int32_t ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 579 ixgbe_link_speed speed, int autoneg, 580 int autoneg_wait_to_complete) 581 { 582 int32_t status = IXGBE_SUCCESS; 583 ixgbe_link_speed link_speed; 584 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 585 uint32_t speedcnt = 0; 586 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 587 uint32_t i = 0; 588 int link_up = FALSE; 589 int negotiation; 590 591 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 592 593 /* Mask off requested but non-supported speeds */ 594 status = ixgbe_hw(hw, get_link_capabilities, &link_speed, &negotiation); 595 if (status != IXGBE_SUCCESS) 596 return status; 597 598 speed &= link_speed; 599 600 /* 601 * Try each speed one by one, highest priority first. We do this in 602 * software because 10gb fiber doesn't support speed autonegotiation. 603 */ 604 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 605 speedcnt++; 606 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 607 608 /* If we already have link at this speed, just jump out */ 609 status = ixgbe_hw(hw, check_link, &link_speed, &link_up, FALSE); 610 if (status != IXGBE_SUCCESS) 611 return status; 612 613 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 614 goto out; 615 616 /* Set the module link speed */ 617 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 618 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 619 IXGBE_WRITE_FLUSH(hw); 620 621 /* Allow module to change analog characteristics (1G->10G) */ 622 msec_delay(40); 623 624 status = ixgbe_setup_mac_link_82599(hw, 625 IXGBE_LINK_SPEED_10GB_FULL, 626 autoneg, 627 autoneg_wait_to_complete); 628 if (status != IXGBE_SUCCESS) 629 return status; 630 631 /* Flap the tx laser if it has not already been done */ 632 ixgbe_hw(hw, flap_tx_laser); 633 634 /* 635 * Wait for the controller to acquire link. Per IEEE 802.3ap, 636 * Section 73.10.2, we may have to wait up to 500ms if KR is 637 * attempted. 82599 uses the same timing for 10g SFI. 638 */ 639 for (i = 0; i < 5; i++) { 640 /* Wait for the link partner to also set speed */ 641 msec_delay(100); 642 643 /* If we have link, just jump out */ 644 status = ixgbe_hw(hw, check_link, &link_speed, 645 &link_up, FALSE); 646 if (status != IXGBE_SUCCESS) 647 return status; 648 649 if (link_up) 650 goto out; 651 } 652 } 653 654 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 655 speedcnt++; 656 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 657 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 658 659 /* If we already have link at this speed, just jump out */ 660 status = ixgbe_hw(hw, check_link, &link_speed, &link_up, FALSE); 661 if (status != IXGBE_SUCCESS) 662 return status; 663 664 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 665 goto out; 666 667 /* Set the module link speed */ 668 esdp_reg &= ~IXGBE_ESDP_SDP5; 669 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 670 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 671 IXGBE_WRITE_FLUSH(hw); 672 673 /* Allow module to change analog characteristics (10G->1G) */ 674 msec_delay(40); 675 676 status = ixgbe_setup_mac_link_82599(hw, 677 IXGBE_LINK_SPEED_1GB_FULL, 678 autoneg, 679 autoneg_wait_to_complete); 680 if (status != IXGBE_SUCCESS) 681 return status; 682 683 /* Flap the tx laser if it has not already been done */ 684 ixgbe_hw(hw, flap_tx_laser); 685 686 /* Wait for the link partner to also set speed */ 687 msec_delay(100); 688 689 /* If we have link, just jump out */ 690 status = ixgbe_hw(hw, check_link, &link_speed, &link_up, FALSE); 691 if (status != IXGBE_SUCCESS) 692 return status; 693 694 if (link_up) 695 goto out; 696 } 697 698 /* 699 * We didn't get link. Configure back to the highest speed we tried, 700 * (if there was more than one). We call ourselves back with just the 701 * single highest speed that the user requested. 702 */ 703 if (speedcnt > 1) 704 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 705 highest_link_speed, autoneg, autoneg_wait_to_complete); 706 707 out: 708 /* Set autoneg_advertised value based on input link speed */ 709 hw->phy.autoneg_advertised = 0; 710 711 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 712 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 713 714 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 715 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 716 717 return status; 718 } 719 720 /** 721 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 722 * @hw: pointer to hardware structure 723 * @speed: new link speed 724 * @autoneg: TRUE if autonegotiation enabled 725 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 726 * 727 * Implements the Intel SmartSpeed algorithm. 728 **/ 729 int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 730 ixgbe_link_speed speed, int autoneg, 731 int autoneg_wait_to_complete) 732 { 733 int32_t status = IXGBE_SUCCESS; 734 ixgbe_link_speed link_speed; 735 int32_t i, j; 736 int link_up = FALSE; 737 uint32_t autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 738 739 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 740 741 /* Set autoneg_advertised value based on input link speed */ 742 hw->phy.autoneg_advertised = 0; 743 744 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 745 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 746 747 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 748 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 749 750 if (speed & IXGBE_LINK_SPEED_100_FULL) 751 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 752 753 /* 754 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 755 * autoneg advertisement if link is unable to be established at the 756 * highest negotiated rate. This can sometimes happen due to integrity 757 * issues with the physical media connection. 758 */ 759 760 /* First, try to get link with full advertisement */ 761 hw->phy.smart_speed_active = FALSE; 762 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 763 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 764 autoneg_wait_to_complete); 765 if (status != IXGBE_SUCCESS) 766 goto out; 767 768 /* 769 * Wait for the controller to acquire link. Per IEEE 802.3ap, 770 * Section 73.10.2, we may have to wait up to 500ms if KR is 771 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 772 * Table 9 in the AN MAS. 773 */ 774 for (i = 0; i < 5; i++) { 775 msec_delay(100); 776 777 /* If we have link, just jump out */ 778 status = ixgbe_hw(hw, check_link, &link_speed, &link_up, 779 FALSE); 780 if (status != IXGBE_SUCCESS) 781 goto out; 782 783 if (link_up) 784 goto out; 785 } 786 } 787 788 /* 789 * We didn't get link. If we advertised KR plus one of KX4/KX 790 * (or BX4/BX), then disable KR and try again. 791 */ 792 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 793 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 794 goto out; 795 796 /* Turn SmartSpeed on to disable KR support */ 797 hw->phy.smart_speed_active = TRUE; 798 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 799 autoneg_wait_to_complete); 800 if (status != IXGBE_SUCCESS) 801 goto out; 802 803 /* 804 * Wait for the controller to acquire link. 600ms will allow for 805 * the AN link_fail_inhibit_timer as well for multiple cycles of 806 * parallel detect, both 10g and 1g. This allows for the maximum 807 * connect attempts as defined in the AN MAS table 73-7. 808 */ 809 for (i = 0; i < 6; i++) { 810 msec_delay(100); 811 812 /* If we have link, just jump out */ 813 status = ixgbe_hw(hw, check_link, &link_speed, &link_up, FALSE); 814 if (status != IXGBE_SUCCESS) 815 goto out; 816 817 if (link_up) 818 goto out; 819 } 820 821 /* We didn't get link. Turn SmartSpeed back off. */ 822 hw->phy.smart_speed_active = FALSE; 823 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 824 autoneg_wait_to_complete); 825 826 out: 827 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 828 DEBUGOUT("Smartspeed has downgraded the link speed " 829 "from the maximum advertised\n"); 830 return status; 831 } 832 833 /** 834 * ixgbe_setup_mac_link_82599 - Set MAC link speed 835 * @hw: pointer to hardware structure 836 * @speed: new link speed 837 * @autoneg: TRUE if autonegotiation enabled 838 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 839 * 840 * Set the link speed in the AUTOC register and restarts link. 841 **/ 842 int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 843 ixgbe_link_speed speed, int autoneg, 844 int autoneg_wait_to_complete) 845 { 846 int32_t status = IXGBE_SUCCESS; 847 uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 848 uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 849 uint32_t start_autoc = autoc; 850 uint32_t orig_autoc = 0; 851 uint32_t link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 852 uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 853 uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 854 uint32_t links_reg; 855 uint32_t i; 856 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 857 858 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 859 860 /* Check to see if speed passed in is supported. */ 861 status = ixgbe_hw(hw, get_link_capabilities, &link_capabilities, &autoneg); 862 if (status != IXGBE_SUCCESS) 863 goto out; 864 865 speed &= link_capabilities; 866 867 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 868 status = IXGBE_ERR_LINK_SETUP; 869 goto out; 870 } 871 872 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 873 if (hw->mac.orig_link_settings_stored) 874 orig_autoc = hw->mac.orig_autoc; 875 else 876 orig_autoc = autoc; 877 878 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 879 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 880 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 881 /* Set KX4/KX/KR support according to speed requested */ 882 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 883 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 884 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 885 autoc |= IXGBE_AUTOC_KX4_SUPP; 886 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 887 (hw->phy.smart_speed_active == FALSE)) 888 autoc |= IXGBE_AUTOC_KR_SUPP; 889 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 890 autoc |= IXGBE_AUTOC_KX_SUPP; 891 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 892 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 893 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 894 /* Switch from 1G SFI to 10G SFI if requested */ 895 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 896 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 897 autoc &= ~IXGBE_AUTOC_LMS_MASK; 898 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 899 } 900 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 901 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 902 /* Switch from 10G SFI to 1G SFI if requested */ 903 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 904 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 905 autoc &= ~IXGBE_AUTOC_LMS_MASK; 906 if (autoneg) 907 autoc |= IXGBE_AUTOC_LMS_1G_AN; 908 else 909 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 910 } 911 } 912 913 if (autoc != start_autoc) { 914 /* Restart link */ 915 autoc |= IXGBE_AUTOC_AN_RESTART; 916 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 917 918 /* Only poll for autoneg to complete if specified to do so */ 919 if (autoneg_wait_to_complete) { 920 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 921 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 922 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 923 links_reg = 0; /*Just in case Autoneg time=0*/ 924 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 925 links_reg = 926 IXGBE_READ_REG(hw, IXGBE_LINKS); 927 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 928 break; 929 msec_delay(100); 930 } 931 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 932 status = 933 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 934 DEBUGOUT("Autoneg did not complete.\n"); 935 } 936 } 937 } 938 939 /* Add delay to filter out noises during initial link setup */ 940 msec_delay(50); 941 } 942 943 out: 944 return status; 945 } 946 947 /** 948 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 949 * @hw: pointer to hardware structure 950 * @speed: new link speed 951 * @autoneg: TRUE if autonegotiation enabled 952 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 953 * 954 * Restarts link on PHY and MAC based on settings passed in. 955 **/ 956 int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 957 ixgbe_link_speed speed, 958 int autoneg, 959 int autoneg_wait_to_complete) 960 { 961 int32_t status; 962 963 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 964 965 /* Setup the PHY according to input speed */ 966 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 967 autoneg_wait_to_complete); 968 /* Set up MAC */ 969 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 970 971 return status; 972 } 973 /** 974 * ixgbe_reset_hw_82599 - Perform hardware reset 975 * @hw: pointer to hardware structure 976 * 977 * Resets the hardware by resetting the transmit and receive units, masks 978 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 979 * reset. 980 **/ 981 int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 982 { 983 int32_t status = IXGBE_SUCCESS; 984 uint32_t ctrl; 985 uint32_t i; 986 uint32_t autoc; 987 uint32_t autoc2; 988 989 DEBUGFUNC("ixgbe_reset_hw_82599"); 990 991 /* Call adapter stop to disable tx/rx and clear interrupts */ 992 hw->mac.ops.stop_adapter(hw); 993 994 /* PHY ops must be identified and initialized prior to reset */ 995 996 /* Identify PHY and related function pointers */ 997 status = hw->phy.ops.init(hw); 998 999 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1000 goto reset_hw_out; 1001 1002 /* Setup SFP module if there is one present. */ 1003 if (hw->phy.sfp_setup_needed) { 1004 status = hw->mac.ops.setup_sfp(hw); 1005 hw->phy.sfp_setup_needed = FALSE; 1006 } 1007 1008 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1009 goto reset_hw_out; 1010 1011 /* Reset PHY */ 1012 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) 1013 hw->phy.ops.reset(hw); 1014 1015 /* 1016 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 1017 * access and verify no pending requests before reset 1018 */ 1019 ixgbe_disable_pcie_master(hw); 1020 1021 mac_reset_top: 1022 /* 1023 * Issue global reset to the MAC. This needs to be a SW reset. 1024 * If link reset is used, it might reset the MAC when mng is using it 1025 */ 1026 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1027 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 1028 IXGBE_WRITE_FLUSH(hw); 1029 1030 /* Poll for reset bit to self-clear indicating reset is complete */ 1031 for (i = 0; i < 10; i++) { 1032 usec_delay(1); 1033 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1034 if (!(ctrl & IXGBE_CTRL_RST)) 1035 break; 1036 } 1037 if (ctrl & IXGBE_CTRL_RST) { 1038 status = IXGBE_ERR_RESET_FAILED; 1039 DEBUGOUT("Reset polling failed to complete.\n"); 1040 } 1041 1042 /* 1043 * Double resets are required for recovery from certain error 1044 * conditions. Between resets, it is necessary to stall to allow time 1045 * for any pending HW events to complete. We use 1usec since that is 1046 * what is needed for ixgbe_disable_pcie_master(). The second reset 1047 * then clears out any effects of those events. 1048 */ 1049 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1050 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1051 usec_delay(1); 1052 goto mac_reset_top; 1053 } 1054 1055 msec_delay(50); 1056 1057 /* 1058 * Store the original AUTOC/AUTOC2 values if they have not been 1059 * stored off yet. Otherwise restore the stored original 1060 * values since the reset operation sets back to defaults. 1061 */ 1062 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1063 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1064 if (hw->mac.orig_link_settings_stored == FALSE) { 1065 hw->mac.orig_autoc = autoc; 1066 hw->mac.orig_autoc2 = autoc2; 1067 hw->mac.orig_link_settings_stored = TRUE; 1068 } else { 1069 if (autoc != hw->mac.orig_autoc) 1070 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | 1071 IXGBE_AUTOC_AN_RESTART)); 1072 1073 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1074 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1075 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1076 autoc2 |= (hw->mac.orig_autoc2 & 1077 IXGBE_AUTOC2_UPPER_MASK); 1078 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1079 } 1080 } 1081 1082 /* Store the permanent mac address */ 1083 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1084 1085 /* 1086 * Store MAC address from RAR0, clear receive address registers, and 1087 * clear the multicast table. Also reset num_rar_entries to 128, 1088 * since we modify this value when programming the SAN MAC address. 1089 */ 1090 hw->mac.num_rar_entries = 128; 1091 hw->mac.ops.init_rx_addrs(hw); 1092 1093 #if 0 1094 /* Store the permanent SAN mac address */ 1095 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1096 1097 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1098 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1099 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1100 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1101 1102 /* Reserve the last RAR for the SAN MAC address */ 1103 hw->mac.num_rar_entries--; 1104 } 1105 1106 /* Store the alternative WWNN/WWPN prefix */ 1107 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1108 &hw->mac.wwpn_prefix); 1109 #endif 1110 reset_hw_out: 1111 return status; 1112 } 1113 1114 /** 1115 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1116 * @hw: pointer to hardware structure 1117 * @reg: analog register to read 1118 * @val: read value 1119 * 1120 * Performs read operation to Omer analog register specified. 1121 **/ 1122 int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val) 1123 { 1124 uint32_t core_ctl; 1125 1126 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 1127 1128 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1129 (reg << 8)); 1130 IXGBE_WRITE_FLUSH(hw); 1131 usec_delay(10); 1132 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1133 *val = (uint8_t)core_ctl; 1134 1135 return IXGBE_SUCCESS; 1136 } 1137 1138 /** 1139 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1140 * @hw: pointer to hardware structure 1141 * @reg: atlas register to write 1142 * @val: value to write 1143 * 1144 * Performs write operation to Omer analog register specified. 1145 **/ 1146 int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, uint8_t val) 1147 { 1148 uint32_t core_ctl; 1149 1150 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 1151 1152 core_ctl = (reg << 8) | val; 1153 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1154 IXGBE_WRITE_FLUSH(hw); 1155 usec_delay(10); 1156 1157 return IXGBE_SUCCESS; 1158 } 1159 1160 /** 1161 * ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx 1162 * @hw: pointer to hardware structure 1163 * 1164 * Starts the hardware using the generic start_hw function 1165 * and the generation start_hw function. 1166 * Then performs revision-specific operations, if any. 1167 **/ 1168 int32_t ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw) 1169 { 1170 int32_t ret_val = IXGBE_SUCCESS; 1171 uint32_t gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 1172 1173 DEBUGFUNC("ixgbe_start_hw_rev_1__82599"); 1174 1175 ret_val = ixgbe_start_hw_generic(hw); 1176 if (ret_val != IXGBE_SUCCESS) 1177 goto out; 1178 1179 ret_val = ixgbe_start_hw_gen2(hw); 1180 if (ret_val != IXGBE_SUCCESS) 1181 goto out; 1182 1183 /* We need to run link autotry after the driver loads */ 1184 hw->mac.autotry_restart = TRUE; 1185 1186 /* 1187 * From the 82599 specification update: 1188 * set the completion timeout value for 16ms to 55ms if needed 1189 */ 1190 if (gcr & IXGBE_GCR_CAP_VER2) { 1191 uint16_t reg; 1192 reg = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 1193 if ((reg & 0x0f) == 0) { 1194 reg |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 1195 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, 1196 reg); 1197 } 1198 } 1199 1200 if (ret_val == IXGBE_SUCCESS) 1201 ret_val = ixgbe_verify_fw_version_82599(hw); 1202 out: 1203 return ret_val; 1204 } 1205 1206 /** 1207 * ixgbe_identify_phy_82599 - Get physical layer module 1208 * @hw: pointer to hardware structure 1209 * 1210 * Determines the physical layer module found on the current adapter. 1211 * If PHY already detected, maintains current PHY type in hw struct, 1212 * otherwise executes the PHY detection routine. 1213 **/ 1214 int32_t ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1215 { 1216 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 1217 1218 DEBUGFUNC("ixgbe_identify_phy_82599"); 1219 1220 /* Detect PHY if not unknown - returns success if already detected. */ 1221 status = ixgbe_identify_phy_generic(hw); 1222 if (status != IXGBE_SUCCESS) { 1223 /* 82599 10GBASE-T requires an external PHY */ 1224 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1225 goto out; 1226 else 1227 status = ixgbe_identify_sfp_module_generic(hw); 1228 } 1229 1230 /* Set PHY type none if no PHY detected */ 1231 if (hw->phy.type == ixgbe_phy_unknown) { 1232 hw->phy.type = ixgbe_phy_none; 1233 status = IXGBE_SUCCESS; 1234 } 1235 1236 /* Return error if SFP module has been detected but is not supported */ 1237 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1238 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1239 1240 out: 1241 return status; 1242 } 1243 1244 /** 1245 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1246 * @hw: pointer to hardware structure 1247 * 1248 * Determines physical layer capabilities of the current configuration. 1249 **/ 1250 uint32_t ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1251 { 1252 uint32_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1253 uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1254 uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1255 uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1256 uint32_t pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1257 uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1258 uint16_t ext_ability = 0; 1259 uint8_t comp_codes_10g = 0; 1260 uint8_t comp_codes_1g = 0; 1261 1262 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 1263 1264 hw->phy.ops.identify(hw); 1265 1266 switch (hw->phy.type) { 1267 case ixgbe_phy_tn: 1268 case ixgbe_phy_aq: 1269 case ixgbe_phy_cu_unknown: 1270 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1271 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1272 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1273 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1274 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1275 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1276 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1277 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1278 goto out; 1279 default: 1280 break; 1281 } 1282 1283 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1284 case IXGBE_AUTOC_LMS_1G_AN: 1285 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1286 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1287 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1288 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1289 goto out; 1290 } else 1291 /* SFI mode so read SFP module */ 1292 goto sfp_check; 1293 break; 1294 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1295 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 1296 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1297 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 1298 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1299 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 1300 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 1301 goto out; 1302 break; 1303 case IXGBE_AUTOC_LMS_10G_SERIAL: 1304 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 1305 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1306 goto out; 1307 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 1308 goto sfp_check; 1309 break; 1310 case IXGBE_AUTOC_LMS_KX4_KX_KR: 1311 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 1312 if (autoc & IXGBE_AUTOC_KX_SUPP) 1313 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1314 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1315 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1316 if (autoc & IXGBE_AUTOC_KR_SUPP) 1317 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1318 goto out; 1319 break; 1320 default: 1321 goto out; 1322 break; 1323 } 1324 1325 sfp_check: 1326 /* SFP check must be done last since DA modules are sometimes used to 1327 * test KR mode - we need to id KR mode correctly before SFP module. 1328 * Call identify_sfp because the pluggable module may have changed */ 1329 hw->phy.ops.identify_sfp(hw); 1330 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1331 goto out; 1332 1333 switch (hw->phy.type) { 1334 case ixgbe_phy_sfp_passive_tyco: 1335 case ixgbe_phy_sfp_passive_unknown: 1336 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1337 break; 1338 case ixgbe_phy_sfp_ftl_active: 1339 case ixgbe_phy_sfp_active_unknown: 1340 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1341 break; 1342 case ixgbe_phy_sfp_avago: 1343 case ixgbe_phy_sfp_ftl: 1344 case ixgbe_phy_sfp_intel: 1345 case ixgbe_phy_sfp_unknown: 1346 hw->phy.ops.read_i2c_eeprom(hw, 1347 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1348 hw->phy.ops.read_i2c_eeprom(hw, 1349 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1350 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1351 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1352 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1353 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1354 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1355 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1356 break; 1357 default: 1358 break; 1359 } 1360 1361 out: 1362 return physical_layer; 1363 } 1364 1365 /** 1366 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1367 * @hw: pointer to hardware structure 1368 * @regval: register value to write to RXCTRL 1369 * 1370 * Enables the Rx DMA unit for 82599 1371 **/ 1372 int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval) 1373 { 1374 #define IXGBE_MAX_SECRX_POLL 30 1375 int i; 1376 int secrxreg; 1377 1378 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 1379 1380 /* 1381 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1382 * If traffic is incoming before we enable the Rx unit, it could hang 1383 * the Rx DMA unit. Therefore, make sure the security engine is 1384 * completely disabled prior to enabling the Rx unit. 1385 */ 1386 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 1387 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 1388 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 1389 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 1390 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 1391 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 1392 break; 1393 else 1394 /* Use interrupt-safe sleep just in case */ 1395 usec_delay(10); 1396 } 1397 1398 /* For informational purposes only */ 1399 if (i >= IXGBE_MAX_SECRX_POLL) 1400 DEBUGOUT("Rx unit being enabled before security " 1401 "path fully disabled. Continuing with init.\n"); 1402 1403 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 1404 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 1405 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 1406 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 1407 IXGBE_WRITE_FLUSH(hw); 1408 1409 return IXGBE_SUCCESS; 1410 } 1411 1412 /** 1413 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1414 * @hw: pointer to hardware structure 1415 * 1416 * Verifies that installed the firmware version is 0.6 or higher 1417 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1418 * 1419 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 1420 * if the FW version is not supported. 1421 **/ 1422 int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1423 { 1424 int32_t status = IXGBE_ERR_EEPROM_VERSION; 1425 uint16_t fw_offset, fw_ptp_cfg_offset; 1426 uint16_t fw_version = 0; 1427 1428 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 1429 1430 /* firmware check is only necessary for SFI devices */ 1431 if (hw->phy.media_type != ixgbe_media_type_fiber) { 1432 status = IXGBE_SUCCESS; 1433 goto fw_version_out; 1434 } 1435 1436 /* get the offset to the Firmware Module block */ 1437 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1438 1439 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 1440 goto fw_version_out; 1441 1442 /* get the offset to the Pass Through Patch Configuration block */ 1443 hw->eeprom.ops.read(hw, (fw_offset + 1444 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 1445 &fw_ptp_cfg_offset); 1446 1447 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 1448 goto fw_version_out; 1449 1450 /* get the firmware version */ 1451 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 1452 IXGBE_FW_PATCH_VERSION_4), 1453 &fw_version); 1454 1455 if (fw_version > 0x5) 1456 status = IXGBE_SUCCESS; 1457 1458 fw_version_out: 1459 return status; 1460 } 1461 1462 /** 1463 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 1464 * @hw: pointer to hardware structure 1465 * 1466 * Returns TRUE if the LESM FW module is present and enabled. Otherwise 1467 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. 1468 **/ 1469 int ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 1470 { 1471 int lesm_enabled = FALSE; 1472 uint16_t fw_offset, fw_lesm_param_offset, fw_lesm_state; 1473 int32_t status; 1474 1475 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 1476 1477 /* get the offset to the Firmware Module block */ 1478 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1479 1480 if ((status != IXGBE_SUCCESS) || 1481 (fw_offset == 0) || (fw_offset == 0xFFFF)) 1482 goto out; 1483 1484 /* get the offset to the LESM Parameters block */ 1485 status = hw->eeprom.ops.read(hw, (fw_offset + 1486 IXGBE_FW_LESM_PARAMETERS_PTR), 1487 &fw_lesm_param_offset); 1488 1489 if ((status != IXGBE_SUCCESS) || 1490 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 1491 goto out; 1492 1493 /* get the lesm state word */ 1494 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 1495 IXGBE_FW_LESM_STATE_1), 1496 &fw_lesm_state); 1497 1498 if ((status == IXGBE_SUCCESS) && 1499 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 1500 lesm_enabled = TRUE; 1501 1502 out: 1503 return lesm_enabled; 1504 } 1505