1 /* $OpenBSD: ixgbe_82599.c,v 1.10 2013/08/05 19:58:06 mikeb Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2013, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /* FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c 251964 Jun 18 21:28:19 2013 UTC */ 36 37 #include <dev/pci/ixgbe.h> 38 #include <dev/pci/ixgbe_type.h> 39 40 int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 41 ixgbe_link_speed *speed, 42 bool *autoneg); 43 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); 44 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 45 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 47 void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw, 48 ixgbe_link_speed speed); 49 int32_t ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, 51 bool autoneg_wait_to_complete); 52 int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 53 ixgbe_link_speed speed, 54 bool autoneg_wait_to_complete); 55 int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 56 bool autoneg_wait_to_complete); 57 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw); 58 int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 59 ixgbe_link_speed speed, 60 bool autoneg_wait_to_complete); 61 int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 62 ixgbe_link_speed speed, 63 bool autoneg_wait_to_complete); 64 int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); 65 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); 66 int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw); 67 int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 68 uint8_t *val); 69 int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 70 uint8_t val); 71 int32_t ixgbe_start_hw_82599(struct ixgbe_hw *hw); 72 int32_t ixgbe_identify_phy_82599(struct ixgbe_hw *hw); 73 int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); 74 uint32_t ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); 75 int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval); 76 int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 77 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 78 int32_t ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 79 uint16_t offset, uint16_t *data); 80 int32_t ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw); 81 int32_t ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, uint32_t index); 82 int32_t ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, uint32_t index); 83 84 static bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 85 { 86 uint32_t fwsm, manc, factps; 87 88 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 89 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 90 return FALSE; 91 92 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 93 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 94 return FALSE; 95 96 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS); 97 if (factps & IXGBE_FACTPS_MNGCG) 98 return FALSE; 99 100 return TRUE; 101 } 102 103 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 104 { 105 struct ixgbe_mac_info *mac = &hw->mac; 106 107 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 108 109 /* 110 * enable the laser control functions for SFP+ fiber 111 * and MNG not enabled 112 */ 113 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 114 !hw->mng_fw_enabled) { 115 mac->ops.disable_tx_laser = 116 &ixgbe_disable_tx_laser_multispeed_fiber; 117 mac->ops.enable_tx_laser = 118 &ixgbe_enable_tx_laser_multispeed_fiber; 119 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 120 121 } else { 122 mac->ops.disable_tx_laser = NULL; 123 mac->ops.enable_tx_laser = NULL; 124 mac->ops.flap_tx_laser = NULL; 125 } 126 127 if (hw->phy.multispeed_fiber) { 128 /* Set up dual speed SFP+ support */ 129 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 130 } else { 131 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 132 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 133 hw->phy.smart_speed == ixgbe_smart_speed_on) && 134 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 135 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 136 } else { 137 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 138 } 139 } 140 } 141 142 /** 143 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 144 * @hw: pointer to hardware structure 145 * 146 * Initialize any function pointers that were not able to be 147 * set during init_shared_code because the PHY/SFP type was 148 * not known. Perform the SFP init if necessary. 149 * 150 **/ 151 int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 152 { 153 struct ixgbe_mac_info *mac = &hw->mac; 154 struct ixgbe_phy_info *phy = &hw->phy; 155 int32_t ret_val = IXGBE_SUCCESS; 156 157 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 158 159 /* Identify the PHY or SFP module */ 160 ret_val = phy->ops.identify(hw); 161 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 162 goto init_phy_ops_out; 163 164 /* Setup function pointers based on detected SFP module and speeds */ 165 ixgbe_init_mac_link_ops_82599(hw); 166 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 167 hw->phy.ops.reset = NULL; 168 169 /* If copper media, overwrite with copper function pointers */ 170 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 171 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 172 mac->ops.get_link_capabilities = 173 &ixgbe_get_copper_link_capabilities_generic; 174 } 175 176 /* Set necessary function pointers based on phy type */ 177 switch (hw->phy.type) { 178 case ixgbe_phy_tn: 179 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 180 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 181 phy->ops.get_firmware_version = 182 &ixgbe_get_phy_firmware_version_tnx; 183 break; 184 default: 185 break; 186 } 187 init_phy_ops_out: 188 return ret_val; 189 } 190 191 int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 192 { 193 int32_t ret_val = IXGBE_SUCCESS; 194 uint16_t list_offset, data_offset, data_value; 195 bool got_lock = FALSE; 196 197 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 198 199 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 200 ixgbe_init_mac_link_ops_82599(hw); 201 202 hw->phy.ops.reset = NULL; 203 204 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 205 &data_offset); 206 if (ret_val != IXGBE_SUCCESS) 207 goto setup_sfp_out; 208 209 /* PHY config will finish before releasing the semaphore */ 210 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 211 IXGBE_GSSR_MAC_CSR_SM); 212 if (ret_val != IXGBE_SUCCESS) { 213 ret_val = IXGBE_ERR_SWFW_SYNC; 214 goto setup_sfp_out; 215 } 216 217 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 218 goto setup_sfp_err; 219 while (data_value != 0xffff) { 220 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 221 IXGBE_WRITE_FLUSH(hw); 222 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 223 goto setup_sfp_err; 224 } 225 226 /* Release the semaphore */ 227 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 228 /* Delay obtaining semaphore again to allow FW access */ 229 msec_delay(hw->eeprom.semaphore_delay); 230 231 /* Need SW/FW semaphore around AUTOC writes if LESM on, 232 * likewise reset_pipeline requires lock as it also writes 233 * AUTOC. 234 */ 235 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 236 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 237 IXGBE_GSSR_MAC_CSR_SM); 238 if (ret_val != IXGBE_SUCCESS) { 239 ret_val = IXGBE_ERR_SWFW_SYNC; 240 goto setup_sfp_out; 241 } 242 243 got_lock = TRUE; 244 } 245 246 /* Restart DSP and set SFI mode */ 247 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((hw->mac.orig_autoc) | 248 IXGBE_AUTOC_LMS_10G_SERIAL)); 249 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 250 ret_val = ixgbe_reset_pipeline_82599(hw); 251 252 if (got_lock) { 253 hw->mac.ops.release_swfw_sync(hw, 254 IXGBE_GSSR_MAC_CSR_SM); 255 got_lock = FALSE; 256 } 257 258 if (ret_val) { 259 DEBUGOUT("sfp module setup not complete\n"); 260 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 261 goto setup_sfp_out; 262 } 263 264 } 265 266 setup_sfp_out: 267 return ret_val; 268 269 setup_sfp_err: 270 /* Release the semaphore */ 271 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 272 /* Delay obtaining semaphore again to allow FW access */ 273 msec_delay(hw->eeprom.semaphore_delay); 274 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 275 "eeprom read at offset %d failed", data_offset); 276 return IXGBE_ERR_PHY; 277 } 278 279 /** 280 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 281 * @hw: pointer to hardware structure 282 * 283 * Initialize the function pointers and assign the MAC type for 82599. 284 * Does not touch the hardware. 285 **/ 286 287 int32_t ixgbe_init_ops_82599(struct ixgbe_hw *hw) 288 { 289 struct ixgbe_mac_info *mac = &hw->mac; 290 struct ixgbe_phy_info *phy = &hw->phy; 291 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 292 int32_t ret_val; 293 294 DEBUGFUNC("ixgbe_init_ops_82599"); 295 296 ixgbe_init_phy_ops_generic(hw); 297 ret_val = ixgbe_init_ops_generic(hw); 298 299 /* PHY */ 300 phy->ops.identify = &ixgbe_identify_phy_82599; 301 phy->ops.init = &ixgbe_init_phy_ops_82599; 302 303 /* MAC */ 304 mac->ops.reset_hw = &ixgbe_reset_hw_82599; 305 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 306 mac->ops.get_media_type = &ixgbe_get_media_type_82599; 307 mac->ops.get_supported_physical_layer = 308 &ixgbe_get_supported_physical_layer_82599; 309 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; 310 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; 311 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; 312 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; 313 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; 314 mac->ops.start_hw = &ixgbe_start_hw_82599; 315 316 /* RAR, Multicast, VLAN */ 317 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 318 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 319 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 320 mac->rar_highwater = 1; 321 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 322 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; 323 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 324 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 325 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; 326 327 mac->ops.verify_lesm_fw_enabled = &ixgbe_verify_lesm_fw_enabled_82599; 328 mac->ops.reset_pipeline = &ixgbe_reset_pipeline_82599; 329 mac->ops.stop_mac_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599; 330 331 /* Link */ 332 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; 333 mac->ops.check_link = &ixgbe_check_mac_link_generic; 334 ixgbe_init_mac_link_ops_82599(hw); 335 336 mac->mcft_size = 128; 337 mac->vft_size = 128; 338 mac->num_rar_entries = 128; 339 mac->rx_pb_size = 512; 340 mac->max_tx_queues = 128; 341 mac->max_rx_queues = 128; 342 mac->max_msix_vectors = 0 /*ixgbe_get_pcie_msix_count_generic(hw)*/; 343 344 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 345 346 /* EEPROM */ 347 eeprom->ops.read = &ixgbe_read_eeprom_82599; 348 349 /* Cache if MNG FW is up */ 350 hw->mng_fw_enabled = ixgbe_mng_enabled(hw); 351 352 return ret_val; 353 } 354 355 /** 356 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 357 * @hw: pointer to hardware structure 358 * @speed: pointer to link speed 359 * @autoneg: TRUE when autoneg or autotry is enabled 360 * 361 * Determines the link capabilities by reading the AUTOC register. 362 **/ 363 int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 364 ixgbe_link_speed *speed, 365 bool *autoneg) 366 { 367 int32_t status = IXGBE_SUCCESS; 368 uint32_t autoc = 0; 369 370 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 371 372 /* Check if 1G SFP module. */ 373 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 374 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 375 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 376 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 377 *speed = IXGBE_LINK_SPEED_1GB_FULL; 378 *autoneg = TRUE; 379 goto out; 380 } 381 382 /* 383 * Determine link capabilities based on the stored value of AUTOC, 384 * which represents EEPROM defaults. If AUTOC value has not 385 * been stored, use the current register values. 386 */ 387 if (hw->mac.orig_link_settings_stored) 388 autoc = hw->mac.orig_autoc; 389 else 390 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 391 392 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 393 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 394 *speed = IXGBE_LINK_SPEED_1GB_FULL; 395 *autoneg = FALSE; 396 break; 397 398 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 399 *speed = IXGBE_LINK_SPEED_10GB_FULL; 400 *autoneg = FALSE; 401 break; 402 403 case IXGBE_AUTOC_LMS_1G_AN: 404 *speed = IXGBE_LINK_SPEED_1GB_FULL; 405 *autoneg = TRUE; 406 break; 407 408 case IXGBE_AUTOC_LMS_10G_SERIAL: 409 *speed = IXGBE_LINK_SPEED_10GB_FULL; 410 *autoneg = FALSE; 411 break; 412 413 case IXGBE_AUTOC_LMS_KX4_KX_KR: 414 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 415 *speed = IXGBE_LINK_SPEED_UNKNOWN; 416 if (autoc & IXGBE_AUTOC_KR_SUPP) 417 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 418 if (autoc & IXGBE_AUTOC_KX4_SUPP) 419 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 420 if (autoc & IXGBE_AUTOC_KX_SUPP) 421 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 422 *autoneg = TRUE; 423 break; 424 425 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 426 *speed = IXGBE_LINK_SPEED_100_FULL; 427 if (autoc & IXGBE_AUTOC_KR_SUPP) 428 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 429 if (autoc & IXGBE_AUTOC_KX4_SUPP) 430 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 431 if (autoc & IXGBE_AUTOC_KX_SUPP) 432 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 433 *autoneg = TRUE; 434 break; 435 436 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 437 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 438 *autoneg = FALSE; 439 break; 440 441 default: 442 status = IXGBE_ERR_LINK_SETUP; 443 goto out; 444 break; 445 } 446 447 if (hw->phy.multispeed_fiber) { 448 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 449 IXGBE_LINK_SPEED_1GB_FULL; 450 *autoneg = TRUE; 451 } 452 453 out: 454 return status; 455 } 456 457 /** 458 * ixgbe_get_media_type_82599 - Get media type 459 * @hw: pointer to hardware structure 460 * 461 * Returns the media type (fiber, copper, backplane) 462 **/ 463 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 464 { 465 enum ixgbe_media_type media_type; 466 467 DEBUGFUNC("ixgbe_get_media_type_82599"); 468 469 /* Detect if there is a copper PHY attached. */ 470 switch (hw->phy.type) { 471 case ixgbe_phy_cu_unknown: 472 case ixgbe_phy_tn: 473 media_type = ixgbe_media_type_copper; 474 goto out; 475 default: 476 break; 477 } 478 479 switch (hw->device_id) { 480 case IXGBE_DEV_ID_82599_KX4: 481 case IXGBE_DEV_ID_82599_KX4_MEZZ: 482 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 483 case IXGBE_DEV_ID_82599_KR: 484 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 485 case IXGBE_DEV_ID_82599_XAUI_LOM: 486 /* Default device ID is mezzanine card KX/KX4 */ 487 media_type = ixgbe_media_type_backplane; 488 break; 489 case IXGBE_DEV_ID_82599_SFP: 490 case IXGBE_DEV_ID_82599_SFP_FCOE: 491 case IXGBE_DEV_ID_82599_SFP_EM: 492 case IXGBE_DEV_ID_82599_SFP_SF2: 493 case IXGBE_DEV_ID_82599_SFP_SF_QP: 494 case IXGBE_DEV_ID_82599EN_SFP: 495 media_type = ixgbe_media_type_fiber; 496 break; 497 case IXGBE_DEV_ID_82599_CX4: 498 media_type = ixgbe_media_type_cx4; 499 break; 500 case IXGBE_DEV_ID_82599_T3_LOM: 501 media_type = ixgbe_media_type_copper; 502 break; 503 case IXGBE_DEV_ID_82599_BYPASS: 504 media_type = ixgbe_media_type_fiber_fixed; 505 hw->phy.multispeed_fiber = TRUE; 506 break; 507 default: 508 media_type = ixgbe_media_type_unknown; 509 break; 510 } 511 out: 512 return media_type; 513 } 514 515 /** 516 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 517 * @hw: pointer to hardware structure 518 * 519 * Disables link during D3 power down sequence. 520 * 521 **/ 522 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 523 { 524 uint32_t autoc2_reg; 525 uint16_t ee_ctrl_2 = 0; 526 527 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599"); 528 ixgbe_read_eeprom_82599(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 529 530 if (!hw->mng_fw_enabled && ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 531 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 532 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 533 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 534 } 535 } 536 537 /** 538 * ixgbe_start_mac_link_82599 - Setup MAC link settings 539 * @hw: pointer to hardware structure 540 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 541 * 542 * Configures link settings based on values in the ixgbe_hw struct. 543 * Restarts the link. Performs autonegotiation if needed. 544 **/ 545 int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 546 bool autoneg_wait_to_complete) 547 { 548 uint32_t autoc_reg; 549 uint32_t links_reg; 550 uint32_t i; 551 int32_t status = IXGBE_SUCCESS; 552 bool got_lock = FALSE; 553 554 DEBUGFUNC("ixgbe_start_mac_link_82599"); 555 556 557 /* reset_pipeline requires us to hold this lock as it writes to 558 * AUTOC. 559 */ 560 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 561 status = hw->mac.ops.acquire_swfw_sync(hw, 562 IXGBE_GSSR_MAC_CSR_SM); 563 if (status != IXGBE_SUCCESS) 564 goto out; 565 566 got_lock = TRUE; 567 } 568 569 /* Restart link */ 570 ixgbe_reset_pipeline_82599(hw); 571 572 if (got_lock) 573 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 574 575 /* Only poll for autoneg to complete if specified to do so */ 576 if (autoneg_wait_to_complete) { 577 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 578 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 579 IXGBE_AUTOC_LMS_KX4_KX_KR || 580 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 581 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 582 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 583 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 584 links_reg = 0; /* Just in case Autoneg time = 0 */ 585 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 586 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 587 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 588 break; 589 msec_delay(100); 590 } 591 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 592 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 593 DEBUGOUT("Autoneg did not complete.\n"); 594 } 595 } 596 } 597 598 /* Add delay to filter out noises during initial link setup */ 599 msec_delay(50); 600 601 out: 602 return status; 603 } 604 605 /** 606 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 607 * @hw: pointer to hardware structure 608 * 609 * The base drivers may require better control over SFP+ module 610 * PHY states. This includes selectively shutting down the Tx 611 * laser on the PHY, effectively halting physical link. 612 **/ 613 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 614 { 615 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 616 617 /* Disable tx laser; allow 100us to go dark per spec */ 618 esdp_reg |= IXGBE_ESDP_SDP3; 619 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 620 IXGBE_WRITE_FLUSH(hw); 621 usec_delay(100); 622 } 623 624 /** 625 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 626 * @hw: pointer to hardware structure 627 * 628 * The base drivers may require better control over SFP+ module 629 * PHY states. This includes selectively turning on the Tx 630 * laser on the PHY, effectively starting physical link. 631 **/ 632 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 633 { 634 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 635 636 /* Enable tx laser; allow 100ms to light up */ 637 esdp_reg &= ~IXGBE_ESDP_SDP3; 638 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 639 IXGBE_WRITE_FLUSH(hw); 640 msec_delay(100); 641 } 642 643 /** 644 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 645 * @hw: pointer to hardware structure 646 * 647 * When the driver changes the link speeds that it can support, 648 * it sets autotry_restart to TRUE to indicate that we need to 649 * initiate a new autotry session with the link partner. To do 650 * so, we set the speed then disable and re-enable the tx laser, to 651 * alert the link partner that it also needs to restart autotry on its 652 * end. This is consistent with TRUE clause 37 autoneg, which also 653 * involves a loss of signal. 654 **/ 655 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 656 { 657 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 658 659 if (hw->mac.autotry_restart) { 660 ixgbe_disable_tx_laser_multispeed_fiber(hw); 661 ixgbe_enable_tx_laser_multispeed_fiber(hw); 662 hw->mac.autotry_restart = FALSE; 663 } 664 } 665 666 /** 667 * ixgbe_set_fiber_fixed_speed - Set module link speed for fixed fiber 668 * @hw: pointer to hardware structure 669 * @speed: link speed to set 670 * 671 * We set the module speed differently for fixed fiber. For other 672 * multi-speed devices we don't have an error value so here if we 673 * detect an error we just log it and exit. 674 */ 675 void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw, 676 ixgbe_link_speed speed) 677 { 678 int32_t status; 679 uint8_t rs, eeprom_data; 680 681 switch (speed) { 682 case IXGBE_LINK_SPEED_10GB_FULL: 683 /* one bit mask same as setting on */ 684 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 685 break; 686 case IXGBE_LINK_SPEED_1GB_FULL: 687 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 688 break; 689 default: 690 DEBUGOUT("Invalid fixed module speed\n"); 691 return; 692 } 693 694 /* Set RS0 */ 695 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 696 IXGBE_I2C_EEPROM_DEV_ADDR2, 697 &eeprom_data); 698 if (status) { 699 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 700 goto out; 701 } 702 703 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs; 704 705 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 706 IXGBE_I2C_EEPROM_DEV_ADDR2, 707 eeprom_data); 708 if (status) { 709 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 710 goto out; 711 } 712 713 /* Set RS1 */ 714 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 715 IXGBE_I2C_EEPROM_DEV_ADDR2, 716 &eeprom_data); 717 if (status) { 718 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 719 goto out; 720 } 721 722 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs; 723 724 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 725 IXGBE_I2C_EEPROM_DEV_ADDR2, 726 eeprom_data); 727 if (status) { 728 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 729 goto out; 730 } 731 out: 732 return; 733 } 734 735 /** 736 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 737 * @hw: pointer to hardware structure 738 * @speed: new link speed 739 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 740 * 741 * Set the link speed in the AUTOC register and restarts link. 742 **/ 743 int32_t ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 744 ixgbe_link_speed speed, 745 bool autoneg_wait_to_complete) 746 { 747 int32_t status = IXGBE_SUCCESS; 748 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 749 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 750 uint32_t speedcnt = 0; 751 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 752 uint32_t i = 0; 753 bool autoneg, link_up = FALSE; 754 755 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 756 757 /* Mask off requested but non-supported speeds */ 758 status = ixgbe_get_link_capabilities_82599(hw, &link_speed, &autoneg); 759 if (status != IXGBE_SUCCESS) 760 return status; 761 762 speed &= link_speed; 763 764 /* 765 * Try each speed one by one, highest priority first. We do this in 766 * software because 10gb fiber doesn't support speed autonegotiation. 767 */ 768 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 769 speedcnt++; 770 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 771 772 /* If we already have link at this speed, just jump out */ 773 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 774 if (status != IXGBE_SUCCESS) 775 return status; 776 777 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 778 goto out; 779 780 /* Set the module link speed */ 781 if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) { 782 ixgbe_set_fiber_fixed_speed(hw, 783 IXGBE_LINK_SPEED_10GB_FULL); 784 } else { 785 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 786 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 787 IXGBE_WRITE_FLUSH(hw); 788 } 789 790 /* Allow module to change analog characteristics (1G->10G) */ 791 msec_delay(40); 792 793 status = ixgbe_setup_mac_link_82599(hw, 794 IXGBE_LINK_SPEED_10GB_FULL, 795 autoneg_wait_to_complete); 796 if (status != IXGBE_SUCCESS) 797 return status; 798 799 /* Flap the tx laser if it has not already been done */ 800 ixgbe_flap_tx_laser(hw); 801 802 /* 803 * Wait for the controller to acquire link. Per IEEE 802.3ap, 804 * Section 73.10.2, we may have to wait up to 500ms if KR is 805 * attempted. 82599 uses the same timing for 10g SFI. 806 */ 807 for (i = 0; i < 5; i++) { 808 /* Wait for the link partner to also set speed */ 809 msec_delay(100); 810 811 /* If we have link, just jump out */ 812 status = ixgbe_check_link(hw, &link_speed, 813 &link_up, FALSE); 814 if (status != IXGBE_SUCCESS) 815 return status; 816 817 if (link_up) 818 goto out; 819 } 820 } 821 822 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 823 speedcnt++; 824 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 825 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 826 827 /* If we already have link at this speed, just jump out */ 828 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 829 if (status != IXGBE_SUCCESS) 830 return status; 831 832 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 833 goto out; 834 835 /* Set the module link speed */ 836 if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) { 837 ixgbe_set_fiber_fixed_speed(hw, 838 IXGBE_LINK_SPEED_1GB_FULL); 839 } else { 840 esdp_reg &= ~IXGBE_ESDP_SDP5; 841 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 842 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 843 IXGBE_WRITE_FLUSH(hw); 844 } 845 846 /* Allow module to change analog characteristics (10G->1G) */ 847 msec_delay(40); 848 849 status = ixgbe_setup_mac_link_82599(hw, 850 IXGBE_LINK_SPEED_1GB_FULL, 851 autoneg_wait_to_complete); 852 if (status != IXGBE_SUCCESS) 853 return status; 854 855 /* Flap the tx laser if it has not already been done */ 856 ixgbe_flap_tx_laser(hw); 857 858 /* Wait for the link partner to also set speed */ 859 msec_delay(100); 860 861 /* If we have link, just jump out */ 862 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 863 if (status != IXGBE_SUCCESS) 864 return status; 865 866 if (link_up) 867 goto out; 868 } 869 870 /* 871 * We didn't get link. Configure back to the highest speed we tried, 872 * (if there was more than one). We call ourselves back with just the 873 * single highest speed that the user requested. 874 */ 875 if (speedcnt > 1) 876 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 877 highest_link_speed, autoneg_wait_to_complete); 878 879 out: 880 /* Set autoneg_advertised value based on input link speed */ 881 hw->phy.autoneg_advertised = 0; 882 883 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 884 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 885 886 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 887 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 888 889 return status; 890 } 891 892 /** 893 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 894 * @hw: pointer to hardware structure 895 * @speed: new link speed 896 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 897 * 898 * Implements the Intel SmartSpeed algorithm. 899 **/ 900 int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 901 ixgbe_link_speed speed, 902 bool autoneg_wait_to_complete) 903 { 904 int32_t status = IXGBE_SUCCESS; 905 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 906 int32_t i, j; 907 bool link_up = FALSE; 908 uint32_t autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 909 910 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 911 912 /* Set autoneg_advertised value based on input link speed */ 913 hw->phy.autoneg_advertised = 0; 914 915 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 916 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 917 918 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 919 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 920 921 if (speed & IXGBE_LINK_SPEED_100_FULL) 922 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 923 924 /* 925 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 926 * autoneg advertisement if link is unable to be established at the 927 * highest negotiated rate. This can sometimes happen due to integrity 928 * issues with the physical media connection. 929 */ 930 931 /* First, try to get link with full advertisement */ 932 hw->phy.smart_speed_active = FALSE; 933 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 934 status = ixgbe_setup_mac_link_82599(hw, speed, 935 autoneg_wait_to_complete); 936 if (status != IXGBE_SUCCESS) 937 goto out; 938 939 /* 940 * Wait for the controller to acquire link. Per IEEE 802.3ap, 941 * Section 73.10.2, we may have to wait up to 500ms if KR is 942 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 943 * Table 9 in the AN MAS. 944 */ 945 for (i = 0; i < 5; i++) { 946 msec_delay(100); 947 948 /* If we have link, just jump out */ 949 status = ixgbe_check_link(hw, &link_speed, &link_up, 950 FALSE); 951 if (status != IXGBE_SUCCESS) 952 goto out; 953 954 if (link_up) 955 goto out; 956 } 957 } 958 959 /* 960 * We didn't get link. If we advertised KR plus one of KX4/KX 961 * (or BX4/BX), then disable KR and try again. 962 */ 963 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 964 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 965 goto out; 966 967 /* Turn SmartSpeed on to disable KR support */ 968 hw->phy.smart_speed_active = TRUE; 969 status = ixgbe_setup_mac_link_82599(hw, speed, 970 autoneg_wait_to_complete); 971 if (status != IXGBE_SUCCESS) 972 goto out; 973 974 /* 975 * Wait for the controller to acquire link. 600ms will allow for 976 * the AN link_fail_inhibit_timer as well for multiple cycles of 977 * parallel detect, both 10g and 1g. This allows for the maximum 978 * connect attempts as defined in the AN MAS table 73-7. 979 */ 980 for (i = 0; i < 6; i++) { 981 msec_delay(100); 982 983 /* If we have link, just jump out */ 984 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 985 if (status != IXGBE_SUCCESS) 986 goto out; 987 988 if (link_up) 989 goto out; 990 } 991 992 /* We didn't get link. Turn SmartSpeed back off. */ 993 hw->phy.smart_speed_active = FALSE; 994 status = ixgbe_setup_mac_link_82599(hw, speed, 995 autoneg_wait_to_complete); 996 997 out: 998 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 999 DEBUGOUT("Smartspeed has downgraded the link speed " 1000 "from the maximum advertised\n"); 1001 return status; 1002 } 1003 1004 /** 1005 * ixgbe_setup_mac_link_82599 - Set MAC link speed 1006 * @hw: pointer to hardware structure 1007 * @speed: new link speed 1008 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 1009 * 1010 * Set the link speed in the AUTOC register and restarts link. 1011 **/ 1012 int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 1013 ixgbe_link_speed speed, 1014 bool autoneg_wait_to_complete) 1015 { 1016 bool autoneg = FALSE; 1017 int32_t status = IXGBE_SUCCESS; 1018 uint32_t autoc, pma_pmd_1g, link_mode, start_autoc; 1019 uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1020 uint32_t orig_autoc = 0; 1021 uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1022 uint32_t links_reg; 1023 uint32_t i; 1024 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 1025 bool got_lock = FALSE; 1026 1027 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 1028 1029 /* Check to see if speed passed in is supported. */ 1030 status = ixgbe_get_link_capabilities_82599(hw, &link_capabilities, &autoneg); 1031 if (status) 1032 goto out; 1033 1034 speed &= link_capabilities; 1035 1036 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 1037 status = IXGBE_ERR_LINK_SETUP; 1038 goto out; 1039 } 1040 1041 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 1042 if (hw->mac.orig_link_settings_stored) 1043 autoc = hw->mac.orig_autoc; 1044 else 1045 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1046 1047 orig_autoc = autoc; 1048 start_autoc = hw->mac.cached_autoc; 1049 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 1050 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1051 1052 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 1053 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 1054 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 1055 /* Set KX4/KX/KR support according to speed requested */ 1056 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 1057 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1058 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 1059 autoc |= IXGBE_AUTOC_KX4_SUPP; 1060 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 1061 (hw->phy.smart_speed_active == FALSE)) 1062 autoc |= IXGBE_AUTOC_KR_SUPP; 1063 } 1064 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1065 autoc |= IXGBE_AUTOC_KX_SUPP; 1066 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 1067 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 1068 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 1069 /* Switch from 1G SFI to 10G SFI if requested */ 1070 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 1071 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 1072 autoc &= ~IXGBE_AUTOC_LMS_MASK; 1073 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 1074 } 1075 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 1076 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 1077 /* Switch from 10G SFI to 1G SFI if requested */ 1078 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 1079 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 1080 autoc &= ~IXGBE_AUTOC_LMS_MASK; 1081 if (autoneg) 1082 autoc |= IXGBE_AUTOC_LMS_1G_AN; 1083 else 1084 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 1085 } 1086 } 1087 1088 if (autoc != start_autoc) { 1089 /* Need SW/FW semaphore around AUTOC writes if LESM is on, 1090 * likewise reset_pipeline requires us to hold this lock as 1091 * it also writes to AUTOC. 1092 */ 1093 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 1094 status = hw->mac.ops.acquire_swfw_sync(hw, 1095 IXGBE_GSSR_MAC_CSR_SM); 1096 if (status != IXGBE_SUCCESS) { 1097 status = IXGBE_ERR_SWFW_SYNC; 1098 goto out; 1099 } 1100 1101 got_lock = TRUE; 1102 } 1103 1104 /* Restart link */ 1105 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 1106 hw->mac.cached_autoc = autoc; 1107 ixgbe_reset_pipeline_82599(hw); 1108 1109 if (got_lock) { 1110 hw->mac.ops.release_swfw_sync(hw, 1111 IXGBE_GSSR_MAC_CSR_SM); 1112 got_lock = FALSE; 1113 } 1114 1115 /* Only poll for autoneg to complete if specified to do so */ 1116 if (autoneg_wait_to_complete) { 1117 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 1118 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 1119 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 1120 links_reg = 0; /*Just in case Autoneg time=0*/ 1121 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 1122 links_reg = 1123 IXGBE_READ_REG(hw, IXGBE_LINKS); 1124 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 1125 break; 1126 msec_delay(100); 1127 } 1128 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 1129 status = 1130 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 1131 DEBUGOUT("Autoneg did not complete.\n"); 1132 } 1133 } 1134 } 1135 1136 /* Add delay to filter out noises during initial link setup */ 1137 msec_delay(50); 1138 } 1139 1140 out: 1141 return status; 1142 } 1143 1144 /** 1145 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 1146 * @hw: pointer to hardware structure 1147 * @speed: new link speed 1148 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 1149 * 1150 * Restarts link on PHY and MAC based on settings passed in. 1151 **/ 1152 int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 1153 ixgbe_link_speed speed, 1154 bool autoneg_wait_to_complete) 1155 { 1156 int32_t status; 1157 1158 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 1159 1160 /* Setup the PHY according to input speed */ 1161 status = hw->phy.ops.setup_link_speed(hw, speed, 1162 autoneg_wait_to_complete); 1163 /* Set up MAC */ 1164 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 1165 1166 return status; 1167 } 1168 1169 /** 1170 * ixgbe_reset_hw_82599 - Perform hardware reset 1171 * @hw: pointer to hardware structure 1172 * 1173 * Resets the hardware by resetting the transmit and receive units, masks 1174 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1175 * reset. 1176 **/ 1177 int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 1178 { 1179 ixgbe_link_speed link_speed; 1180 int32_t status; 1181 uint32_t ctrl, i, autoc2; 1182 uint32_t curr_lms; 1183 bool link_up = FALSE; 1184 1185 DEBUGFUNC("ixgbe_reset_hw_82599"); 1186 1187 /* Call adapter stop to disable tx/rx and clear interrupts */ 1188 status = hw->mac.ops.stop_adapter(hw); 1189 if (status != IXGBE_SUCCESS) 1190 goto reset_hw_out; 1191 1192 /* flush pending Tx transactions */ 1193 ixgbe_clear_tx_pending(hw); 1194 1195 /* PHY ops must be identified and initialized prior to reset */ 1196 1197 /* Identify PHY and related function pointers */ 1198 status = hw->phy.ops.init(hw); 1199 1200 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1201 goto reset_hw_out; 1202 1203 /* Setup SFP module if there is one present. */ 1204 if (hw->phy.sfp_setup_needed) { 1205 status = hw->mac.ops.setup_sfp(hw); 1206 hw->phy.sfp_setup_needed = FALSE; 1207 } 1208 1209 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1210 goto reset_hw_out; 1211 1212 /* Reset PHY */ 1213 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) 1214 hw->phy.ops.reset(hw); 1215 1216 /* remember AUTOC from before we reset */ 1217 if (hw->mac.cached_autoc) 1218 curr_lms = hw->mac.cached_autoc & IXGBE_AUTOC_LMS_MASK; 1219 else 1220 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & 1221 IXGBE_AUTOC_LMS_MASK; 1222 1223 mac_reset_top: 1224 /* 1225 * Issue global reset to the MAC. Needs to be SW reset if link is up. 1226 * If link reset is used when link is up, it might reset the PHY when 1227 * mng is using it. If link is down or the flag to force full link 1228 * reset is set, then perform link reset. 1229 */ 1230 ctrl = IXGBE_CTRL_LNK_RST; 1231 if (!hw->force_full_reset) { 1232 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 1233 if (link_up) 1234 ctrl = IXGBE_CTRL_RST; 1235 } 1236 1237 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1238 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1239 IXGBE_WRITE_FLUSH(hw); 1240 1241 /* Poll for reset bit to self-clear indicating reset is complete */ 1242 for (i = 0; i < 10; i++) { 1243 usec_delay(1); 1244 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1245 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1246 break; 1247 } 1248 1249 if (ctrl & IXGBE_CTRL_RST_MASK) { 1250 status = IXGBE_ERR_RESET_FAILED; 1251 DEBUGOUT("Reset polling failed to complete.\n"); 1252 } 1253 1254 msec_delay(50); 1255 1256 /* 1257 * Double resets are required for recovery from certain error 1258 * conditions. Between resets, it is necessary to stall to allow time 1259 * for any pending HW events to complete. 1260 */ 1261 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1262 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1263 goto mac_reset_top; 1264 } 1265 1266 /* 1267 * Store the original AUTOC/AUTOC2 values if they have not been 1268 * stored off yet. Otherwise restore the stored original 1269 * values since the reset operation sets back to defaults. 1270 */ 1271 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1272 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1273 1274 /* Enable link if disabled in NVM */ 1275 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1276 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1277 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1278 IXGBE_WRITE_FLUSH(hw); 1279 } 1280 1281 if (hw->mac.orig_link_settings_stored == FALSE) { 1282 hw->mac.orig_autoc = hw->mac.cached_autoc; 1283 hw->mac.orig_autoc2 = autoc2; 1284 hw->mac.orig_link_settings_stored = TRUE; 1285 } else { 1286 1287 /* If MNG FW is running on a multi-speed device that 1288 * doesn't autoneg with out driver support we need to 1289 * leave LMS in the state it was before we MAC reset. 1290 * Likewise if we support WoL we don't want change the 1291 * LMS state. 1292 */ 1293 if (hw->phy.multispeed_fiber && hw->mng_fw_enabled) 1294 hw->mac.orig_autoc = 1295 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1296 curr_lms; 1297 1298 if (hw->mac.cached_autoc != hw->mac.orig_autoc) { 1299 /* Need SW/FW semaphore around AUTOC writes if LESM is 1300 * on, likewise reset_pipeline requires us to hold 1301 * this lock as it also writes to AUTOC. 1302 */ 1303 bool got_lock = FALSE; 1304 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 1305 status = hw->mac.ops.acquire_swfw_sync(hw, 1306 IXGBE_GSSR_MAC_CSR_SM); 1307 if (status != IXGBE_SUCCESS) { 1308 status = IXGBE_ERR_SWFW_SYNC; 1309 goto reset_hw_out; 1310 } 1311 1312 got_lock = TRUE; 1313 } 1314 1315 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 1316 hw->mac.cached_autoc = hw->mac.orig_autoc; 1317 ixgbe_reset_pipeline_82599(hw); 1318 1319 if (got_lock) 1320 hw->mac.ops.release_swfw_sync(hw, 1321 IXGBE_GSSR_MAC_CSR_SM); 1322 } 1323 1324 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1325 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1326 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1327 autoc2 |= (hw->mac.orig_autoc2 & 1328 IXGBE_AUTOC2_UPPER_MASK); 1329 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1330 } 1331 } 1332 1333 /* Store the permanent mac address */ 1334 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1335 1336 /* 1337 * Store MAC address from RAR0, clear receive address registers, and 1338 * clear the multicast table. Also reset num_rar_entries to 128, 1339 * since we modify this value when programming the SAN MAC address. 1340 */ 1341 hw->mac.num_rar_entries = 128; 1342 hw->mac.ops.init_rx_addrs(hw); 1343 1344 reset_hw_out: 1345 return status; 1346 } 1347 1348 /** 1349 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1350 * @hw: pointer to hardware structure 1351 * @reg: analog register to read 1352 * @val: read value 1353 * 1354 * Performs read operation to Omer analog register specified. 1355 **/ 1356 int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 1357 uint8_t *val) 1358 { 1359 uint32_t core_ctl; 1360 1361 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 1362 1363 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1364 (reg << 8)); 1365 IXGBE_WRITE_FLUSH(hw); 1366 usec_delay(10); 1367 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1368 *val = (uint8_t)core_ctl; 1369 1370 return IXGBE_SUCCESS; 1371 } 1372 1373 /** 1374 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1375 * @hw: pointer to hardware structure 1376 * @reg: atlas register to write 1377 * @val: value to write 1378 * 1379 * Performs write operation to Omer analog register specified. 1380 **/ 1381 int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 1382 uint8_t val) 1383 { 1384 uint32_t core_ctl; 1385 1386 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 1387 1388 core_ctl = (reg << 8) | val; 1389 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1390 IXGBE_WRITE_FLUSH(hw); 1391 usec_delay(10); 1392 1393 return IXGBE_SUCCESS; 1394 } 1395 1396 /** 1397 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1398 * @hw: pointer to hardware structure 1399 * 1400 * Starts the hardware using the generic start_hw function 1401 * and the generation start_hw function. 1402 * Then performs revision-specific operations, if any. 1403 **/ 1404 int32_t ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1405 { 1406 int32_t ret_val = IXGBE_SUCCESS; 1407 1408 DEBUGFUNC("ixgbe_start_hw_82599"); 1409 1410 ret_val = ixgbe_start_hw_generic(hw); 1411 if (ret_val != IXGBE_SUCCESS) 1412 goto out; 1413 1414 ret_val = ixgbe_start_hw_gen2(hw); 1415 if (ret_val != IXGBE_SUCCESS) 1416 goto out; 1417 1418 /* We need to run link autotry after the driver loads */ 1419 hw->mac.autotry_restart = TRUE; 1420 1421 if (ret_val == IXGBE_SUCCESS) 1422 ret_val = ixgbe_verify_fw_version_82599(hw); 1423 out: 1424 return ret_val; 1425 } 1426 1427 /** 1428 * ixgbe_identify_phy_82599 - Get physical layer module 1429 * @hw: pointer to hardware structure 1430 * 1431 * Determines the physical layer module found on the current adapter. 1432 * If PHY already detected, maintains current PHY type in hw struct, 1433 * otherwise executes the PHY detection routine. 1434 **/ 1435 int32_t ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1436 { 1437 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 1438 1439 DEBUGFUNC("ixgbe_identify_phy_82599"); 1440 1441 /* Detect PHY if not unknown - returns success if already detected. */ 1442 status = ixgbe_identify_phy_generic(hw); 1443 if (status != IXGBE_SUCCESS) { 1444 /* 82599 10GBASE-T requires an external PHY */ 1445 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1446 goto out; 1447 else 1448 status = ixgbe_identify_module_generic(hw); 1449 } 1450 1451 /* Set PHY type none if no PHY detected */ 1452 if (hw->phy.type == ixgbe_phy_unknown) { 1453 hw->phy.type = ixgbe_phy_none; 1454 status = IXGBE_SUCCESS; 1455 } 1456 1457 /* Return error if SFP module has been detected but is not supported */ 1458 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1459 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1460 1461 out: 1462 return status; 1463 } 1464 1465 /** 1466 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1467 * @hw: pointer to hardware structure 1468 * 1469 * Determines physical layer capabilities of the current configuration. 1470 **/ 1471 uint32_t ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1472 { 1473 uint32_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1474 uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1475 uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1476 uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1477 uint32_t pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1478 uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1479 uint16_t ext_ability = 0; 1480 uint8_t comp_codes_10g = 0; 1481 uint8_t comp_codes_1g = 0; 1482 1483 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 1484 1485 hw->phy.ops.identify(hw); 1486 1487 switch (hw->phy.type) { 1488 case ixgbe_phy_tn: 1489 case ixgbe_phy_cu_unknown: 1490 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1491 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1492 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1493 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1494 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1495 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1496 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1497 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1498 goto out; 1499 default: 1500 break; 1501 } 1502 1503 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1504 case IXGBE_AUTOC_LMS_1G_AN: 1505 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1506 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1507 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1508 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1509 goto out; 1510 } else 1511 /* SFI mode so read SFP module */ 1512 goto sfp_check; 1513 break; 1514 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1515 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 1516 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1517 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 1518 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1519 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 1520 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 1521 goto out; 1522 break; 1523 case IXGBE_AUTOC_LMS_10G_SERIAL: 1524 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 1525 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1526 goto out; 1527 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 1528 goto sfp_check; 1529 break; 1530 case IXGBE_AUTOC_LMS_KX4_KX_KR: 1531 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 1532 if (autoc & IXGBE_AUTOC_KX_SUPP) 1533 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1534 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1535 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1536 if (autoc & IXGBE_AUTOC_KR_SUPP) 1537 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1538 goto out; 1539 break; 1540 default: 1541 goto out; 1542 break; 1543 } 1544 1545 sfp_check: 1546 /* SFP check must be done last since DA modules are sometimes used to 1547 * test KR mode - we need to id KR mode correctly before SFP module. 1548 * Call identify_sfp because the pluggable module may have changed */ 1549 hw->phy.ops.identify_sfp(hw); 1550 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1551 goto out; 1552 1553 switch (hw->phy.type) { 1554 case ixgbe_phy_sfp_passive_tyco: 1555 case ixgbe_phy_sfp_passive_unknown: 1556 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1557 break; 1558 case ixgbe_phy_sfp_ftl_active: 1559 case ixgbe_phy_sfp_active_unknown: 1560 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1561 break; 1562 case ixgbe_phy_sfp_avago: 1563 case ixgbe_phy_sfp_ftl: 1564 case ixgbe_phy_sfp_intel: 1565 case ixgbe_phy_sfp_unknown: 1566 hw->phy.ops.read_i2c_eeprom(hw, 1567 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1568 hw->phy.ops.read_i2c_eeprom(hw, 1569 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1570 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1571 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1572 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1573 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1574 else if (comp_codes_10g & 1575 (IXGBE_SFF_DA_PASSIVE_CABLE | IXGBE_SFF_DA_BAD_HP_CABLE)) 1576 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1577 else if (comp_codes_10g & IXGBE_SFF_DA_ACTIVE_CABLE) 1578 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1579 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1580 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1581 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1582 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 out: 1589 return physical_layer; 1590 } 1591 1592 /** 1593 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1594 * @hw: pointer to hardware structure 1595 * @regval: register value to write to RXCTRL 1596 * 1597 * Enables the Rx DMA unit for 82599 1598 **/ 1599 int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval) 1600 { 1601 1602 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 1603 1604 /* 1605 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1606 * If traffic is incoming before we enable the Rx unit, it could hang 1607 * the Rx DMA unit. Therefore, make sure the security engine is 1608 * completely disabled prior to enabling the Rx unit. 1609 */ 1610 1611 hw->mac.ops.disable_sec_rx_path(hw); 1612 1613 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 1614 1615 hw->mac.ops.enable_sec_rx_path(hw); 1616 1617 return IXGBE_SUCCESS; 1618 } 1619 1620 /** 1621 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1622 * @hw: pointer to hardware structure 1623 * 1624 * Verifies that installed the firmware version is 0.6 or higher 1625 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1626 * 1627 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 1628 * if the FW version is not supported. 1629 **/ 1630 int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1631 { 1632 int32_t status = IXGBE_ERR_EEPROM_VERSION; 1633 uint16_t fw_offset, fw_ptp_cfg_offset; 1634 uint16_t fw_version; 1635 1636 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 1637 1638 /* firmware check is only necessary for SFI devices */ 1639 if (hw->phy.media_type != ixgbe_media_type_fiber) { 1640 status = IXGBE_SUCCESS; 1641 goto fw_version_out; 1642 } 1643 1644 /* get the offset to the Firmware Module block */ 1645 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) { 1646 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1647 "eeprom read at offset %d failed", IXGBE_FW_PTR); 1648 return IXGBE_ERR_EEPROM_VERSION; 1649 } 1650 1651 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 1652 goto fw_version_out; 1653 1654 /* get the offset to the Pass Through Patch Configuration block */ 1655 if (hw->eeprom.ops.read(hw, (fw_offset + 1656 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 1657 &fw_ptp_cfg_offset)) { 1658 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1659 "eeprom read at offset %d failed", 1660 fw_offset + 1661 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR); 1662 return IXGBE_ERR_EEPROM_VERSION; 1663 } 1664 1665 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 1666 goto fw_version_out; 1667 1668 /* get the firmware version */ 1669 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 1670 IXGBE_FW_PATCH_VERSION_4), &fw_version)) { 1671 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1672 "eeprom read at offset %d failed", 1673 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4); 1674 return IXGBE_ERR_EEPROM_VERSION; 1675 } 1676 1677 if (fw_version > 0x5) 1678 status = IXGBE_SUCCESS; 1679 1680 fw_version_out: 1681 return status; 1682 } 1683 1684 /** 1685 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 1686 * @hw: pointer to hardware structure 1687 * 1688 * Returns TRUE if the LESM FW module is present and enabled. Otherwise 1689 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. 1690 **/ 1691 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 1692 { 1693 bool lesm_enabled = FALSE; 1694 uint16_t fw_offset, fw_lesm_param_offset, fw_lesm_state; 1695 int32_t status; 1696 1697 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 1698 1699 /* get the offset to the Firmware Module block */ 1700 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1701 1702 if ((status != IXGBE_SUCCESS) || 1703 (fw_offset == 0) || (fw_offset == 0xFFFF)) 1704 goto out; 1705 1706 /* get the offset to the LESM Parameters block */ 1707 status = hw->eeprom.ops.read(hw, (fw_offset + 1708 IXGBE_FW_LESM_PARAMETERS_PTR), 1709 &fw_lesm_param_offset); 1710 1711 if ((status != IXGBE_SUCCESS) || 1712 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 1713 goto out; 1714 1715 /* get the lesm state word */ 1716 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 1717 IXGBE_FW_LESM_STATE_1), 1718 &fw_lesm_state); 1719 1720 if ((status == IXGBE_SUCCESS) && 1721 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 1722 lesm_enabled = TRUE; 1723 1724 out: 1725 return lesm_enabled; 1726 } 1727 1728 /** 1729 * ixgbe_read_eeprom_82599 - Read EEPROM word using 1730 * fastest available method 1731 * 1732 * @hw: pointer to hardware structure 1733 * @offset: offset of word in the EEPROM to read 1734 * @data: word read from the EEPROM 1735 * 1736 * Reads a 16 bit word from the EEPROM 1737 **/ 1738 int32_t ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 1739 uint16_t offset, uint16_t *data) 1740 { 1741 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1742 int32_t ret_val = IXGBE_ERR_CONFIG; 1743 1744 DEBUGFUNC("ixgbe_read_eeprom_82599"); 1745 1746 /* 1747 * If EEPROM is detected and can be addressed using 14 bits, 1748 * use EERD otherwise use bit bang 1749 */ 1750 if ((eeprom->type == ixgbe_eeprom_spi) && 1751 (offset <= IXGBE_EERD_MAX_ADDR)) 1752 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 1753 else 1754 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 1755 1756 return ret_val; 1757 } 1758 1759 /** 1760 * ixgbe_reset_pipeline_82599 - perform pipeline reset 1761 * 1762 * @hw: pointer to hardware structure 1763 * 1764 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 1765 * full pipeline reset 1766 **/ 1767 int32_t ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 1768 { 1769 int32_t ret_val; 1770 uint32_t anlp1_reg = 0; 1771 uint32_t i, autoc_reg, autoc2_reg; 1772 1773 /* Enable link if disabled in NVM */ 1774 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1775 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1776 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1777 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 1778 IXGBE_WRITE_FLUSH(hw); 1779 } 1780 1781 autoc_reg = hw->mac.cached_autoc; 1782 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 1783 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 1784 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN); 1785 /* Wait for AN to leave state 0 */ 1786 for (i = 0; i < 10; i++) { 1787 msec_delay(4); 1788 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 1789 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 1790 break; 1791 } 1792 1793 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 1794 DEBUGOUT("auto negotiation not completed\n"); 1795 ret_val = IXGBE_ERR_RESET_FAILED; 1796 goto reset_pipeline_out; 1797 } 1798 1799 ret_val = IXGBE_SUCCESS; 1800 1801 reset_pipeline_out: 1802 /* Write AUTOC register with original LMS field and Restart_AN */ 1803 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 1804 IXGBE_WRITE_FLUSH(hw); 1805 1806 return ret_val; 1807 } 1808