1 /* $OpenBSD: mpiireg.h,v 1.3 2012/09/28 12:46:41 mikeb Exp $ */ 2 /* 3 * Copyright (c) 2010 Mike Belopuhov 4 * Copyright (c) 2009 James Giannoules 5 * Copyright (c) 2005 - 2010 David Gwynne <dlg@openbsd.org> 6 * Copyright (c) 2005 - 2010 Marco Peereboom <marco@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define MPII_DOORBELL (0x00) 22 /* doorbell read bits */ 23 #define MPII_DOORBELL_STATE (0xf<<28) /* ioc state */ 24 #define MPII_DOORBELL_STATE_RESET (0x0<<28) 25 #define MPII_DOORBELL_STATE_READY (0x1<<28) 26 #define MPII_DOORBELL_STATE_OPER (0x2<<28) 27 #define MPII_DOORBELL_STATE_FAULT (0x4<<28) 28 #define MPII_DOORBELL_INUSE (0x1<<27) /* doorbell used */ 29 #define MPII_DOORBELL_WHOINIT (0x7<<24) /* last to reset ioc */ 30 #define MPII_DOORBELL_WHOINIT_NOONE (0x0<<24) /* not initialized */ 31 #define MPII_DOORBELL_WHOINIT_SYSBIOS (0x1<<24) /* system bios */ 32 #define MPII_DOORBELL_WHOINIT_ROMBIOS (0x2<<24) /* rom bios */ 33 #define MPII_DOORBELL_WHOINIT_PCIPEER (0x3<<24) /* pci peer */ 34 #define MPII_DOORBELL_WHOINIT_DRIVER (0x4<<24) /* host driver */ 35 #define MPII_DOORBELL_WHOINIT_MANUFACT (0x5<<24) /* manufacturing */ 36 #define MPII_DOORBELL_FAULT (0xffff<<0) /* fault code */ 37 /* doorbell write bits */ 38 #define MPII_DOORBELL_FUNCTION_SHIFT (24) 39 #define MPII_DOORBELL_FUNCTION_MASK (0xff << MPII_DOORBELL_FUNCTION_SHIFT) 40 #define MPII_DOORBELL_FUNCTION(x) \ 41 (((x) << MPII_DOORBELL_FUNCTION_SHIFT) & MPII_DOORBELL_FUNCTION_MASK) 42 #define MPII_DOORBELL_DWORDS_SHIFT 16 43 #define MPII_DOORBELL_DWORDS_MASK (0xff << MPII_DOORBELL_DWORDS_SHIFT) 44 #define MPII_DOORBELL_DWORDS(x) \ 45 (((x) << MPII_DOORBELL_DWORDS_SHIFT) & MPII_DOORBELL_DWORDS_MASK) 46 #define MPII_DOORBELL_DATA_MASK (0xffff) 47 48 #define MPII_WRITESEQ (0x04) 49 #define MPII_WRITESEQ_KEY_VALUE_MASK (0x0000000f) /* key value */ 50 #define MPII_WRITESEQ_FLUSH (0x00) 51 #define MPII_WRITESEQ_1 (0x0f) 52 #define MPII_WRITESEQ_2 (0x04) 53 #define MPII_WRITESEQ_3 (0x0b) 54 #define MPII_WRITESEQ_4 (0x02) 55 #define MPII_WRITESEQ_5 (0x07) 56 #define MPII_WRITESEQ_6 (0x0d) 57 58 #define MPII_HOSTDIAG (0x08) 59 #define MPII_HOSTDIAG_BDS_MASK (0x00001800) /* boot device select */ 60 #define MPII_HOSTDIAG_BDS_DEFAULT (0<<11) /* default address map, flash */ 61 #define MPII_HOSTDIAG_BDS_HCDW (1<<11) /* host code and data window */ 62 #define MPII_HOSTDIAG_CLEARFBS (1<<10) /* clear flash bad sig */ 63 #define MPII_HOSTDIAG_FORCE_HCB_ONBOOT (1<<9) /* force host controlled boot */ 64 #define MPII_HOSTDIAG_HCB_MODE (1<<8) /* host controlled boot mode */ 65 #define MPII_HOSTDIAG_DWRE (1<<7) /* diag reg write enabled */ 66 #define MPII_HOSTDIAG_FBS (1<<6) /* flash bad sig */ 67 #define MPII_HOSTDIAG_RESET_HIST (1<<5) /* reset history */ 68 #define MPII_HOSTDIAG_DIAGWR_EN (1<<4) /* diagnostic write enabled */ 69 #define MPII_HOSTDIAG_RESET_ADAPTER (1<<2) /* reset adapter */ 70 #define MPII_HOSTDIAG_HOLD_IOC_RESET (1<<1) /* hold ioc in reset */ 71 #define MPII_HOSTDIAG_DIAGMEM_EN (1<<0) /* diag mem enable */ 72 73 #define MPII_DIAGRWDATA (0x10) 74 75 #define MPII_DIAGRWADDRLOW (0x14) 76 77 #define MPII_DIAGRWADDRHIGH (0x18) 78 79 #define MPII_INTR_STATUS (0x30) 80 #define MPII_INTR_STATUS_SYS2IOCDB (1<<31) /* ioc written to by host */ 81 #define MPII_INTR_STATUS_RESET (1<<30) /* physical ioc reset */ 82 #define MPII_INTR_STATUS_REPLY (1<<3) /* reply message interrupt */ 83 #define MPII_INTR_STATUS_IOC2SYSDB (1<<0) /* ioc write to doorbell */ 84 85 #define MPII_INTR_MASK (0x34) 86 #define MPII_INTR_MASK_RESET (1<<30) /* ioc reset intr mask */ 87 #define MPII_INTR_MASK_REPLY (1<<3) /* reply message intr mask */ 88 #define MPII_INTR_MASK_DOORBELL (1<<0) /* doorbell interrupt mask */ 89 90 #define MPII_DCR_DATA (0x38) 91 92 #define MPII_DCR_ADDRESS (0x3c) 93 94 #define MPII_REPLY_FREE_HOST_INDEX (0x48) 95 96 #define MPII_REPLY_POST_HOST_INDEX (0x6c) 97 98 #define MPII_HCB_SIZE (0x74) 99 100 #define MPII_HCB_ADDRESS_LOW (0x78) 101 #define MPII_HCB_ADDRESS_HIGH (0x7c) 102 103 #define MPII_REQ_DESCR_POST_LOW (0xc0) 104 #define MPII_REQ_DESCR_POST_HIGH (0xc4) 105 106 /* 107 * Scatter Gather Lists 108 */ 109 110 #define MPII_SGE_FL_LAST (0x1<<31) /* last element in segment */ 111 #define MPII_SGE_FL_EOB (0x1<<30) /* last element of buffer */ 112 #define MPII_SGE_FL_TYPE (0x3<<28) /* element type */ 113 #define MPII_SGE_FL_TYPE_SIMPLE (0x1<<28) /* simple element */ 114 #define MPII_SGE_FL_TYPE_CHAIN (0x3<<28) /* chain element */ 115 #define MPII_SGE_FL_TYPE_XACTCTX (0x0<<28) /* transaction context */ 116 #define MPII_SGE_FL_LOCAL (0x1<<27) /* local address */ 117 #define MPII_SGE_FL_DIR (0x1<<26) /* direction */ 118 #define MPII_SGE_FL_DIR_OUT (0x1<<26) 119 #define MPII_SGE_FL_DIR_IN (0x0<<26) 120 #define MPII_SGE_FL_SIZE (0x1<<25) /* address size */ 121 #define MPII_SGE_FL_SIZE_32 (0x0<<25) 122 #define MPII_SGE_FL_SIZE_64 (0x1<<25) 123 #define MPII_SGE_FL_EOL (0x1<<24) /* end of list */ 124 125 struct mpii_sge { 126 u_int32_t sg_hdr; 127 u_int32_t sg_lo_addr; 128 u_int32_t sg_hi_addr; 129 } __packed; 130 131 struct mpii_fw_tce { 132 u_int8_t reserved1; 133 u_int8_t context_size; 134 u_int8_t details_length; 135 u_int8_t flags; 136 137 u_int32_t reserved2; 138 139 u_int32_t image_offset; 140 141 u_int32_t image_size; 142 } __packed; 143 144 /* 145 * Messages 146 */ 147 148 /* functions */ 149 #define MPII_FUNCTION_SCSI_IO_REQUEST (0x00) 150 #define MPII_FUNCTION_SCSI_TASK_MGMT (0x01) 151 #define MPII_FUNCTION_IOC_INIT (0x02) 152 #define MPII_FUNCTION_IOC_FACTS (0x03) 153 #define MPII_FUNCTION_CONFIG (0x04) 154 #define MPII_FUNCTION_PORT_FACTS (0x05) 155 #define MPII_FUNCTION_PORT_ENABLE (0x06) 156 #define MPII_FUNCTION_EVENT_NOTIFICATION (0x07) 157 #define MPII_FUNCTION_EVENT_ACK (0x08) 158 #define MPII_FUNCTION_FW_DOWNLOAD (0x09) 159 #define MPII_FUNCTION_TARGET_CMD_BUFFER_POST (0x0a) 160 #define MPII_FUNCTION_TARGET_ASSIST (0x0b) 161 #define MPII_FUNCTION_TARGET_STATUS_SEND (0x0c) 162 #define MPII_FUNCTION_TARGET_MODE_ABORT (0x0d) 163 #define MPII_FUNCTION_FW_UPLOAD (0x12) 164 165 #define MPII_FUNCTION_RAID_ACTION (0x15) 166 #define MPII_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 167 168 #define MPII_FUNCTION_TOOLBOX (0x17) 169 170 #define MPII_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 171 172 #define MPII_FUNCTION_SMP_PASSTHROUGH (0x1a) 173 #define MPII_FUNCTION_SAS_IO_UNIT_CONTROL (0x1b) 174 #define MPII_FUNCTION_SATA_PASSTHROUGH (0x1c) 175 176 #define MPII_FUNCTION_DIAG_BUFFER_POST (0x1d) 177 #define MPII_FUNCTION_DIAG_RELEASE (0x1e) 178 179 #define MPII_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 180 #define MPII_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 181 182 #define MPII_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 183 #define MPII_FUNCTION_IO_UNIT_RESET (0x41) 184 #define MPII_FUNCTION_HANDSHAKE (0x42) 185 186 /* Common IOCStatus values for all replies */ 187 #define MPII_IOCSTATUS_MASK (0x7fff) 188 #define MPII_IOCSTATUS_SUCCESS (0x0000) 189 #define MPII_IOCSTATUS_INVALID_FUNCTION (0x0001) 190 #define MPII_IOCSTATUS_BUSY (0x0002) 191 #define MPII_IOCSTATUS_INVALID_SGL (0x0003) 192 #define MPII_IOCSTATUS_INTERNAL_ERROR (0x0004) 193 #define MPII_IOCSTATUS_INVALID_VPID (0x0005) 194 #define MPII_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 195 #define MPII_IOCSTATUS_INVALID_FIELD (0x0007) 196 #define MPII_IOCSTATUS_INVALID_STATE (0x0008) 197 #define MPII_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 198 /* Config IOCStatus values */ 199 #define MPII_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 200 #define MPII_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 201 #define MPII_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 202 #define MPII_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 203 #define MPII_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 204 #define MPII_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 205 /* SCSIIO Reply initiator values */ 206 #define MPII_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 207 #define MPII_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 208 #define MPII_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 209 #define MPII_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 210 #define MPII_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 211 #define MPII_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 212 #define MPII_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 213 #define MPII_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 214 #define MPII_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 215 #define MPII_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004a) 216 #define MPII_IOCSTATUS_SCSI_IOC_TERMINATED (0x004b) 217 #define MPII_IOCSTATUS_SCSI_EXT_TERMINATED (0x004c) 218 /* For use by SCSI Initiator and SCSI Target end-to-end data protection */ 219 #define MPII_IOCSTATUS_EEDP_GUARD_ERROR (0x004d) 220 #define MPII_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004e) 221 #define MPII_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004f) 222 /* SCSI (SPI & FCP) target values */ 223 #define MPII_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 224 #define MPII_IOCSTATUS_TARGET_ABORTED (0x0063) 225 #define MPII_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 226 #define MPII_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 227 #define MPII_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006a) 228 #define MPII_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006d) 229 #define MPII_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006e) 230 #define MPII_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006f) 231 #define MPII_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 232 #define MPII_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 233 /* Serial Attached SCSI values */ 234 #define MPII_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 235 #define MPII_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 236 /* Diagnostic Tools values */ 237 #define MPII_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00a0) 238 239 #define MPII_REP_IOCLOGINFO_TYPE (0xf<<28) 240 #define MPII_REP_IOCLOGINFO_TYPE_NONE (0x0<<28) 241 #define MPII_REP_IOCLOGINFO_TYPE_SCSI (0x1<<28) 242 #define MPII_REP_IOCLOGINFO_TYPE_FC (0x2<<28) 243 #define MPII_REP_IOCLOGINFO_TYPE_SAS (0x3<<28) 244 #define MPII_REP_IOCLOGINFO_TYPE_ISCSI (0x4<<28) 245 #define MPII_REP_IOCLOGINFO_DATA (0x0fffffff) 246 247 /* event notification types */ 248 #define MPII_EVENT_NONE (0x00) 249 #define MPII_EVENT_LOG_DATA (0x01) 250 #define MPII_EVENT_STATE_CHANGE (0x02) 251 #define MPII_EVENT_HARD_RESET_RECEIVED (0x05) 252 #define MPII_EVENT_EVENT_CHANGE (0x0a) 253 #define MPII_EVENT_TASK_SET_FULL (0x0e) 254 #define MPII_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0f) 255 #define MPII_EVENT_IR_OPERATION_STATUS (0x14) 256 #define MPII_EVENT_SAS_DISCOVERY (0x16) 257 #define MPII_EVENT_SAS_BROADCAST_PRIMITIVE (0x17) 258 #define MPII_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x18) 259 #define MPII_EVENT_SAS_INIT_TABLE_OVERFLOW (0x19) 260 #define MPII_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x1c) 261 #define MPII_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x1d) 262 #define MPII_EVENT_IR_VOLUME (0x1e) 263 #define MPII_EVENT_IR_PHYSICAL_DISK (0x1f) 264 #define MPII_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x20) 265 #define MPII_EVENT_LOG_ENTRY_ADDED (0x21) 266 267 /* messages */ 268 269 #define MPII_WHOINIT_NOONE (0x00) 270 #define MPII_WHOINIT_SYSTEM_BIOS (0x01) 271 #define MPII_WHOINIT_ROM_BIOS (0x02) 272 #define MPII_WHOINIT_PCI_PEER (0x03) 273 #define MPII_WHOINIT_HOST_DRIVER (0x04) 274 #define MPII_WHOINIT_MANUFACTURER (0x05) 275 276 /* default messages */ 277 278 struct mpii_msg_request { 279 u_int8_t reserved1; 280 u_int8_t reserved2; 281 u_int8_t chain_offset; 282 u_int8_t function; 283 284 u_int8_t reserved3; 285 u_int8_t reserved4; 286 u_int8_t reserved5; 287 u_int8_t msg_flags; 288 289 u_int8_t vp_id; 290 u_int8_t vf_id; 291 u_int16_t reserved6; 292 } __packed; 293 294 struct mpii_msg_reply { 295 u_int16_t reserved1; 296 u_int8_t msg_length; 297 u_int8_t function; 298 299 u_int16_t reserved2; 300 u_int8_t reserved3; 301 u_int8_t msg_flags; 302 303 u_int8_t vp_id; 304 u_int8_t vf_if; 305 u_int16_t reserved4; 306 307 u_int16_t reserved5; 308 u_int16_t ioc_status; 309 310 u_int32_t ioc_loginfo; 311 } __packed; 312 313 /* ioc init */ 314 315 struct mpii_msg_iocinit_request { 316 u_int8_t whoinit; 317 u_int8_t reserved1; 318 u_int8_t chain_offset; 319 u_int8_t function; 320 321 u_int16_t reserved2; 322 u_int8_t reserved3; 323 u_int8_t msg_flags; 324 325 u_int8_t vp_id; 326 u_int8_t vf_id; 327 u_int16_t reserved4; 328 329 u_int8_t msg_version_min; 330 u_int8_t msg_version_maj; 331 u_int8_t hdr_version_unit; 332 u_int8_t hdr_version_dev; 333 334 u_int32_t reserved5; 335 336 u_int32_t reserved6; 337 338 u_int16_t reserved7; 339 u_int16_t system_request_frame_size; 340 341 u_int16_t reply_descriptor_post_queue_depth; 342 u_int16_t reply_free_queue_depth; 343 344 u_int32_t sense_buffer_address_high; 345 346 u_int32_t system_reply_address_high; 347 348 u_int64_t system_request_frame_base_address; 349 350 u_int64_t reply_descriptor_post_queue_address; 351 352 u_int64_t reply_free_queue_address; 353 354 u_int64_t timestamp; 355 } __packed; 356 357 struct mpii_msg_iocinit_reply { 358 u_int8_t whoinit; 359 u_int8_t reserved1; 360 u_int8_t msg_length; 361 u_int8_t function; 362 363 u_int16_t reserved2; 364 u_int8_t reserved3; 365 u_int8_t msg_flags; 366 367 u_int8_t vp_id; 368 u_int8_t vf_id; 369 u_int16_t reserved4; 370 371 u_int16_t reserved5; 372 u_int16_t ioc_status; 373 374 u_int32_t ioc_loginfo; 375 } __packed; 376 377 struct mpii_msg_iocfacts_request { 378 u_int16_t reserved1; 379 u_int8_t chain_offset; 380 u_int8_t function; 381 382 u_int16_t reserved2; 383 u_int8_t reserved3; 384 u_int8_t msg_flags; 385 386 u_int8_t vp_id; 387 u_int8_t vf_id; 388 u_int16_t reserved4; 389 } __packed; 390 391 struct mpii_msg_iocfacts_reply { 392 u_int8_t msg_version_min; 393 u_int8_t msg_version_maj; 394 u_int8_t msg_length; 395 u_int8_t function; 396 397 u_int8_t header_version_dev; 398 u_int8_t header_version_unit; 399 u_int8_t ioc_number; 400 u_int8_t msg_flags; 401 402 u_int8_t vp_id; 403 u_int8_t vf_id; 404 u_int16_t reserved1; 405 406 u_int16_t ioc_exceptions; 407 #define MPII_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (1<<0) 408 #define MPII_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (1<<1) 409 #define MPII_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (1<<2) 410 #define MPII_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (1<<3) 411 #define MPII_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (1<<4) 412 #define MPII_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAC (1<<8) 413 /* XXX JPG BOOT_STATUS in bits[7:5] */ 414 /* XXX JPG all these #defines need to be fixed up */ 415 u_int16_t ioc_status; 416 417 u_int32_t ioc_loginfo; 418 419 u_int8_t max_chain_depth; 420 u_int8_t whoinit; 421 u_int8_t number_of_ports; 422 u_int8_t reserved2; 423 424 u_int16_t request_credit; 425 u_int16_t product_id; 426 427 u_int32_t ioc_capabilities; 428 #define MPII_IOCFACTS_CAPABILITY_EVENT_REPLAY (1<<13) 429 #define MPII_IOCFACTS_CAPABILITY_INTEGRATED_RAID (1<<12) 430 #define MPII_IOCFACTS_CAPABILITY_TLR (1<<11) 431 #define MPII_IOCFACTS_CAPABILITY_MULTICAST (1<<8) 432 #define MPII_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (1<<7) 433 #define MPII_IOCFACTS_CAPABILITY_EEDP (1<<6) 434 #define MPII_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (1<<4) 435 #define MPII_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (1<<3) 436 #define MPII_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (1<<2) 437 438 u_int8_t fw_version_dev; 439 u_int8_t fw_version_unit; 440 u_int8_t fw_version_min; 441 u_int8_t fw_version_maj; 442 443 u_int16_t ioc_request_frame_size; 444 u_int16_t reserved3; 445 446 u_int16_t max_initiators; 447 u_int16_t max_targets; 448 449 u_int16_t max_sas_expanders; 450 u_int16_t max_enclosures; 451 452 u_int16_t protocol_flags; 453 u_int16_t high_priority_credit; 454 455 u_int16_t max_reply_descriptor_post_queue_depth; 456 u_int8_t reply_frame_size; 457 u_int8_t max_volumes; 458 459 u_int16_t max_dev_handle; 460 u_int16_t max_persistent_entries; 461 462 u_int32_t reserved4; 463 } __packed; 464 465 struct mpii_msg_portfacts_request { 466 u_int16_t reserved1; 467 u_int8_t chain_offset; 468 u_int8_t function; 469 470 u_int16_t reserved2; 471 u_int8_t port_number; 472 u_int8_t msg_flags; 473 474 u_int8_t vp_id; 475 u_int8_t vf_id; 476 u_int16_t reserved3; 477 } __packed; 478 479 struct mpii_msg_portfacts_reply { 480 u_int16_t reserved1; 481 u_int8_t msg_length; 482 u_int8_t function; 483 484 u_int16_t reserved2; 485 u_int8_t port_number; 486 u_int8_t msg_flags; 487 488 u_int8_t vp_id; 489 u_int8_t vf_id; 490 u_int16_t reserved3; 491 492 u_int16_t reserved4; 493 u_int16_t ioc_status; 494 495 u_int32_t ioc_loginfo; 496 497 u_int8_t reserved5; 498 u_int8_t port_type; 499 #define MPII_PORTFACTS_PORTTYPE_INACTIVE (0x00) 500 #define MPII_PORTFACTS_PORTTYPE_FC (0x10) 501 #define MPII_PORTFACTS_PORTTYPE_ISCSI (0x20) 502 #define MPII_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 503 #define MPII_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 504 u_int16_t reserved6; 505 506 u_int16_t max_posted_cmd_buffers; 507 u_int16_t reserved7; 508 } __packed; 509 510 struct mpii_msg_portenable_request { 511 u_int16_t reserved1; 512 u_int8_t chain_offset; 513 u_int8_t function; 514 515 u_int8_t reserved2; 516 u_int8_t port_flags; 517 u_int8_t reserved3; 518 u_int8_t msg_flags; 519 520 u_int8_t vp_id; 521 u_int8_t vf_id; 522 u_int16_t reserved4; 523 } __packed; 524 525 struct mpii_msg_portenable_reply { 526 u_int16_t reserved1; 527 u_int8_t msg_length; 528 u_int8_t function; 529 530 u_int8_t reserved2; 531 u_int8_t port_flags; 532 u_int8_t reserved3; 533 u_int8_t msg_flags; 534 535 u_int8_t vp_id; 536 u_int8_t vf_id; 537 u_int16_t reserved4; 538 539 u_int16_t reserved5; 540 u_int16_t ioc_status; 541 542 u_int32_t ioc_loginfo; 543 } __packed; 544 545 struct mpii_msg_event_request { 546 u_int16_t reserved1; 547 u_int8_t chain_offset; 548 u_int8_t function; 549 550 u_int16_t reserved2; 551 u_int8_t reserved3; 552 u_int8_t msg_flags; 553 554 u_int8_t vp_id; 555 u_int8_t vf_id; 556 u_int16_t reserved4; 557 558 u_int32_t reserved5; 559 560 u_int32_t reserved6; 561 562 u_int32_t event_masks[4]; 563 564 u_int16_t sas_broadcase_primitive_masks; 565 u_int16_t reserved7; 566 567 u_int32_t reserved8; 568 } __packed; 569 570 struct mpii_msg_event_reply { 571 u_int16_t event_data_length; 572 u_int8_t msg_length; 573 u_int8_t function; 574 575 u_int16_t reserved1; 576 u_int8_t ack_required; 577 #define MPII_EVENT_ACK_REQUIRED (0x01) 578 u_int8_t msg_flags; 579 #define MPII_EVENT_FLAGS_REPLY_KEPT (1<<7) 580 581 u_int8_t vp_id; 582 u_int8_t vf_id; 583 u_int16_t reserved2; 584 585 u_int16_t reserved3; 586 u_int16_t ioc_status; 587 588 u_int32_t ioc_loginfo; 589 590 u_int16_t event; 591 u_int16_t reserved4; 592 593 u_int32_t event_context; 594 595 /* event data follows */ 596 } __packed; 597 598 struct mpii_msg_eventack_request { 599 u_int16_t reserved1; 600 u_int8_t chain_offset; 601 u_int8_t function; 602 603 u_int8_t reserved2[3]; 604 u_int8_t msg_flags; 605 606 u_int8_t vp_id; 607 u_int8_t vf_id; 608 u_int16_t reserved3; 609 610 u_int16_t event; 611 u_int16_t reserved4; 612 613 u_int32_t event_context; 614 } __packed; 615 616 struct mpii_msg_eventack_reply { 617 u_int16_t reserved1; 618 u_int8_t msg_length; 619 u_int8_t function; 620 621 u_int8_t reserved2[3]; 622 u_int8_t msg_flags; 623 624 u_int8_t vp_id; 625 u_int8_t vf_id; 626 u_int16_t reserved3; 627 628 u_int16_t reserved4; 629 u_int16_t ioc_status; 630 631 u_int32_t ioc_loginfo; 632 } __packed; 633 634 struct mpii_msg_fwupload_request { 635 u_int8_t image_type; 636 #define MPII_FWUPLOAD_IMAGETYPE_IOC_FW (0x00) 637 #define MPII_FWUPLOAD_IMAGETYPE_NV_FW (0x01) 638 #define MPII_FWUPLOAD_IMAGETYPE_NV_BACKUP (0x05) 639 #define MPII_FWUPLOAD_IMAGETYPE_NV_MANUFACTURING (0x06) 640 #define MPII_FWUPLOAD_IMAGETYPE_NV_CONFIG_1 (0x07) 641 #define MPII_FWUPLOAD_IMAGETYPE_NV_CONFIG_2 (0x08) 642 #define MPII_FWUPLOAD_IMAGETYPE_NV_MEGARAID (0x09) 643 #define MPII_FWUPLOAD_IMAGETYPE_NV_COMPLETE (0x0a) 644 #define MPII_FWUPLOAD_IMAGETYPE_COMMON_BOOT_BLOCK (0x0b) 645 u_int8_t reserved1; 646 u_int8_t chain_offset; 647 u_int8_t function; 648 649 u_int8_t reserved2[3]; 650 u_int8_t msg_flags; 651 652 u_int8_t vp_id; 653 u_int8_t vf_id; 654 u_int16_t reserved3; 655 656 u_int32_t reserved4; 657 658 u_int32_t reserved5; 659 660 struct mpii_fw_tce tce; 661 662 /* followed by an sgl */ 663 } __packed; 664 665 struct mpii_msg_fwupload_reply { 666 u_int8_t image_type; 667 u_int8_t reserved1; 668 u_int8_t msg_length; 669 u_int8_t function; 670 671 u_int8_t reserved2[3]; 672 u_int8_t msg_flags; 673 674 u_int8_t vp_id; 675 u_int8_t vf_id; 676 u_int16_t reserved3; 677 678 u_int16_t reserved4; 679 u_int16_t ioc_status; 680 681 u_int32_t ioc_loginfo; 682 683 u_int32_t actual_image_size; 684 } __packed; 685 686 struct mpii_msg_scsi_io { 687 u_int16_t dev_handle; 688 u_int8_t chain_offset; 689 u_int8_t function; 690 691 u_int16_t reserved1; 692 u_int8_t reserved2; 693 u_int8_t msg_flags; 694 695 u_int8_t vp_id; 696 u_int8_t vf_id; 697 u_int16_t reserved3; 698 699 u_int32_t sense_buffer_low_address; 700 701 u_int16_t sgl_flags; 702 u_int8_t sense_buffer_length; 703 u_int8_t reserved4; 704 705 u_int8_t sgl_offset0; 706 u_int8_t sgl_offset1; 707 u_int8_t sgl_offset2; 708 u_int8_t sgl_offset3; 709 710 u_int32_t skip_count; 711 712 u_int32_t data_length; 713 714 u_int32_t bidirectional_data_length; 715 716 u_int16_t io_flags; 717 u_int16_t eedp_flags; 718 719 u_int32_t eedp_block_size; 720 721 u_int32_t secondary_reference_tag; 722 723 u_int16_t secondary_application_tag; 724 u_int16_t application_tag_translation_mask; 725 726 u_int16_t lun[4]; 727 728 /* the following 16 bits are defined in MPI2 as the control field */ 729 u_int8_t reserved5; 730 u_int8_t tagging; 731 #define MPII_SCSIIO_ATTR_SIMPLE_Q (0x0) 732 #define MPII_SCSIIO_ATTR_HEAD_OF_Q (0x1) 733 #define MPII_SCSIIO_ATTR_ORDERED_Q (0x2) 734 #define MPII_SCSIIO_ATTR_ACA_Q (0x4) 735 #define MPII_SCSIIO_ATTR_UNTAGGED (0x5) 736 #define MPII_SCSIIO_ATTR_NO_DISCONNECT (0x7) 737 u_int8_t reserved6; 738 u_int8_t direction; 739 #define MPII_SCSIIO_DIR_NONE (0x0) 740 #define MPII_SCSIIO_DIR_WRITE (0x1) 741 #define MPII_SCSIIO_DIR_READ (0x2) 742 743 #define MPII_CDB_LEN (32) 744 u_int8_t cdb[MPII_CDB_LEN]; 745 746 /* followed by an sgl */ 747 } __packed; 748 749 struct mpii_msg_scsi_io_error { 750 u_int16_t dev_handle; 751 u_int8_t msg_length; 752 u_int8_t function; 753 754 u_int16_t reserved1; 755 u_int8_t reserved2; 756 u_int8_t msg_flags; 757 758 u_int8_t vp_id; 759 u_int8_t vf_id; 760 u_int16_t reserved3; 761 762 u_int8_t scsi_status; 763 /* XXX JPG validate this */ 764 #if notyet 765 #define MPII_SCSIIO_ERR_STATUS_SUCCESS 766 #define MPII_SCSIIO_ERR_STATUS_CHECK_COND 767 #define MPII_SCSIIO_ERR_STATUS_BUSY 768 #define MPII_SCSIIO_ERR_STATUS_INTERMEDIATE 769 #define MPII_SCSIIO_ERR_STATUS_INTERMEDIATE_CONDMET 770 #define MPII_SCSIIO_ERR_STATUS_RESERVATION_CONFLICT 771 #define MPII_SCSIIO_ERR_STATUS_CMD_TERM 772 #define MPII_SCSIIO_ERR_STATUS_TASK_SET_FULL 773 #define MPII_SCSIIO_ERR_STATUS_ACA_ACTIVE 774 #endif 775 u_int8_t scsi_state; 776 #define MPII_SCSIIO_ERR_STATE_AUTOSENSE_VALID (1<<0) 777 #define MPII_SCSIIO_ERR_STATE_AUTOSENSE_FAILED (1<<1) 778 #define MPII_SCSIIO_ERR_STATE_NO_SCSI_STATUS (1<<2) 779 #define MPII_SCSIIO_ERR_STATE_TERMINATED (1<<3) 780 #define MPII_SCSIIO_ERR_STATE_RESPONSE_INFO_VALID (1<<4) 781 #define MPII_SCSIIO_ERR_STATE_QUEUE_TAG_REJECTED (0xffff) 782 u_int16_t ioc_status; 783 784 u_int32_t ioc_loginfo; 785 786 u_int32_t transfer_count; 787 788 u_int32_t sense_count; 789 790 u_int32_t response_info; 791 792 u_int16_t task_tag; 793 u_int16_t reserved4; 794 795 u_int32_t bidirectional_transfer_count; 796 797 u_int32_t reserved5; 798 799 u_int32_t reserved6; 800 } __packed; 801 802 struct mpii_request_descr { 803 u_int8_t request_flags; 804 #define MPII_REQ_DESCR_TYPE_MASK (0x0e) 805 #define MPII_REQ_DESCR_SCSI_IO (0x00) 806 #define MPII_REQ_DESCR_SCSI_TARGET (0x02) 807 #define MPII_REQ_DESCR_HIGH_PRIORITY (0x06) 808 #define MPII_REQ_DESCR_DEFAULT (0x08) 809 u_int8_t vf_id; 810 u_int16_t smid; 811 812 u_int16_t lmid; 813 u_int16_t dev_handle; 814 } __packed; 815 816 struct mpii_reply_descr { 817 u_int8_t reply_flags; 818 #define MPII_REPLY_DESCR_TYPE_MASK (0x0f) 819 #define MPII_REPLY_DESCR_SCSI_IO_SUCCESS (0x00) 820 #define MPII_REPLY_DESCR_ADDRESS_REPLY (0x01) 821 #define MPII_REPLY_DESCR_TARGET_ASSIST_SUCCESS (0x02) 822 #define MPII_REPLY_DESCR_TARGET_COMMAND_BUFFER (0x03) 823 #define MPII_REPLY_DESCR_UNUSED (0x0f) 824 u_int8_t vf_id; 825 u_int16_t smid; 826 827 union { 828 u_int32_t data; 829 u_int32_t frame_addr; /* Address Reply */ 830 }; 831 } __packed; 832 833 struct mpii_request_header { 834 u_int16_t function_dependent1; 835 u_int8_t chain_offset; 836 u_int8_t function; 837 838 u_int16_t function_dependent2; 839 u_int8_t function_dependent3; 840 u_int8_t message_flags; 841 842 u_int8_t vp_id; 843 u_int8_t vf_id; 844 u_int16_t reserved; 845 } __packed; 846 847 struct mpii_msg_scsi_task_request { 848 u_int16_t dev_handle; 849 u_int8_t chain_offset; 850 u_int8_t function; 851 852 u_int8_t reserved1; 853 u_int8_t task_type; 854 #define MPII_SCSI_TASK_ABORT_TASK (0x01) 855 #define MPII_SCSI_TASK_ABRT_TASK_SET (0x02) 856 #define MPII_SCSI_TASK_TARGET_RESET (0x03) 857 #define MPII_SCSI_TASK_RESET_BUS (0x04) 858 #define MPII_SCSI_TASK_LOGICAL_UNIT_RESET (0x05) 859 u_int8_t reserved2; 860 u_int8_t msg_flags; 861 862 u_int8_t vp_id; 863 u_int8_t vf_id; 864 u_int16_t reserved3; 865 866 u_int16_t lun[4]; 867 868 u_int32_t reserved4[7]; 869 870 u_int16_t task_mid; 871 u_int16_t reserved5; 872 } __packed; 873 874 struct mpii_msg_scsi_task_reply { 875 u_int16_t dev_handle; 876 u_int8_t msg_length; 877 u_int8_t function; 878 879 u_int8_t response_code; 880 u_int8_t task_type; 881 u_int8_t reserved1; 882 u_int8_t msg_flags; 883 884 u_int8_t vp_id; 885 u_int8_t vf_id; 886 u_int16_t reserved2; 887 888 u_int16_t reserved3; 889 u_int16_t ioc_status; 890 891 u_int32_t ioc_loginfo; 892 893 u_int32_t termination_count; 894 } __packed; 895 896 struct mpii_msg_sas_oper_request { 897 u_int8_t operation; 898 #define MPII_SAS_OP_CLEAR_PERSISTENT (0x02) 899 #define MPII_SAS_OP_PHY_LINK_RESET (0x06) 900 #define MPII_SAS_OP_PHY_HARD_RESET (0x07) 901 #define MPII_SAS_OP_PHY_CLEAR_ERROR_LOG (0x08) 902 #define MPII_SAS_OP_SEND_PRIMITIVE (0x0a) 903 #define MPII_SAS_OP_FORCE_FULL_DISCOVERY (0x0b) 904 #define MPII_SAS_OP_TRANSMIT_PORT_SELECT (0x0c) 905 #define MPII_SAS_OP_REMOVE_DEVICE (0x0d) 906 #define MPII_SAS_OP_LOOKUP_MAPPING (0x0e) 907 #define MPII_SAS_OP_SET_IOC_PARAM (0x0f) 908 u_int8_t reserved1; 909 u_int8_t chain_offset; 910 u_int8_t function; 911 912 u_int16_t dev_handle; 913 u_int8_t ioc_param; 914 u_int8_t msg_flags; 915 916 u_int8_t vp_id; 917 u_int8_t vf_id; 918 u_int16_t reserved2; 919 920 u_int16_t reserved3; 921 u_int8_t phy_num; 922 u_int8_t prim_flags; 923 924 u_int32_t primitive; 925 926 u_int8_t lookup_method; 927 #define MPII_SAS_LOOKUP_METHOD_SAS_ADDR (0x01) 928 #define MPII_SAS_LOOKUP_METHOD_SAS_ENCL (0x02) 929 #define MPII_SAS_LOOKUP_METHOD_SAS_DEVNAME (0x03) 930 u_int8_t reserved4; 931 u_int16_t slot_num; 932 933 u_int64_t lookup_addr; 934 935 u_int32_t ioc_param_value; 936 937 u_int64_t reserved5; 938 } __packed; 939 940 struct mpii_msg_sas_oper_reply { 941 u_int8_t operation; 942 u_int8_t reserved1; 943 u_int8_t chain_offset; 944 u_int8_t function; 945 946 u_int16_t dev_handle; 947 u_int8_t ioc_param; 948 u_int8_t msg_flags; 949 950 u_int8_t vp_id; 951 u_int8_t vf_id; 952 u_int16_t reserved2; 953 954 u_int16_t reserved3; 955 u_int16_t ioc_status; 956 957 u_int32_t ioc_loginfo; 958 } __packed; 959 960 struct mpii_msg_raid_action_request { 961 u_int8_t action; 962 #define MPII_RAID_ACTION_CHANGE_VOL_WRITE_CACHE (0x17) 963 u_int8_t reserved1; 964 u_int8_t chain_offset; 965 u_int8_t function; 966 967 u_int16_t vol_dev_handle; 968 u_int8_t phys_disk_num; 969 u_int8_t msg_flags; 970 971 u_int8_t vp_id; 972 u_int8_t vf_if; 973 u_int16_t reserved2; 974 975 u_int32_t reserved3; 976 977 u_int32_t action_data; 978 #define MPII_RAID_VOL_WRITE_CACHE_MASK (0x03) 979 #define MPII_RAID_VOL_WRITE_CACHE_DISABLE (0x01) 980 #define MPII_RAID_VOL_WRITE_CACHE_ENABLE (0x02) 981 982 struct mpii_sge action_sge; 983 } __packed; 984 985 struct mpii_msg_raid_action_reply { 986 u_int8_t action; 987 u_int8_t reserved1; 988 u_int8_t chain_offset; 989 u_int8_t function; 990 991 u_int16_t vol_dev_handle; 992 u_int8_t phys_disk_num; 993 u_int8_t msg_flags; 994 995 u_int8_t vp_id; 996 u_int8_t vf_if; 997 u_int16_t reserved2; 998 999 u_int16_t reserved3; 1000 u_int16_t ioc_status; 1001 1002 u_int32_t action_data[5]; 1003 } __packed; 1004 1005 struct mpii_cfg_hdr { 1006 u_int8_t page_version; 1007 u_int8_t page_length; 1008 u_int8_t page_number; 1009 u_int8_t page_type; 1010 #define MPII_CONFIG_REQ_PAGE_TYPE_ATTRIBUTE (0xf0) 1011 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 1012 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 1013 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 1014 1015 #define MPII_CONFIG_REQ_PAGE_TYPE_MASK (0x0f) 1016 #define MPII_CONFIG_REQ_PAGE_TYPE_IO_UNIT (0x00) 1017 #define MPII_CONFIG_REQ_PAGE_TYPE_IOC (0x01) 1018 #define MPII_CONFIG_REQ_PAGE_TYPE_BIOS (0x02) 1019 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_VOL (0x08) 1020 #define MPII_CONFIG_REQ_PAGE_TYPE_MANUFACTURING (0x09) 1021 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_PD (0x0a) 1022 #define MPII_CONFIG_REQ_PAGE_TYPE_EXTENDED (0x0f) 1023 } __packed; 1024 1025 struct mpii_ecfg_hdr { 1026 u_int8_t page_version; 1027 u_int8_t reserved1; 1028 u_int8_t page_number; 1029 u_int8_t page_type; 1030 1031 u_int16_t ext_page_length; 1032 u_int8_t ext_page_type; 1033 #define MPII_CONFIG_REQ_PAGE_TYPE_SAS_DEVICE (0x12) 1034 #define MPII_CONFIG_REQ_PAGE_TYPE_RAID_CONFIG (0x16) 1035 #define MPII_CONFIG_REQ_PAGE_TYPE_DRIVER_MAPPING (0x17) 1036 u_int8_t reserved2; 1037 } __packed; 1038 1039 struct mpii_msg_config_request { 1040 u_int8_t action; 1041 #define MPII_CONFIG_REQ_ACTION_PAGE_HEADER (0x00) 1042 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_CURRENT (0x01) 1043 #define MPII_CONFIG_REQ_ACTION_PAGE_WRITE_CURRENT (0x02) 1044 #define MPII_CONFIG_REQ_ACTION_PAGE_DEFAULT (0x03) 1045 #define MPII_CONFIG_REQ_ACTION_PAGE_WRITE_NVRAM (0x04) 1046 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_DEFAULT (0x05) 1047 #define MPII_CONFIG_REQ_ACTION_PAGE_READ_NVRAM (0x06) 1048 u_int8_t sgl_flags; 1049 u_int8_t chain_offset; 1050 u_int8_t function; 1051 1052 u_int16_t ext_page_len; 1053 u_int8_t ext_page_type; 1054 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_IO_UNIT (0x10) 1055 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_EXPANDER (0x11) 1056 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_DEVICE (0x12) 1057 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_PHY (0x13) 1058 #define MPII_CONFIG_REQ_EXTPAGE_TYPE_LOG (0x14) 1059 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 1060 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 1061 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 1062 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 1063 u_int8_t msg_flags; 1064 1065 u_int8_t vp_id; 1066 u_int8_t vf_id; 1067 u_int16_t reserved1; 1068 1069 u_int32_t reserved2[2]; 1070 1071 struct mpii_cfg_hdr config_header; 1072 1073 u_int32_t page_address; 1074 /* XXX lots of defns here */ 1075 1076 struct mpii_sge page_buffer; 1077 } __packed; 1078 1079 struct mpii_msg_config_reply { 1080 u_int8_t action; 1081 u_int8_t sgl_flags; 1082 u_int8_t msg_length; 1083 u_int8_t function; 1084 1085 u_int16_t ext_page_length; 1086 u_int8_t ext_page_type; 1087 u_int8_t msg_flags; 1088 1089 u_int8_t vp_id; 1090 u_int8_t vf_id; 1091 u_int16_t reserved1; 1092 1093 u_int16_t reserved2; 1094 u_int16_t ioc_status; 1095 1096 u_int32_t ioc_loginfo; 1097 1098 struct mpii_cfg_hdr config_header; 1099 } __packed; 1100 1101 struct mpii_cfg_manufacturing_pg0 { 1102 struct mpii_cfg_hdr config_header; 1103 1104 char chip_name[16]; 1105 char chip_revision[8]; 1106 char board_name[16]; 1107 char board_assembly[16]; 1108 char board_tracer_number[16]; 1109 } __packed; 1110 1111 struct mpii_cfg_ioc_pg1 { 1112 struct mpii_cfg_hdr config_header; 1113 1114 u_int32_t flags; 1115 1116 u_int32_t coalescing_timeout; 1117 #define MPII_CFG_IOC_1_REPLY_COALESCING (1<<0) 1118 1119 u_int8_t coalescing_depth; 1120 u_int8_t pci_slot_num; 1121 u_int8_t pci_bus_num; 1122 u_int8_t pci_domain_segment; 1123 1124 u_int32_t reserved1; 1125 1126 u_int32_t reserved2; 1127 } __packed; 1128 1129 struct mpii_cfg_ioc_pg3 { 1130 struct mpii_cfg_hdr config_header; 1131 1132 u_int8_t no_phys_disks; 1133 u_int8_t reserved[3]; 1134 1135 /* followed by a list of mpii_cfg_raid_physdisk structs */ 1136 } __packed; 1137 1138 struct mpii_cfg_ioc_pg8 { 1139 struct mpii_cfg_hdr config_header; 1140 1141 u_int8_t num_devs_per_enclosure; 1142 u_int8_t reserved1; 1143 u_int16_t reserved2; 1144 1145 u_int16_t max_persistent_entries; 1146 u_int16_t max_num_physical_mapped_ids; 1147 1148 u_int16_t flags; 1149 #define MPII_IOC_PG8_FLAGS_DA_START_SLOT_1 (1<<5) 1150 #define MPII_IOC_PG8_FLAGS_RESERVED_TARGETID_0 (1<<4) 1151 #define MPII_IOC_PG8_FLAGS_MAPPING_MODE_MASK (0x0000000e) 1152 #define MPII_IOC_PG8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0<<1) 1153 #define MPII_IOC_PG8_FLAGS_ENCLOSURE_SLOT_MAPPING (1<<1) 1154 #define MPII_IOC_PG8_FLAGS_DISABLE_PERSISTENT_MAPPING (1<<0) 1155 #define MPII_IOC_PG8_FLAGS_ENABLE_PERSISTENT_MAPPING (0<<0) 1156 u_int16_t reserved3; 1157 1158 u_int16_t ir_volume_mapping_flags; 1159 #define MPII_IOC_PG8_IRFLAGS_VOLUME_MAPPING_MODE_MASK (0x00000003) 1160 #define MPII_IOC_PG8_IRFLAGS_LOW_VOLUME_MAPPING (0<<0) 1161 #define MPII_IOC_PG8_IRFLAGS_HIGH_VOLUME_MAPPING (1<<0) 1162 u_int16_t reserved4; 1163 1164 u_int32_t reserved5; 1165 } __packed; 1166 1167 struct mpii_cfg_raid_physdisk { 1168 u_int8_t phys_disk_id; 1169 u_int8_t phys_disk_bus; 1170 u_int8_t phys_disk_ioc; 1171 u_int8_t phys_disk_num; 1172 } __packed; 1173 1174 struct mpii_cfg_fc_port_pg0 { 1175 struct mpii_cfg_hdr config_header; 1176 1177 u_int32_t flags; 1178 1179 u_int8_t mpii_port_nr; 1180 u_int8_t link_type; 1181 u_int8_t port_state; 1182 u_int8_t reserved1; 1183 1184 u_int32_t port_id; 1185 1186 u_int64_t wwnn; 1187 1188 u_int64_t wwpn; 1189 1190 u_int32_t supported_service_class; 1191 1192 u_int32_t supported_speeds; 1193 1194 u_int32_t current_speed; 1195 1196 u_int32_t max_frame_size; 1197 1198 u_int64_t fabric_wwnn; 1199 1200 u_int64_t fabric_wwpn; 1201 1202 u_int32_t discovered_port_count; 1203 1204 u_int32_t max_initiators; 1205 1206 u_int8_t max_aliases_supported; 1207 u_int8_t max_hard_aliases_supported; 1208 u_int8_t num_current_aliases; 1209 u_int8_t reserved2; 1210 } __packed; 1211 1212 struct mpii_cfg_fc_port_pg1 { 1213 struct mpii_cfg_hdr config_header; 1214 1215 u_int32_t flags; 1216 1217 u_int64_t noseepromwwnn; 1218 1219 u_int64_t noseepromwwpn; 1220 1221 u_int8_t hard_alpa; 1222 u_int8_t link_config; 1223 u_int8_t topology_config; 1224 u_int8_t alt_connector; 1225 1226 u_int8_t num_req_aliases; 1227 u_int8_t rr_tov; 1228 u_int8_t initiator_dev_to; 1229 u_int8_t initiator_lo_pend_to; 1230 } __packed; 1231 1232 struct mpii_cfg_fc_device_pg0 { 1233 struct mpii_cfg_hdr config_header; 1234 1235 u_int64_t wwnn; 1236 1237 u_int64_t wwpn; 1238 1239 u_int32_t port_id; 1240 1241 u_int8_t protocol; 1242 u_int8_t flags; 1243 u_int16_t bb_credit; 1244 1245 u_int16_t max_rx_frame_size; 1246 u_int8_t adisc_hard_alpa; 1247 u_int8_t port_nr; 1248 1249 u_int8_t fc_ph_low_version; 1250 u_int8_t fc_ph_high_version; 1251 u_int8_t current_target_id; 1252 u_int8_t current_bus; 1253 } __packed; 1254 1255 #define MPII_CFG_RAID_VOL_ADDR_HANDLE (1<<28) 1256 1257 struct mpii_cfg_raid_vol_pg0 { 1258 struct mpii_cfg_hdr config_header; 1259 1260 u_int16_t volume_handle; 1261 u_int8_t volume_state; 1262 #define MPII_CFG_RAID_VOL_0_STATE_MISSING (0x00) 1263 #define MPII_CFG_RAID_VOL_0_STATE_FAILED (0x01) 1264 #define MPII_CFG_RAID_VOL_0_STATE_INITIALIZING (0x02) 1265 #define MPII_CFG_RAID_VOL_0_STATE_ONLINE (0x03) 1266 #define MPII_CFG_RAID_VOL_0_STATE_DEGRADED (0x04) 1267 #define MPII_CFG_RAID_VOL_0_STATE_OPTIMAL (0x05) 1268 u_int8_t volume_type; 1269 #define MPII_CFG_RAID_VOL_0_TYPE_RAID0 (0x00) 1270 #define MPII_CFG_RAID_VOL_0_TYPE_RAID1E (0x01) 1271 #define MPII_CFG_RAID_VOL_0_TYPE_RAID1 (0x02) 1272 #define MPII_CFG_RAID_VOL_0_TYPE_RAID10 (0x05) 1273 #define MPII_CFG_RAID_VOL_0_TYPE_UNKNOWN (0xff) 1274 1275 u_int32_t volume_status; 1276 #define MPII_CFG_RAID_VOL_0_STATUS_SCRUB (1<<20) 1277 #define MPII_CFG_RAID_VOL_0_STATUS_RESYNC (1<<16) 1278 1279 u_int16_t volume_settings; 1280 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_MASK (0x3<<0) 1281 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_UNCHANGED (0x0<<0) 1282 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_DISABLED (0x1<<0) 1283 #define MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_ENABLED (0x2<<0) 1284 1285 u_int8_t hot_spare_pool; 1286 u_int8_t reserved1; 1287 1288 u_int64_t max_lba; 1289 1290 u_int32_t stripe_size; 1291 1292 u_int16_t block_size; 1293 u_int16_t reserved2; 1294 1295 u_int8_t phys_disk_types; 1296 u_int8_t resync_rate; 1297 u_int16_t data_scrub_rate; 1298 1299 u_int8_t num_phys_disks; 1300 u_int16_t reserved3; 1301 u_int8_t inactive_status; 1302 #define MPII_CFG_RAID_VOL_0_INACTIVE_UNKNOWN (0x00) 1303 #define MPII_CFG_RAID_VOL_0_INACTIVE_STALE_META (0x01) 1304 #define MPII_CFG_RAID_VOL_0_INACTIVE_FOREIGN_VOL (0x02) 1305 #define MPII_CFG_RAID_VOL_0_INACTIVE_NO_RESOURCES (0x03) 1306 #define MPII_CFG_RAID_VOL_0_INACTIVE_CLONED_VOL (0x04) 1307 #define MPII_CFG_RAID_VOL_0_INACTIVE_INSUF_META (0x05) 1308 1309 /* followed by a list of mpii_cfg_raid_vol_pg0_physdisk structs */ 1310 } __packed; 1311 1312 struct mpii_cfg_raid_vol_pg0_physdisk { 1313 u_int8_t raid_set_num; 1314 u_int8_t phys_disk_map; 1315 u_int8_t phys_disk_num; 1316 u_int8_t reserved; 1317 } __packed; 1318 1319 struct mpii_cfg_raid_vol_pg1 { 1320 struct mpii_cfg_hdr config_header; 1321 1322 u_int8_t volume_id; 1323 u_int8_t volume_bus; 1324 u_int8_t volume_ioc; 1325 u_int8_t reserved1; 1326 1327 u_int8_t guid[24]; 1328 1329 u_int8_t name[32]; 1330 1331 u_int64_t wwid; 1332 1333 u_int32_t reserved2; 1334 1335 u_int32_t reserved3; 1336 } __packed; 1337 1338 #define MPII_CFG_RAID_PHYS_DISK_ADDR_NUMBER (1<<28) 1339 1340 struct mpii_cfg_raid_physdisk_pg0 { 1341 struct mpii_cfg_hdr config_header; 1342 1343 u_int16_t dev_handle; 1344 u_int8_t reserved1; 1345 u_int8_t phys_disk_num; 1346 1347 u_int8_t enc_id; 1348 u_int8_t enc_bus; 1349 u_int8_t hot_spare_pool; 1350 u_int8_t enc_type; 1351 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_NONE (0x0) 1352 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_SAFTE (0x1) 1353 #define MPII_CFG_RAID_PHYDISK_0_ENCTYPE_SES (0x2) 1354 1355 u_int32_t reserved2; 1356 1357 u_int8_t vendor_id[8]; 1358 1359 u_int8_t product_id[16]; 1360 1361 u_int8_t product_rev[4]; 1362 1363 u_int8_t serial[32]; 1364 1365 u_int32_t reserved3; 1366 1367 u_int8_t phys_disk_state; 1368 #define MPII_CFG_RAID_PHYDISK_0_STATE_NOTCONFIGURED (0x00) 1369 #define MPII_CFG_RAID_PHYDISK_0_STATE_NOTCOMPATIBLE (0x01) 1370 #define MPII_CFG_RAID_PHYDISK_0_STATE_OFFLINE (0x02) 1371 #define MPII_CFG_RAID_PHYDISK_0_STATE_ONLINE (0x03) 1372 #define MPII_CFG_RAID_PHYDISK_0_STATE_HOTSPARE (0x04) 1373 #define MPII_CFG_RAID_PHYDISK_0_STATE_DEGRADED (0x05) 1374 #define MPII_CFG_RAID_PHYDISK_0_STATE_REBUILDING (0x06) 1375 #define MPII_CFG_RAID_PHYDISK_0_STATE_OPTIMAL (0x07) 1376 u_int8_t offline_reason; 1377 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_MISSING (0x01) 1378 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILED (0x03) 1379 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_INITIALIZING (0x04) 1380 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_REQUESTED (0x05) 1381 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILEDREQ (0x06) 1382 #define MPII_CFG_RAID_PHYDISK_0_OFFLINE_OTHER (0xff) 1383 1384 u_int8_t incompat_reason; 1385 u_int8_t phys_disk_attrs; 1386 1387 u_int32_t phys_disk_status; 1388 #define MPII_CFG_RAID_PHYDISK_0_STATUS_OUTOFSYNC (1<<0) 1389 #define MPII_CFG_RAID_PHYDISK_0_STATUS_QUIESCED (1<<1) 1390 1391 u_int64_t dev_max_lba; 1392 1393 u_int64_t host_max_lba; 1394 1395 u_int64_t coerced_max_lba; 1396 1397 u_int16_t block_size; 1398 u_int16_t reserved4; 1399 1400 u_int32_t reserved5; 1401 } __packed; 1402 1403 struct mpii_cfg_raid_physdisk_pg1 { 1404 struct mpii_cfg_hdr config_header; 1405 1406 u_int8_t num_phys_disk_paths; 1407 u_int8_t phys_disk_num; 1408 u_int16_t reserved1; 1409 1410 u_int32_t reserved2; 1411 1412 /* followed by mpii_cfg_raid_physdisk_path structs */ 1413 } __packed; 1414 1415 struct mpii_cfg_raid_physdisk_path { 1416 u_int8_t phys_disk_id; 1417 u_int8_t phys_disk_bus; 1418 u_int16_t reserved1; 1419 1420 u_int64_t wwwid; 1421 1422 u_int64_t owner_wwid; 1423 1424 u_int8_t ownder_id; 1425 u_int8_t reserved2; 1426 u_int16_t flags; 1427 #define MPII_CFG_RAID_PHYDISK_PATH_INVALID (1<<0) 1428 #define MPII_CFG_RAID_PHYDISK_PATH_BROKEN (1<<1) 1429 } __packed; 1430 1431 #define MPII_CFG_SAS_DEV_ADDR_NEXT (0<<28) 1432 #define MPII_CFG_SAS_DEV_ADDR_BUS (1<<28) 1433 #define MPII_CFG_SAS_DEV_ADDR_HANDLE (2<<28) 1434 1435 struct mpii_cfg_sas_dev_pg0 { 1436 struct mpii_ecfg_hdr config_header; 1437 1438 u_int16_t slot; 1439 u_int16_t enc_handle; 1440 1441 u_int64_t sas_addr; 1442 1443 u_int16_t parent_dev_handle; 1444 u_int8_t phy_num; 1445 u_int8_t access_status; 1446 1447 u_int16_t dev_handle; 1448 u_int8_t target; 1449 u_int8_t bus; 1450 1451 u_int32_t device_info; 1452 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE (0x7) 1453 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_NONE (0x0) 1454 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_END (0x1) 1455 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_EDGE_EXPANDER (0x2) 1456 #define MPII_CFG_SAS_DEV_0_DEVINFO_TYPE_FANOUT_EXPANDER (0x3) 1457 #define MPII_CFG_SAS_DEV_0_DEVINFO_SATA_HOST (1<<3) 1458 #define MPII_CFG_SAS_DEV_0_DEVINFO_SMP_INITIATOR (1<<4) 1459 #define MPII_CFG_SAS_DEV_0_DEVINFO_STP_INITIATOR (1<<5) 1460 #define MPII_CFG_SAS_DEV_0_DEVINFO_SSP_INITIATOR (1<<6) 1461 #define MPII_CFG_SAS_DEV_0_DEVINFO_SATA_DEVICE (1<<7) 1462 #define MPII_CFG_SAS_DEV_0_DEVINFO_SMP_TARGET (1<<8) 1463 #define MPII_CFG_SAS_DEV_0_DEVINFO_STP_TARGET (1<<9) 1464 #define MPII_CFG_SAS_DEV_0_DEVINFO_SSP_TARGET (1<<10) 1465 #define MPII_CFG_SAS_DEV_0_DEVINFO_DIRECT_ATTACHED (1<<11) 1466 #define MPII_CFG_SAS_DEV_0_DEVINFO_LSI_DEVICE (1<<12) 1467 #define MPII_CFG_SAS_DEV_0_DEVINFO_ATAPI_DEVICE (1<<13) 1468 #define MPII_CFG_SAS_DEV_0_DEVINFO_SEP_DEVICE (1<<14) 1469 1470 u_int16_t flags; 1471 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_PRESENT (1<<0) 1472 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED (1<<1) 1473 #define MPII_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED_PERSISTENT (1<<2) 1474 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_PORT_SELECTOR (1<<3) 1475 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_FUA (1<<4) 1476 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_NCQ (1<<5) 1477 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_SMART (1<<6) 1478 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_LBA48 (1<<7) 1479 #define MPII_CFG_SAS_DEV_0_FLAGS_UNSUPPORTED (1<<8) 1480 #define MPII_CFG_SAS_DEV_0_FLAGS_SATA_SETTINGS (1<<9) 1481 u_int8_t physical_port; 1482 u_int8_t max_port_conn; 1483 1484 u_int64_t device_name; 1485 1486 u_int8_t port_groups; 1487 u_int8_t dma_group; 1488 u_int8_t ctrl_group; 1489 u_int8_t reserved1; 1490 1491 u_int64_t reserved2; 1492 } __packed; 1493 1494 #define MPII_CFG_RAID_CONFIG_ACTIVE_CONFIG (2<<28) 1495 1496 struct mpii_cfg_raid_config_pg0 { 1497 struct mpii_ecfg_hdr config_header; 1498 1499 u_int8_t num_hot_spares; 1500 u_int8_t num_phys_disks; 1501 u_int8_t num_volumes; 1502 u_int8_t config_num; 1503 1504 u_int32_t flags; 1505 #define MPII_CFG_RAID_CONFIG_0_FLAGS_NATIVE (0<<0) 1506 #define MPII_CFG_RAID_CONFIG_0_FLAGS_FOREIGN (1<<0) 1507 1508 u_int32_t config_guid[6]; 1509 1510 u_int32_t reserved1; 1511 1512 u_int8_t num_elements; 1513 u_int8_t reserved2[3]; 1514 1515 /* followed by struct mpii_raid_config_element structs */ 1516 } __packed; 1517 1518 struct mpii_raid_config_element { 1519 u_int16_t element_flags; 1520 #define MPII_RAID_CONFIG_ELEMENT_FLAG_VOLUME (0x0) 1521 #define MPII_RAID_CONFIG_ELEMENT_FLAG_VOLUME_PHYS_DISK (0x1) 1522 #define MPII_RAID_CONFIG_ELEMENT_FLAG_HSP_PHYS_DISK (0x2) 1523 #define MPII_RAID_CONFIG_ELEMENT_ONLINE_CE_PHYS_DISK (0x3) 1524 u_int16_t vol_dev_handle; 1525 1526 u_int8_t hot_spare_pool; 1527 u_int8_t phys_disk_num; 1528 u_int16_t phys_disk_dev_handle; 1529 } __packed; 1530 1531 struct mpii_cfg_dpm_pg0 { 1532 struct mpii_ecfg_hdr config_header; 1533 #define MPII_DPM_ADDRESS_FORM_MASK (0xf0000000) 1534 #define MPII_DPM_ADDRESS_FORM_ENTRY_RANGE (0x00000000) 1535 #define MPII_DPM_ADDRESS_ENTRY_COUNT_MASK (0x0fff0000) 1536 #define MPII_DPM_ADDRESS_ENTRY_COUNT_SHIFT (16) 1537 #define MPII_DPM_ADDRESS_START_ENTRY_MASK (0x0000ffff) 1538 1539 /* followed by struct mpii_dpm_entry structs */ 1540 } __packed; 1541 1542 struct mpii_dpm_entry { 1543 u_int64_t physical_identifier; 1544 1545 u_int16_t mapping_information; 1546 u_int16_t device_index; 1547 1548 u_int32_t physical_bits_mapping; 1549 1550 u_int32_t reserved1; 1551 } __packed; 1552 1553 struct mpii_evt_sas_discovery { 1554 u_int8_t flags; 1555 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_MASK (1<<1) 1556 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_NO_CHANGE (0<<1) 1557 #define MPII_EVENT_SAS_DISC_FLAGS_DEV_CHANGE_CHANGE (1<<1) 1558 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_IN_PROG_MASK (1<<0) 1559 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_NOT_IN_PROGRESS (1<<0) 1560 #define MPII_EVENT_SAS_DISC_FLAGS_DISC_IN_PROGRESS (0<<0) 1561 u_int8_t reason_code; 1562 #define MPII_EVENT_SAS_DISC_REASON_CODE_STARTED (0x01) 1563 #define MPII_EVENT_SAS_DISC_REASON_CODE_COMPLETED (0x02) 1564 u_int8_t physical_port; 1565 u_int8_t reserved1; 1566 1567 u_int32_t discovery_status; 1568 } __packed; 1569 1570 struct mpii_evt_ir_status { 1571 u_int16_t vol_dev_handle; 1572 u_int16_t reserved1; 1573 1574 u_int8_t operation; 1575 #define MPII_EVENT_IR_RAIDOP_RESYNC (0x00) 1576 #define MPII_EVENT_IR_RAIDOP_OCE (0x01) 1577 #define MPII_EVENT_IR_RAIDOP_CONS_CHECK (0x02) 1578 #define MPII_EVENT_IR_RAIDOP_BG_INIT (0x03) 1579 #define MPII_EVENT_IR_RAIDOP_MAKE_CONS (0x04) 1580 u_int8_t percent; 1581 u_int16_t reserved2; 1582 1583 u_int32_t reserved3; 1584 }; 1585 1586 struct mpii_evt_ir_volume { 1587 u_int16_t vol_dev_handle; 1588 u_int8_t reason_code; 1589 #define MPII_EVENT_IR_VOL_RC_SETTINGS_CHANGED (0x01) 1590 #define MPII_EVENT_IR_VOL_RC_STATUS_CHANGED (0x02) 1591 #define MPII_EVENT_IR_VOL_RC_STATE_CHANGED (0x03) 1592 u_int8_t reserved1; 1593 1594 u_int32_t new_value; 1595 u_int32_t prev_value; 1596 } __packed; 1597 1598 struct mpii_evt_ir_physical_disk { 1599 u_int16_t reserved1; 1600 u_int8_t reason_code; 1601 #define MPII_EVENT_IR_PD_RC_SETTINGS_CHANGED (0x01) 1602 #define MPII_EVENT_IR_PD_RC_STATUS_FLAGS_CHANGED (0x02) 1603 #define MPII_EVENT_IR_PD_RC_STATUS_CHANGED (0x03) 1604 u_int8_t phys_disk_num; 1605 1606 u_int16_t phys_disk_dev_handle; 1607 u_int16_t reserved2; 1608 1609 u_int16_t slot; 1610 u_int16_t enclosure_handle; 1611 1612 u_int32_t new_value; 1613 u_int32_t previous_value; 1614 } __packed; 1615 1616 struct mpii_evt_sas_tcl { 1617 u_int16_t enclosure_handle; 1618 u_int16_t expander_handle; 1619 1620 u_int8_t num_phys; 1621 u_int8_t reserved1[3]; 1622 1623 u_int8_t num_entries; 1624 u_int8_t start_phy_num; 1625 u_int8_t expn_status; 1626 #define MPII_EVENT_SAS_TOPO_ES_ADDED (0x01) 1627 #define MPII_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 1628 #define MPII_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 1629 #define MPII_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 1630 u_int8_t physical_port; 1631 1632 /* followed by num_entries number of struct mpii_evt_phy_entry */ 1633 } __packed; 1634 1635 struct mpii_evt_phy_entry { 1636 u_int16_t dev_handle; 1637 u_int8_t link_rate; 1638 u_int8_t phy_status; 1639 #define MPII_EVENT_SAS_TOPO_PS_RC_MASK (0x0f) 1640 #define MPII_EVENT_SAS_TOPO_PS_RC_ADDED (0x01) 1641 #define MPII_EVENT_SAS_TOPO_PS_RC_MISSING (0x02) 1642 } __packed; 1643 1644 struct mpii_evt_ir_cfg_change_list { 1645 u_int8_t num_elements; 1646 u_int16_t reserved; 1647 u_int8_t config_num; 1648 1649 u_int32_t flags; 1650 #define MPII_EVT_IR_CFG_CHANGE_LIST_FOREIGN (0x1) 1651 1652 /* followed by num_elements struct mpii_evt_ir_cfg_elements */ 1653 } __packed; 1654 1655 struct mpii_evt_ir_cfg_element { 1656 u_int16_t element_flags; 1657 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_MASK (0xf) 1658 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME (0x0) 1659 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME_DISK (0x1) 1660 #define MPII_EVT_IR_CFG_ELEMENT_TYPE_HOT_SPARE (0x2) 1661 u_int16_t vol_dev_handle; 1662 1663 u_int8_t reason_code; 1664 #define MPII_EVT_IR_CFG_ELEMENT_RC_ADDED (0x01) 1665 #define MPII_EVT_IR_CFG_ELEMENT_RC_REMOVED (0x02) 1666 #define MPII_EVT_IR_CFG_ELEMENT_RC_NO_CHANGE (0x03) 1667 #define MPII_EVT_IR_CFG_ELEMENT_RC_HIDE (0x04) 1668 #define MPII_EVT_IR_CFG_ELEMENT_RC_UNHIDE (0x05) 1669 #define MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_CREATED (0x06) 1670 #define MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_DELETED (0x07) 1671 #define MPII_EVT_IR_CFG_ELEMENT_RC_PD_CREATED (0x08) 1672 #define MPII_EVT_IR_CFG_ELEMENT_RC_PD_DELETED (0x09) 1673 u_int8_t phys_disk_num; 1674 u_int16_t phys_disk_dev_handle; 1675 } __packed; 1676