1 /* $OpenBSD: pccbb.c,v 1.105 2024/05/24 06:02:58 jsg Exp $ */ 2 /* $NetBSD: pccbb.c,v 1.96 2004/03/28 09:49:31 nakayama Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 and 2000 6 * HAYAKAWA Koichi. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 #define CBB_DEBUG 31 #define SHOW_REGS 32 #define PCCBB_PCMCIA_POLL 33 */ 34 35 /* 36 #define CB_PCMCIA_POLL 37 #define CB_PCMCIA_POLL_ONLY 38 #define LEVEL2 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/evcount.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 #include <sys/task.h> 47 #include <sys/time.h> 48 #include <sys/timeout.h> 49 50 #include <machine/intr.h> 51 #include <machine/bus.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/pci/pccbbreg.h> 58 59 #include <dev/cardbus/cardslotvar.h> 60 61 #include <dev/cardbus/cardbusvar.h> 62 63 #include <dev/pcmcia/pcmciareg.h> 64 #include <dev/pcmcia/pcmciavar.h> 65 66 #include <dev/ic/i82365reg.h> 67 #include <dev/ic/i82365var.h> 68 #include <dev/pci/pccbbvar.h> 69 70 struct cfdriver cbb_cd = { 71 NULL, "cbb", DV_DULL 72 }; 73 74 #if defined CBB_DEBUG 75 #define DPRINTF(x) printf x 76 #else 77 #define DPRINTF(x) 78 #endif 79 80 int pcicbbmatch(struct device *, void *, void *); 81 void pccbbattach(struct device *, struct device *, void *); 82 int pccbbactivate(struct device *, int); 83 int pccbbintr(void *); 84 void pccbb_shutdown(void *); 85 void pci113x_insert(void *); 86 int pccbbintr_function(struct pccbb_softc *); 87 88 int pccbb_checksockstat(struct pccbb_softc *); 89 int pccbb_detect_card(struct pccbb_softc *); 90 91 void pccbb_pcmcia_write(struct pcic_handle *, int, int); 92 u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 93 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 94 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 95 96 int cb_reset(struct pccbb_softc *); 97 int cb_detect_voltage(struct pccbb_softc *); 98 int cbbprint(void *, const char *); 99 100 int cb_chipset(u_int32_t, int *); 101 void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 102 struct pcmciabus_attach_args *); 103 #if 0 104 void pccbb_pcmcia_attach_card(struct pcic_handle *); 105 void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 106 #endif 107 108 int pccbb_ctrl(cardbus_chipset_tag_t, int); 109 int pccbb_power(cardbus_chipset_tag_t, int); 110 int pccbb_cardenable(struct pccbb_softc * sc, int function); 111 void *pccbb_intr_establish(struct pccbb_softc *, int irq, int level, 112 int (*ih) (void *), void *sc, const char *); 113 void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 114 115 void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, int level, 116 int (*ih) (void *), void *sc, const char *); 117 void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 118 119 void pccbb_legacy_disable(struct pccbb_softc *sc); 120 void pccbb_chipinit(struct pccbb_softc *); 121 122 int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 123 struct pcmcia_mem_handle *); 124 void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 125 struct pcmcia_mem_handle *); 126 int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 127 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 128 void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 129 int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 130 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 131 void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 132 struct pcmcia_io_handle *); 133 int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 134 bus_size_t, struct pcmcia_io_handle *, int *); 135 void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 136 void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 137 struct pcmcia_function *, int, int (*)(void *), void *, char *); 138 void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 139 const char *pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t, void *); 140 void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 141 void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 142 int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 143 144 void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 145 void pccbb_pcmcia_wait_ready(struct pcic_handle *); 146 void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 147 148 /* bus-space allocation and deallocation functions */ 149 int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 150 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 151 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 152 int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 153 bus_space_handle_t, bus_size_t); 154 155 int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 156 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 157 int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 158 bus_space_handle_t, bus_size_t); 159 int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 160 bus_size_t, bus_space_handle_t, int); 161 int pccbb_winlist_delete(struct pccbb_win_chain_head *, 162 bus_space_handle_t, bus_size_t); 163 void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 164 bus_space_tag_t); 165 166 /* for config_defer */ 167 void pccbb_pci_callback(struct device *); 168 169 #if defined SHOW_REGS 170 void cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t, 171 bus_space_handle_t memh); 172 #endif 173 174 const struct cfattach cbb_pci_ca = { 175 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach, NULL, 176 pccbbactivate 177 }; 178 179 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 180 pccbb_pcmcia_mem_alloc, 181 pccbb_pcmcia_mem_free, 182 pccbb_pcmcia_mem_map, 183 pccbb_pcmcia_mem_unmap, 184 pccbb_pcmcia_io_alloc, 185 pccbb_pcmcia_io_free, 186 pccbb_pcmcia_io_map, 187 pccbb_pcmcia_io_unmap, 188 pccbb_pcmcia_intr_establish, 189 pccbb_pcmcia_intr_disestablish, 190 pccbb_pcmcia_intr_string, 191 pccbb_pcmcia_socket_enable, 192 pccbb_pcmcia_socket_disable, 193 pccbb_pcmcia_card_detect 194 }; 195 196 static struct cardbus_functions pccbb_funcs = { 197 pccbb_rbus_cb_space_alloc, 198 pccbb_rbus_cb_space_free, 199 pccbb_cb_intr_establish, 200 pccbb_cb_intr_disestablish, 201 pccbb_ctrl, 202 pccbb_power, 203 }; 204 205 /* 206 * delay_ms() is wait in milliseconds. It should be used instead 207 * of delay() if you want to wait more than 1 ms. 208 */ 209 static inline void 210 delay_ms(int millis, void *param) 211 { 212 if (cold) 213 delay(millis * 1000); 214 else 215 tsleep_nsec(param, PWAIT, "pccbb", MSEC_TO_NSEC(millis)); 216 } 217 218 int 219 pcicbbmatch(struct device *parent, void *match, void *aux) 220 { 221 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 222 223 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 224 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 225 PCI_INTERFACE(pa->pa_class) == 0) { 226 return 1; 227 } 228 229 return 0; 230 } 231 232 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 233 | ((prod) << PCI_PRODUCT_SHIFT)) 234 235 struct yenta_chipinfo { 236 pcireg_t yc_id; /* vendor tag | product tag */ 237 int yc_chiptype; 238 int yc_flags; 239 } yc_chipsets[] = { 240 /* Texas Instruments chips */ 241 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 242 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 243 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 244 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 245 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 246 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 247 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 248 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 249 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 250 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 251 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 252 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 253 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 254 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7XX1), CB_TI12XX, 270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 271 272 /* Ricoh chips */ 273 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, 274 PCCBB_PCMCIA_MEM_32}, 275 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, 276 PCCBB_PCMCIA_MEM_32}, 277 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, 278 PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, 280 PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, 282 PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, 284 PCCBB_PCMCIA_MEM_32}, 285 286 /* Toshiba products */ 287 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_TOPIC95), 288 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_TOPIC95B), 290 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_TOPIC97), 292 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_TOPIC100), 294 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 295 296 /* Cirrus Logic products */ 297 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 298 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 300 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 301 302 /* older O2Micro bridges */ 303 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 304 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 306 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), /* 68[71]2 */ 308 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 310 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 312 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 313 314 /* sentinel, or Generic chip */ 315 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 316 }; 317 318 int 319 cb_chipset(u_int32_t pci_id, int *flagp) 320 { 321 struct yenta_chipinfo *yc; 322 323 /* Loop over except the last default entry. */ 324 for (yc = yc_chipsets; yc < yc_chipsets + 325 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 326 if (pci_id == yc->yc_id) 327 break; 328 329 if (flagp != NULL) 330 *flagp = yc->yc_flags; 331 332 return (yc->yc_chiptype); 333 } 334 335 void 336 pccbb_shutdown(void *arg) 337 { 338 struct pccbb_softc *sc = arg; 339 pcireg_t command; 340 341 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 342 343 /* turn off power */ 344 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 345 346 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 347 0); 348 349 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 350 351 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 352 PCI_COMMAND_MASTER_ENABLE); 353 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 354 } 355 356 void 357 pccbbattach(struct device *parent, struct device *self, void *aux) 358 { 359 struct pccbb_softc *sc = (void *)self; 360 struct pci_attach_args *pa = aux; 361 pci_chipset_tag_t pc = pa->pa_pc; 362 pci_intr_handle_t ih; 363 const char *intrstr = NULL; 364 u_long busnum; 365 int flags; 366 367 pccbb_attach_hook(parent, self, pa); 368 369 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 370 sc->sc_id = pa->pa_id; 371 372 #ifdef CBB_DEBUG 373 printf(" (chipflags %x)", flags); 374 #endif 375 376 TAILQ_INIT(&sc->sc_memwindow); 377 TAILQ_INIT(&sc->sc_iowindow); 378 379 sc->sc_rbus_iot = rbus_pccbb_parent_io(self, pa); 380 sc->sc_rbus_memt = rbus_pccbb_parent_mem(self, pa); 381 382 /* 383 * MAP socket registers and ExCA registers on memory-space 384 */ 385 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 386 &sc->sc_base_memt, &sc->sc_base_memh, NULL, NULL, 0)) { 387 printf("can't map registers\n"); 388 return; 389 } 390 391 sc->sc_busnum = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 392 393 #if defined CBB_DEBUG 394 { 395 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 396 printf(": intrpin %s, line %d\n", 397 intrname[pa->pa_intrpin], pa->pa_intrline); 398 } 399 #endif 400 401 /* setup softc */ 402 sc->sc_pc = pc; 403 sc->sc_iot = pa->pa_iot; 404 sc->sc_memt = pa->pa_memt; 405 sc->sc_dmat = pa->pa_dmat; 406 sc->sc_tag = pa->pa_tag; 407 sc->sc_function = pa->pa_function; 408 sc->sc_intrtag = pa->pa_intrtag; 409 sc->sc_intrpin = pa->pa_intrpin; 410 411 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 412 413 /* Map and establish the interrupt. */ 414 if (pci_intr_map(pa, &ih)) { 415 printf(": couldn't map interrupt\n"); 416 return; 417 } 418 intrstr = pci_intr_string(pc, ih); 419 /* must do this after intr is mapped and established */ 420 sc->sc_intrline = pci_intr_line(pc, ih); 421 422 /* 423 * XXX pccbbintr should be called under the priority lower 424 * than any other hard interrupts. 425 */ 426 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, 427 sc->sc_dev.dv_xname); 428 429 if (sc->sc_ih == NULL) { 430 printf(": couldn't establish interrupt"); 431 if (intrstr != NULL) { 432 printf(" at %s", intrstr); 433 } 434 printf("\n"); 435 return; 436 } 437 printf(": %s", intrstr); 438 439 /* 440 * When the bus number isn't configured, try to allocate one 441 * ourselves. 442 */ 443 if ((sc->sc_busnum & 0x00ffff00) == 0 && pa->pa_busex && 444 extent_alloc(pa->pa_busex, 1, 1, 0, 0, EX_NOWAIT, &busnum) == 0) { 445 sc->sc_busnum |= (busnum << 8); 446 sc->sc_busnum |= (busnum << 16); 447 pci_conf_write(pc, pa->pa_tag, PCI_BUSNUM, sc->sc_busnum); 448 } 449 450 /* 451 * When the bus number still isn't set correctly, give up 452 * using 32-bit CardBus mode. 453 */ 454 if (((sc->sc_busnum >> 8) & 0xff) == 0) { 455 printf(", CardBus support disabled"); 456 sc->sc_pcmcia_flags |= PCCBB_PCMCIA_16BITONLY; 457 } 458 459 printf("\n"); 460 461 /* Disable legacy register mapping. */ 462 pccbb_legacy_disable(sc); 463 464 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); 465 config_defer(self, pccbb_pci_callback); 466 } 467 468 /* 469 * void pccbb_pci_callback(struct device *self) 470 * 471 * The actual attach routine: get memory space for YENTA register 472 * space, setup YENTA register and route interrupt. 473 * 474 * This function should be deferred because this device may obtain 475 * memory space dynamically. This function must avoid obtaining 476 * memory area which has already kept for another device. Also, 477 * this function MUST be done before ISA attach process because this 478 * function kills pcic compatible port used by ISA pcic. 479 */ 480 void 481 pccbb_pci_callback(struct device *self) 482 { 483 struct pccbb_softc *sc = (void *)self; 484 pci_chipset_tag_t pc = sc->sc_pc; 485 bus_space_tag_t base_memt; 486 bus_space_handle_t base_memh; 487 u_int32_t maskreg; 488 struct cbslot_attach_args cba; 489 struct pcmciabus_attach_args paa; 490 struct cardslot_attach_args caa; 491 struct cardslot_softc *csc; 492 u_int32_t sockstat; 493 494 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 495 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 496 497 /* bus bridge initialization */ 498 pccbb_chipinit(sc); 499 500 /* clear data structure for child device interrupt handlers */ 501 sc->sc_pil = NULL; 502 sc->sc_pil_intr_enable = 1; 503 504 sockstat = bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 505 if ((sockstat & CB_SOCKET_STAT_CD) == 0) 506 sc->sc_flags |= CBB_CARDEXIST; 507 508 /* 509 * attach cardbus 510 */ 511 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 512 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 513 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 514 515 /* initialize cbslot_attach */ 516 cba.cba_busname = "cardbus"; 517 cba.cba_iot = sc->sc_iot; 518 cba.cba_memt = sc->sc_memt; 519 cba.cba_dmat = sc->sc_dmat; 520 cba.cba_bus = (busreg >> 8) & 0x0ff; 521 cba.cba_cc = (void *)sc; 522 cba.cba_pc = sc->sc_pc; 523 cba.cba_cf = &pccbb_funcs; 524 cba.cba_intrline = sc->sc_intrline; 525 526 cba.cba_rbus_iot = sc->sc_rbus_iot; 527 cba.cba_rbus_memt = sc->sc_rbus_memt; 528 529 cba.cba_cacheline = PCI_CACHELINE(bhlc); 530 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 531 532 #if defined CBB_DEBUG 533 printf("%s: cacheline 0x%x lattimer 0x%x\n", 534 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 535 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 536 busreg); 537 #endif 538 #if defined SHOW_REGS 539 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 540 sc->sc_base_memh); 541 #endif 542 } 543 544 pccbb_pcmcia_attach_setup(sc, &paa); 545 caa.caa_cb_attach = NULL; 546 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 547 caa.caa_cb_attach = &cba; 548 } 549 caa.caa_16_attach = &paa; 550 caa.caa_ph = &sc->sc_pcmcia_h; 551 552 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 553 DPRINTF(("pccbbattach: found cardslot\n")); 554 sc->sc_csc = csc; 555 } 556 557 sc->sc_ints_on = 1; 558 559 /* CSC Interrupt: Card detect interrupt on */ 560 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 561 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 562 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 563 /* reset interrupt */ 564 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 565 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 566 567 return; 568 } 569 570 void 571 pccbb_legacy_disable(struct pccbb_softc *sc) 572 { 573 pcireg_t reg; 574 575 switch (sc->sc_chipset) { 576 case CB_RX5C46X: 577 /* 578 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 579 * cannot be disabled by substituting 0 into PCI_LEGACY 580 * register. Ricoh CardBus bridges have special bits on Bridge 581 * control reg (addr 0x3e on PCI config space). 582 */ 583 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 584 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 585 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 586 break; 587 588 default: 589 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_LEGACY, 0x0); 590 break; 591 } 592 } 593 594 /* 595 * void pccbb_chipinit(struct pccbb_softc *sc) 596 * 597 * This function initialize YENTA chip registers listed below: 598 * 1) PCI command reg, 599 * 2) PCI and CardBus latency timer, 600 * 3) route PCI interrupt, 601 * 4) close all memory and io windows. 602 */ 603 void 604 pccbb_chipinit(struct pccbb_softc *sc) 605 { 606 pci_chipset_tag_t pc = sc->sc_pc; 607 pcitag_t tag = sc->sc_tag; 608 pcireg_t reg; 609 610 /* Power on the controller if the BIOS didn't */ 611 pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0); 612 613 /* 614 * Set PCI command reg. 615 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 616 */ 617 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 618 /* I believe it is harmless. */ 619 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 620 PCI_COMMAND_MASTER_ENABLE); 621 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 622 623 /* 624 * Set CardBus latency timer. 625 */ 626 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 627 if (PCI_CB_LATENCY(reg) < 0x20) { 628 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 629 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 630 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 631 } 632 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 633 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 634 635 /* 636 * Set PCI latency timer. 637 */ 638 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 639 if (PCI_LATTIMER(reg) < 0x10) { 640 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 641 reg |= (0x10 << PCI_LATTIMER_SHIFT); 642 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 643 } 644 DPRINTF(("PCI latency timer 0x%x (%x)\n", 645 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 646 647 /* Route functional interrupts to PCI. */ 648 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 649 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 650 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 651 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 652 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 653 654 switch (sc->sc_chipset) { 655 case CB_TI113X: 656 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 657 /* This bit is shared, but may read as 0 on some chips, so set 658 it explicitly on both functions. */ 659 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 660 /* CSC intr enable */ 661 reg |= PCI113X_CBCTRL_PCI_CSC; 662 /* functional intr prohibit | prohibit ISA routing */ 663 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 664 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 665 break; 666 667 case CB_TI12XX: 668 /* 669 * Some TI 12xx (and [14][45]xx) based pci cards 670 * sometimes have issues with the MFUNC register not 671 * being initialized due to a bad EEPROM on board. 672 * Laptops that this matters on have this register 673 * properly initialized. 674 * 675 * The TI125X parts have a different register. 676 */ 677 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 678 if (reg == PCI12XX_MFUNC_DEFAULT) { 679 reg &= ~PCI12XX_MFUNC_PIN0; 680 reg |= PCI12XX_MFUNC_PIN0_INTA; 681 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 682 PCI12XX_SYSCTRL_INTRTIE) == 0) { 683 reg &= ~PCI12XX_MFUNC_PIN1; 684 reg |= PCI12XX_MFUNC_PIN1_INTB; 685 } 686 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 687 } 688 /* FALLTHROUGH */ 689 690 case CB_TI125X: 691 /* 692 * Disable zoom video. Some machines initialize this 693 * improperly and experience has shown that this helps 694 * prevent strange behavior. 695 */ 696 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 697 698 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 699 reg |= PCI12XX_SYSCTRL_VCCPROT; 700 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 701 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 702 reg |= PCI12XX_CBCTRL_CSC; 703 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 704 break; 705 706 case CB_TOPIC95B: 707 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 708 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 709 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 710 711 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 712 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 713 sc->sc_dev.dv_xname, reg)); 714 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 715 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 716 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 717 DPRINTF(("0x%x\n", reg)); 718 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 719 break; 720 721 case CB_TOPIC97: 722 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 723 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 724 sc->sc_dev.dv_xname, reg)); 725 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 726 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 727 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 728 reg |= TOPIC97_SLOT_CTRL_PCIINT; 729 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 730 DPRINTF(("0x%x\n", reg)); 731 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 732 733 /* make sure to assert LV card support bits */ 734 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 735 0x800 + 0x3e, bus_space_read_1(sc->sc_base_memt, 736 sc->sc_base_memh, 0x800 + 0x3e) | 0x03); 737 break; 738 739 case CB_OLDO2MICRO: 740 /* 741 * older bridges have problems with both read prefetch and 742 * write bursting depending on the combination of the chipset, 743 * bridge and the cardbus card. so disable them to be on the 744 * safe side. One example is O2Micro 6812 with Atheros AR5012 745 * chipsets 746 */ 747 DPRINTF(("%s: old O2Micro bridge found\n", 748 sc->sc_dev.dv_xname, reg)); 749 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED1); 750 pci_conf_write(pc, tag, O2MICRO_RESERVED1, reg & 751 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 752 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED2); 753 pci_conf_write(pc, tag, O2MICRO_RESERVED2, reg & 754 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 755 break; 756 } 757 758 /* Close all memory and I/O windows. */ 759 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 760 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 761 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 762 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 763 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 764 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 765 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 766 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 767 768 /* reset 16-bit pcmcia bus */ 769 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 770 0x800 + PCIC_INTR, 771 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 772 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 773 774 /* turn off power */ 775 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 776 } 777 778 779 780 781 /* 782 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 783 * struct pcmciabus_attach_args *paa) 784 * 785 * This function attaches 16-bit PCcard bus. 786 */ 787 void 788 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 789 struct pcmciabus_attach_args *paa) 790 { 791 struct pcic_handle *ph = &sc->sc_pcmcia_h; 792 rbus_tag_t rb; 793 794 /* initialize pcmcia part in pccbb_softc */ 795 ph->ph_parent = (struct device *)sc; 796 ph->sock = sc->sc_function; 797 ph->flags = 0; 798 ph->shutdown = 0; 799 ph->ih_irq = sc->sc_intrline; 800 ph->ph_bus_t = sc->sc_base_memt; 801 ph->ph_bus_h = sc->sc_base_memh; 802 ph->ph_read = pccbb_pcmcia_read; 803 ph->ph_write = pccbb_pcmcia_write; 804 sc->sc_pct = &pccbb_pcmcia_funcs; 805 806 /* 807 * We need to do a few things here: 808 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 809 * setting the IRQ numbers to 0. 810 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 811 * routing of CSC interrupts (e.g. card removal) to PCI while in 812 * PCMCIA mode. We just leave this set all the time. 813 * 3) Enable card insertion/removal interrupts in case the chip also 814 * needs that while in PCMCIA mode. 815 * 4) Clear any pending CSC interrupt. 816 */ 817 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 818 if (sc->sc_chipset == CB_TI113X) { 819 Pcic_write(ph, PCIC_CSC_INTR, 0); 820 } else { 821 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 822 Pcic_read(ph, PCIC_CSC); 823 } 824 825 /* initialize pcmcia bus attachment */ 826 paa->paa_busname = "pcmcia"; 827 paa->pct = sc->sc_pct; 828 paa->pch = ph; 829 paa->iobase = 0; /* I don't use them */ 830 paa->iosize = 0; 831 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 832 paa->iobase = rb->rb_start + rb->rb_offset; 833 paa->iosize = rb->rb_end - rb->rb_start; 834 835 return; 836 } 837 838 #if 0 839 void 840 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 841 { 842 if (ph->flags & PCIC_FLAG_CARDP) { 843 panic("pccbb_pcmcia_attach_card: already attached"); 844 } 845 846 /* call the MI attach function */ 847 pcmcia_card_attach(ph->pcmcia); 848 849 ph->flags |= PCIC_FLAG_CARDP; 850 } 851 852 void 853 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 854 { 855 if (!(ph->flags & PCIC_FLAG_CARDP)) { 856 panic("pccbb_pcmcia_detach_card: already detached"); 857 } 858 859 ph->flags &= ~PCIC_FLAG_CARDP; 860 861 /* call the MI detach function */ 862 pcmcia_card_detach(ph->pcmcia, flags); 863 } 864 #endif 865 866 int 867 pccbb_checksockstat(struct pccbb_softc *sc) 868 { 869 u_int32_t sockstate; 870 871 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 872 CB_SOCKET_STAT); 873 874 if ((sockstate & CB_SOCKET_STAT_CD) != 0) { 875 /* A card should be removed. */ 876 if (sc->sc_flags & CBB_CARDEXIST) { 877 DPRINTF(("%s: card removed, 0x%08x\n", 878 sc->sc_dev.dv_xname, sockstate)); 879 sc->sc_flags &= ~CBB_CARDEXIST; 880 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 881 #if 0 882 struct pcic_handle *ph = 883 &sc->sc_pcmcia_h; 884 885 pcmcia_card_deactivate(ph->pcmcia); 886 pccbb_pcmcia_socket_disable(ph); 887 pccbb_pcmcia_detach_card(ph, 888 DETACH_FORCE); 889 #endif 890 cardslot_event_throw(sc->sc_csc, 891 CARDSLOT_EVENT_REMOVAL_16); 892 } else if (sc->sc_csc->sc_status & 893 CARDSLOT_STATUS_CARD_CB) { 894 /* Cardbus intr removed */ 895 cardslot_event_throw(sc->sc_csc, 896 CARDSLOT_EVENT_REMOVAL_CB); 897 } 898 } 899 return (1); 900 } else if ((sockstate & CB_SOCKET_STAT_CD) == 0 && 901 (sc->sc_flags & CBB_CARDEXIST) == 0) { 902 timeout_add_msec(&sc->sc_ins_tmo, 100); 903 sc->sc_flags |= CBB_INSERTING; 904 return (1); 905 } 906 return (0); 907 } 908 909 /* 910 * int pccbbintr(arg) 911 * void *arg; 912 * This routine handles the interrupt from Yenta PCI-CardBus bridge 913 * itself. 914 */ 915 int 916 pccbbintr(void *arg) 917 { 918 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 919 u_int32_t sockevent; 920 struct pcic_handle *ph = &sc->sc_pcmcia_h; 921 922 if (!sc->sc_ints_on) 923 return 0; 924 925 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 926 CB_SOCKET_EVENT); 927 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, 928 CB_SOCKET_EVENT, sockevent); 929 Pcic_read(ph, PCIC_CSC); 930 931 if (sockevent & CB_SOCKET_EVENT_CD) { 932 if (pccbb_checksockstat(sc)) 933 return (1); 934 } 935 936 if (sc->sc_pil_intr_enable) 937 return pccbbintr_function(sc); 938 return (0); 939 } 940 941 /* 942 * int pccbbintr_function(struct pccbb_softc *sc) 943 * 944 * This function calls each interrupt handler registered at the 945 * bridge. The interrupt handlers are called in registered order. 946 */ 947 int 948 pccbbintr_function(struct pccbb_softc *sc) 949 { 950 int retval = 0, val; 951 struct pccbb_intrhand_list *pil; 952 int s; 953 954 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 955 s = splraise(pil->pil_level); 956 957 val = (*pil->pil_func)(pil->pil_arg); 958 if (val != 0) 959 pil->pil_count.ec_count++; 960 961 splx(s); 962 963 if (retval == 0 || val != 0) 964 retval = val; 965 } 966 967 return retval; 968 } 969 970 void 971 pci113x_insert(void *arg) 972 { 973 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 974 u_int32_t sockevent, sockstate; 975 976 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 977 CB_SOCKET_EVENT); 978 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 979 CB_SOCKET_STAT); 980 981 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 982 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 983 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 984 sc->sc_flags |= CBB_CARDEXIST; 985 /* call pccard interrupt handler here */ 986 if (sockstate & CB_SOCKET_STAT_16BIT) { 987 /* 16-bit card found */ 988 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 989 cardslot_event_throw(sc->sc_csc, 990 CARDSLOT_EVENT_INSERTION_16); 991 } else if (sockstate & CB_SOCKET_STAT_CB) { 992 /* cardbus card found */ 993 /* cardbus_attach_card(sc->sc_csc); */ 994 cardslot_event_throw(sc->sc_csc, 995 CARDSLOT_EVENT_INSERTION_CB); 996 } else { 997 /* who are you? */ 998 } 999 } else { 1000 timeout_add_msec(&sc->sc_ins_tmo, 100); 1001 } 1002 } 1003 1004 #define PCCBB_PCMCIA_OFFSET 0x800 1005 u_int8_t 1006 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1007 { 1008 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1009 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1010 1011 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1012 PCCBB_PCMCIA_OFFSET + reg); 1013 } 1014 1015 void 1016 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, int val) 1017 { 1018 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1019 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1020 1021 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1022 val); 1023 } 1024 1025 /* 1026 * int pccbb_ctrl(cardbus_chipset_tag_t, int) 1027 */ 1028 int 1029 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1030 { 1031 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1032 1033 switch (command) { 1034 case CARDBUS_CD: 1035 if (2 == pccbb_detect_card(sc)) { 1036 int retval = 0; 1037 int status = cb_detect_voltage(sc); 1038 if (PCCARD_VCC_5V & status) { 1039 retval |= CARDBUS_5V_CARD; 1040 } 1041 if (PCCARD_VCC_3V & status) { 1042 retval |= CARDBUS_3V_CARD; 1043 } 1044 if (PCCARD_VCC_XV & status) { 1045 retval |= CARDBUS_XV_CARD; 1046 } 1047 if (PCCARD_VCC_YV & status) { 1048 retval |= CARDBUS_YV_CARD; 1049 } 1050 return retval; 1051 } else { 1052 return 0; 1053 } 1054 break; 1055 case CARDBUS_RESET: 1056 return cb_reset(sc); 1057 break; 1058 case CARDBUS_IO_ENABLE: /* fallthrough */ 1059 case CARDBUS_IO_DISABLE: /* fallthrough */ 1060 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1061 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1062 case CARDBUS_BM_ENABLE: /* fallthrough */ 1063 case CARDBUS_BM_DISABLE: /* fallthrough */ 1064 return pccbb_cardenable(sc, command); 1065 break; 1066 } 1067 1068 return 0; 1069 } 1070 1071 /* 1072 * int pccbb_power(cardbus_chipset_tag_t, int) 1073 * This function returns true when it succeeds and returns false when 1074 * it fails. 1075 */ 1076 int 1077 pccbb_power(cardbus_chipset_tag_t ct, int command) 1078 { 1079 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1080 1081 u_int32_t status, sock_ctrl; 1082 bus_space_tag_t memt = sc->sc_base_memt; 1083 bus_space_handle_t memh = sc->sc_base_memh; 1084 1085 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1086 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1087 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1088 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1089 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1090 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1091 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1092 "UNKNOWN", 1093 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1094 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1095 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1096 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1097 "UNKNOWN", command)); 1098 1099 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1100 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1101 1102 switch (command & CARDBUS_VCCMASK) { 1103 case CARDBUS_VCC_UC: 1104 break; 1105 case CARDBUS_VCC_5V: 1106 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1107 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1108 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1109 } else { 1110 printf("%s: BAD voltage request: no 5 V card\n", 1111 sc->sc_dev.dv_xname); 1112 } 1113 break; 1114 case CARDBUS_VCC_3V: 1115 if (CB_SOCKET_STAT_3VCARD & status) { 1116 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1117 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1118 } else { 1119 printf("%s: BAD voltage request: no 3.3 V card\n", 1120 sc->sc_dev.dv_xname); 1121 } 1122 break; 1123 case CARDBUS_VCC_0V: 1124 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1125 break; 1126 default: 1127 return 0; /* power NEVER changed */ 1128 break; 1129 } 1130 1131 switch (command & CARDBUS_VPPMASK) { 1132 case CARDBUS_VPP_UC: 1133 break; 1134 case CARDBUS_VPP_0V: 1135 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1136 break; 1137 case CARDBUS_VPP_VCC: 1138 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1139 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1140 break; 1141 case CARDBUS_VPP_12V: 1142 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1143 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1144 break; 1145 } 1146 1147 #if 0 1148 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1149 #endif 1150 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1151 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1152 1153 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1154 printf 1155 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1156 sc->sc_dev.dv_xname, sock_ctrl, status); 1157 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1158 (command & CARDBUS_VCCMASK) == 1159 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1160 CARDBUS_VCCMASK) == 1161 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1162 CARDBUS_VCCMASK) == 1163 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1164 CARDBUS_VCCMASK) == 1165 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1166 CARDBUS_VCCMASK) == 1167 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1168 CARDBUS_VCCMASK) == 1169 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1170 (command & CARDBUS_VPPMASK) == 1171 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1172 CARDBUS_VPPMASK) == 1173 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1174 CARDBUS_VPPMASK) == 1175 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1176 CARDBUS_VPPMASK) == 1177 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1178 #if 0 1179 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1180 u_int32_t force = 1181 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1182 /* Reset Bad Vcc request */ 1183 force &= ~CB_SOCKET_FORCE_BADVCC; 1184 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1185 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1186 CB_SOCKET_STAT)); 1187 return 1; 1188 } 1189 #endif 1190 return 0; 1191 } 1192 1193 /* 1194 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1195 * time is 20 ms, some PC-Card bridge requires longer duration. 1196 */ 1197 delay(300 * 1000); 1198 1199 return 1; /* power changed correctly */ 1200 } 1201 1202 #if defined CB_PCMCIA_POLL 1203 struct cb_poll_str { 1204 void *arg; 1205 int (*func)(void *); 1206 int level; 1207 pccard_chipset_tag_t ct; 1208 int count; 1209 }; 1210 1211 static struct cb_poll_str cb_poll[10]; 1212 static int cb_poll_n = 0; 1213 static struct timeout cb_poll_timeout; 1214 1215 void cb_pcmcia_poll(void *arg); 1216 1217 void 1218 cb_pcmcia_poll(void *arg) 1219 { 1220 struct cb_poll_str *poll = arg; 1221 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1222 struct pccbb_softc *sc = psc->cpc_parent; 1223 int s; 1224 u_int32_t spsr; /* socket present-state reg */ 1225 1226 timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg); 1227 timeout_add_msec(&cb_poll_timeout, 1000 / 10); 1228 switch (poll->level) { 1229 case IPL_NET: 1230 s = splnet(); 1231 break; 1232 case IPL_BIO: 1233 s = splbio(); 1234 break; 1235 case IPL_TTY: /* fallthrough */ 1236 default: 1237 s = spltty(); 1238 break; 1239 } 1240 1241 spsr = 1242 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1243 CB_SOCKET_STAT); 1244 1245 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1246 if (!(spsr & 0x40)) { /* CINT low */ 1247 #else 1248 if (1) { 1249 #endif 1250 if ((*poll->func) (poll->arg) == 1) { 1251 ++poll->count; 1252 printf("intr: reported from poller, 0x%x\n", spsr); 1253 #if defined LEVEL2 1254 } else { 1255 printf("intr: miss! 0x%x\n", spsr); 1256 #endif 1257 } 1258 } 1259 splx(s); 1260 } 1261 #endif /* defined CB_PCMCIA_POLL */ 1262 1263 /* 1264 * int pccbb_detect_card(struct pccbb_softc *sc) 1265 * return value: 0 if no card exists. 1266 * 1 if 16-bit card exists. 1267 * 2 if cardbus card exists. 1268 */ 1269 int 1270 pccbb_detect_card(struct pccbb_softc *sc) 1271 { 1272 bus_space_handle_t base_memh = sc->sc_base_memh; 1273 bus_space_tag_t base_memt = sc->sc_base_memt; 1274 u_int32_t sockstat = 1275 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1276 int retval = 0; 1277 1278 /* 1279 * The SCM Microsystems TI1225-based PCI-CardBus dock card that 1280 * ships with some Lucent WaveLAN cards has only one physical slot 1281 * but OpenBSD probes two. The phantom card in the second slot can 1282 * be ignored by punting on unsupported voltages. 1283 */ 1284 if (sockstat & CB_SOCKET_STAT_XVCARD) 1285 return 0; 1286 1287 /* CD1 and CD2 asserted */ 1288 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1289 /* card must be present */ 1290 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1291 /* NOTACARD DEASSERTED */ 1292 if (CB_SOCKET_STAT_CB & sockstat) { 1293 /* CardBus mode */ 1294 retval = 2; 1295 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1296 /* 16-bit mode */ 1297 retval = 1; 1298 } 1299 } 1300 } 1301 return retval; 1302 } 1303 1304 /* 1305 * int cb_reset(struct pccbb_softc *sc) 1306 * This function resets CardBus card. 1307 */ 1308 int 1309 cb_reset(struct pccbb_softc *sc) 1310 { 1311 /* 1312 * Reset Assert at least 20 ms 1313 * Some machines request longer duration. 1314 */ 1315 int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1316 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1317 1318 /* Reset bit Assert (bit 6 at 0x3E) */ 1319 bcr |= CB_BCR_RESET_ENABLE; 1320 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1321 delay_ms(reset_duration, sc); 1322 1323 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1324 /* Reset bit Deassert (bit 6 at 0x3E) */ 1325 bcr &= ~CB_BCR_RESET_ENABLE; 1326 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1327 delay_ms(reset_duration, sc); 1328 } 1329 /* No card found on the slot. Keep Reset. */ 1330 return 1; 1331 } 1332 1333 /* 1334 * int cb_detect_voltage(struct pccbb_softc *sc) 1335 * This function detect card Voltage. 1336 */ 1337 int 1338 cb_detect_voltage(struct pccbb_softc *sc) 1339 { 1340 u_int32_t psr; /* socket present-state reg */ 1341 bus_space_tag_t iot = sc->sc_base_memt; 1342 bus_space_handle_t ioh = sc->sc_base_memh; 1343 int vol = PCCARD_VCC_UKN; /* set 0 */ 1344 1345 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1346 1347 if (0x400u & psr) { 1348 vol |= PCCARD_VCC_5V; 1349 } 1350 if (0x800u & psr) { 1351 vol |= PCCARD_VCC_3V; 1352 } 1353 1354 return vol; 1355 } 1356 1357 int 1358 cbbprint(void *aux, const char *pcic) 1359 { 1360 /* 1361 struct cbslot_attach_args *cba = aux; 1362 1363 if (cba->cba_slot >= 0) { 1364 printf(" slot %d", cba->cba_slot); 1365 } 1366 */ 1367 return UNCONF; 1368 } 1369 1370 /* 1371 * int pccbb_cardenable(struct pccbb_softc *sc, int function) 1372 * This function enables and disables the card 1373 */ 1374 int 1375 pccbb_cardenable(struct pccbb_softc *sc, int function) 1376 { 1377 u_int32_t command = 1378 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1379 1380 DPRINTF(("pccbb_cardenable:")); 1381 switch (function) { 1382 case CARDBUS_IO_ENABLE: 1383 command |= PCI_COMMAND_IO_ENABLE; 1384 break; 1385 case CARDBUS_IO_DISABLE: 1386 command &= ~PCI_COMMAND_IO_ENABLE; 1387 break; 1388 case CARDBUS_MEM_ENABLE: 1389 command |= PCI_COMMAND_MEM_ENABLE; 1390 break; 1391 case CARDBUS_MEM_DISABLE: 1392 command &= ~PCI_COMMAND_MEM_ENABLE; 1393 break; 1394 case CARDBUS_BM_ENABLE: 1395 command |= PCI_COMMAND_MASTER_ENABLE; 1396 break; 1397 case CARDBUS_BM_DISABLE: 1398 command &= ~PCI_COMMAND_MASTER_ENABLE; 1399 break; 1400 default: 1401 return 0; 1402 } 1403 1404 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1405 DPRINTF((" command reg 0x%x\n", command)); 1406 return 1; 1407 } 1408 1409 /* 1410 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1411 * int irq, 1412 * int level, 1413 * int (* func)(void *), 1414 * void *arg, 1415 * const char *name) 1416 * 1417 * This function registers an interrupt handler at the bridge, in 1418 * order not to call the interrupt handlers of child devices when 1419 * a card-deletion interrupt occurs. 1420 * 1421 * The arguments irq is not used because pccbb selects intr vector. 1422 */ 1423 void * 1424 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1425 int (*func)(void *), void *arg, const char *name) 1426 { 1427 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1428 1429 return pccbb_intr_establish(sc, irq, level, func, arg, name); 1430 } 1431 1432 1433 /* 1434 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1435 * void *ih) 1436 * 1437 * This function removes an interrupt handler pointed by ih. 1438 */ 1439 void 1440 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1441 { 1442 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1443 1444 pccbb_intr_disestablish(sc, ih); 1445 } 1446 1447 1448 /* 1449 * void *pccbb_intr_establish(struct pccbb_softc *sc, 1450 * int irq, 1451 * int level, 1452 * int (* func)(void *), 1453 * void *arg, 1454 * const char *name) 1455 * 1456 * This function registers an interrupt handler at the bridge, in 1457 * order not to call the interrupt handlers of child devices when 1458 * a card-deletion interrupt occurs. 1459 * 1460 * The arguments irq and level are not used. 1461 */ 1462 void * 1463 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1464 int (*func)(void *), void *arg, const char *name) 1465 { 1466 struct pccbb_intrhand_list *pil, *newpil; 1467 pcireg_t reg; 1468 1469 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1470 1471 if (sc->sc_pil == NULL) { 1472 /* initialize bridge intr routing */ 1473 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1474 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1475 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1476 1477 switch (sc->sc_chipset) { 1478 case CB_TI113X: 1479 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1480 /* functional intr enabled */ 1481 reg |= PCI113X_CBCTRL_PCI_INTR; 1482 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1483 break; 1484 default: 1485 break; 1486 } 1487 } 1488 1489 /* 1490 * Allocate a room for interrupt handler structure. 1491 */ 1492 newpil = (struct pccbb_intrhand_list *) 1493 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK); 1494 1495 newpil->pil_func = func; 1496 newpil->pil_arg = arg; 1497 newpil->pil_level = level; 1498 evcount_attach(&newpil->pil_count, name, &sc->sc_intrline); 1499 newpil->pil_next = NULL; 1500 1501 if (sc->sc_pil == NULL) { 1502 sc->sc_pil = newpil; 1503 } else { 1504 for (pil = sc->sc_pil; pil->pil_next != NULL; 1505 pil = pil->pil_next); 1506 pil->pil_next = newpil; 1507 } 1508 1509 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1510 1511 return newpil; 1512 } 1513 1514 /* 1515 * void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1516 * void *ih) 1517 * 1518 * This function removes an interrupt handler pointed by ih. 1519 */ 1520 void 1521 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1522 { 1523 struct pccbb_intrhand_list *pil, **pil_prev; 1524 pcireg_t reg; 1525 1526 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1527 1528 pil_prev = &sc->sc_pil; 1529 1530 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1531 if (pil == ih) { 1532 evcount_detach(&pil->pil_count); 1533 *pil_prev = pil->pil_next; 1534 free(pil, M_DEVBUF, sizeof *pil); 1535 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1536 break; 1537 } 1538 pil_prev = &pil->pil_next; 1539 } 1540 1541 if (sc->sc_pil == NULL) { 1542 /* No interrupt handlers */ 1543 1544 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1545 1546 /* stop routing PCI intr */ 1547 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1548 reg |= CB_BCR_INTR_IREQ_ENABLE; 1549 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1550 1551 switch (sc->sc_chipset) { 1552 case CB_TI113X: 1553 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1554 /* functional intr disabled */ 1555 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1556 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1557 break; 1558 default: 1559 break; 1560 } 1561 } 1562 } 1563 1564 #if defined SHOW_REGS 1565 void 1566 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1567 bus_space_handle_t memh) 1568 { 1569 int i; 1570 printf("PCI config regs:"); 1571 for (i = 0; i < 0x50; i += 4) { 1572 if (i % 16 == 0) { 1573 printf("\n 0x%02x:", i); 1574 } 1575 printf(" %08x", pci_conf_read(pc, tag, i)); 1576 } 1577 for (i = 0x80; i < 0xb0; i += 4) { 1578 if (i % 16 == 0) { 1579 printf("\n 0x%02x:", i); 1580 } 1581 printf(" %08x", pci_conf_read(pc, tag, i)); 1582 } 1583 1584 if (memh == 0) { 1585 printf("\n"); 1586 return; 1587 } 1588 1589 printf("\nsocket regs:"); 1590 for (i = 0; i <= 0x10; i += 0x04) { 1591 printf(" %08x", bus_space_read_4(memt, memh, i)); 1592 } 1593 printf("\nExCA regs:"); 1594 for (i = 0; i < 0x08; ++i) { 1595 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1596 } 1597 printf("\n"); 1598 return; 1599 } 1600 #endif 1601 1602 /* 1603 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1604 * bus_addr_t start, bus_size_t size, 1605 * bus_size_t align, 1606 * struct pcmcia_io_handle *pcihp 1607 * 1608 * This function only allocates I/O region for pccard. This function 1609 * never maps the allocated region to pccard I/O area. 1610 * 1611 * XXX: The interface of this function is not very good, I believe. 1612 */ 1613 int 1614 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1615 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1616 { 1617 struct pcic_handle *ph = (struct pcic_handle *)pch; 1618 bus_addr_t ioaddr; 1619 int flags = 0; 1620 bus_space_tag_t iot; 1621 bus_space_handle_t ioh; 1622 bus_addr_t mask; 1623 rbus_tag_t rb; 1624 1625 if (align == 0) { 1626 align = size; /* XXX: funny??? */ 1627 } 1628 1629 if (start != 0) { 1630 /* XXX: assume all card decode lower 10 bits by its hardware */ 1631 mask = 0x3ff; 1632 /* enforce to use only masked address */ 1633 start &= mask; 1634 } else { 1635 /* 1636 * calculate mask: 1637 * 1. get the most significant bit of size (call it msb). 1638 * 2. compare msb with the value of size. 1639 * 3. if size is larger, shift msb left once. 1640 * 4. obtain mask value to decrement msb. 1641 */ 1642 bus_size_t size_tmp = size; 1643 int shifts = 0; 1644 1645 while (size_tmp) { 1646 ++shifts; 1647 size_tmp >>= 1; 1648 } 1649 mask = (1 << shifts); 1650 if (mask < size) { 1651 mask <<= 1; 1652 } 1653 mask--; 1654 } 1655 1656 /* 1657 * Allocate some arbitrary I/O space. 1658 */ 1659 1660 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1661 1662 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1663 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1664 return 1; 1665 } 1666 1667 pcihp->iot = iot; 1668 pcihp->ioh = ioh; 1669 pcihp->addr = ioaddr; 1670 pcihp->size = size; 1671 pcihp->flags = flags; 1672 1673 return 0; 1674 } 1675 1676 /* 1677 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1678 * struct pcmcia_io_handle *pcihp) 1679 * 1680 * This function only frees I/O region for pccard. 1681 * 1682 * XXX: The interface of this function is not very good, I believe. 1683 */ 1684 void 1685 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1686 struct pcmcia_io_handle *pcihp) 1687 { 1688 bus_space_handle_t ioh = pcihp->ioh; 1689 bus_size_t size = pcihp->size; 1690 1691 struct pccbb_softc *sc = 1692 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1693 rbus_tag_t rb = sc->sc_rbus_iot; 1694 1695 rbus_space_free(rb, ioh, size, NULL); 1696 } 1697 1698 /* 1699 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1700 * bus_addr_t offset, bus_size_t size, 1701 * struct pcmcia_io_handle *pcihp, 1702 * int *windowp) 1703 * 1704 * This function maps the allocated I/O region to pccard. This function 1705 * never allocates any I/O region for pccard I/O area. I don't 1706 * understand why the original authors of pcmciabus separated alloc and 1707 * map. I believe the two must be unite. 1708 * 1709 * XXX: no wait timing control? 1710 */ 1711 int 1712 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 1713 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 1714 { 1715 struct pcic_handle *ph = (struct pcic_handle *)pch; 1716 bus_addr_t ioaddr = pcihp->addr + offset; 1717 int i, win; 1718 #if defined CBB_DEBUG 1719 static char *width_names[] = { "dynamic", "io8", "io16" }; 1720 #endif 1721 1722 /* Sanity check I/O handle. */ 1723 1724 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1725 panic("pccbb_pcmcia_io_map iot is bogus"); 1726 } 1727 1728 /* XXX Sanity check offset/size. */ 1729 1730 win = -1; 1731 for (i = 0; i < PCIC_IO_WINS; i++) { 1732 if ((ph->ioalloc & (1 << i)) == 0) { 1733 win = i; 1734 ph->ioalloc |= (1 << i); 1735 break; 1736 } 1737 } 1738 1739 if (win == -1) { 1740 return 1; 1741 } 1742 1743 *windowp = win; 1744 1745 /* XXX this is pretty gross */ 1746 1747 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1748 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1749 1750 /* XXX wtf is this doing here? */ 1751 1752 #if 0 1753 printf(" port 0x%lx", (u_long) ioaddr); 1754 if (size > 1) { 1755 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1756 } 1757 #endif 1758 1759 ph->io[win].addr = ioaddr; 1760 ph->io[win].size = size; 1761 ph->io[win].width = width; 1762 1763 /* actual dirty register-value changing in the function below. */ 1764 pccbb_pcmcia_do_io_map(ph, win); 1765 1766 return 0; 1767 } 1768 1769 /* 1770 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1771 * 1772 * This function changes register-value to map I/O region for pccard. 1773 */ 1774 void 1775 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 1776 { 1777 static u_int8_t pcic_iowidth[3] = { 1778 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1779 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1780 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1781 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1782 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1783 }; 1784 1785 #define PCIC_SIA_START_LOW 0 1786 #define PCIC_SIA_START_HIGH 1 1787 #define PCIC_SIA_STOP_LOW 2 1788 #define PCIC_SIA_STOP_HIGH 3 1789 1790 int regbase_win = 0x8 + win * 0x04; 1791 u_int8_t ioctl, enable; 1792 1793 DPRINTF( 1794 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1795 win, (long)ph->io[win].addr, (long)ph->io[win].size, 1796 ph->io[win].width * 8)); 1797 1798 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1799 ph->io[win].addr & 0xff); 1800 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1801 (ph->io[win].addr >> 8) & 0xff); 1802 1803 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1804 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1805 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1806 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1807 1808 ioctl = Pcic_read(ph, PCIC_IOCTL); 1809 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1810 switch (win) { 1811 case 0: 1812 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1813 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 1814 PCIC_IOCTL_IO0_DATASIZE_MASK); 1815 ioctl |= pcic_iowidth[ph->io[win].width]; 1816 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1817 break; 1818 case 1: 1819 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1820 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 1821 PCIC_IOCTL_IO1_DATASIZE_MASK); 1822 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1823 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1824 break; 1825 } 1826 Pcic_write(ph, PCIC_IOCTL, ioctl); 1827 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1828 #if defined CBB_DEBUG 1829 { 1830 u_int8_t start_low = 1831 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1832 u_int8_t start_high = 1833 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1834 u_int8_t stop_low = 1835 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1836 u_int8_t stop_high = 1837 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1838 printf 1839 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1840 start_low, start_high, stop_low, stop_high, ioctl, enable); 1841 } 1842 #endif 1843 } 1844 1845 /* 1846 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1847 * 1848 * This function unmaps I/O region. No return value. 1849 */ 1850 void 1851 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 1852 { 1853 struct pcic_handle *ph = (struct pcic_handle *)pch; 1854 int reg; 1855 1856 if (win >= PCIC_IO_WINS || win < 0) { 1857 panic("pccbb_pcmcia_io_unmap: window out of range"); 1858 } 1859 1860 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1861 switch (win) { 1862 case 0: 1863 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1864 break; 1865 case 1: 1866 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1867 break; 1868 } 1869 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 1870 1871 ph->ioalloc &= ~(1 << win); 1872 } 1873 1874 /* 1875 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1876 * 1877 * This function enables the card. All information is stored in 1878 * the first argument, pcmcia_chipset_handle_t. 1879 */ 1880 void 1881 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1882 { 1883 int i; 1884 1885 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 1886 Pcic_read(ph, PCIC_IF_STATUS))); 1887 1888 for (i = 0; i < 10000; i++) { 1889 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1890 return; 1891 } 1892 delay(500); 1893 #ifdef CBB_DEBUG 1894 if ((i > 5000) && (i % 100 == 99)) 1895 printf("."); 1896 #endif 1897 } 1898 1899 #ifdef DIAGNOSTIC 1900 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1901 Pcic_read(ph, PCIC_IF_STATUS)); 1902 #endif 1903 } 1904 1905 /* 1906 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 1907 * 1908 * This function enables the card. All information is stored in 1909 * the first argument, pcmcia_chipset_handle_t. 1910 */ 1911 void 1912 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 1913 { 1914 struct pcic_handle *ph = (struct pcic_handle *)pch; 1915 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 1916 int cardtype, win; 1917 u_int8_t power, intr; 1918 pcireg_t spsr; 1919 int voltage; 1920 1921 /* this bit is mostly stolen from pcic_attach_card */ 1922 1923 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 1924 1925 /* get card Vcc info */ 1926 1927 spsr = 1928 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1929 CB_SOCKET_STAT); 1930 if (spsr & CB_SOCKET_STAT_5VCARD) { 1931 DPRINTF(("5V card\n")); 1932 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 1933 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 1934 DPRINTF(("3V card\n")); 1935 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 1936 } else { 1937 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 1938 return; 1939 } 1940 1941 /* disable socket i/o: negate output enable bit */ 1942 1943 power = 0; 1944 Pcic_write(ph, PCIC_PWRCTL, power); 1945 1946 /* power down the socket to reset it, clear the card reset pin */ 1947 1948 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 1949 1950 /* 1951 * wait 200ms until power fails (Tpf). Then, wait 100ms since 1952 * we are changing Vcc (Toff). 1953 */ 1954 /* delay(300*1000); too much */ 1955 1956 /* assert reset bit */ 1957 intr = Pcic_read(ph, PCIC_INTR); 1958 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 1959 Pcic_write(ph, PCIC_INTR, intr); 1960 1961 /* Power up the socket. */ 1962 power = Pcic_read(ph, PCIC_PWRCTL); 1963 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 1964 pccbb_power((cardbus_chipset_tag_t)sc, voltage); 1965 1966 /* Now output enable */ 1967 power = Pcic_read(ph, PCIC_PWRCTL); 1968 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 1969 1970 /* 1971 * hold RESET at least 10us. 1972 */ 1973 delay(10); 1974 delay(2 * 1000); /* XXX: TI1130 requires it. */ 1975 delay(20 * 1000); /* XXX: TI1130 requires it. */ 1976 1977 /* clear the reset flag */ 1978 1979 intr |= PCIC_INTR_RESET; 1980 Pcic_write(ph, PCIC_INTR, intr); 1981 1982 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1983 1984 delay(20000); 1985 1986 /* wait for the chip to finish initializing */ 1987 1988 pccbb_pcmcia_wait_ready(ph); 1989 1990 /* zero out the address windows */ 1991 1992 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 1993 1994 /* set the card type */ 1995 1996 cardtype = pcmcia_card_gettype(ph->pcmcia); 1997 1998 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1999 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2000 Pcic_write(ph, PCIC_INTR, intr); 2001 2002 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2003 ph->ph_parent->dv_xname, ph->sock, 2004 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2005 2006 /* reinstall all the memory and io mappings */ 2007 2008 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2009 if (ph->memalloc & (1 << win)) { 2010 pccbb_pcmcia_do_mem_map(ph, win); 2011 } 2012 } 2013 2014 for (win = 0; win < PCIC_IO_WINS; ++win) { 2015 if (ph->ioalloc & (1 << win)) { 2016 pccbb_pcmcia_do_io_map(ph, win); 2017 } 2018 } 2019 } 2020 2021 /* 2022 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2023 * 2024 * This function disables the card. All information is stored in 2025 * the first argument, pcmcia_chipset_handle_t. 2026 */ 2027 void 2028 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2029 { 2030 struct pcic_handle *ph = (struct pcic_handle *)pch; 2031 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2032 u_int8_t power, intr; 2033 2034 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2035 2036 /* reset signal asserting... */ 2037 2038 intr = Pcic_read(ph, PCIC_INTR); 2039 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2040 Pcic_write(ph, PCIC_INTR, intr); 2041 delay(2 * 1000); 2042 2043 /* power down the socket */ 2044 power = Pcic_read(ph, PCIC_PWRCTL); 2045 power &= ~PCIC_PWRCTL_OE; 2046 Pcic_write(ph, PCIC_PWRCTL, power); 2047 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2048 /* 2049 * wait 300ms until power fails (Tpf). 2050 */ 2051 delay(300 * 1000); 2052 } 2053 2054 /* 2055 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2056 * 2057 * This function detects whether a card is in the slot or not. 2058 * If a card is inserted, return 1. Otherwise, return 0. 2059 */ 2060 int 2061 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2062 { 2063 struct pcic_handle *ph = (struct pcic_handle *)pch; 2064 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2065 2066 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2067 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2068 } 2069 2070 /* 2071 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2072 * bus_size_t size, 2073 * struct pcmcia_mem_handle *pcmhp) 2074 * 2075 * This function only allocates memory region for pccard. This 2076 * function never maps the allocated region to pccard memory area. 2077 * 2078 * XXX: Why the argument of start address is not in? 2079 */ 2080 int 2081 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2082 struct pcmcia_mem_handle *pcmhp) 2083 { 2084 struct pcic_handle *ph = (struct pcic_handle *)pch; 2085 bus_space_handle_t memh; 2086 bus_addr_t addr; 2087 bus_size_t sizepg; 2088 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2089 rbus_tag_t rb; 2090 2091 /* out of sc->memh, allocate as many pages as necessary */ 2092 2093 /* convert size to PCIC pages */ 2094 /* 2095 * This is not enough; when the requested region is on the page 2096 * boundaries, this may calculate wrong result. 2097 */ 2098 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2099 #if 0 2100 if (sizepg > PCIC_MAX_MEM_PAGES) { 2101 return 1; 2102 } 2103 #endif 2104 2105 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2106 return 1; 2107 } 2108 2109 addr = 0; /* XXX gcc -Wuninitialized */ 2110 2111 rb = sc->sc_rbus_memt; 2112 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2113 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2114 &addr, &memh)) { 2115 return 1; 2116 } 2117 2118 DPRINTF( 2119 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2120 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2121 2122 pcmhp->memt = sc->sc_memt; 2123 pcmhp->memh = memh; 2124 pcmhp->addr = addr; 2125 pcmhp->size = size; 2126 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2127 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2128 pcmhp->mhandle = 0; 2129 /* No offset??? Funny. */ 2130 2131 return 0; 2132 } 2133 2134 /* 2135 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2136 * struct pcmcia_mem_handle *pcmhp) 2137 * 2138 * This function release the memory space allocated by the function 2139 * pccbb_pcmcia_mem_alloc(). 2140 */ 2141 void 2142 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2143 struct pcmcia_mem_handle *pcmhp) 2144 { 2145 struct pcic_handle *ph = (struct pcic_handle *)pch; 2146 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2147 2148 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2149 } 2150 2151 /* 2152 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2153 * 2154 * This function release the memory space allocated by the function 2155 * pccbb_pcmcia_mem_alloc(). 2156 */ 2157 void 2158 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2159 { 2160 int regbase_win; 2161 bus_addr_t phys_addr; 2162 bus_addr_t phys_end; 2163 2164 #define PCIC_SMM_START_LOW 0 2165 #define PCIC_SMM_START_HIGH 1 2166 #define PCIC_SMM_STOP_LOW 2 2167 #define PCIC_SMM_STOP_HIGH 3 2168 #define PCIC_CMA_LOW 4 2169 #define PCIC_CMA_HIGH 5 2170 2171 u_int8_t start_low, start_high = 0; 2172 u_int8_t stop_low, stop_high; 2173 u_int8_t off_low, off_high; 2174 u_int8_t mem_window; 2175 int reg; 2176 2177 regbase_win = 0x10 + win * 0x08; 2178 2179 phys_addr = ph->mem[win].addr; 2180 phys_end = phys_addr + ph->mem[win].size; 2181 2182 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2183 phys_addr, phys_end, ph->mem[win].offset)); 2184 2185 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2186 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2187 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2188 2189 /* bit 19:12 */ 2190 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2191 /* bit 23:20 and bit 7 on */ 2192 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2193 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2194 /* bit 31:24, for 32-bit address */ 2195 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2196 2197 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2198 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2199 2200 if (((struct pccbb_softc *)ph-> 2201 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2202 Pcic_write(ph, 0x40 + win, mem_window); 2203 } 2204 2205 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2206 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2207 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2208 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2209 2210 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2211 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2212 2213 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2214 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2215 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2216 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2217 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2218 2219 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2220 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2221 2222 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2223 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2224 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2225 2226 #if defined CBB_DEBUG 2227 { 2228 int r1, r2, r3, r4, r5, r6, r7 = 0; 2229 2230 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2231 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2232 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2233 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2234 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2235 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2236 if (((struct pccbb_softc *)(ph-> 2237 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2238 r7 = Pcic_read(ph, 0x40 + win); 2239 } 2240 2241 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2242 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2243 if (((struct pccbb_softc *)(ph-> 2244 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2245 DPRINTF((" %02x", r7)); 2246 } 2247 DPRINTF(("\n")); 2248 } 2249 #endif 2250 } 2251 2252 /* 2253 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2254 * bus_addr_t card_addr, bus_size_t size, 2255 * struct pcmcia_mem_handle *pcmhp, 2256 * bus_size_t *offsetp, int *windowp) 2257 * 2258 * This function maps memory space allocated by the function 2259 * pccbb_pcmcia_mem_alloc(). 2260 */ 2261 int 2262 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2263 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2264 bus_size_t *offsetp, int *windowp) 2265 { 2266 struct pcic_handle *ph = (struct pcic_handle *)pch; 2267 bus_addr_t busaddr; 2268 long card_offset; 2269 int win; 2270 2271 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2272 if ((ph->memalloc & (1 << win)) == 0) { 2273 ph->memalloc |= (1 << win); 2274 break; 2275 } 2276 } 2277 2278 if (win == PCIC_MEM_WINS) { 2279 return 1; 2280 } 2281 2282 *windowp = win; 2283 2284 /* XXX this is pretty gross */ 2285 2286 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2287 panic("pccbb_pcmcia_mem_map memt is bogus"); 2288 } 2289 2290 busaddr = pcmhp->addr; 2291 2292 /* 2293 * compute the address offset to the pcmcia address space for the 2294 * pcic. this is intentionally signed. The masks and shifts below 2295 * will cause TRT to happen in the pcic registers. Deal with making 2296 * sure the address is aligned, and return the alignment offset. 2297 */ 2298 2299 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2300 card_addr -= *offsetp; 2301 2302 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2303 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2304 (u_long) card_addr)); 2305 2306 /* 2307 * include the offset in the size, and decrement size by one, since 2308 * the hw wants start/stop 2309 */ 2310 size += *offsetp - 1; 2311 2312 card_offset = (((long)card_addr) - ((long)busaddr)); 2313 2314 ph->mem[win].addr = busaddr; 2315 ph->mem[win].size = size; 2316 ph->mem[win].offset = card_offset; 2317 ph->mem[win].kind = kind; 2318 2319 pccbb_pcmcia_do_mem_map(ph, win); 2320 2321 return 0; 2322 } 2323 2324 /* 2325 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2326 * int window) 2327 * 2328 * This function unmaps memory space which mapped by the function 2329 * pccbb_pcmcia_mem_map(). 2330 */ 2331 void 2332 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2333 { 2334 struct pcic_handle *ph = (struct pcic_handle *)pch; 2335 int reg; 2336 2337 if (window >= PCIC_MEM_WINS) { 2338 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2339 } 2340 2341 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2342 reg &= ~(1 << window); 2343 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2344 2345 ph->memalloc &= ~(1 << window); 2346 } 2347 2348 #if defined PCCBB_PCMCIA_POLL 2349 struct pccbb_poll_str { 2350 void *arg; 2351 int (*func)(void *); 2352 int level; 2353 struct pcic_handle *ph; 2354 int count; 2355 int num; 2356 }; 2357 2358 static struct pccbb_poll_str pccbb_poll[10]; 2359 static int pccbb_poll_n = 0; 2360 static struct timeout pccbb_poll_timeout; 2361 2362 void pccbb_pcmcia_poll(void *arg); 2363 2364 void 2365 pccbb_pcmcia_poll(void *arg) 2366 { 2367 struct pccbb_poll_str *poll = arg; 2368 struct pcic_handle *ph = poll->ph; 2369 struct pccbb_softc *sc = ph->sc; 2370 int s; 2371 u_int32_t spsr; /* socket present-state reg */ 2372 2373 timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg); 2374 timeout_add_sec(&pccbb_poll_timeout, 2); 2375 switch (poll->level) { 2376 case IPL_NET: 2377 s = splnet(); 2378 break; 2379 case IPL_BIO: 2380 s = splbio(); 2381 break; 2382 case IPL_TTY: /* fallthrough */ 2383 default: 2384 s = spltty(); 2385 break; 2386 } 2387 2388 spsr = 2389 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2390 CB_SOCKET_STAT); 2391 2392 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2393 if (!(spsr & 0x40)) /* CINT low */ 2394 #else 2395 if (1) 2396 #endif 2397 { 2398 if ((*poll->func) (poll->arg) > 0) { 2399 ++poll->count; 2400 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2401 #if defined LEVEL2 2402 } else { 2403 printf("intr: miss! 0x%x\n", spsr); 2404 #endif 2405 } 2406 } 2407 splx(s); 2408 } 2409 #endif /* defined CB_PCMCIA_POLL */ 2410 2411 /* 2412 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2413 * struct pcmcia_function *pf, 2414 * int ipl, 2415 * int (*func)(void *), 2416 * void *arg); 2417 * 2418 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2419 */ 2420 void * 2421 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2422 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg, 2423 char *xname) 2424 { 2425 struct pcic_handle *ph = (struct pcic_handle *)pch; 2426 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2427 2428 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2429 /* what should I do? */ 2430 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2431 DPRINTF( 2432 ("%s does not provide edge nor pulse interrupt\n", 2433 sc->sc_dev.dv_xname)); 2434 return NULL; 2435 } 2436 /* 2437 * XXX Noooooo! The interrupt flag must set properly!! 2438 * dumb pcmcia driver!! 2439 */ 2440 } 2441 2442 return pccbb_intr_establish(sc, -1, ipl, func, arg, xname); 2443 } 2444 2445 /* 2446 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2447 * void *ih) 2448 * 2449 * This function disables PC-Card interrupt. 2450 */ 2451 void 2452 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2453 { 2454 struct pcic_handle *ph = (struct pcic_handle *)pch; 2455 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2456 2457 pccbb_intr_disestablish(sc, ih); 2458 } 2459 2460 const char * 2461 pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t pch, void *ih) 2462 { 2463 if (ih == NULL) 2464 return "couldn't establish interrupt"; 2465 else 2466 return ""; /* card shares interrupt of the bridge */ 2467 } 2468 2469 /* 2470 * int 2471 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2472 * bus_addr_t addr, bus_size_t size, 2473 * bus_addr_t mask, bus_size_t align, 2474 * int flags, bus_addr_t *addrp; 2475 * bus_space_handle_t *bshp) 2476 * 2477 * This function allocates a portion of memory or io space for 2478 * clients. This function is called from CardBus card drivers. 2479 */ 2480 int 2481 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2482 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2483 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2484 { 2485 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2486 2487 DPRINTF( 2488 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2489 addr, size, mask, align)); 2490 2491 align = max(align, 4); 2492 mask = max(mask, (4 - 1)); 2493 if (rb->rb_bt == sc->sc_memt) { 2494 align = max(align, 0x1000); 2495 mask = max(mask, (0x1000 - 1)); 2496 } 2497 2498 if (rb->rb_bt == sc->sc_iot) { 2499 /* XXX: hack for avoiding ISA image */ 2500 if (mask < 0x0100) { 2501 mask = 0x3ff; 2502 addr = 0x300; 2503 } 2504 } 2505 2506 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2507 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2508 return 1; 2509 } 2510 2511 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2512 2513 return 0; 2514 } 2515 2516 /* 2517 * int 2518 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2519 * bus_space_handle_t *bshp, bus_size_t size); 2520 * 2521 * This function is called from CardBus card drivers. 2522 */ 2523 int 2524 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2525 bus_space_handle_t bsh, bus_size_t size) 2526 { 2527 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2528 bus_space_tag_t bt = rb->rb_bt; 2529 2530 pccbb_close_win(sc, bt, bsh, size); 2531 2532 if (bt == sc->sc_memt) { 2533 } else if (bt == sc->sc_iot) { 2534 } else { 2535 return 1; 2536 /* XXX: panic here? */ 2537 } 2538 2539 return rbus_space_free(rb, bsh, size, NULL); 2540 } 2541 2542 int 2543 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2544 bus_size_t size, bus_space_handle_t bsh, int flags) 2545 { 2546 struct pccbb_win_chain_head *head; 2547 bus_addr_t align; 2548 2549 head = &sc->sc_iowindow; 2550 align = 0x04; 2551 if (sc->sc_memt == bst) { 2552 head = &sc->sc_memwindow; 2553 align = 0x1000; 2554 DPRINTF(("using memory window, %x %x %x\n\n", 2555 sc->sc_iot, sc->sc_memt, bst)); 2556 } 2557 2558 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2559 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2560 sc->sc_dev.dv_xname, 2561 (head == &sc->sc_memwindow) ? "mem" : "io"); 2562 } 2563 pccbb_winset(align, sc, bst); 2564 2565 return 0; 2566 } 2567 2568 int 2569 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2570 bus_space_handle_t bsh, bus_size_t size) 2571 { 2572 struct pccbb_win_chain_head *head; 2573 bus_addr_t align; 2574 2575 head = &sc->sc_iowindow; 2576 align = 0x04; 2577 if (sc->sc_memt == bst) { 2578 head = &sc->sc_memwindow; 2579 align = 0x1000; 2580 } 2581 2582 if (pccbb_winlist_delete(head, bsh, size)) { 2583 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2584 sc->sc_dev.dv_xname, 2585 (head == &sc->sc_memwindow) ? "mem" : "io"); 2586 } 2587 pccbb_winset(align, sc, bst); 2588 2589 return 0; 2590 } 2591 2592 int 2593 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2594 bus_size_t size, bus_space_handle_t bsh, int flags) 2595 { 2596 struct pccbb_win_chain *chainp, *elem; 2597 2598 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2599 M_NOWAIT)) == NULL) 2600 return (1); /* fail */ 2601 2602 elem->wc_start = start; 2603 elem->wc_end = start + (size - 1); 2604 elem->wc_handle = bsh; 2605 elem->wc_flags = flags; 2606 2607 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2608 chainp = TAILQ_NEXT(chainp, wc_list)) { 2609 if (chainp->wc_end < start) 2610 continue; 2611 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2612 return (0); 2613 } 2614 2615 TAILQ_INSERT_TAIL(head, elem, wc_list); 2616 return (0); 2617 } 2618 2619 int 2620 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2621 bus_size_t size) 2622 { 2623 struct pccbb_win_chain *chainp; 2624 2625 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2626 chainp = TAILQ_NEXT(chainp, wc_list)) { 2627 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 2628 continue; 2629 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2630 printf("pccbb_winlist_delete: window 0x%lx size " 2631 "inconsistent: 0x%lx, 0x%lx\n", 2632 chainp->wc_start, 2633 chainp->wc_end - chainp->wc_start, 2634 size - 1); 2635 return 1; 2636 } 2637 2638 TAILQ_REMOVE(head, chainp, wc_list); 2639 free(chainp, M_DEVBUF, sizeof *chainp); 2640 2641 return 0; 2642 } 2643 2644 return 1; /* fail: no candidate to remove */ 2645 } 2646 2647 void 2648 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 2649 { 2650 pci_chipset_tag_t pc; 2651 pcitag_t tag; 2652 bus_addr_t mask = ~(align - 1); 2653 struct { 2654 pcireg_t win_start; 2655 pcireg_t win_limit; 2656 int win_flags; 2657 } win[2]; 2658 struct pccbb_win_chain *chainp; 2659 int offs; 2660 2661 win[0].win_start = win[1].win_start = 0xffffffff; 2662 win[0].win_limit = win[1].win_limit = 0; 2663 win[0].win_flags = win[1].win_flags = 0; 2664 2665 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2666 offs = PCI_CB_IOBASE0; 2667 if (sc->sc_memt == bst) { 2668 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2669 offs = PCI_CB_MEMBASE0; 2670 } 2671 2672 if (chainp != NULL) { 2673 win[0].win_start = chainp->wc_start & mask; 2674 win[0].win_limit = chainp->wc_end & mask; 2675 win[0].win_flags = chainp->wc_flags; 2676 chainp = TAILQ_NEXT(chainp, wc_list); 2677 } 2678 2679 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2680 if (win[1].win_start == 0xffffffff) { 2681 /* window 1 is not used */ 2682 if ((win[0].win_flags == chainp->wc_flags) && 2683 (win[0].win_limit + align >= 2684 (chainp->wc_start & mask))) { 2685 /* concatenate */ 2686 win[0].win_limit = chainp->wc_end & mask; 2687 } else { 2688 /* make new window */ 2689 win[1].win_start = chainp->wc_start & mask; 2690 win[1].win_limit = chainp->wc_end & mask; 2691 win[1].win_flags = chainp->wc_flags; 2692 } 2693 continue; 2694 } 2695 2696 /* Both windows are engaged. */ 2697 if (win[0].win_flags == win[1].win_flags) { 2698 /* same flags */ 2699 if (win[0].win_flags == chainp->wc_flags) { 2700 if (win[1].win_start - (win[0].win_limit + 2701 align) < 2702 (chainp->wc_start & mask) - 2703 ((chainp->wc_end & mask) + align)) { 2704 /* 2705 * merge window 0 and 1, and set win1 2706 * to chainp 2707 */ 2708 win[0].win_limit = win[1].win_limit; 2709 win[1].win_start = 2710 chainp->wc_start & mask; 2711 win[1].win_limit = 2712 chainp->wc_end & mask; 2713 } else { 2714 win[1].win_limit = 2715 chainp->wc_end & mask; 2716 } 2717 } else { 2718 /* different flags */ 2719 2720 /* concatenate win0 and win1 */ 2721 win[0].win_limit = win[1].win_limit; 2722 /* allocate win[1] to new space */ 2723 win[1].win_start = chainp->wc_start & mask; 2724 win[1].win_limit = chainp->wc_end & mask; 2725 win[1].win_flags = chainp->wc_flags; 2726 } 2727 } else { 2728 /* the flags of win[0] and win[1] are different */ 2729 if (win[0].win_flags == chainp->wc_flags) { 2730 win[0].win_limit = chainp->wc_end & mask; 2731 /* 2732 * XXX this creates overlapping windows, so 2733 * what should the poor bridge do if one is 2734 * cachable, and the other is not? 2735 */ 2736 printf("%s: overlapping windows\n", 2737 sc->sc_dev.dv_xname); 2738 } else { 2739 win[1].win_limit = chainp->wc_end & mask; 2740 } 2741 } 2742 } 2743 2744 pc = sc->sc_pc; 2745 tag = sc->sc_tag; 2746 pci_conf_write(pc, tag, offs, win[0].win_start); 2747 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 2748 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 2749 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 2750 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 2751 pci_conf_read(pc, tag, offs), 2752 pci_conf_read(pc, tag, offs + 4) + align, 2753 pci_conf_read(pc, tag, offs + 8), 2754 pci_conf_read(pc, tag, offs + 12) + align)); 2755 2756 if (bst == sc->sc_memt) { 2757 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 2758 2759 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 2760 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 2761 bcr |= CB_BCR_PREFETCH_MEMWIN0; 2762 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 2763 bcr |= CB_BCR_PREFETCH_MEMWIN1; 2764 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 2765 } 2766 } 2767 2768 int 2769 pccbbactivate(struct device *self, int act) 2770 { 2771 struct pccbb_softc *sc = (struct pccbb_softc *)self; 2772 pci_chipset_tag_t pc = sc->sc_pc; 2773 pcitag_t tag = sc->sc_tag; 2774 pcireg_t csr; 2775 u_int32_t reg; 2776 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 2777 bus_space_handle_t base_memh = sc->sc_base_memh; 2778 int rv = 0; 2779 2780 switch (act) { 2781 case DVACT_SUSPEND: 2782 rv = config_activate_children(self, act); 2783 2784 sc->sc_pil_intr_enable = 0; 2785 2786 /* Save registers that may get lost. */ 2787 sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 2788 sc->sc_bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 2789 sc->sc_int = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 2790 2791 sc->sc_sockbase = pci_conf_read(pc, tag, PCI_SOCKBASE); 2792 sc->sc_busnum = pci_conf_read(pc, tag, PCI_BUSNUM); 2793 2794 sc->sc_membase[0] = pci_conf_read(pc, tag, PCI_CB_MEMBASE0); 2795 sc->sc_memlimit[0] = pci_conf_read(pc, tag, PCI_CB_MEMLIMIT0); 2796 sc->sc_membase[1] = pci_conf_read(pc, tag, PCI_CB_MEMBASE1); 2797 sc->sc_memlimit[1] = pci_conf_read(pc, tag, PCI_CB_MEMLIMIT1); 2798 sc->sc_iobase[0] = pci_conf_read(pc, tag, PCI_CB_IOBASE0); 2799 sc->sc_iolimit[0] = pci_conf_read(pc, tag, PCI_CB_IOLIMIT0); 2800 sc->sc_iobase[1] = pci_conf_read(pc, tag, PCI_CB_IOBASE1); 2801 sc->sc_iolimit[1] = pci_conf_read(pc, tag, PCI_CB_IOLIMIT1); 2802 break; 2803 case DVACT_RESUME: 2804 /* Restore the registers saved above. */ 2805 pci_conf_write(pc, tag, PCI_BHLC_REG, sc->sc_bhlcr); 2806 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, sc->sc_int); 2807 2808 pci_conf_write(pc, tag, PCI_SOCKBASE, sc->sc_sockbase); 2809 pci_conf_write(pc, tag, PCI_BUSNUM, sc->sc_busnum); 2810 2811 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, sc->sc_membase[0]); 2812 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, sc->sc_memlimit[0]); 2813 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, sc->sc_membase[1]); 2814 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, sc->sc_memlimit[1]); 2815 pci_conf_write(pc, tag, PCI_CB_IOBASE0, sc->sc_iobase[0]); 2816 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, sc->sc_iolimit[0]); 2817 pci_conf_write(pc, tag, PCI_CB_IOBASE1, sc->sc_iobase[1]); 2818 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, sc->sc_iolimit[1]); 2819 2820 /* Disable legacy register mapping. */ 2821 pccbb_legacy_disable(sc); 2822 2823 /* 2824 * Restore command register last to avoid exposing 2825 * uninitialised windows. 2826 */ 2827 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 2828 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 2829 (csr & 0xffff0000) | (sc->sc_csr & 0x0000ffff)); 2830 2831 /* CSC Interrupt: Card detect interrupt on */ 2832 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 2833 /* Card detect intr is turned on. */ 2834 reg |= CB_SOCKET_MASK_CD; 2835 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 2836 2837 /* reset interrupt */ 2838 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 2839 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 2840 2841 /* re-check all cards */ 2842 pccbb_checksockstat(sc); 2843 2844 /* 2845 * XXX Because the cardslot stuff is so obfuscated with threads, 2846 * here we are activating children which may have been 2847 * ejected while we were asleep. This needs to be solved. 2848 */ 2849 rv = config_activate_children(self, act); 2850 2851 sc->sc_pil_intr_enable = 1; 2852 break; 2853 case DVACT_POWERDOWN: 2854 rv = config_activate_children(self, act); 2855 pccbb_shutdown(self); 2856 break; 2857 default: 2858 rv = config_activate_children(self, act); 2859 break; 2860 } 2861 return (rv); 2862 } 2863