1 /* $OpenBSD: pci.c,v 1.118 2020/06/26 10:16:00 dlg Exp $ */ 2 /* $NetBSD: pci.c,v 1.31 1997/06/06 23:48:04 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/ppbreg.h> 47 48 int pcimatch(struct device *, void *, void *); 49 void pciattach(struct device *, struct device *, void *); 50 int pcidetach(struct device *, int); 51 int pciactivate(struct device *, int); 52 void pci_suspend(struct pci_softc *); 53 void pci_powerdown(struct pci_softc *); 54 void pci_resume(struct pci_softc *); 55 56 struct msix_vector { 57 uint32_t mv_ma; 58 uint32_t mv_mau32; 59 uint32_t mv_md; 60 uint32_t mv_vc; 61 }; 62 63 #define NMAPREG ((PCI_MAPREG_END - PCI_MAPREG_START) / \ 64 sizeof(pcireg_t)) 65 struct pci_dev { 66 struct device *pd_dev; 67 LIST_ENTRY(pci_dev) pd_next; 68 pcitag_t pd_tag; /* pci register tag */ 69 pcireg_t pd_csr; 70 pcireg_t pd_bhlc; 71 pcireg_t pd_int; 72 pcireg_t pd_map[NMAPREG]; 73 pcireg_t pd_mask[NMAPREG]; 74 pcireg_t pd_msi_mc; 75 pcireg_t pd_msi_ma; 76 pcireg_t pd_msi_mau32; 77 pcireg_t pd_msi_md; 78 pcireg_t pd_msix_mc; 79 struct msix_vector *pd_msix_table; 80 int pd_pmcsr_state; 81 int pd_vga_decode; 82 }; 83 84 #ifdef APERTURE 85 extern int allowaperture; 86 #endif 87 88 struct cfattach pci_ca = { 89 sizeof(struct pci_softc), pcimatch, pciattach, pcidetach, pciactivate 90 }; 91 92 struct cfdriver pci_cd = { 93 NULL, "pci", DV_DULL 94 }; 95 96 int pci_ndomains; 97 98 struct proc *pci_vga_proc; 99 struct pci_softc *pci_vga_pci; 100 pcitag_t pci_vga_tag; 101 102 int pci_dopm; 103 104 int pciprint(void *, const char *); 105 int pcisubmatch(struct device *, void *, void *); 106 107 #ifdef PCI_MACHDEP_ENUMERATE_BUS 108 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 109 #else 110 int pci_enumerate_bus(struct pci_softc *, 111 int (*)(struct pci_attach_args *), struct pci_attach_args *); 112 #endif 113 int pci_reserve_resources(struct pci_attach_args *); 114 int pci_primary_vga(struct pci_attach_args *); 115 116 /* 117 * Important note about PCI-ISA bridges: 118 * 119 * Callbacks are used to configure these devices so that ISA/EISA bridges 120 * can attach their child busses after PCI configuration is done. 121 * 122 * This works because: 123 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 124 * (2) any ISA/EISA bridges must be attached to primary PCI 125 * busses (i.e. bus zero). 126 * 127 * That boils down to: there can only be one of these outstanding 128 * at a time, it is cleared when configuring PCI bus 0 before any 129 * subdevices have been found, and it is run after all subdevices 130 * of PCI bus 0 have been found. 131 * 132 * This is needed because there are some (legacy) PCI devices which 133 * can show up as ISA/EISA devices as well (the prime example of which 134 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 135 * and the bridge is seen before the video board is, the board can show 136 * up as an ISA device, and that can (bogusly) complicate the PCI device's 137 * attach code, or make the PCI device not be properly attached at all. 138 * 139 * We use the generic config_defer() facility to achieve this. 140 */ 141 142 int 143 pcimatch(struct device *parent, void *match, void *aux) 144 { 145 struct cfdata *cf = match; 146 struct pcibus_attach_args *pba = aux; 147 148 if (strcmp(pba->pba_busname, cf->cf_driver->cd_name)) 149 return (0); 150 151 /* Check the locators */ 152 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 153 cf->pcibuscf_bus != pba->pba_bus) 154 return (0); 155 156 /* sanity */ 157 if (pba->pba_bus < 0 || pba->pba_bus > 255) 158 return (0); 159 160 /* 161 * XXX check other (hardware?) indicators 162 */ 163 164 return (1); 165 } 166 167 void 168 pciattach(struct device *parent, struct device *self, void *aux) 169 { 170 struct pcibus_attach_args *pba = aux; 171 struct pci_softc *sc = (struct pci_softc *)self; 172 173 pci_attach_hook(parent, self, pba); 174 175 printf("\n"); 176 177 LIST_INIT(&sc->sc_devs); 178 179 sc->sc_iot = pba->pba_iot; 180 sc->sc_memt = pba->pba_memt; 181 sc->sc_dmat = pba->pba_dmat; 182 sc->sc_pc = pba->pba_pc; 183 sc->sc_flags = pba->pba_flags; 184 sc->sc_ioex = pba->pba_ioex; 185 sc->sc_memex = pba->pba_memex; 186 sc->sc_pmemex = pba->pba_pmemex; 187 sc->sc_busex = pba->pba_busex; 188 sc->sc_domain = pba->pba_domain; 189 sc->sc_bus = pba->pba_bus; 190 sc->sc_bridgetag = pba->pba_bridgetag; 191 sc->sc_bridgeih = pba->pba_bridgeih; 192 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 193 sc->sc_intrswiz = pba->pba_intrswiz; 194 sc->sc_intrtag = pba->pba_intrtag; 195 196 /* Reserve our own bus number. */ 197 if (sc->sc_busex) 198 extent_alloc_region(sc->sc_busex, sc->sc_bus, 1, EX_NOWAIT); 199 200 pci_enumerate_bus(sc, pci_reserve_resources, NULL); 201 202 /* Find the VGA device that's currently active. */ 203 if (pci_enumerate_bus(sc, pci_primary_vga, NULL)) 204 pci_vga_pci = sc; 205 206 pci_enumerate_bus(sc, NULL, NULL); 207 } 208 209 int 210 pcidetach(struct device *self, int flags) 211 { 212 return pci_detach_devices((struct pci_softc *)self, flags); 213 } 214 215 int 216 pciactivate(struct device *self, int act) 217 { 218 int rv = 0; 219 220 switch (act) { 221 case DVACT_SUSPEND: 222 rv = config_activate_children(self, act); 223 pci_suspend((struct pci_softc *)self); 224 break; 225 case DVACT_RESUME: 226 pci_resume((struct pci_softc *)self); 227 rv = config_activate_children(self, act); 228 break; 229 case DVACT_POWERDOWN: 230 rv = config_activate_children(self, act); 231 pci_powerdown((struct pci_softc *)self); 232 break; 233 default: 234 rv = config_activate_children(self, act); 235 break; 236 } 237 return (rv); 238 } 239 240 void 241 pci_suspend(struct pci_softc *sc) 242 { 243 struct pci_dev *pd; 244 pcireg_t bhlc, reg; 245 int off, i; 246 247 LIST_FOREACH(pd, &sc->sc_devs, pd_next) { 248 /* 249 * Only handle header type 0 here; PCI-PCI bridges and 250 * CardBus bridges need special handling, which will 251 * be done in their specific drivers. 252 */ 253 bhlc = pci_conf_read(sc->sc_pc, pd->pd_tag, PCI_BHLC_REG); 254 if (PCI_HDRTYPE_TYPE(bhlc) != 0) 255 continue; 256 257 /* Save registers that may get lost. */ 258 for (i = 0; i < NMAPREG; i++) 259 pd->pd_map[i] = pci_conf_read(sc->sc_pc, pd->pd_tag, 260 PCI_MAPREG_START + (i * 4)); 261 pd->pd_csr = pci_conf_read(sc->sc_pc, pd->pd_tag, 262 PCI_COMMAND_STATUS_REG); 263 pd->pd_bhlc = pci_conf_read(sc->sc_pc, pd->pd_tag, 264 PCI_BHLC_REG); 265 pd->pd_int = pci_conf_read(sc->sc_pc, pd->pd_tag, 266 PCI_INTERRUPT_REG); 267 268 if (pci_get_capability(sc->sc_pc, pd->pd_tag, 269 PCI_CAP_MSI, &off, ®)) { 270 pd->pd_msi_ma = pci_conf_read(sc->sc_pc, pd->pd_tag, 271 off + PCI_MSI_MA); 272 if (reg & PCI_MSI_MC_C64) { 273 pd->pd_msi_mau32 = pci_conf_read(sc->sc_pc, 274 pd->pd_tag, off + PCI_MSI_MAU32); 275 pd->pd_msi_md = pci_conf_read(sc->sc_pc, 276 pd->pd_tag, off + PCI_MSI_MD64); 277 } else { 278 pd->pd_msi_md = pci_conf_read(sc->sc_pc, 279 pd->pd_tag, off + PCI_MSI_MD32); 280 } 281 pd->pd_msi_mc = reg; 282 } 283 284 pci_suspend_msix(sc->sc_pc, pd->pd_tag, sc->sc_memt, 285 &pd->pd_msix_mc, pd->pd_msix_table); 286 } 287 } 288 289 void 290 pci_powerdown(struct pci_softc *sc) 291 { 292 struct pci_dev *pd; 293 pcireg_t bhlc; 294 295 LIST_FOREACH(pd, &sc->sc_devs, pd_next) { 296 /* 297 * Only handle header type 0 here; PCI-PCI bridges and 298 * CardBus bridges need special handling, which will 299 * be done in their specific drivers. 300 */ 301 bhlc = pci_conf_read(sc->sc_pc, pd->pd_tag, PCI_BHLC_REG); 302 if (PCI_HDRTYPE_TYPE(bhlc) != 0) 303 continue; 304 305 if (pci_dopm) { 306 /* 307 * Place the device into the lowest possible 308 * power state. 309 */ 310 pd->pd_pmcsr_state = pci_get_powerstate(sc->sc_pc, 311 pd->pd_tag); 312 pci_set_powerstate(sc->sc_pc, pd->pd_tag, 313 pci_min_powerstate(sc->sc_pc, pd->pd_tag)); 314 } 315 } 316 } 317 318 void 319 pci_resume(struct pci_softc *sc) 320 { 321 struct pci_dev *pd; 322 pcireg_t bhlc, reg; 323 int off, i; 324 325 LIST_FOREACH(pd, &sc->sc_devs, pd_next) { 326 /* 327 * Only handle header type 0 here; PCI-PCI bridges and 328 * CardBus bridges need special handling, which will 329 * be done in their specific drivers. 330 */ 331 bhlc = pci_conf_read(sc->sc_pc, pd->pd_tag, PCI_BHLC_REG); 332 if (PCI_HDRTYPE_TYPE(bhlc) != 0) 333 continue; 334 335 /* Restore power. */ 336 if (pci_dopm) 337 pci_set_powerstate(sc->sc_pc, pd->pd_tag, 338 pd->pd_pmcsr_state); 339 340 /* Restore the registers saved above. */ 341 for (i = 0; i < NMAPREG; i++) 342 pci_conf_write(sc->sc_pc, pd->pd_tag, 343 PCI_MAPREG_START + (i * 4), pd->pd_map[i]); 344 reg = pci_conf_read(sc->sc_pc, pd->pd_tag, 345 PCI_COMMAND_STATUS_REG); 346 pci_conf_write(sc->sc_pc, pd->pd_tag, PCI_COMMAND_STATUS_REG, 347 (reg & 0xffff0000) | (pd->pd_csr & 0x0000ffff)); 348 pci_conf_write(sc->sc_pc, pd->pd_tag, PCI_BHLC_REG, 349 pd->pd_bhlc); 350 pci_conf_write(sc->sc_pc, pd->pd_tag, PCI_INTERRUPT_REG, 351 pd->pd_int); 352 353 if (pci_get_capability(sc->sc_pc, pd->pd_tag, 354 PCI_CAP_MSI, &off, ®)) { 355 pci_conf_write(sc->sc_pc, pd->pd_tag, 356 off + PCI_MSI_MA, pd->pd_msi_ma); 357 if (reg & PCI_MSI_MC_C64) { 358 pci_conf_write(sc->sc_pc, pd->pd_tag, 359 off + PCI_MSI_MAU32, pd->pd_msi_mau32); 360 pci_conf_write(sc->sc_pc, pd->pd_tag, 361 off + PCI_MSI_MD64, pd->pd_msi_md); 362 } else { 363 pci_conf_write(sc->sc_pc, pd->pd_tag, 364 off + PCI_MSI_MD32, pd->pd_msi_md); 365 } 366 pci_conf_write(sc->sc_pc, pd->pd_tag, 367 off + PCI_MSI_MC, pd->pd_msi_mc); 368 } 369 370 pci_resume_msix(sc->sc_pc, pd->pd_tag, sc->sc_memt, 371 pd->pd_msix_mc, pd->pd_msix_table); 372 } 373 } 374 375 int 376 pciprint(void *aux, const char *pnp) 377 { 378 struct pci_attach_args *pa = aux; 379 char devinfo[256]; 380 381 if (pnp) { 382 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, 383 sizeof devinfo); 384 printf("%s at %s", devinfo, pnp); 385 } 386 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 387 if (!pnp) { 388 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, 389 sizeof devinfo); 390 printf(" %s", devinfo); 391 } 392 393 return (UNCONF); 394 } 395 396 int 397 pcisubmatch(struct device *parent, void *match, void *aux) 398 { 399 struct cfdata *cf = match; 400 struct pci_attach_args *pa = aux; 401 402 if (cf->pcicf_dev != PCI_UNK_DEV && 403 cf->pcicf_dev != pa->pa_device) 404 return (0); 405 if (cf->pcicf_function != PCI_UNK_FUNCTION && 406 cf->pcicf_function != pa->pa_function) 407 return (0); 408 409 return ((*cf->cf_attach->ca_match)(parent, match, aux)); 410 } 411 412 int 413 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 414 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 415 { 416 pci_chipset_tag_t pc = sc->sc_pc; 417 struct pci_attach_args pa; 418 struct pci_dev *pd; 419 pcireg_t id, class, intr, bhlcr, cap; 420 int pin, bus, device, function; 421 int off, ret = 0; 422 uint64_t addr; 423 424 pci_decompose_tag(pc, tag, &bus, &device, &function); 425 426 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 427 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 428 return (0); 429 430 id = pci_conf_read(pc, tag, PCI_ID_REG); 431 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 432 433 /* Invalid vendor ID value? */ 434 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 435 return (0); 436 /* XXX Not invalid, but we've done this ~forever. */ 437 if (PCI_VENDOR(id) == 0) 438 return (0); 439 440 pa.pa_iot = sc->sc_iot; 441 pa.pa_memt = sc->sc_memt; 442 pa.pa_dmat = sc->sc_dmat; 443 pa.pa_pc = pc; 444 pa.pa_ioex = sc->sc_ioex; 445 pa.pa_memex = sc->sc_memex; 446 pa.pa_pmemex = sc->sc_pmemex; 447 pa.pa_busex = sc->sc_busex; 448 pa.pa_domain = sc->sc_domain; 449 pa.pa_bus = bus; 450 pa.pa_device = device; 451 pa.pa_function = function; 452 pa.pa_tag = tag; 453 pa.pa_id = id; 454 pa.pa_class = class; 455 pa.pa_bridgetag = sc->sc_bridgetag; 456 pa.pa_bridgeih = sc->sc_bridgeih; 457 458 /* This is a simplification of the NetBSD code. 459 We don't support turning off I/O or memory 460 on broken hardware. <csapuntz@stanford.edu> */ 461 pa.pa_flags = sc->sc_flags; 462 pa.pa_flags |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 463 464 if (sc->sc_bridgetag == NULL) { 465 pa.pa_intrswiz = 0; 466 pa.pa_intrtag = tag; 467 } else { 468 pa.pa_intrswiz = sc->sc_intrswiz + device; 469 pa.pa_intrtag = sc->sc_intrtag; 470 } 471 472 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 473 474 pin = PCI_INTERRUPT_PIN(intr); 475 pa.pa_rawintrpin = pin; 476 if (pin == PCI_INTERRUPT_PIN_NONE) { 477 /* no interrupt */ 478 pa.pa_intrpin = 0; 479 } else { 480 /* 481 * swizzle it based on the number of busses we're 482 * behind and our device number. 483 */ 484 pa.pa_intrpin = /* XXX */ 485 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 486 } 487 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 488 489 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSI, &off, &cap)) { 490 /* 491 * XXX Should we enable MSI mapping ourselves on 492 * systems that have it disabled? 493 */ 494 if (cap & PCI_HT_MSI_ENABLED) { 495 if ((cap & PCI_HT_MSI_FIXED) == 0) { 496 addr = pci_conf_read(pc, tag, 497 off + PCI_HT_MSI_ADDR); 498 addr |= (uint64_t)pci_conf_read(pc, tag, 499 off + PCI_HT_MSI_ADDR_HI32) << 32; 500 } else 501 addr = PCI_HT_MSI_FIXED_ADDR; 502 503 /* 504 * XXX This will fail to enable MSI on systems 505 * that don't use the canonical address. 506 */ 507 if (addr == PCI_HT_MSI_FIXED_ADDR) 508 pa.pa_flags |= PCI_FLAGS_MSI_ENABLED; 509 } 510 } 511 512 /* 513 * Give the MD code a chance to alter pci_attach_args and/or 514 * skip devices. 515 */ 516 if (pci_probe_device_hook(pc, &pa) != 0) 517 return (0); 518 519 if (match != NULL) { 520 ret = (*match)(&pa); 521 if (ret != 0 && pap != NULL) 522 *pap = pa; 523 } else { 524 pcireg_t address, csr; 525 int i, reg, reg_start, reg_end; 526 int s; 527 528 pd = malloc(sizeof *pd, M_DEVBUF, M_ZERO | M_WAITOK); 529 pd->pd_tag = tag; 530 LIST_INSERT_HEAD(&sc->sc_devs, pd, pd_next); 531 532 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 533 case 0: 534 reg_start = PCI_MAPREG_START; 535 reg_end = PCI_MAPREG_END; 536 break; 537 case 1: /* PCI-PCI bridge */ 538 reg_start = PCI_MAPREG_START; 539 reg_end = PCI_MAPREG_PPB_END; 540 break; 541 case 2: /* PCI-CardBus bridge */ 542 reg_start = PCI_MAPREG_START; 543 reg_end = PCI_MAPREG_PCB_END; 544 break; 545 default: 546 return (0); 547 } 548 549 pd->pd_msix_table = pci_alloc_msix_table(sc->sc_pc, pd->pd_tag); 550 551 s = splhigh(); 552 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 553 if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 554 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr & 555 ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)); 556 557 for (reg = reg_start, i = 0; reg < reg_end; reg += 4, i++) { 558 address = pci_conf_read(pc, tag, reg); 559 pci_conf_write(pc, tag, reg, 0xffffffff); 560 pd->pd_mask[i] = pci_conf_read(pc, tag, reg); 561 pci_conf_write(pc, tag, reg, address); 562 } 563 564 if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 565 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 566 splx(s); 567 568 if ((PCI_CLASS(class) == PCI_CLASS_DISPLAY && 569 PCI_SUBCLASS(class) == PCI_SUBCLASS_DISPLAY_VGA) || 570 (PCI_CLASS(class) == PCI_CLASS_PREHISTORIC && 571 PCI_SUBCLASS(class) == PCI_SUBCLASS_PREHISTORIC_VGA)) 572 pd->pd_vga_decode = 1; 573 574 pd->pd_dev = config_found_sm(&sc->sc_dev, &pa, pciprint, 575 pcisubmatch); 576 if (pd->pd_dev) 577 pci_dev_postattach(pd->pd_dev, &pa); 578 } 579 580 return (ret); 581 } 582 583 int 584 pci_detach_devices(struct pci_softc *sc, int flags) 585 { 586 struct pci_dev *pd, *next; 587 int ret; 588 589 ret = config_detach_children(&sc->sc_dev, flags); 590 if (ret != 0) 591 return (ret); 592 593 for (pd = LIST_FIRST(&sc->sc_devs); pd != NULL; pd = next) { 594 pci_free_msix_table(sc->sc_pc, pd->pd_tag, pd->pd_msix_table); 595 next = LIST_NEXT(pd, pd_next); 596 free(pd, M_DEVBUF, sizeof *pd); 597 } 598 LIST_INIT(&sc->sc_devs); 599 600 return (0); 601 } 602 603 int 604 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 605 int *offset, pcireg_t *value) 606 { 607 pcireg_t reg; 608 unsigned int ofs; 609 610 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 611 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 612 return (0); 613 614 /* Determine the Capability List Pointer register to start with. */ 615 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 616 switch (PCI_HDRTYPE_TYPE(reg)) { 617 case 0: /* standard device header */ 618 case 1: /* PCI-PCI bridge header */ 619 ofs = PCI_CAPLISTPTR_REG; 620 break; 621 case 2: /* PCI-CardBus bridge header */ 622 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 623 break; 624 default: 625 return (0); 626 } 627 628 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 629 while (ofs != 0) { 630 /* 631 * Some devices, like parts of the NVIDIA C51 chipset, 632 * have a broken Capabilities List. So we need to do 633 * a sanity check here. 634 */ 635 if ((ofs & 3) || (ofs < 0x40)) 636 return (0); 637 reg = pci_conf_read(pc, tag, ofs); 638 if (PCI_CAPLIST_CAP(reg) == capid) { 639 if (offset) 640 *offset = ofs; 641 if (value) 642 *value = reg; 643 return (1); 644 } 645 ofs = PCI_CAPLIST_NEXT(reg); 646 } 647 648 return (0); 649 } 650 651 int 652 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 653 int *offset, pcireg_t *value) 654 { 655 pcireg_t reg; 656 unsigned int ofs; 657 658 if (pci_get_capability(pc, tag, PCI_CAP_HT, &ofs, NULL) == 0) 659 return (0); 660 661 while (ofs != 0) { 662 #ifdef DIAGNOSTIC 663 if ((ofs & 3) || (ofs < 0x40)) 664 panic("pci_get_ht_capability"); 665 #endif 666 reg = pci_conf_read(pc, tag, ofs); 667 if (PCI_HT_CAP(reg) == capid) { 668 if (offset) 669 *offset = ofs; 670 if (value) 671 *value = reg; 672 return (1); 673 } 674 ofs = PCI_CAPLIST_NEXT(reg); 675 } 676 677 return (0); 678 } 679 680 uint16_t 681 pci_requester_id(pci_chipset_tag_t pc, pcitag_t tag) 682 { 683 int bus, dev, func; 684 685 pci_decompose_tag(pc, tag, &bus, &dev, &func); 686 return ((bus << 8) | (dev << 3) | func); 687 } 688 689 int 690 pci_find_device(struct pci_attach_args *pa, 691 int (*match)(struct pci_attach_args *)) 692 { 693 extern struct cfdriver pci_cd; 694 struct device *pcidev; 695 int i; 696 697 for (i = 0; i < pci_cd.cd_ndevs; i++) { 698 pcidev = pci_cd.cd_devs[i]; 699 if (pcidev != NULL && 700 pci_enumerate_bus((struct pci_softc *)pcidev, 701 match, pa) != 0) 702 return (1); 703 } 704 return (0); 705 } 706 707 int 708 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag) 709 { 710 pcireg_t reg; 711 int offset; 712 713 if (pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, 0)) { 714 reg = pci_conf_read(pc, tag, offset + PCI_PMCSR); 715 return (reg & PCI_PMCSR_STATE_MASK); 716 } 717 return (PCI_PMCSR_STATE_D0); 718 } 719 720 int 721 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, int state) 722 { 723 pcireg_t reg; 724 int offset, ostate = state; 725 726 /* 727 * Warn the firmware that we are going to put the device 728 * into the given state. 729 */ 730 pci_set_powerstate_md(pc, tag, state, 1); 731 732 if (pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, 0)) { 733 if (state == PCI_PMCSR_STATE_D3) { 734 /* 735 * The PCI Power Management spec says we 736 * should disable I/O and memory space as well 737 * as bus mastering before we place the device 738 * into D3. 739 */ 740 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 741 reg &= ~PCI_COMMAND_IO_ENABLE; 742 reg &= ~PCI_COMMAND_MEM_ENABLE; 743 reg &= ~PCI_COMMAND_MASTER_ENABLE; 744 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 745 } 746 reg = pci_conf_read(pc, tag, offset + PCI_PMCSR); 747 if ((reg & PCI_PMCSR_STATE_MASK) != state) { 748 ostate = reg & PCI_PMCSR_STATE_MASK; 749 750 pci_conf_write(pc, tag, offset + PCI_PMCSR, 751 (reg & ~PCI_PMCSR_STATE_MASK) | state); 752 if (state == PCI_PMCSR_STATE_D3 || 753 ostate == PCI_PMCSR_STATE_D3) 754 delay(10 * 1000); 755 } 756 } 757 758 /* 759 * Warn the firmware that the device is now in the given 760 * state. 761 */ 762 pci_set_powerstate_md(pc, tag, state, 0); 763 764 return (ostate); 765 } 766 767 #ifndef PCI_MACHDEP_ENUMERATE_BUS 768 /* 769 * Generic PCI bus enumeration routine. Used unless machine-dependent 770 * code needs to provide something else. 771 */ 772 int 773 pci_enumerate_bus(struct pci_softc *sc, 774 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 775 { 776 pci_chipset_tag_t pc = sc->sc_pc; 777 int device, function, nfunctions, ret; 778 const struct pci_quirkdata *qd; 779 pcireg_t id, bhlcr; 780 pcitag_t tag; 781 782 for (device = 0; device < sc->sc_maxndevs; device++) { 783 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 784 785 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 786 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 787 continue; 788 789 id = pci_conf_read(pc, tag, PCI_ID_REG); 790 791 /* Invalid vendor ID value? */ 792 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 793 continue; 794 /* XXX Not invalid, but we've done this ~forever. */ 795 if (PCI_VENDOR(id) == 0) 796 continue; 797 798 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 799 800 if (qd != NULL && 801 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 802 nfunctions = 8; 803 else if (qd != NULL && 804 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 805 nfunctions = 1; 806 else 807 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 808 809 for (function = 0; function < nfunctions; function++) { 810 tag = pci_make_tag(pc, sc->sc_bus, device, function); 811 ret = pci_probe_device(sc, tag, match, pap); 812 if (match != NULL && ret != 0) 813 return (ret); 814 } 815 } 816 817 return (0); 818 } 819 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 820 821 int 822 pci_reserve_resources(struct pci_attach_args *pa) 823 { 824 pci_chipset_tag_t pc = pa->pa_pc; 825 pcitag_t tag = pa->pa_tag; 826 pcireg_t bhlc, blr, type, bir; 827 pcireg_t addr, mask; 828 bus_addr_t base, limit; 829 bus_size_t size; 830 int reg, reg_start, reg_end, reg_rom; 831 int bus, dev, func; 832 int sec, sub; 833 int flags; 834 int s; 835 836 pci_decompose_tag(pc, tag, &bus, &dev, &func); 837 838 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 839 switch (PCI_HDRTYPE_TYPE(bhlc)) { 840 case 0: 841 reg_start = PCI_MAPREG_START; 842 reg_end = PCI_MAPREG_END; 843 reg_rom = PCI_ROM_REG; 844 break; 845 case 1: /* PCI-PCI bridge */ 846 reg_start = PCI_MAPREG_START; 847 reg_end = PCI_MAPREG_PPB_END; 848 reg_rom = 0; /* 0x38 */ 849 break; 850 case 2: /* PCI-CardBus bridge */ 851 reg_start = PCI_MAPREG_START; 852 reg_end = PCI_MAPREG_PCB_END; 853 reg_rom = 0; 854 break; 855 default: 856 return (0); 857 } 858 859 for (reg = reg_start; reg < reg_end; reg += 4) { 860 if (!pci_mapreg_probe(pc, tag, reg, &type)) 861 continue; 862 863 if (pci_mapreg_info(pc, tag, reg, type, &base, &size, &flags)) 864 continue; 865 866 if (base == 0) 867 continue; 868 869 switch (type) { 870 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 871 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 872 if (ISSET(flags, BUS_SPACE_MAP_PREFETCHABLE) && 873 pa->pa_pmemex && extent_alloc_region(pa->pa_pmemex, 874 base, size, EX_NOWAIT) == 0) { 875 break; 876 } 877 #ifdef __sparc64__ 878 /* 879 * Certain SPARC T5 systems assign 880 * non-prefetchable 64-bit BARs of its onboard 881 * mpii(4) controllers addresses in the 882 * prefetchable memory range. This is 883 * (probably) safe, as reads from the device 884 * registers mapped by these BARs are 885 * side-effect free. So assume the firmware 886 * knows what it is doing. 887 */ 888 if (base >= 0x100000000 && 889 pa->pa_pmemex && extent_alloc_region(pa->pa_pmemex, 890 base, size, EX_NOWAIT) == 0) { 891 break; 892 } 893 #endif 894 if (pa->pa_memex && extent_alloc_region(pa->pa_memex, 895 base, size, EX_NOWAIT)) { 896 printf("%d:%d:%d: mem address conflict 0x%lx/0x%lx\n", 897 bus, dev, func, base, size); 898 pci_conf_write(pc, tag, reg, 0); 899 if (type & PCI_MAPREG_MEM_TYPE_64BIT) 900 pci_conf_write(pc, tag, reg + 4, 0); 901 } 902 break; 903 case PCI_MAPREG_TYPE_IO: 904 if (pa->pa_ioex && extent_alloc_region(pa->pa_ioex, 905 base, size, EX_NOWAIT)) { 906 printf("%d:%d:%d: io address conflict 0x%lx/0x%lx\n", 907 bus, dev, func, base, size); 908 pci_conf_write(pc, tag, reg, 0); 909 } 910 break; 911 } 912 913 if (type & PCI_MAPREG_MEM_TYPE_64BIT) 914 reg += 4; 915 } 916 917 if (reg_rom != 0) { 918 s = splhigh(); 919 addr = pci_conf_read(pc, tag, PCI_ROM_REG); 920 pci_conf_write(pc, tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 921 mask = pci_conf_read(pc, tag, PCI_ROM_REG); 922 pci_conf_write(pc, tag, PCI_ROM_REG, addr); 923 splx(s); 924 925 base = PCI_ROM_ADDR(addr); 926 size = PCI_ROM_SIZE(mask); 927 if (base != 0 && size != 0) { 928 if (pa->pa_pmemex && extent_alloc_region(pa->pa_pmemex, 929 base, size, EX_NOWAIT) && 930 pa->pa_memex && extent_alloc_region(pa->pa_memex, 931 base, size, EX_NOWAIT)) { 932 printf("%d:%d:%d: rom address conflict 0x%lx/0x%lx\n", 933 bus, dev, func, base, size); 934 pci_conf_write(pc, tag, PCI_ROM_REG, 0); 935 } 936 } 937 } 938 939 if (PCI_HDRTYPE_TYPE(bhlc) != 1) 940 return (0); 941 942 /* Figure out the I/O address range of the bridge. */ 943 blr = pci_conf_read(pc, tag, PPB_REG_IOSTATUS); 944 base = (blr & 0x000000f0) << 8; 945 limit = (blr & 0x000f000) | 0x00000fff; 946 blr = pci_conf_read(pc, tag, PPB_REG_IO_HI); 947 base |= (blr & 0x0000ffff) << 16; 948 limit |= (blr & 0xffff0000); 949 if (limit > base) 950 size = (limit - base + 1); 951 else 952 size = 0; 953 if (pa->pa_ioex && base > 0 && size > 0) { 954 if (extent_alloc_region(pa->pa_ioex, base, size, EX_NOWAIT)) { 955 printf("%d:%d:%d: bridge io address conflict 0x%lx/0x%lx\n", 956 bus, dev, func, base, size); 957 blr &= 0xffff0000; 958 blr |= 0x000000f0; 959 pci_conf_write(pc, tag, PPB_REG_IOSTATUS, blr); 960 } 961 } 962 963 /* Figure out the memory mapped I/O address range of the bridge. */ 964 blr = pci_conf_read(pc, tag, PPB_REG_MEM); 965 base = (blr & 0x0000fff0) << 16; 966 limit = (blr & 0xfff00000) | 0x000fffff; 967 if (limit > base) 968 size = (limit - base + 1); 969 else 970 size = 0; 971 if (pa->pa_memex && base > 0 && size > 0) { 972 if (extent_alloc_region(pa->pa_memex, base, size, EX_NOWAIT)) { 973 printf("%d:%d:%d: bridge mem address conflict 0x%lx/0x%lx\n", 974 bus, dev, func, base, size); 975 pci_conf_write(pc, tag, PPB_REG_MEM, 0x0000fff0); 976 } 977 } 978 979 /* Figure out the prefetchable memory address range of the bridge. */ 980 blr = pci_conf_read(pc, tag, PPB_REG_PREFMEM); 981 base = (blr & 0x0000fff0) << 16; 982 limit = (blr & 0xfff00000) | 0x000fffff; 983 #ifdef __LP64__ 984 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFBASE_HI32); 985 base |= ((uint64_t)blr) << 32; 986 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFLIM_HI32); 987 limit |= ((uint64_t)blr) << 32; 988 #endif 989 if (limit > base) 990 size = (limit - base + 1); 991 else 992 size = 0; 993 if (pa->pa_pmemex && base > 0 && size > 0) { 994 if (extent_alloc_region(pa->pa_pmemex, base, size, EX_NOWAIT)) { 995 printf("%d:%d:%d: bridge mem address conflict 0x%lx/0x%lx\n", 996 bus, dev, func, base, size); 997 pci_conf_write(pc, tag, PPB_REG_PREFMEM, 0x0000fff0); 998 } 999 } else if (pa->pa_memex && base > 0 && size > 0) { 1000 if (extent_alloc_region(pa->pa_memex, base, size, EX_NOWAIT)) { 1001 printf("%d:%d:%d: bridge mem address conflict 0x%lx/0x%lx\n", 1002 bus, dev, func, base, size); 1003 pci_conf_write(pc, tag, PPB_REG_PREFMEM, 0x0000fff0); 1004 } 1005 } 1006 1007 /* Figure out the bus range handled by the bridge. */ 1008 bir = pci_conf_read(pc, tag, PPB_REG_BUSINFO); 1009 sec = PPB_BUSINFO_SECONDARY(bir); 1010 sub = PPB_BUSINFO_SUBORDINATE(bir); 1011 if (pa->pa_busex && sub >= sec && sub > 0) { 1012 if (extent_alloc_region(pa->pa_busex, sec, sub - sec + 1, 1013 EX_NOWAIT)) { 1014 printf("%d:%d:%d: bridge bus conflict %d-%d\n", 1015 bus, dev, func, sec, sub); 1016 } 1017 } 1018 1019 return (0); 1020 } 1021 1022 /* 1023 * Vital Product Data (PCI 2.2) 1024 */ 1025 1026 int 1027 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 1028 pcireg_t *data) 1029 { 1030 uint32_t reg; 1031 int ofs, i, j; 1032 1033 KASSERT(data != NULL); 1034 if ((offset + count) >= PCI_VPD_ADDRESS_MASK) 1035 return (EINVAL); 1036 1037 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 1038 return (ENXIO); 1039 1040 for (i = 0; i < count; offset += sizeof(*data), i++) { 1041 reg &= 0x0000ffff; 1042 reg &= ~PCI_VPD_OPFLAG; 1043 reg |= PCI_VPD_ADDRESS(offset); 1044 pci_conf_write(pc, tag, ofs, reg); 1045 1046 /* 1047 * PCI 2.2 does not specify how long we should poll 1048 * for completion nor whether the operation can fail. 1049 */ 1050 j = 0; 1051 do { 1052 if (j++ == 20) 1053 return (EIO); 1054 delay(4); 1055 reg = pci_conf_read(pc, tag, ofs); 1056 } while ((reg & PCI_VPD_OPFLAG) == 0); 1057 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 1058 } 1059 1060 return (0); 1061 } 1062 1063 int 1064 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 1065 pcireg_t *data) 1066 { 1067 pcireg_t reg; 1068 int ofs, i, j; 1069 1070 KASSERT(data != NULL); 1071 KASSERT((offset + count) < 0x7fff); 1072 1073 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 1074 return (1); 1075 1076 for (i = 0; i < count; offset += sizeof(*data), i++) { 1077 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 1078 1079 reg &= 0x0000ffff; 1080 reg |= PCI_VPD_OPFLAG; 1081 reg |= PCI_VPD_ADDRESS(offset); 1082 pci_conf_write(pc, tag, ofs, reg); 1083 1084 /* 1085 * PCI 2.2 does not specify how long we should poll 1086 * for completion nor whether the operation can fail. 1087 */ 1088 j = 0; 1089 do { 1090 if (j++ == 20) 1091 return (1); 1092 delay(1); 1093 reg = pci_conf_read(pc, tag, ofs); 1094 } while (reg & PCI_VPD_OPFLAG); 1095 } 1096 1097 return (0); 1098 } 1099 1100 int 1101 pci_matchbyid(struct pci_attach_args *pa, const struct pci_matchid *ids, 1102 int nent) 1103 { 1104 const struct pci_matchid *pm; 1105 int i; 1106 1107 for (i = 0, pm = ids; i < nent; i++, pm++) 1108 if (PCI_VENDOR(pa->pa_id) == pm->pm_vid && 1109 PCI_PRODUCT(pa->pa_id) == pm->pm_pid) 1110 return (1); 1111 return (0); 1112 } 1113 1114 void 1115 pci_disable_legacy_vga(struct device *dev) 1116 { 1117 struct pci_softc *pci; 1118 struct pci_dev *pd; 1119 1120 /* XXX Until we attach the drm drivers directly to pci. */ 1121 while (dev->dv_parent->dv_cfdata->cf_driver != &pci_cd) 1122 dev = dev->dv_parent; 1123 1124 pci = (struct pci_softc *)dev->dv_parent; 1125 LIST_FOREACH(pd, &pci->sc_devs, pd_next) { 1126 if (pd->pd_dev == dev) { 1127 pd->pd_vga_decode = 0; 1128 break; 1129 } 1130 } 1131 } 1132 1133 #ifdef USER_PCICONF 1134 /* 1135 * This is the user interface to PCI configuration space. 1136 */ 1137 1138 #include <sys/pciio.h> 1139 #include <sys/fcntl.h> 1140 1141 #ifdef DEBUG 1142 #define PCIDEBUG(x) printf x 1143 #else 1144 #define PCIDEBUG(x) 1145 #endif 1146 1147 void pci_disable_vga(pci_chipset_tag_t, pcitag_t); 1148 void pci_enable_vga(pci_chipset_tag_t, pcitag_t); 1149 void pci_route_vga(struct pci_softc *); 1150 void pci_unroute_vga(struct pci_softc *); 1151 1152 int pciopen(dev_t dev, int oflags, int devtype, struct proc *p); 1153 int pciclose(dev_t dev, int flag, int devtype, struct proc *p); 1154 int pciioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p); 1155 1156 int 1157 pciopen(dev_t dev, int oflags, int devtype, struct proc *p) 1158 { 1159 PCIDEBUG(("pciopen ndevs: %d\n" , pci_cd.cd_ndevs)); 1160 1161 if (minor(dev) >= pci_ndomains) { 1162 return ENXIO; 1163 } 1164 1165 #ifndef APERTURE 1166 if ((oflags & FWRITE) && securelevel > 0) { 1167 return EPERM; 1168 } 1169 #else 1170 if ((oflags & FWRITE) && securelevel > 0 && allowaperture == 0) { 1171 return EPERM; 1172 } 1173 #endif 1174 return (0); 1175 } 1176 1177 int 1178 pciclose(dev_t dev, int flag, int devtype, struct proc *p) 1179 { 1180 PCIDEBUG(("pciclose\n")); 1181 1182 pci_vga_proc = NULL; 1183 return (0); 1184 } 1185 1186 int 1187 pciioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1188 { 1189 struct pcisel *sel = (struct pcisel *)data; 1190 struct pci_io *io; 1191 struct pci_rom *rom; 1192 int i, error; 1193 pcitag_t tag; 1194 struct pci_softc *pci; 1195 pci_chipset_tag_t pc; 1196 1197 switch (cmd) { 1198 case PCIOCREAD: 1199 case PCIOCREADMASK: 1200 break; 1201 case PCIOCWRITE: 1202 if (!(flag & FWRITE)) 1203 return EPERM; 1204 break; 1205 case PCIOCGETROMLEN: 1206 case PCIOCGETROM: 1207 case PCIOCGETVPD: 1208 break; 1209 case PCIOCGETVGA: 1210 case PCIOCSETVGA: 1211 if (pci_vga_pci == NULL) 1212 return EINVAL; 1213 break; 1214 default: 1215 return ENOTTY; 1216 } 1217 1218 for (i = 0; i < pci_cd.cd_ndevs; i++) { 1219 pci = pci_cd.cd_devs[i]; 1220 if (pci != NULL && pci->sc_domain == minor(dev) && 1221 pci->sc_bus == sel->pc_bus) 1222 break; 1223 } 1224 if (i >= pci_cd.cd_ndevs) 1225 return ENXIO; 1226 1227 /* Check bounds */ 1228 if (pci->sc_bus >= 256 || 1229 sel->pc_dev >= pci_bus_maxdevs(pci->sc_pc, pci->sc_bus) || 1230 sel->pc_func >= 8) 1231 return EINVAL; 1232 1233 pc = pci->sc_pc; 1234 tag = pci_make_tag(pc, sel->pc_bus, sel->pc_dev, sel->pc_func); 1235 1236 switch (cmd) { 1237 case PCIOCREAD: 1238 io = (struct pci_io *)data; 1239 switch (io->pi_width) { 1240 case 4: 1241 /* Configuration space bounds check */ 1242 if (io->pi_reg < 0 || 1243 io->pi_reg >= pci_conf_size(pc, tag)) 1244 return EINVAL; 1245 /* Make sure the register is properly aligned */ 1246 if (io->pi_reg & 0x3) 1247 return EINVAL; 1248 io->pi_data = pci_conf_read(pc, tag, io->pi_reg); 1249 error = 0; 1250 break; 1251 default: 1252 error = EINVAL; 1253 break; 1254 } 1255 break; 1256 1257 case PCIOCWRITE: 1258 io = (struct pci_io *)data; 1259 switch (io->pi_width) { 1260 case 4: 1261 /* Configuration space bounds check */ 1262 if (io->pi_reg < 0 || 1263 io->pi_reg >= pci_conf_size(pc, tag)) 1264 return EINVAL; 1265 /* Make sure the register is properly aligned */ 1266 if (io->pi_reg & 0x3) 1267 return EINVAL; 1268 pci_conf_write(pc, tag, io->pi_reg, io->pi_data); 1269 error = 0; 1270 break; 1271 default: 1272 error = EINVAL; 1273 break; 1274 } 1275 break; 1276 1277 case PCIOCREADMASK: 1278 { 1279 io = (struct pci_io *)data; 1280 struct pci_dev *pd; 1281 int dev, func, i; 1282 1283 if (io->pi_width != 4 || io->pi_reg & 0x3 || 1284 io->pi_reg < PCI_MAPREG_START || 1285 io->pi_reg >= PCI_MAPREG_END) 1286 return (EINVAL); 1287 1288 error = ENODEV; 1289 LIST_FOREACH(pd, &pci->sc_devs, pd_next) { 1290 pci_decompose_tag(pc, pd->pd_tag, NULL, &dev, &func); 1291 if (dev == sel->pc_dev && func == sel->pc_func) { 1292 i = (io->pi_reg - PCI_MAPREG_START) / 4; 1293 io->pi_data = pd->pd_mask[i]; 1294 error = 0; 1295 break; 1296 } 1297 } 1298 break; 1299 } 1300 1301 case PCIOCGETROMLEN: 1302 case PCIOCGETROM: 1303 { 1304 pcireg_t addr, mask, bhlc; 1305 bus_space_handle_t h; 1306 bus_size_t len, off; 1307 char buf[256]; 1308 int s; 1309 1310 rom = (struct pci_rom *)data; 1311 1312 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 1313 if (PCI_HDRTYPE_TYPE(bhlc) != 0) 1314 return (ENODEV); 1315 1316 s = splhigh(); 1317 addr = pci_conf_read(pc, tag, PCI_ROM_REG); 1318 pci_conf_write(pc, tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 1319 mask = pci_conf_read(pc, tag, PCI_ROM_REG); 1320 pci_conf_write(pc, tag, PCI_ROM_REG, addr); 1321 splx(s); 1322 1323 /* 1324 * Section 6.2.5.2 `Expansion ROM Base Addres Register', 1325 * 1326 * tells us that only the upper 21 bits are writable. 1327 * This means that the size of a ROM must be a 1328 * multiple of 2 KB. So reading the ROM in chunks of 1329 * 256 bytes should work just fine. 1330 */ 1331 if ((PCI_ROM_ADDR(addr) == 0 || 1332 PCI_ROM_SIZE(mask) % sizeof(buf)) != 0) 1333 return (ENODEV); 1334 1335 /* If we're just after the size, skip reading the ROM. */ 1336 if (cmd == PCIOCGETROMLEN) { 1337 error = 0; 1338 goto fail; 1339 } 1340 1341 if (rom->pr_romlen < PCI_ROM_SIZE(mask)) { 1342 error = ENOMEM; 1343 goto fail; 1344 } 1345 1346 error = bus_space_map(pci->sc_memt, PCI_ROM_ADDR(addr), 1347 PCI_ROM_SIZE(mask), 0, &h); 1348 if (error) 1349 goto fail; 1350 1351 off = 0; 1352 len = PCI_ROM_SIZE(mask); 1353 while (len > 0 && error == 0) { 1354 s = splhigh(); 1355 pci_conf_write(pc, tag, PCI_ROM_REG, 1356 addr | PCI_ROM_ENABLE); 1357 bus_space_read_region_1(pci->sc_memt, h, off, 1358 buf, sizeof(buf)); 1359 pci_conf_write(pc, tag, PCI_ROM_REG, addr); 1360 splx(s); 1361 1362 error = copyout(buf, rom->pr_rom + off, sizeof(buf)); 1363 off += sizeof(buf); 1364 len -= sizeof(buf); 1365 } 1366 1367 bus_space_unmap(pci->sc_memt, h, PCI_ROM_SIZE(mask)); 1368 1369 fail: 1370 rom->pr_romlen = PCI_ROM_SIZE(mask); 1371 break; 1372 } 1373 1374 case PCIOCGETVPD: { 1375 struct pci_vpd_req *pv = (struct pci_vpd_req *)data; 1376 pcireg_t *data; 1377 size_t len; 1378 unsigned int i; 1379 int s; 1380 1381 CTASSERT(sizeof(*data) == sizeof(*pv->pv_data)); 1382 1383 data = mallocarray(pv->pv_count, sizeof(*data), M_TEMP, 1384 M_WAITOK|M_CANFAIL); 1385 if (data == NULL) { 1386 error = ENOMEM; 1387 break; 1388 } 1389 1390 s = splhigh(); 1391 error = pci_vpd_read(pc, tag, pv->pv_offset, pv->pv_count, 1392 data); 1393 splx(s); 1394 1395 len = pv->pv_count * sizeof(*pv->pv_data); 1396 1397 if (error == 0) { 1398 for (i = 0; i < pv->pv_count; i++) 1399 data[i] = letoh32(data[i]); 1400 1401 error = copyout(data, pv->pv_data, len); 1402 } 1403 1404 free(data, M_TEMP, len); 1405 break; 1406 } 1407 1408 case PCIOCGETVGA: 1409 { 1410 struct pci_vga *vga = (struct pci_vga *)data; 1411 struct pci_dev *pd; 1412 int bus, dev, func; 1413 1414 vga->pv_decode = 0; 1415 LIST_FOREACH(pd, &pci->sc_devs, pd_next) { 1416 pci_decompose_tag(pc, pd->pd_tag, NULL, &dev, &func); 1417 if (dev == sel->pc_dev && func == sel->pc_func) { 1418 if (pd->pd_vga_decode) 1419 vga->pv_decode = PCI_VGA_IO_ENABLE | 1420 PCI_VGA_MEM_ENABLE; 1421 break; 1422 } 1423 } 1424 1425 pci_decompose_tag(pci_vga_pci->sc_pc, 1426 pci_vga_tag, &bus, &dev, &func); 1427 vga->pv_sel.pc_bus = bus; 1428 vga->pv_sel.pc_dev = dev; 1429 vga->pv_sel.pc_func = func; 1430 error = 0; 1431 break; 1432 } 1433 case PCIOCSETVGA: 1434 { 1435 struct pci_vga *vga = (struct pci_vga *)data; 1436 int bus, dev, func; 1437 1438 switch (vga->pv_lock) { 1439 case PCI_VGA_UNLOCK: 1440 case PCI_VGA_LOCK: 1441 case PCI_VGA_TRYLOCK: 1442 break; 1443 default: 1444 return (EINVAL); 1445 } 1446 1447 if (vga->pv_lock == PCI_VGA_UNLOCK) { 1448 if (pci_vga_proc != p) 1449 return (EINVAL); 1450 pci_vga_proc = NULL; 1451 wakeup(&pci_vga_proc); 1452 return (0); 1453 } 1454 1455 while (pci_vga_proc != p && pci_vga_proc != NULL) { 1456 if (vga->pv_lock == PCI_VGA_TRYLOCK) 1457 return (EBUSY); 1458 error = tsleep_nsec(&pci_vga_proc, PLOCK | PCATCH, 1459 "vgalk", INFSLP); 1460 if (error) 1461 return (error); 1462 } 1463 pci_vga_proc = p; 1464 1465 pci_decompose_tag(pci_vga_pci->sc_pc, 1466 pci_vga_tag, &bus, &dev, &func); 1467 if (bus != vga->pv_sel.pc_bus || dev != vga->pv_sel.pc_dev || 1468 func != vga->pv_sel.pc_func) { 1469 pci_disable_vga(pci_vga_pci->sc_pc, pci_vga_tag); 1470 if (pci != pci_vga_pci) { 1471 pci_unroute_vga(pci_vga_pci); 1472 pci_route_vga(pci); 1473 pci_vga_pci = pci; 1474 } 1475 pci_enable_vga(pc, tag); 1476 pci_vga_tag = tag; 1477 } 1478 1479 error = 0; 1480 break; 1481 } 1482 1483 default: 1484 error = ENOTTY; 1485 break; 1486 } 1487 1488 return (error); 1489 } 1490 1491 void 1492 pci_disable_vga(pci_chipset_tag_t pc, pcitag_t tag) 1493 { 1494 pcireg_t csr; 1495 1496 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 1497 csr &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1498 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 1499 } 1500 1501 void 1502 pci_enable_vga(pci_chipset_tag_t pc, pcitag_t tag) 1503 { 1504 pcireg_t csr; 1505 1506 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 1507 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 1508 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 1509 } 1510 1511 void 1512 pci_route_vga(struct pci_softc *sc) 1513 { 1514 pci_chipset_tag_t pc = sc->sc_pc; 1515 pcireg_t bc; 1516 1517 if (sc->sc_bridgetag == NULL) 1518 return; 1519 1520 bc = pci_conf_read(pc, *sc->sc_bridgetag, PPB_REG_BRIDGECONTROL); 1521 bc |= PPB_BC_VGA_ENABLE; 1522 pci_conf_write(pc, *sc->sc_bridgetag, PPB_REG_BRIDGECONTROL, bc); 1523 1524 pci_route_vga((struct pci_softc *)sc->sc_dev.dv_parent->dv_parent); 1525 } 1526 1527 void 1528 pci_unroute_vga(struct pci_softc *sc) 1529 { 1530 pci_chipset_tag_t pc = sc->sc_pc; 1531 pcireg_t bc; 1532 1533 if (sc->sc_bridgetag == NULL) 1534 return; 1535 1536 bc = pci_conf_read(pc, *sc->sc_bridgetag, PPB_REG_BRIDGECONTROL); 1537 bc &= ~PPB_BC_VGA_ENABLE; 1538 pci_conf_write(pc, *sc->sc_bridgetag, PPB_REG_BRIDGECONTROL, bc); 1539 1540 pci_unroute_vga((struct pci_softc *)sc->sc_dev.dv_parent->dv_parent); 1541 } 1542 #endif /* USER_PCICONF */ 1543 1544 int 1545 pci_primary_vga(struct pci_attach_args *pa) 1546 { 1547 /* XXX For now, only handle the first PCI domain. */ 1548 if (pa->pa_domain != 0) 1549 return (0); 1550 1551 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 1552 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) && 1553 (PCI_CLASS(pa->pa_class) != PCI_CLASS_PREHISTORIC || 1554 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_PREHISTORIC_VGA)) 1555 return (0); 1556 1557 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 1558 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 1559 != (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 1560 return (0); 1561 1562 pci_vga_tag = pa->pa_tag; 1563 1564 return (1); 1565 } 1566 1567 #ifdef __HAVE_PCI_MSIX 1568 1569 struct msix_vector * 1570 pci_alloc_msix_table(pci_chipset_tag_t pc, pcitag_t tag) 1571 { 1572 struct msix_vector *table; 1573 pcireg_t reg; 1574 int tblsz; 1575 1576 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 1577 return NULL; 1578 1579 tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1; 1580 table = mallocarray(tblsz, sizeof(*table), M_DEVBUF, M_WAITOK); 1581 1582 return table; 1583 } 1584 1585 void 1586 pci_free_msix_table(pci_chipset_tag_t pc, pcitag_t tag, 1587 struct msix_vector *table) 1588 { 1589 pcireg_t reg; 1590 int tblsz; 1591 1592 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 1593 return; 1594 1595 tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1; 1596 free(table, M_DEVBUF, tblsz * sizeof(*table)); 1597 } 1598 1599 void 1600 pci_suspend_msix(pci_chipset_tag_t pc, pcitag_t tag, 1601 bus_space_tag_t memt, pcireg_t *mc, struct msix_vector *table) 1602 { 1603 bus_space_handle_t memh; 1604 pcireg_t reg; 1605 int tblsz, i; 1606 1607 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 1608 return; 1609 1610 KASSERT(table != NULL); 1611 1612 if (pci_msix_table_map(pc, tag, memt, &memh)) 1613 return; 1614 1615 tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1; 1616 for (i = 0; i < tblsz; i++) { 1617 table[i].mv_ma = bus_space_read_4(memt, memh, PCI_MSIX_MA(i)); 1618 table[i].mv_mau32 = bus_space_read_4(memt, memh, 1619 PCI_MSIX_MAU32(i)); 1620 table[i].mv_md = bus_space_read_4(memt, memh, PCI_MSIX_MD(i)); 1621 table[i].mv_vc = bus_space_read_4(memt, memh, PCI_MSIX_VC(i)); 1622 } 1623 1624 pci_msix_table_unmap(pc, tag, memt, memh); 1625 1626 *mc = reg; 1627 } 1628 1629 void 1630 pci_resume_msix(pci_chipset_tag_t pc, pcitag_t tag, 1631 bus_space_tag_t memt, pcireg_t mc, struct msix_vector *table) 1632 { 1633 bus_space_handle_t memh; 1634 pcireg_t reg; 1635 int tblsz, i; 1636 int off; 1637 1638 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0) 1639 return; 1640 1641 KASSERT(table != NULL); 1642 1643 if (pci_msix_table_map(pc, tag, memt, &memh)) 1644 return; 1645 1646 tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1; 1647 for (i = 0; i < tblsz; i++) { 1648 bus_space_write_4(memt, memh, PCI_MSIX_MA(i), table[i].mv_ma); 1649 bus_space_write_4(memt, memh, PCI_MSIX_MAU32(i), 1650 table[i].mv_mau32); 1651 bus_space_write_4(memt, memh, PCI_MSIX_MD(i), table[i].mv_md); 1652 bus_space_barrier(memt, memh, PCI_MSIX_MA(i), 16, 1653 BUS_SPACE_BARRIER_WRITE); 1654 bus_space_write_4(memt, memh, PCI_MSIX_VC(i), table[i].mv_vc); 1655 bus_space_barrier(memt, memh, PCI_MSIX_VC(i), 4, 1656 BUS_SPACE_BARRIER_WRITE); 1657 } 1658 1659 pci_msix_table_unmap(pc, tag, memt, memh); 1660 1661 pci_conf_write(pc, tag, off, mc); 1662 } 1663 1664 int 1665 pci_intr_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 1666 { 1667 pcireg_t reg; 1668 1669 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0) 1670 return (0); 1671 1672 return (PCI_MSIX_MC_TBLSZ(reg) + 1); 1673 } 1674 1675 #else /* __HAVE_PCI_MSIX */ 1676 1677 struct msix_vector * 1678 pci_alloc_msix_table(pci_chipset_tag_t pc, pcitag_t tag) 1679 { 1680 return NULL; 1681 } 1682 1683 void 1684 pci_free_msix_table(pci_chipset_tag_t pc, pcitag_t tag, 1685 struct msix_vector *table) 1686 { 1687 } 1688 1689 void 1690 pci_suspend_msix(pci_chipset_tag_t pc, pcitag_t tag, 1691 bus_space_tag_t memt, pcireg_t *mc, struct msix_vector *table) 1692 { 1693 } 1694 1695 void 1696 pci_resume_msix(pci_chipset_tag_t pc, pcitag_t tag, 1697 bus_space_tag_t memt, pcireg_t mc, struct msix_vector *table) 1698 { 1699 } 1700 1701 int 1702 pci_intr_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 1703 { 1704 return (0); 1705 } 1706 1707 #endif /* __HAVE_PCI_MSIX */ 1708