1 /* $OpenBSD: pciide.c,v 1.366 2024/05/15 07:46:25 jsg Exp $ */ 2 /* $NetBSD: pciide.c,v 1.127 2001/08/03 01:31:08 tsutsui Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 /* 30 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 3. All advertising materials mentioning features or use of this software 41 * must display the following acknowledgement: 42 * This product includes software developed by Christopher G. Demetriou 43 * for the NetBSD Project. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * PCI IDE controller driver. 61 * 62 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 63 * sys/dev/pci/ppb.c, revision 1.16). 64 * 65 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 66 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 67 * 5/16/94" from the PCI SIG. 68 * 69 */ 70 71 #define DEBUG_DMA 0x01 72 #define DEBUG_XFERS 0x02 73 #define DEBUG_FUNCS 0x08 74 #define DEBUG_PROBE 0x10 75 76 #ifdef WDCDEBUG 77 #ifndef WDCDEBUG_PCIIDE_MASK 78 #define WDCDEBUG_PCIIDE_MASK 0x00 79 #endif 80 int wdcdebug_pciide_mask = WDCDEBUG_PCIIDE_MASK; 81 #define WDCDEBUG_PRINT(args, level) do { \ 82 if ((wdcdebug_pciide_mask & (level)) != 0) \ 83 printf args; \ 84 } while (0) 85 #else 86 #define WDCDEBUG_PRINT(args, level) 87 #endif 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/device.h> 91 #include <sys/malloc.h> 92 #include <sys/endian.h> 93 94 #include <machine/bus.h> 95 96 #include <dev/ata/atavar.h> 97 #include <dev/ata/satareg.h> 98 #include <dev/ic/wdcreg.h> 99 #include <dev/ic/wdcvar.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 105 #include <dev/pci/pciidereg.h> 106 #include <dev/pci/pciidevar.h> 107 #include <dev/pci/pciide_piix_reg.h> 108 #include <dev/pci/pciide_amd_reg.h> 109 #include <dev/pci/pciide_apollo_reg.h> 110 #include <dev/pci/pciide_cmd_reg.h> 111 #include <dev/pci/pciide_sii3112_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/pci/pciide_hpt_reg.h> 117 #include <dev/pci/pciide_acard_reg.h> 118 #include <dev/pci/pciide_natsemi_reg.h> 119 #include <dev/pci/pciide_nforce_reg.h> 120 #include <dev/pci/pciide_ite_reg.h> 121 #include <dev/pci/pciide_ixp_reg.h> 122 #include <dev/pci/pciide_svwsata_reg.h> 123 #include <dev/pci/pciide_jmicron_reg.h> 124 #include <dev/pci/pciide_rdc_reg.h> 125 #include <dev/pci/cy82c693var.h> 126 127 int pciide_skip_ata; 128 int pciide_skip_atapi; 129 130 /* functions for reading/writing 8-bit PCI registers */ 131 132 u_int8_t pciide_pci_read(pci_chipset_tag_t, pcitag_t, 133 int); 134 void pciide_pci_write(pci_chipset_tag_t, pcitag_t, 135 int, u_int8_t); 136 137 u_int8_t 138 pciide_pci_read(pci_chipset_tag_t pc, pcitag_t pa, int reg) 139 { 140 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 141 ((reg & 0x03) * 8) & 0xff); 142 } 143 144 void 145 pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, u_int8_t val) 146 { 147 pcireg_t pcival; 148 149 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 150 pcival &= ~(0xff << ((reg & 0x03) * 8)); 151 pcival |= (val << ((reg & 0x03) * 8)); 152 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 153 } 154 155 void default_chip_map(struct pciide_softc *, struct pci_attach_args *); 156 157 void sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 158 void sata_setup_channel(struct channel_softc *); 159 160 void piix_chip_map(struct pciide_softc *, struct pci_attach_args *); 161 void piixsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 162 void piix_setup_channel(struct channel_softc *); 163 void piix3_4_setup_channel(struct channel_softc *); 164 void piix_timing_debug(struct pciide_softc *); 165 166 u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 167 u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 168 u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 169 170 void amd756_chip_map(struct pciide_softc *, struct pci_attach_args *); 171 void amd756_setup_channel(struct channel_softc *); 172 173 void apollo_chip_map(struct pciide_softc *, struct pci_attach_args *); 174 void apollo_setup_channel(struct channel_softc *); 175 176 void cmd_chip_map(struct pciide_softc *, struct pci_attach_args *); 177 void cmd0643_9_chip_map(struct pciide_softc *, struct pci_attach_args *); 178 void cmd0643_9_setup_channel(struct channel_softc *); 179 void cmd680_chip_map(struct pciide_softc *, struct pci_attach_args *); 180 void cmd680_setup_channel(struct channel_softc *); 181 void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, int); 182 void cmd_channel_map(struct pci_attach_args *, 183 struct pciide_softc *, int); 184 int cmd_pci_intr(void *); 185 void cmd646_9_irqack(struct channel_softc *); 186 187 void sii_fixup_cacheline(struct pciide_softc *, struct pci_attach_args *); 188 void sii3112_chip_map(struct pciide_softc *, struct pci_attach_args *); 189 void sii3112_setup_channel(struct channel_softc *); 190 void sii3112_drv_probe(struct channel_softc *); 191 void sii3114_chip_map(struct pciide_softc *, struct pci_attach_args *); 192 void sii3114_mapreg_dma(struct pciide_softc *, struct pci_attach_args *); 193 int sii3114_chansetup(struct pciide_softc *, int); 194 void sii3114_mapchan(struct pciide_channel *); 195 u_int8_t sii3114_dmacmd_read(struct pciide_softc *, int); 196 void sii3114_dmacmd_write(struct pciide_softc *, int, u_int8_t); 197 u_int8_t sii3114_dmactl_read(struct pciide_softc *, int); 198 void sii3114_dmactl_write(struct pciide_softc *, int, u_int8_t); 199 void sii3114_dmatbl_write(struct pciide_softc *, int, u_int32_t); 200 201 void cy693_chip_map(struct pciide_softc *, struct pci_attach_args *); 202 void cy693_setup_channel(struct channel_softc *); 203 204 void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 205 void sis_setup_channel(struct channel_softc *); 206 void sis96x_setup_channel(struct channel_softc *); 207 int sis_hostbr_match(struct pci_attach_args *); 208 int sis_south_match(struct pci_attach_args *); 209 210 void natsemi_chip_map(struct pciide_softc *, struct pci_attach_args *); 211 void natsemi_setup_channel(struct channel_softc *); 212 int natsemi_pci_intr(void *); 213 void natsemi_irqack(struct channel_softc *); 214 void ns_scx200_chip_map(struct pciide_softc *, struct pci_attach_args *); 215 void ns_scx200_setup_channel(struct channel_softc *); 216 217 void acer_chip_map(struct pciide_softc *, struct pci_attach_args *); 218 void acer_setup_channel(struct channel_softc *); 219 int acer_pci_intr(void *); 220 int acer_dma_init(void *, int, int, void *, size_t, int); 221 222 void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *); 223 void pdc202xx_setup_channel(struct channel_softc *); 224 void pdc20268_setup_channel(struct channel_softc *); 225 int pdc202xx_pci_intr(void *); 226 int pdc20265_pci_intr(void *); 227 void pdc20262_dma_start(void *, int, int); 228 int pdc20262_dma_finish(void *, int, int, int); 229 230 u_int8_t pdc268_config_read(struct channel_softc *, int); 231 232 void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 233 void pdc203xx_setup_channel(struct channel_softc *); 234 int pdc203xx_pci_intr(void *); 235 void pdc203xx_irqack(struct channel_softc *); 236 void pdc203xx_dma_start(void *,int ,int); 237 int pdc203xx_dma_finish(void *, int, int, int); 238 int pdc205xx_pci_intr(void *); 239 void pdc205xx_do_reset(struct channel_softc *); 240 void pdc205xx_drv_probe(struct channel_softc *); 241 242 void hpt_chip_map(struct pciide_softc *, struct pci_attach_args *); 243 void hpt_setup_channel(struct channel_softc *); 244 int hpt_pci_intr(void *); 245 246 void acard_chip_map(struct pciide_softc *, struct pci_attach_args *); 247 void acard_setup_channel(struct channel_softc *); 248 249 void serverworks_chip_map(struct pciide_softc *, struct pci_attach_args *); 250 void serverworks_setup_channel(struct channel_softc *); 251 int serverworks_pci_intr(void *); 252 253 void svwsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 254 void svwsata_mapreg_dma(struct pciide_softc *, struct pci_attach_args *); 255 void svwsata_mapchan(struct pciide_channel *); 256 u_int8_t svwsata_dmacmd_read(struct pciide_softc *, int); 257 void svwsata_dmacmd_write(struct pciide_softc *, int, u_int8_t); 258 u_int8_t svwsata_dmactl_read(struct pciide_softc *, int); 259 void svwsata_dmactl_write(struct pciide_softc *, int, u_int8_t); 260 void svwsata_dmatbl_write(struct pciide_softc *, int, u_int32_t); 261 void svwsata_drv_probe(struct channel_softc *); 262 263 void nforce_chip_map(struct pciide_softc *, struct pci_attach_args *); 264 void nforce_setup_channel(struct channel_softc *); 265 int nforce_pci_intr(void *); 266 267 void artisea_chip_map(struct pciide_softc *, struct pci_attach_args *); 268 269 void ite_chip_map(struct pciide_softc *, struct pci_attach_args *); 270 void ite_setup_channel(struct channel_softc *); 271 272 void ixp_chip_map(struct pciide_softc *, struct pci_attach_args *); 273 void ixp_setup_channel(struct channel_softc *); 274 275 void jmicron_chip_map(struct pciide_softc *, struct pci_attach_args *); 276 void jmicron_setup_channel(struct channel_softc *); 277 278 void phison_chip_map(struct pciide_softc *, struct pci_attach_args *); 279 void phison_setup_channel(struct channel_softc *); 280 281 void sch_chip_map(struct pciide_softc *, struct pci_attach_args *); 282 void sch_setup_channel(struct channel_softc *); 283 284 void rdc_chip_map(struct pciide_softc *, struct pci_attach_args *); 285 void rdc_setup_channel(struct channel_softc *); 286 287 struct pciide_product_desc { 288 u_int32_t ide_product; 289 u_short ide_flags; 290 /* map and setup chip, probe drives */ 291 void (*chip_map)(struct pciide_softc *, struct pci_attach_args *); 292 }; 293 294 /* Flags for ide_flags */ 295 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 296 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 297 298 /* Default product description for devices not known from this controller */ 299 const struct pciide_product_desc default_product_desc = { 300 0, /* Generic PCI IDE controller */ 301 0, 302 default_chip_map 303 }; 304 305 const struct pciide_product_desc pciide_intel_products[] = { 306 { PCI_PRODUCT_INTEL_31244, /* Intel 31244 SATA */ 307 0, 308 artisea_chip_map 309 }, 310 { PCI_PRODUCT_INTEL_82092AA, /* Intel 82092AA IDE */ 311 0, 312 default_chip_map 313 }, 314 { PCI_PRODUCT_INTEL_82371FB_IDE, /* Intel 82371FB IDE (PIIX) */ 315 0, 316 piix_chip_map 317 }, 318 { PCI_PRODUCT_INTEL_82371FB_ISA, /* Intel 82371FB IDE (PIIX) */ 319 0, 320 piix_chip_map 321 }, 322 { PCI_PRODUCT_INTEL_82372FB_IDE, /* Intel 82372FB IDE (PIIX4) */ 323 0, 324 piix_chip_map 325 }, 326 { PCI_PRODUCT_INTEL_82371SB_IDE, /* Intel 82371SB IDE (PIIX3) */ 327 0, 328 piix_chip_map 329 }, 330 { PCI_PRODUCT_INTEL_82371AB_IDE, /* Intel 82371AB IDE (PIIX4) */ 331 0, 332 piix_chip_map 333 }, 334 { PCI_PRODUCT_INTEL_82371MX, /* Intel 82371MX IDE */ 335 0, 336 piix_chip_map 337 }, 338 { PCI_PRODUCT_INTEL_82440MX_IDE, /* Intel 82440MX IDE */ 339 0, 340 piix_chip_map 341 }, 342 { PCI_PRODUCT_INTEL_82451NX, /* Intel 82451NX (PIIX4) IDE */ 343 0, 344 piix_chip_map 345 }, 346 { PCI_PRODUCT_INTEL_82801AA_IDE, /* Intel 82801AA IDE (ICH) */ 347 0, 348 piix_chip_map 349 }, 350 { PCI_PRODUCT_INTEL_82801AB_IDE, /* Intel 82801AB IDE (ICH0) */ 351 0, 352 piix_chip_map 353 }, 354 { PCI_PRODUCT_INTEL_82801BAM_IDE, /* Intel 82801BAM IDE (ICH2) */ 355 0, 356 piix_chip_map 357 }, 358 { PCI_PRODUCT_INTEL_82801BA_IDE, /* Intel 82801BA IDE (ICH2) */ 359 0, 360 piix_chip_map 361 }, 362 { PCI_PRODUCT_INTEL_82801CAM_IDE, /* Intel 82801CAM IDE (ICH3) */ 363 0, 364 piix_chip_map 365 }, 366 { PCI_PRODUCT_INTEL_82801CA_IDE, /* Intel 82801CA IDE (ICH3) */ 367 0, 368 piix_chip_map 369 }, 370 { PCI_PRODUCT_INTEL_82801DB_IDE, /* Intel 82801DB IDE (ICH4) */ 371 0, 372 piix_chip_map 373 }, 374 { PCI_PRODUCT_INTEL_82801DBL_IDE, /* Intel 82801DBL IDE (ICH4-L) */ 375 0, 376 piix_chip_map 377 }, 378 { PCI_PRODUCT_INTEL_82801DBM_IDE, /* Intel 82801DBM IDE (ICH4-M) */ 379 0, 380 piix_chip_map 381 }, 382 { PCI_PRODUCT_INTEL_82801EB_IDE, /* Intel 82801EB/ER (ICH5/5R) IDE */ 383 0, 384 piix_chip_map 385 }, 386 { PCI_PRODUCT_INTEL_82801EB_SATA, /* Intel 82801EB (ICH5) SATA */ 387 0, 388 piixsata_chip_map 389 }, 390 { PCI_PRODUCT_INTEL_82801ER_SATA, /* Intel 82801ER (ICH5R) SATA */ 391 0, 392 piixsata_chip_map 393 }, 394 { PCI_PRODUCT_INTEL_6300ESB_IDE, /* Intel 6300ESB IDE */ 395 0, 396 piix_chip_map 397 }, 398 { PCI_PRODUCT_INTEL_6300ESB_SATA, /* Intel 6300ESB SATA */ 399 0, 400 piixsata_chip_map 401 }, 402 { PCI_PRODUCT_INTEL_6300ESB_SATA2, /* Intel 6300ESB SATA */ 403 0, 404 piixsata_chip_map 405 }, 406 { PCI_PRODUCT_INTEL_6321ESB_IDE, /* Intel 6321ESB IDE */ 407 0, 408 piix_chip_map 409 }, 410 { PCI_PRODUCT_INTEL_82801FB_IDE, /* Intel 82801FB (ICH6) IDE */ 411 0, 412 piix_chip_map 413 }, 414 { PCI_PRODUCT_INTEL_82801FBM_SATA, /* Intel 82801FBM (ICH6M) SATA */ 415 0, 416 piixsata_chip_map 417 }, 418 { PCI_PRODUCT_INTEL_82801FB_SATA, /* Intel 82801FB (ICH6) SATA */ 419 0, 420 piixsata_chip_map 421 }, 422 { PCI_PRODUCT_INTEL_82801FR_SATA, /* Intel 82801FR (ICH6R) SATA */ 423 0, 424 piixsata_chip_map 425 }, 426 { PCI_PRODUCT_INTEL_82801GB_IDE, /* Intel 82801GB (ICH7) IDE */ 427 0, 428 piix_chip_map 429 }, 430 { PCI_PRODUCT_INTEL_82801GB_SATA, /* Intel 82801GB (ICH7) SATA */ 431 0, 432 piixsata_chip_map 433 }, 434 { PCI_PRODUCT_INTEL_82801GR_AHCI, /* Intel 82801GR (ICH7R) AHCI */ 435 0, 436 piixsata_chip_map 437 }, 438 { PCI_PRODUCT_INTEL_82801GR_RAID, /* Intel 82801GR (ICH7R) RAID */ 439 0, 440 piixsata_chip_map 441 }, 442 { PCI_PRODUCT_INTEL_82801GBM_SATA, /* Intel 82801GBM (ICH7M) SATA */ 443 0, 444 piixsata_chip_map 445 }, 446 { PCI_PRODUCT_INTEL_82801GBM_AHCI, /* Intel 82801GBM (ICH7M) AHCI */ 447 0, 448 piixsata_chip_map 449 }, 450 { PCI_PRODUCT_INTEL_82801GHM_RAID, /* Intel 82801GHM (ICH7M DH) RAID */ 451 0, 452 piixsata_chip_map 453 }, 454 { PCI_PRODUCT_INTEL_82801H_SATA_1, /* Intel 82801H (ICH8) SATA */ 455 0, 456 piixsata_chip_map 457 }, 458 { PCI_PRODUCT_INTEL_82801H_AHCI_6P, /* Intel 82801H (ICH8) AHCI */ 459 0, 460 piixsata_chip_map 461 }, 462 { PCI_PRODUCT_INTEL_82801H_RAID, /* Intel 82801H (ICH8) RAID */ 463 0, 464 piixsata_chip_map 465 }, 466 { PCI_PRODUCT_INTEL_82801H_AHCI_4P, /* Intel 82801H (ICH8) AHCI */ 467 0, 468 piixsata_chip_map 469 }, 470 { PCI_PRODUCT_INTEL_82801H_SATA_2, /* Intel 82801H (ICH8) SATA */ 471 0, 472 piixsata_chip_map 473 }, 474 { PCI_PRODUCT_INTEL_82801HBM_SATA, /* Intel 82801HBM (ICH8M) SATA */ 475 0, 476 piixsata_chip_map 477 }, 478 { PCI_PRODUCT_INTEL_82801HBM_AHCI, /* Intel 82801HBM (ICH8M) AHCI */ 479 0, 480 piixsata_chip_map 481 }, 482 { PCI_PRODUCT_INTEL_82801HBM_RAID, /* Intel 82801HBM (ICH8M) RAID */ 483 0, 484 piixsata_chip_map 485 }, 486 { PCI_PRODUCT_INTEL_82801HBM_IDE, /* Intel 82801HBM (ICH8M) IDE */ 487 0, 488 piix_chip_map 489 }, 490 { PCI_PRODUCT_INTEL_82801I_SATA_1, /* Intel 82801I (ICH9) SATA */ 491 0, 492 piixsata_chip_map 493 }, 494 { PCI_PRODUCT_INTEL_82801I_SATA_2, /* Intel 82801I (ICH9) SATA */ 495 0, 496 piixsata_chip_map 497 }, 498 { PCI_PRODUCT_INTEL_82801I_SATA_3, /* Intel 82801I (ICH9) SATA */ 499 0, 500 piixsata_chip_map 501 }, 502 { PCI_PRODUCT_INTEL_82801I_SATA_4, /* Intel 82801I (ICH9) SATA */ 503 0, 504 piixsata_chip_map 505 }, 506 { PCI_PRODUCT_INTEL_82801I_SATA_5, /* Intel 82801I (ICH9M) SATA */ 507 0, 508 piixsata_chip_map 509 }, 510 { PCI_PRODUCT_INTEL_82801I_SATA_6, /* Intel 82801I (ICH9M) SATA */ 511 0, 512 piixsata_chip_map 513 }, 514 { PCI_PRODUCT_INTEL_82801JD_SATA_1, /* Intel 82801JD (ICH10) SATA */ 515 0, 516 piixsata_chip_map 517 }, 518 { PCI_PRODUCT_INTEL_82801JD_SATA_2, /* Intel 82801JD (ICH10) SATA */ 519 0, 520 piixsata_chip_map 521 }, 522 { PCI_PRODUCT_INTEL_82801JI_SATA_1, /* Intel 82801JI (ICH10) SATA */ 523 0, 524 piixsata_chip_map 525 }, 526 { PCI_PRODUCT_INTEL_82801JI_SATA_2, /* Intel 82801JI (ICH10) SATA */ 527 0, 528 piixsata_chip_map 529 }, 530 { PCI_PRODUCT_INTEL_6321ESB_SATA, /* Intel 6321ESB SATA */ 531 0, 532 piixsata_chip_map 533 }, 534 { PCI_PRODUCT_INTEL_3400_SATA_1, /* Intel 3400 SATA */ 535 0, 536 piixsata_chip_map 537 }, 538 { PCI_PRODUCT_INTEL_3400_SATA_2, /* Intel 3400 SATA */ 539 0, 540 piixsata_chip_map 541 }, 542 { PCI_PRODUCT_INTEL_3400_SATA_3, /* Intel 3400 SATA */ 543 0, 544 piixsata_chip_map 545 }, 546 { PCI_PRODUCT_INTEL_3400_SATA_4, /* Intel 3400 SATA */ 547 0, 548 piixsata_chip_map 549 }, 550 { PCI_PRODUCT_INTEL_3400_SATA_5, /* Intel 3400 SATA */ 551 0, 552 piixsata_chip_map 553 }, 554 { PCI_PRODUCT_INTEL_3400_SATA_6, /* Intel 3400 SATA */ 555 0, 556 piixsata_chip_map 557 }, 558 { PCI_PRODUCT_INTEL_C600_SATA, /* Intel C600 SATA */ 559 0, 560 piixsata_chip_map 561 }, 562 { PCI_PRODUCT_INTEL_C610_SATA_1, /* Intel C610 SATA */ 563 0, 564 piixsata_chip_map 565 }, 566 { PCI_PRODUCT_INTEL_C610_SATA_2, /* Intel C610 SATA */ 567 0, 568 piixsata_chip_map 569 }, 570 { PCI_PRODUCT_INTEL_C610_SATA_3, /* Intel C610 SATA */ 571 0, 572 piixsata_chip_map 573 }, 574 { PCI_PRODUCT_INTEL_6SERIES_SATA_1, /* Intel 6 Series SATA */ 575 0, 576 piixsata_chip_map 577 }, 578 { PCI_PRODUCT_INTEL_6SERIES_SATA_2, /* Intel 6 Series SATA */ 579 0, 580 piixsata_chip_map 581 }, 582 { PCI_PRODUCT_INTEL_6SERIES_SATA_3, /* Intel 6 Series SATA */ 583 0, 584 piixsata_chip_map 585 }, 586 { PCI_PRODUCT_INTEL_6SERIES_SATA_4, /* Intel 6 Series SATA */ 587 0, 588 piixsata_chip_map 589 }, 590 { PCI_PRODUCT_INTEL_7SERIES_SATA_1, /* Intel 7 Series SATA */ 591 0, 592 piixsata_chip_map 593 }, 594 { PCI_PRODUCT_INTEL_7SERIES_SATA_2, /* Intel 7 Series SATA */ 595 0, 596 piixsata_chip_map 597 }, 598 { PCI_PRODUCT_INTEL_7SERIES_SATA_3, /* Intel 7 Series SATA */ 599 0, 600 piixsata_chip_map 601 }, 602 { PCI_PRODUCT_INTEL_7SERIES_SATA_4, /* Intel 7 Series SATA */ 603 0, 604 piixsata_chip_map 605 }, 606 { PCI_PRODUCT_INTEL_8SERIES_SATA_1, /* Intel 8 Series SATA */ 607 0, 608 piixsata_chip_map 609 }, 610 { PCI_PRODUCT_INTEL_8SERIES_SATA_2, /* Intel 8 Series SATA */ 611 0, 612 piixsata_chip_map 613 }, 614 { PCI_PRODUCT_INTEL_8SERIES_SATA_3, /* Intel 8 Series SATA */ 615 0, 616 piixsata_chip_map 617 }, 618 { PCI_PRODUCT_INTEL_8SERIES_SATA_4, /* Intel 8 Series SATA */ 619 0, 620 piixsata_chip_map 621 }, 622 { PCI_PRODUCT_INTEL_8SERIES_LP_SATA_1, /* Intel 8 Series SATA */ 623 0, 624 piixsata_chip_map 625 }, 626 { PCI_PRODUCT_INTEL_8SERIES_LP_SATA_2, /* Intel 8 Series SATA */ 627 0, 628 piixsata_chip_map 629 }, 630 { PCI_PRODUCT_INTEL_8SERIES_LP_SATA_3, /* Intel 8 Series SATA */ 631 0, 632 piixsata_chip_map 633 }, 634 { PCI_PRODUCT_INTEL_8SERIES_LP_SATA_4, /* Intel 8 Series SATA */ 635 0, 636 piixsata_chip_map 637 }, 638 { PCI_PRODUCT_INTEL_9SERIES_SATA_1, /* Intel 9 Series SATA */ 639 0, 640 piixsata_chip_map 641 }, 642 { PCI_PRODUCT_INTEL_9SERIES_SATA_2, /* Intel 9 Series SATA */ 643 0, 644 piixsata_chip_map 645 }, 646 { PCI_PRODUCT_INTEL_ATOMC2000_SATA_1, /* Intel Atom C2000 SATA */ 647 0, 648 piixsata_chip_map 649 }, 650 { PCI_PRODUCT_INTEL_ATOMC2000_SATA_2, /* Intel Atom C2000 SATA */ 651 0, 652 piixsata_chip_map 653 }, 654 { PCI_PRODUCT_INTEL_ATOMC2000_SATA_3, /* Intel Atom C2000 SATA */ 655 0, 656 piixsata_chip_map 657 }, 658 { PCI_PRODUCT_INTEL_ATOMC2000_SATA_4, /* Intel Atom C2000 SATA */ 659 0, 660 piixsata_chip_map 661 }, 662 { PCI_PRODUCT_INTEL_BAYTRAIL_SATA_1, /* Intel Baytrail SATA */ 663 0, 664 piixsata_chip_map 665 }, 666 { PCI_PRODUCT_INTEL_BAYTRAIL_SATA_2, /* Intel Baytrail SATA */ 667 0, 668 piixsata_chip_map 669 }, 670 { PCI_PRODUCT_INTEL_EP80579_SATA, /* Intel EP80579 SATA */ 671 0, 672 piixsata_chip_map 673 }, 674 { PCI_PRODUCT_INTEL_DH8900_SATA_1, /* Intel DH8900 SATA */ 675 0, 676 piixsata_chip_map 677 }, 678 { PCI_PRODUCT_INTEL_DH8900_SATA_2, /* Intel DH8900 SATA */ 679 0, 680 piixsata_chip_map 681 }, 682 { PCI_PRODUCT_INTEL_SCH_IDE, /* Intel SCH IDE */ 683 0, 684 sch_chip_map 685 } 686 }; 687 688 const struct pciide_product_desc pciide_amd_products[] = { 689 { PCI_PRODUCT_AMD_PBC756_IDE, /* AMD 756 */ 690 0, 691 amd756_chip_map 692 }, 693 { PCI_PRODUCT_AMD_766_IDE, /* AMD 766 */ 694 0, 695 amd756_chip_map 696 }, 697 { PCI_PRODUCT_AMD_PBC768_IDE, 698 0, 699 amd756_chip_map 700 }, 701 { PCI_PRODUCT_AMD_8111_IDE, 702 0, 703 amd756_chip_map 704 }, 705 { PCI_PRODUCT_AMD_CS5536_IDE, 706 0, 707 amd756_chip_map 708 }, 709 { PCI_PRODUCT_AMD_HUDSON2_IDE, 710 0, 711 ixp_chip_map 712 } 713 }; 714 715 const struct pciide_product_desc pciide_cmd_products[] = { 716 { PCI_PRODUCT_CMDTECH_640, /* CMD Technology PCI0640 */ 717 0, 718 cmd_chip_map 719 }, 720 { PCI_PRODUCT_CMDTECH_643, /* CMD Technology PCI0643 */ 721 0, 722 cmd0643_9_chip_map 723 }, 724 { PCI_PRODUCT_CMDTECH_646, /* CMD Technology PCI0646 */ 725 0, 726 cmd0643_9_chip_map 727 }, 728 { PCI_PRODUCT_CMDTECH_648, /* CMD Technology PCI0648 */ 729 0, 730 cmd0643_9_chip_map 731 }, 732 { PCI_PRODUCT_CMDTECH_649, /* CMD Technology PCI0649 */ 733 0, 734 cmd0643_9_chip_map 735 }, 736 { PCI_PRODUCT_CMDTECH_680, /* CMD Technology PCI0680 */ 737 IDE_PCI_CLASS_OVERRIDE, 738 cmd680_chip_map 739 }, 740 { PCI_PRODUCT_CMDTECH_3112, /* SiI3112 SATA */ 741 0, 742 sii3112_chip_map 743 }, 744 { PCI_PRODUCT_CMDTECH_3512, /* SiI3512 SATA */ 745 0, 746 sii3112_chip_map 747 }, 748 { PCI_PRODUCT_CMDTECH_AAR_1210SA, /* Adaptec AAR-1210SA */ 749 0, 750 sii3112_chip_map 751 }, 752 { PCI_PRODUCT_CMDTECH_3114, /* SiI3114 SATA */ 753 0, 754 sii3114_chip_map 755 } 756 }; 757 758 const struct pciide_product_desc pciide_via_products[] = { 759 { PCI_PRODUCT_VIATECH_VT82C416, /* VIA VT82C416 IDE */ 760 0, 761 apollo_chip_map 762 }, 763 { PCI_PRODUCT_VIATECH_VT82C571, /* VIA VT82C571 IDE */ 764 0, 765 apollo_chip_map 766 }, 767 { PCI_PRODUCT_VIATECH_VT6410, /* VIA VT6410 IDE */ 768 IDE_PCI_CLASS_OVERRIDE, 769 apollo_chip_map 770 }, 771 { PCI_PRODUCT_VIATECH_VT6415, /* VIA VT6415 IDE */ 772 IDE_PCI_CLASS_OVERRIDE, 773 apollo_chip_map 774 }, 775 { PCI_PRODUCT_VIATECH_CX700_IDE, /* VIA CX700 IDE */ 776 0, 777 apollo_chip_map 778 }, 779 { PCI_PRODUCT_VIATECH_VX700_IDE, /* VIA VX700 IDE */ 780 0, 781 apollo_chip_map 782 }, 783 { PCI_PRODUCT_VIATECH_VX855_IDE, /* VIA VX855 IDE */ 784 0, 785 apollo_chip_map 786 }, 787 { PCI_PRODUCT_VIATECH_VX900_IDE, /* VIA VX900 IDE */ 788 0, 789 apollo_chip_map 790 }, 791 { PCI_PRODUCT_VIATECH_VT6420_SATA, /* VIA VT6420 SATA */ 792 0, 793 sata_chip_map 794 }, 795 { PCI_PRODUCT_VIATECH_VT6421_SATA, /* VIA VT6421 SATA */ 796 0, 797 sata_chip_map 798 }, 799 { PCI_PRODUCT_VIATECH_VT8237A_SATA, /* VIA VT8237A SATA */ 800 0, 801 sata_chip_map 802 }, 803 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, /* VIA VT8237A SATA */ 804 0, 805 sata_chip_map 806 }, 807 { PCI_PRODUCT_VIATECH_VT8237S_SATA, /* VIA VT8237S SATA */ 808 0, 809 sata_chip_map 810 }, 811 { PCI_PRODUCT_VIATECH_VT8251_SATA, /* VIA VT8251 SATA */ 812 0, 813 sata_chip_map 814 } 815 }; 816 817 const struct pciide_product_desc pciide_cypress_products[] = { 818 { PCI_PRODUCT_CONTAQ_82C693, /* Contaq CY82C693 IDE */ 819 IDE_16BIT_IOSPACE, 820 cy693_chip_map 821 } 822 }; 823 824 const struct pciide_product_desc pciide_sis_products[] = { 825 { PCI_PRODUCT_SIS_5513, /* SIS 5513 EIDE */ 826 0, 827 sis_chip_map 828 }, 829 { PCI_PRODUCT_SIS_180, /* SIS 180 SATA */ 830 0, 831 sata_chip_map 832 }, 833 { PCI_PRODUCT_SIS_181, /* SIS 181 SATA */ 834 0, 835 sata_chip_map 836 }, 837 { PCI_PRODUCT_SIS_182, /* SIS 182 SATA */ 838 0, 839 sata_chip_map 840 }, 841 { PCI_PRODUCT_SIS_1183, /* SIS 1183 SATA */ 842 0, 843 sata_chip_map 844 } 845 }; 846 847 /* 848 * The National/AMD CS5535 requires MSRs to set DMA/PIO modes so it 849 * has been banished to the MD i386 pciide_machdep 850 */ 851 const struct pciide_product_desc pciide_natsemi_products[] = { 852 #ifdef __i386__ 853 { PCI_PRODUCT_NS_CS5535_IDE, /* National/AMD CS5535 IDE */ 854 0, 855 gcsc_chip_map 856 }, 857 #endif 858 { PCI_PRODUCT_NS_PC87415, /* National Semi PC87415 IDE */ 859 0, 860 natsemi_chip_map 861 }, 862 { PCI_PRODUCT_NS_SCX200_IDE, /* National Semi SCx200 IDE */ 863 0, 864 ns_scx200_chip_map 865 } 866 }; 867 868 const struct pciide_product_desc pciide_acer_products[] = { 869 { PCI_PRODUCT_ALI_M5229, /* Acer Labs M5229 UDMA IDE */ 870 0, 871 acer_chip_map 872 } 873 }; 874 875 const struct pciide_product_desc pciide_triones_products[] = { 876 { PCI_PRODUCT_TRIONES_HPT366, /* Highpoint HPT36x/37x IDE */ 877 IDE_PCI_CLASS_OVERRIDE, 878 hpt_chip_map, 879 }, 880 { PCI_PRODUCT_TRIONES_HPT372A, /* Highpoint HPT372A IDE */ 881 IDE_PCI_CLASS_OVERRIDE, 882 hpt_chip_map 883 }, 884 { PCI_PRODUCT_TRIONES_HPT302, /* Highpoint HPT302 IDE */ 885 IDE_PCI_CLASS_OVERRIDE, 886 hpt_chip_map 887 }, 888 { PCI_PRODUCT_TRIONES_HPT371, /* Highpoint HPT371 IDE */ 889 IDE_PCI_CLASS_OVERRIDE, 890 hpt_chip_map 891 }, 892 { PCI_PRODUCT_TRIONES_HPT374, /* Highpoint HPT374 IDE */ 893 IDE_PCI_CLASS_OVERRIDE, 894 hpt_chip_map 895 } 896 }; 897 898 const struct pciide_product_desc pciide_promise_products[] = { 899 { PCI_PRODUCT_PROMISE_PDC20246, 900 IDE_PCI_CLASS_OVERRIDE, 901 pdc202xx_chip_map, 902 }, 903 { PCI_PRODUCT_PROMISE_PDC20262, 904 IDE_PCI_CLASS_OVERRIDE, 905 pdc202xx_chip_map, 906 }, 907 { PCI_PRODUCT_PROMISE_PDC20265, 908 IDE_PCI_CLASS_OVERRIDE, 909 pdc202xx_chip_map, 910 }, 911 { PCI_PRODUCT_PROMISE_PDC20267, 912 IDE_PCI_CLASS_OVERRIDE, 913 pdc202xx_chip_map, 914 }, 915 { PCI_PRODUCT_PROMISE_PDC20268, 916 IDE_PCI_CLASS_OVERRIDE, 917 pdc202xx_chip_map, 918 }, 919 { PCI_PRODUCT_PROMISE_PDC20268R, 920 IDE_PCI_CLASS_OVERRIDE, 921 pdc202xx_chip_map, 922 }, 923 { PCI_PRODUCT_PROMISE_PDC20269, 924 IDE_PCI_CLASS_OVERRIDE, 925 pdc202xx_chip_map, 926 }, 927 { PCI_PRODUCT_PROMISE_PDC20271, 928 IDE_PCI_CLASS_OVERRIDE, 929 pdc202xx_chip_map, 930 }, 931 { PCI_PRODUCT_PROMISE_PDC20275, 932 IDE_PCI_CLASS_OVERRIDE, 933 pdc202xx_chip_map, 934 }, 935 { PCI_PRODUCT_PROMISE_PDC20276, 936 IDE_PCI_CLASS_OVERRIDE, 937 pdc202xx_chip_map, 938 }, 939 { PCI_PRODUCT_PROMISE_PDC20277, 940 IDE_PCI_CLASS_OVERRIDE, 941 pdc202xx_chip_map, 942 }, 943 { PCI_PRODUCT_PROMISE_PDC20318, 944 IDE_PCI_CLASS_OVERRIDE, 945 pdcsata_chip_map, 946 }, 947 { PCI_PRODUCT_PROMISE_PDC20319, 948 IDE_PCI_CLASS_OVERRIDE, 949 pdcsata_chip_map, 950 }, 951 { PCI_PRODUCT_PROMISE_PDC20371, 952 IDE_PCI_CLASS_OVERRIDE, 953 pdcsata_chip_map, 954 }, 955 { PCI_PRODUCT_PROMISE_PDC20375, 956 IDE_PCI_CLASS_OVERRIDE, 957 pdcsata_chip_map, 958 }, 959 { PCI_PRODUCT_PROMISE_PDC20376, 960 IDE_PCI_CLASS_OVERRIDE, 961 pdcsata_chip_map, 962 }, 963 { PCI_PRODUCT_PROMISE_PDC20377, 964 IDE_PCI_CLASS_OVERRIDE, 965 pdcsata_chip_map, 966 }, 967 { PCI_PRODUCT_PROMISE_PDC20378, 968 IDE_PCI_CLASS_OVERRIDE, 969 pdcsata_chip_map, 970 }, 971 { PCI_PRODUCT_PROMISE_PDC20379, 972 IDE_PCI_CLASS_OVERRIDE, 973 pdcsata_chip_map, 974 }, 975 { PCI_PRODUCT_PROMISE_PDC40518, 976 IDE_PCI_CLASS_OVERRIDE, 977 pdcsata_chip_map, 978 }, 979 { PCI_PRODUCT_PROMISE_PDC40519, 980 IDE_PCI_CLASS_OVERRIDE, 981 pdcsata_chip_map, 982 }, 983 { PCI_PRODUCT_PROMISE_PDC40718, 984 IDE_PCI_CLASS_OVERRIDE, 985 pdcsata_chip_map, 986 }, 987 { PCI_PRODUCT_PROMISE_PDC40719, 988 IDE_PCI_CLASS_OVERRIDE, 989 pdcsata_chip_map, 990 }, 991 { PCI_PRODUCT_PROMISE_PDC40779, 992 IDE_PCI_CLASS_OVERRIDE, 993 pdcsata_chip_map, 994 }, 995 { PCI_PRODUCT_PROMISE_PDC20571, 996 IDE_PCI_CLASS_OVERRIDE, 997 pdcsata_chip_map, 998 }, 999 { PCI_PRODUCT_PROMISE_PDC20575, 1000 IDE_PCI_CLASS_OVERRIDE, 1001 pdcsata_chip_map, 1002 }, 1003 { PCI_PRODUCT_PROMISE_PDC20579, 1004 IDE_PCI_CLASS_OVERRIDE, 1005 pdcsata_chip_map, 1006 }, 1007 { PCI_PRODUCT_PROMISE_PDC20771, 1008 IDE_PCI_CLASS_OVERRIDE, 1009 pdcsata_chip_map, 1010 }, 1011 { PCI_PRODUCT_PROMISE_PDC20775, 1012 IDE_PCI_CLASS_OVERRIDE, 1013 pdcsata_chip_map, 1014 } 1015 }; 1016 1017 const struct pciide_product_desc pciide_acard_products[] = { 1018 { PCI_PRODUCT_ACARD_ATP850U, /* Acard ATP850U Ultra33 Controller */ 1019 IDE_PCI_CLASS_OVERRIDE, 1020 acard_chip_map, 1021 }, 1022 { PCI_PRODUCT_ACARD_ATP860, /* Acard ATP860 Ultra66 Controller */ 1023 IDE_PCI_CLASS_OVERRIDE, 1024 acard_chip_map, 1025 }, 1026 { PCI_PRODUCT_ACARD_ATP860A, /* Acard ATP860-A Ultra66 Controller */ 1027 IDE_PCI_CLASS_OVERRIDE, 1028 acard_chip_map, 1029 }, 1030 { PCI_PRODUCT_ACARD_ATP865A, /* Acard ATP865-A Ultra133 Controller */ 1031 IDE_PCI_CLASS_OVERRIDE, 1032 acard_chip_map, 1033 }, 1034 { PCI_PRODUCT_ACARD_ATP865R, /* Acard ATP865-R Ultra133 Controller */ 1035 IDE_PCI_CLASS_OVERRIDE, 1036 acard_chip_map, 1037 } 1038 }; 1039 1040 const struct pciide_product_desc pciide_serverworks_products[] = { 1041 { PCI_PRODUCT_RCC_OSB4_IDE, 1042 0, 1043 serverworks_chip_map, 1044 }, 1045 { PCI_PRODUCT_RCC_CSB5_IDE, 1046 0, 1047 serverworks_chip_map, 1048 }, 1049 { PCI_PRODUCT_RCC_CSB6_IDE, 1050 0, 1051 serverworks_chip_map, 1052 }, 1053 { PCI_PRODUCT_RCC_CSB6_RAID_IDE, 1054 0, 1055 serverworks_chip_map, 1056 }, 1057 { PCI_PRODUCT_RCC_HT_1000_IDE, 1058 0, 1059 serverworks_chip_map, 1060 }, 1061 { PCI_PRODUCT_RCC_K2_SATA, 1062 0, 1063 svwsata_chip_map, 1064 }, 1065 { PCI_PRODUCT_RCC_FRODO4_SATA, 1066 0, 1067 svwsata_chip_map, 1068 }, 1069 { PCI_PRODUCT_RCC_FRODO8_SATA, 1070 0, 1071 svwsata_chip_map, 1072 }, 1073 { PCI_PRODUCT_RCC_HT_1000_SATA_1, 1074 0, 1075 svwsata_chip_map, 1076 }, 1077 { PCI_PRODUCT_RCC_HT_1000_SATA_2, 1078 0, 1079 svwsata_chip_map, 1080 } 1081 }; 1082 1083 const struct pciide_product_desc pciide_nvidia_products[] = { 1084 { PCI_PRODUCT_NVIDIA_NFORCE_IDE, 1085 0, 1086 nforce_chip_map 1087 }, 1088 { PCI_PRODUCT_NVIDIA_NFORCE2_IDE, 1089 0, 1090 nforce_chip_map 1091 }, 1092 { PCI_PRODUCT_NVIDIA_NFORCE2_400_IDE, 1093 0, 1094 nforce_chip_map 1095 }, 1096 { PCI_PRODUCT_NVIDIA_NFORCE3_IDE, 1097 0, 1098 nforce_chip_map 1099 }, 1100 { PCI_PRODUCT_NVIDIA_NFORCE3_250_IDE, 1101 0, 1102 nforce_chip_map 1103 }, 1104 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 1105 0, 1106 nforce_chip_map 1107 }, 1108 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 1109 0, 1110 nforce_chip_map 1111 }, 1112 { PCI_PRODUCT_NVIDIA_MCP51_IDE, 1113 0, 1114 nforce_chip_map 1115 }, 1116 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 1117 0, 1118 nforce_chip_map 1119 }, 1120 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 1121 0, 1122 nforce_chip_map 1123 }, 1124 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 1125 0, 1126 nforce_chip_map 1127 }, 1128 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 1129 0, 1130 nforce_chip_map 1131 }, 1132 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 1133 0, 1134 nforce_chip_map 1135 }, 1136 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 1137 0, 1138 nforce_chip_map 1139 }, 1140 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 1141 0, 1142 sata_chip_map 1143 }, 1144 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 1145 0, 1146 sata_chip_map 1147 }, 1148 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 1149 0, 1150 sata_chip_map 1151 }, 1152 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 1153 0, 1154 sata_chip_map 1155 }, 1156 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 1157 0, 1158 sata_chip_map 1159 }, 1160 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 1161 0, 1162 sata_chip_map 1163 }, 1164 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 1165 0, 1166 sata_chip_map 1167 }, 1168 { PCI_PRODUCT_NVIDIA_MCP51_SATA, 1169 0, 1170 sata_chip_map 1171 }, 1172 { PCI_PRODUCT_NVIDIA_MCP51_SATA2, 1173 0, 1174 sata_chip_map 1175 }, 1176 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 1177 0, 1178 sata_chip_map 1179 }, 1180 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 1181 0, 1182 sata_chip_map 1183 }, 1184 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 1185 0, 1186 sata_chip_map 1187 }, 1188 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 1189 0, 1190 sata_chip_map 1191 }, 1192 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 1193 0, 1194 sata_chip_map 1195 }, 1196 { PCI_PRODUCT_NVIDIA_MCP65_SATA_1, 1197 0, 1198 sata_chip_map 1199 }, 1200 { PCI_PRODUCT_NVIDIA_MCP65_SATA_2, 1201 0, 1202 sata_chip_map 1203 }, 1204 { PCI_PRODUCT_NVIDIA_MCP65_SATA_3, 1205 0, 1206 sata_chip_map 1207 }, 1208 { PCI_PRODUCT_NVIDIA_MCP65_SATA_4, 1209 0, 1210 sata_chip_map 1211 }, 1212 { PCI_PRODUCT_NVIDIA_MCP67_SATA_1, 1213 0, 1214 sata_chip_map 1215 }, 1216 { PCI_PRODUCT_NVIDIA_MCP67_SATA_2, 1217 0, 1218 sata_chip_map 1219 }, 1220 { PCI_PRODUCT_NVIDIA_MCP67_SATA_3, 1221 0, 1222 sata_chip_map 1223 }, 1224 { PCI_PRODUCT_NVIDIA_MCP67_SATA_4, 1225 0, 1226 sata_chip_map 1227 }, 1228 { PCI_PRODUCT_NVIDIA_MCP77_SATA_1, 1229 0, 1230 sata_chip_map 1231 }, 1232 { PCI_PRODUCT_NVIDIA_MCP79_SATA_1, 1233 0, 1234 sata_chip_map 1235 }, 1236 { PCI_PRODUCT_NVIDIA_MCP79_SATA_2, 1237 0, 1238 sata_chip_map 1239 }, 1240 { PCI_PRODUCT_NVIDIA_MCP79_SATA_3, 1241 0, 1242 sata_chip_map 1243 }, 1244 { PCI_PRODUCT_NVIDIA_MCP79_SATA_4, 1245 0, 1246 sata_chip_map 1247 }, 1248 { PCI_PRODUCT_NVIDIA_MCP89_SATA_1, 1249 0, 1250 sata_chip_map 1251 }, 1252 { PCI_PRODUCT_NVIDIA_MCP89_SATA_2, 1253 0, 1254 sata_chip_map 1255 }, 1256 { PCI_PRODUCT_NVIDIA_MCP89_SATA_3, 1257 0, 1258 sata_chip_map 1259 }, 1260 { PCI_PRODUCT_NVIDIA_MCP89_SATA_4, 1261 0, 1262 sata_chip_map 1263 } 1264 }; 1265 1266 const struct pciide_product_desc pciide_ite_products[] = { 1267 { PCI_PRODUCT_ITEXPRESS_IT8211F, 1268 IDE_PCI_CLASS_OVERRIDE, 1269 ite_chip_map 1270 }, 1271 { PCI_PRODUCT_ITEXPRESS_IT8212F, 1272 IDE_PCI_CLASS_OVERRIDE, 1273 ite_chip_map 1274 } 1275 }; 1276 1277 const struct pciide_product_desc pciide_ati_products[] = { 1278 { PCI_PRODUCT_ATI_SB200_IDE, 1279 0, 1280 ixp_chip_map 1281 }, 1282 { PCI_PRODUCT_ATI_SB300_IDE, 1283 0, 1284 ixp_chip_map 1285 }, 1286 { PCI_PRODUCT_ATI_SB400_IDE, 1287 0, 1288 ixp_chip_map 1289 }, 1290 { PCI_PRODUCT_ATI_SB600_IDE, 1291 0, 1292 ixp_chip_map 1293 }, 1294 { PCI_PRODUCT_ATI_SB700_IDE, 1295 0, 1296 ixp_chip_map 1297 }, 1298 { PCI_PRODUCT_ATI_SB300_SATA, 1299 0, 1300 sii3112_chip_map 1301 }, 1302 { PCI_PRODUCT_ATI_SB400_SATA_1, 1303 0, 1304 sii3112_chip_map 1305 }, 1306 { PCI_PRODUCT_ATI_SB400_SATA_2, 1307 0, 1308 sii3112_chip_map 1309 } 1310 }; 1311 1312 const struct pciide_product_desc pciide_jmicron_products[] = { 1313 { PCI_PRODUCT_JMICRON_JMB361, 1314 0, 1315 jmicron_chip_map 1316 }, 1317 { PCI_PRODUCT_JMICRON_JMB363, 1318 0, 1319 jmicron_chip_map 1320 }, 1321 { PCI_PRODUCT_JMICRON_JMB365, 1322 0, 1323 jmicron_chip_map 1324 }, 1325 { PCI_PRODUCT_JMICRON_JMB366, 1326 0, 1327 jmicron_chip_map 1328 }, 1329 { PCI_PRODUCT_JMICRON_JMB368, 1330 0, 1331 jmicron_chip_map 1332 } 1333 }; 1334 1335 const struct pciide_product_desc pciide_phison_products[] = { 1336 { PCI_PRODUCT_PHISON_PS5000, 1337 0, 1338 phison_chip_map 1339 }, 1340 }; 1341 1342 const struct pciide_product_desc pciide_rdc_products[] = { 1343 { PCI_PRODUCT_RDC_R1012_IDE, 1344 0, 1345 rdc_chip_map 1346 }, 1347 }; 1348 1349 struct pciide_vendor_desc { 1350 u_int32_t ide_vendor; 1351 const struct pciide_product_desc *ide_products; 1352 int ide_nproducts; 1353 }; 1354 1355 const struct pciide_vendor_desc pciide_vendors[] = { 1356 { PCI_VENDOR_INTEL, pciide_intel_products, 1357 nitems(pciide_intel_products) }, 1358 { PCI_VENDOR_AMD, pciide_amd_products, 1359 nitems(pciide_amd_products) }, 1360 { PCI_VENDOR_CMDTECH, pciide_cmd_products, 1361 nitems(pciide_cmd_products) }, 1362 { PCI_VENDOR_VIATECH, pciide_via_products, 1363 nitems(pciide_via_products) }, 1364 { PCI_VENDOR_CONTAQ, pciide_cypress_products, 1365 nitems(pciide_cypress_products) }, 1366 { PCI_VENDOR_SIS, pciide_sis_products, 1367 nitems(pciide_sis_products) }, 1368 { PCI_VENDOR_NS, pciide_natsemi_products, 1369 nitems(pciide_natsemi_products) }, 1370 { PCI_VENDOR_ALI, pciide_acer_products, 1371 nitems(pciide_acer_products) }, 1372 { PCI_VENDOR_TRIONES, pciide_triones_products, 1373 nitems(pciide_triones_products) }, 1374 { PCI_VENDOR_ACARD, pciide_acard_products, 1375 nitems(pciide_acard_products) }, 1376 { PCI_VENDOR_RCC, pciide_serverworks_products, 1377 nitems(pciide_serverworks_products) }, 1378 { PCI_VENDOR_PROMISE, pciide_promise_products, 1379 nitems(pciide_promise_products) }, 1380 { PCI_VENDOR_NVIDIA, pciide_nvidia_products, 1381 nitems(pciide_nvidia_products) }, 1382 { PCI_VENDOR_ITEXPRESS, pciide_ite_products, 1383 nitems(pciide_ite_products) }, 1384 { PCI_VENDOR_ATI, pciide_ati_products, 1385 nitems(pciide_ati_products) }, 1386 { PCI_VENDOR_JMICRON, pciide_jmicron_products, 1387 nitems(pciide_jmicron_products) }, 1388 { PCI_VENDOR_PHISON, pciide_phison_products, 1389 nitems(pciide_phison_products) }, 1390 { PCI_VENDOR_RDC, pciide_rdc_products, 1391 nitems(pciide_rdc_products) } 1392 }; 1393 1394 /* options passed via the 'flags' config keyword */ 1395 #define PCIIDE_OPTIONS_DMA 0x01 1396 1397 int pciide_match(struct device *, void *, void *); 1398 void pciide_attach(struct device *, struct device *, void *); 1399 int pciide_detach(struct device *, int); 1400 int pciide_activate(struct device *, int); 1401 1402 const struct cfattach pciide_pci_ca = { 1403 sizeof(struct pciide_softc), pciide_match, pciide_attach, 1404 pciide_detach, pciide_activate 1405 }; 1406 1407 const struct cfattach pciide_jmb_ca = { 1408 sizeof(struct pciide_softc), pciide_match, pciide_attach, 1409 pciide_detach, pciide_activate 1410 }; 1411 1412 struct cfdriver pciide_cd = { 1413 NULL, "pciide", DV_DULL 1414 }; 1415 1416 const struct pciide_product_desc *pciide_lookup_product(u_int32_t); 1417 1418 const struct pciide_product_desc * 1419 pciide_lookup_product(u_int32_t id) 1420 { 1421 const struct pciide_product_desc *pp; 1422 const struct pciide_vendor_desc *vp; 1423 int i; 1424 1425 for (i = 0, vp = pciide_vendors; i < nitems(pciide_vendors); vp++, i++) 1426 if (PCI_VENDOR(id) == vp->ide_vendor) 1427 break; 1428 1429 if (i == nitems(pciide_vendors)) 1430 return (NULL); 1431 1432 for (pp = vp->ide_products, i = 0; i < vp->ide_nproducts; pp++, i++) 1433 if (PCI_PRODUCT(id) == pp->ide_product) 1434 break; 1435 1436 if (i == vp->ide_nproducts) 1437 return (NULL); 1438 return (pp); 1439 } 1440 1441 int 1442 pciide_match(struct device *parent, void *match, void *aux) 1443 { 1444 struct pci_attach_args *pa = aux; 1445 const struct pciide_product_desc *pp; 1446 1447 /* 1448 * Some IDE controllers have severe bugs when used in PCI mode. 1449 * We punt and attach them to the ISA bus instead. 1450 */ 1451 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PCTECH && 1452 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_PCTECH_RZ1000) 1453 return (0); 1454 1455 /* 1456 * Some controllers (e.g. promise Ultra-33) don't claim to be PCI IDE 1457 * controllers. Let see if we can deal with it anyway. 1458 */ 1459 pp = pciide_lookup_product(pa->pa_id); 1460 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) 1461 return (1); 1462 1463 /* 1464 * Check the ID register to see that it's a PCI IDE controller. 1465 * If it is, we assume that we can deal with it; it _should_ 1466 * work in a standardized way... 1467 */ 1468 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE) { 1469 switch (PCI_SUBCLASS(pa->pa_class)) { 1470 case PCI_SUBCLASS_MASS_STORAGE_IDE: 1471 return (1); 1472 1473 /* 1474 * We only match these if we know they have 1475 * a match, as we may not support native interfaces 1476 * on them. 1477 */ 1478 case PCI_SUBCLASS_MASS_STORAGE_SATA: 1479 case PCI_SUBCLASS_MASS_STORAGE_RAID: 1480 case PCI_SUBCLASS_MASS_STORAGE_MISC: 1481 if (pp) 1482 return (1); 1483 else 1484 return (0); 1485 break; 1486 } 1487 } 1488 1489 return (0); 1490 } 1491 1492 void 1493 pciide_attach(struct device *parent, struct device *self, void *aux) 1494 { 1495 struct pciide_softc *sc = (struct pciide_softc *)self; 1496 struct pci_attach_args *pa = aux; 1497 1498 sc->sc_pp = pciide_lookup_product(pa->pa_id); 1499 if (sc->sc_pp == NULL) 1500 sc->sc_pp = &default_product_desc; 1501 sc->sc_rev = PCI_REVISION(pa->pa_class); 1502 1503 sc->sc_pc = pa->pa_pc; 1504 sc->sc_tag = pa->pa_tag; 1505 1506 /* Set up DMA defaults; these might be adjusted by chip_map. */ 1507 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 1508 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 1509 1510 sc->sc_dmacmd_read = pciide_dmacmd_read; 1511 sc->sc_dmacmd_write = pciide_dmacmd_write; 1512 sc->sc_dmactl_read = pciide_dmactl_read; 1513 sc->sc_dmactl_write = pciide_dmactl_write; 1514 sc->sc_dmatbl_write = pciide_dmatbl_write; 1515 1516 WDCDEBUG_PRINT((" sc_pc=%p, sc_tag=0x%x, pa_class=0x%x\n", sc->sc_pc, 1517 (u_int32_t)sc->sc_tag, pa->pa_class), DEBUG_PROBE); 1518 1519 if (pciide_skip_ata) 1520 sc->sc_wdcdev.quirks |= WDC_QUIRK_NOATA; 1521 if (pciide_skip_atapi) 1522 sc->sc_wdcdev.quirks |= WDC_QUIRK_NOATAPI; 1523 1524 sc->sc_pp->chip_map(sc, pa); 1525 1526 WDCDEBUG_PRINT(("pciide: command/status register=0x%x\n", 1527 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG)), 1528 DEBUG_PROBE); 1529 } 1530 1531 int 1532 pciide_detach(struct device *self, int flags) 1533 { 1534 struct pciide_softc *sc = (struct pciide_softc *)self; 1535 if (sc->chip_unmap == NULL) 1536 panic("unmap not yet implemented for this chipset"); 1537 else 1538 sc->chip_unmap(sc, flags); 1539 1540 return 0; 1541 } 1542 1543 int 1544 pciide_activate(struct device *self, int act) 1545 { 1546 int rv = 0; 1547 struct pciide_softc *sc = (struct pciide_softc *)self; 1548 int i; 1549 1550 switch (act) { 1551 case DVACT_SUSPEND: 1552 rv = config_activate_children(self, act); 1553 1554 for (i = 0; i < nitems(sc->sc_save); i++) 1555 sc->sc_save[i] = pci_conf_read(sc->sc_pc, 1556 sc->sc_tag, PCI_MAPREG_END + 0x18 + (i * 4)); 1557 1558 if (sc->sc_pp->chip_map == sch_chip_map) { 1559 sc->sc_save2[0] = pci_conf_read(sc->sc_pc, 1560 sc->sc_tag, SCH_D0TIM); 1561 sc->sc_save2[1] = pci_conf_read(sc->sc_pc, 1562 sc->sc_tag, SCH_D1TIM); 1563 } else if (sc->sc_pp->chip_map == piixsata_chip_map) { 1564 sc->sc_save2[0] = pciide_pci_read(sc->sc_pc, 1565 sc->sc_tag, ICH5_SATA_MAP); 1566 sc->sc_save2[1] = pciide_pci_read(sc->sc_pc, 1567 sc->sc_tag, ICH5_SATA_PI); 1568 sc->sc_save2[2] = pciide_pci_read(sc->sc_pc, 1569 sc->sc_tag, ICH_SATA_PCS); 1570 } else if (sc->sc_pp->chip_map == sii3112_chip_map) { 1571 sc->sc_save2[0] = pci_conf_read(sc->sc_pc, 1572 sc->sc_tag, SII3112_SCS_CMD); 1573 sc->sc_save2[1] = pci_conf_read(sc->sc_pc, 1574 sc->sc_tag, SII3112_PCI_CFGCTL); 1575 } else if (sc->sc_pp->chip_map == ite_chip_map) { 1576 sc->sc_save2[0] = pci_conf_read(sc->sc_pc, 1577 sc->sc_tag, IT_TIM(0)); 1578 } else if (sc->sc_pp->chip_map == nforce_chip_map) { 1579 sc->sc_save2[0] = pci_conf_read(sc->sc_pc, 1580 sc->sc_tag, NFORCE_PIODMATIM); 1581 sc->sc_save2[1] = pci_conf_read(sc->sc_pc, 1582 sc->sc_tag, NFORCE_PIOTIM); 1583 sc->sc_save2[2] = pci_conf_read(sc->sc_pc, 1584 sc->sc_tag, NFORCE_UDMATIM); 1585 } 1586 break; 1587 case DVACT_RESUME: 1588 for (i = 0; i < nitems(sc->sc_save); i++) 1589 pci_conf_write(sc->sc_pc, sc->sc_tag, 1590 PCI_MAPREG_END + 0x18 + (i * 4), 1591 sc->sc_save[i]); 1592 1593 if (sc->sc_pp->chip_map == default_chip_map || 1594 sc->sc_pp->chip_map == sata_chip_map || 1595 sc->sc_pp->chip_map == piix_chip_map || 1596 sc->sc_pp->chip_map == amd756_chip_map || 1597 sc->sc_pp->chip_map == phison_chip_map || 1598 sc->sc_pp->chip_map == rdc_chip_map || 1599 sc->sc_pp->chip_map == ixp_chip_map || 1600 sc->sc_pp->chip_map == acard_chip_map || 1601 sc->sc_pp->chip_map == apollo_chip_map || 1602 sc->sc_pp->chip_map == sis_chip_map) { 1603 /* nothing to restore -- uses only 0x40 - 0x56 */ 1604 } else if (sc->sc_pp->chip_map == sch_chip_map) { 1605 pci_conf_write(sc->sc_pc, sc->sc_tag, 1606 SCH_D0TIM, sc->sc_save2[0]); 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, 1608 SCH_D1TIM, sc->sc_save2[1]); 1609 } else if (sc->sc_pp->chip_map == piixsata_chip_map) { 1610 pciide_pci_write(sc->sc_pc, sc->sc_tag, 1611 ICH5_SATA_MAP, sc->sc_save2[0]); 1612 pciide_pci_write(sc->sc_pc, sc->sc_tag, 1613 ICH5_SATA_PI, sc->sc_save2[1]); 1614 pciide_pci_write(sc->sc_pc, sc->sc_tag, 1615 ICH_SATA_PCS, sc->sc_save2[2]); 1616 } else if (sc->sc_pp->chip_map == sii3112_chip_map) { 1617 pci_conf_write(sc->sc_pc, sc->sc_tag, 1618 SII3112_SCS_CMD, sc->sc_save2[0]); 1619 delay(50 * 1000); 1620 pci_conf_write(sc->sc_pc, sc->sc_tag, 1621 SII3112_PCI_CFGCTL, sc->sc_save2[1]); 1622 delay(50 * 1000); 1623 } else if (sc->sc_pp->chip_map == ite_chip_map) { 1624 pci_conf_write(sc->sc_pc, sc->sc_tag, 1625 IT_TIM(0), sc->sc_save2[0]); 1626 } else if (sc->sc_pp->chip_map == nforce_chip_map) { 1627 pci_conf_write(sc->sc_pc, sc->sc_tag, 1628 NFORCE_PIODMATIM, sc->sc_save2[0]); 1629 pci_conf_write(sc->sc_pc, sc->sc_tag, 1630 NFORCE_PIOTIM, sc->sc_save2[1]); 1631 pci_conf_write(sc->sc_pc, sc->sc_tag, 1632 NFORCE_UDMATIM, sc->sc_save2[2]); 1633 } else { 1634 printf("%s: restore for unknown chip map %x\n", 1635 sc->sc_wdcdev.sc_dev.dv_xname, 1636 sc->sc_pp->ide_product); 1637 } 1638 1639 rv = config_activate_children(self, act); 1640 break; 1641 default: 1642 rv = config_activate_children(self, act); 1643 break; 1644 } 1645 return (rv); 1646 } 1647 1648 int 1649 pciide_mapregs_compat(struct pci_attach_args *pa, struct pciide_channel *cp, 1650 int compatchan, bus_size_t *cmdsizep, bus_size_t *ctlsizep) 1651 { 1652 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1653 struct channel_softc *wdc_cp = &cp->wdc_channel; 1654 pcireg_t csr; 1655 1656 cp->compat = 1; 1657 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 1658 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 1659 1660 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1661 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1662 csr | PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE); 1663 1664 wdc_cp->cmd_iot = pa->pa_iot; 1665 1666 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 1667 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 1668 printf("%s: couldn't map %s cmd regs\n", 1669 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1670 return (0); 1671 } 1672 1673 wdc_cp->ctl_iot = pa->pa_iot; 1674 1675 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 1676 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 1677 printf("%s: couldn't map %s ctl regs\n", 1678 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1679 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 1680 PCIIDE_COMPAT_CMD_SIZE); 1681 return (0); 1682 } 1683 wdc_cp->cmd_iosz = *cmdsizep; 1684 wdc_cp->ctl_iosz = *ctlsizep; 1685 1686 return (1); 1687 } 1688 1689 int 1690 pciide_unmapregs_compat(struct pciide_softc *sc, struct pciide_channel *cp) 1691 { 1692 struct channel_softc *wdc_cp = &cp->wdc_channel; 1693 1694 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, wdc_cp->cmd_iosz); 1695 bus_space_unmap(wdc_cp->ctl_iot, wdc_cp->cmd_ioh, wdc_cp->ctl_iosz); 1696 1697 if (sc->sc_pci_ih != NULL) { 1698 pciide_machdep_compat_intr_disestablish(sc->sc_pc, sc->sc_pci_ih); 1699 sc->sc_pci_ih = NULL; 1700 } 1701 1702 return (0); 1703 } 1704 1705 int 1706 pciide_mapregs_native(struct pci_attach_args *pa, struct pciide_channel *cp, 1707 bus_size_t *cmdsizep, bus_size_t *ctlsizep, int (*pci_intr)(void *)) 1708 { 1709 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1710 struct channel_softc *wdc_cp = &cp->wdc_channel; 1711 const char *intrstr; 1712 pci_intr_handle_t intrhandle; 1713 pcireg_t maptype; 1714 1715 cp->compat = 0; 1716 1717 if (sc->sc_pci_ih == NULL) { 1718 if (pci_intr_map(pa, &intrhandle) != 0) { 1719 printf("%s: couldn't map native-PCI interrupt\n", 1720 sc->sc_wdcdev.sc_dev.dv_xname); 1721 return (0); 1722 } 1723 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1724 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 1725 intrhandle, IPL_BIO, pci_intr, sc, 1726 sc->sc_wdcdev.sc_dev.dv_xname); 1727 if (sc->sc_pci_ih != NULL) { 1728 printf("%s: using %s for native-PCI interrupt\n", 1729 sc->sc_wdcdev.sc_dev.dv_xname, 1730 intrstr ? intrstr : "unknown interrupt"); 1731 } else { 1732 printf("%s: couldn't establish native-PCI interrupt", 1733 sc->sc_wdcdev.sc_dev.dv_xname); 1734 if (intrstr != NULL) 1735 printf(" at %s", intrstr); 1736 printf("\n"); 1737 return (0); 1738 } 1739 } 1740 cp->ih = sc->sc_pci_ih; 1741 sc->sc_pc = pa->pa_pc; 1742 1743 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 1744 PCIIDE_REG_CMD_BASE(wdc_cp->channel)); 1745 WDCDEBUG_PRINT(("%s: %s cmd regs mapping: %s\n", 1746 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1747 (maptype == PCI_MAPREG_TYPE_IO ? "I/O" : "memory")), DEBUG_PROBE); 1748 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 1749 maptype, 0, 1750 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep, 0) != 0) { 1751 printf("%s: couldn't map %s cmd regs\n", 1752 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1753 return (0); 1754 } 1755 1756 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 1757 PCIIDE_REG_CTL_BASE(wdc_cp->channel)); 1758 WDCDEBUG_PRINT(("%s: %s ctl regs mapping: %s\n", 1759 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1760 (maptype == PCI_MAPREG_TYPE_IO ? "I/O": "memory")), DEBUG_PROBE); 1761 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 1762 maptype, 0, 1763 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep, 0) != 0) { 1764 printf("%s: couldn't map %s ctl regs\n", 1765 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1766 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 1767 return (0); 1768 } 1769 /* 1770 * In native mode, 4 bytes of I/O space are mapped for the control 1771 * register, the control register is at offset 2. Pass the generic 1772 * code a handle for only one byte at the right offset. 1773 */ 1774 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 1775 &wdc_cp->ctl_ioh) != 0) { 1776 printf("%s: unable to subregion %s ctl regs\n", 1777 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1778 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 1779 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 1780 return (0); 1781 } 1782 wdc_cp->cmd_iosz = *cmdsizep; 1783 wdc_cp->ctl_iosz = *ctlsizep; 1784 1785 return (1); 1786 } 1787 1788 int 1789 pciide_unmapregs_native(struct pciide_softc *sc, struct pciide_channel *cp) 1790 { 1791 struct channel_softc *wdc_cp = &cp->wdc_channel; 1792 1793 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, wdc_cp->cmd_iosz); 1794 1795 /* Unmap the whole control space, not just the sub-region */ 1796 bus_space_unmap(wdc_cp->ctl_iot, cp->ctl_baseioh, wdc_cp->ctl_iosz); 1797 1798 if (sc->sc_pci_ih != NULL) { 1799 pci_intr_disestablish(sc->sc_pc, sc->sc_pci_ih); 1800 sc->sc_pci_ih = NULL; 1801 } 1802 1803 return (0); 1804 } 1805 1806 void 1807 pciide_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 1808 { 1809 pcireg_t maptype; 1810 bus_addr_t addr; 1811 1812 /* 1813 * Map DMA registers 1814 * 1815 * Note that sc_dma_ok is the right variable to test to see if 1816 * DMA can be done. If the interface doesn't support DMA, 1817 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 1818 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 1819 * non-zero if the interface supports DMA and the registers 1820 * could be mapped. 1821 * 1822 * XXX Note that despite the fact that the Bus Master IDE specs 1823 * XXX say that "The bus master IDE function uses 16 bytes of IO 1824 * XXX space", some controllers (at least the United 1825 * XXX Microelectronics UM8886BF) place it in memory space. 1826 */ 1827 1828 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 1829 PCIIDE_REG_BUS_MASTER_DMA); 1830 1831 switch (maptype) { 1832 case PCI_MAPREG_TYPE_IO: 1833 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 1834 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 1835 &addr, NULL, NULL) == 0); 1836 if (sc->sc_dma_ok == 0) { 1837 printf(", unused (couldn't query registers)"); 1838 break; 1839 } 1840 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 1841 && addr >= 0x10000) { 1842 sc->sc_dma_ok = 0; 1843 printf(", unused (registers at unsafe address %#lx)", addr); 1844 break; 1845 } 1846 /* FALLTHROUGH */ 1847 1848 case PCI_MAPREG_MEM_TYPE_32BIT: 1849 sc->sc_dma_ok = (pci_mapreg_map(pa, 1850 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 1851 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, &sc->sc_dma_iosz, 1852 0) == 0); 1853 sc->sc_dmat = pa->pa_dmat; 1854 if (sc->sc_dma_ok == 0) { 1855 printf(", unused (couldn't map registers)"); 1856 } else { 1857 sc->sc_wdcdev.dma_arg = sc; 1858 sc->sc_wdcdev.dma_init = pciide_dma_init; 1859 sc->sc_wdcdev.dma_start = pciide_dma_start; 1860 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1861 } 1862 break; 1863 1864 default: 1865 sc->sc_dma_ok = 0; 1866 printf(", (unsupported maptype 0x%x)", maptype); 1867 break; 1868 } 1869 } 1870 1871 void 1872 pciide_unmapreg_dma(struct pciide_softc *sc) 1873 { 1874 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_iosz); 1875 } 1876 1877 int 1878 pciide_intr_flag(struct pciide_channel *cp) 1879 { 1880 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1881 int chan = cp->wdc_channel.channel; 1882 1883 if (cp->dma_in_progress) { 1884 int retry = 10; 1885 int status; 1886 1887 /* Check the status register */ 1888 for (retry = 10; retry > 0; retry--) { 1889 status = PCIIDE_DMACTL_READ(sc, chan); 1890 if (status & IDEDMA_CTL_INTR) { 1891 break; 1892 } 1893 DELAY(5); 1894 } 1895 1896 /* Not for us. */ 1897 if (retry == 0) 1898 return (0); 1899 1900 return (1); 1901 } 1902 1903 return (-1); 1904 } 1905 1906 int 1907 pciide_compat_intr(void *arg) 1908 { 1909 struct pciide_channel *cp = arg; 1910 1911 if (pciide_intr_flag(cp) == 0) 1912 return (0); 1913 1914 #ifdef DIAGNOSTIC 1915 /* should only be called for a compat channel */ 1916 if (cp->compat == 0) 1917 panic("pciide compat intr called for non-compat chan %p", cp); 1918 #endif 1919 return (wdcintr(&cp->wdc_channel)); 1920 } 1921 1922 int 1923 pciide_pci_intr(void *arg) 1924 { 1925 struct pciide_softc *sc = arg; 1926 struct pciide_channel *cp; 1927 struct channel_softc *wdc_cp; 1928 int i, rv, crv; 1929 1930 rv = 0; 1931 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1932 cp = &sc->pciide_channels[i]; 1933 wdc_cp = &cp->wdc_channel; 1934 1935 /* If a compat channel skip. */ 1936 if (cp->compat) 1937 continue; 1938 1939 if (cp->hw_ok == 0) 1940 continue; 1941 1942 if (pciide_intr_flag(cp) == 0) 1943 continue; 1944 1945 crv = wdcintr(wdc_cp); 1946 if (crv == 0) 1947 ; /* leave rv alone */ 1948 else if (crv == 1) 1949 rv = 1; /* claim the intr */ 1950 else if (rv == 0) /* crv should be -1 in this case */ 1951 rv = crv; /* if we've done no better, take it */ 1952 } 1953 return (rv); 1954 } 1955 1956 u_int8_t 1957 pciide_dmacmd_read(struct pciide_softc *sc, int chan) 1958 { 1959 return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1960 IDEDMA_CMD(chan))); 1961 } 1962 1963 void 1964 pciide_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val) 1965 { 1966 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1967 IDEDMA_CMD(chan), val); 1968 } 1969 1970 u_int8_t 1971 pciide_dmactl_read(struct pciide_softc *sc, int chan) 1972 { 1973 return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1974 IDEDMA_CTL(chan))); 1975 } 1976 1977 void 1978 pciide_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val) 1979 { 1980 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1981 IDEDMA_CTL(chan), val); 1982 } 1983 1984 void 1985 pciide_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val) 1986 { 1987 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1988 IDEDMA_TBL(chan), val); 1989 } 1990 1991 void 1992 pciide_channel_dma_setup(struct pciide_channel *cp) 1993 { 1994 int drive; 1995 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1996 struct ata_drive_datas *drvp; 1997 1998 for (drive = 0; drive < 2; drive++) { 1999 drvp = &cp->wdc_channel.ch_drive[drive]; 2000 /* If no drive, skip */ 2001 if ((drvp->drive_flags & DRIVE) == 0) 2002 continue; 2003 /* setup DMA if needed */ 2004 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2005 (drvp->drive_flags & DRIVE_UDMA) == 0) || 2006 sc->sc_dma_ok == 0) { 2007 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 2008 continue; 2009 } 2010 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 2011 != 0) { 2012 /* Abort DMA setup */ 2013 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 2014 continue; 2015 } 2016 } 2017 } 2018 2019 int 2020 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive) 2021 { 2022 bus_dma_segment_t seg; 2023 int error, rseg; 2024 const bus_size_t dma_table_size = 2025 sizeof(struct idedma_table) * NIDEDMA_TABLES; 2026 struct pciide_dma_maps *dma_maps = 2027 &sc->pciide_channels[channel].dma_maps[drive]; 2028 2029 /* If table was already allocated, just return */ 2030 if (dma_maps->dma_table) 2031 return (0); 2032 2033 /* Allocate memory for the DMA tables and map it */ 2034 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 2035 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 2036 BUS_DMA_NOWAIT)) != 0) { 2037 printf("%s:%d: unable to allocate table DMA for " 2038 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 2039 channel, drive, error); 2040 return (error); 2041 } 2042 2043 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 2044 dma_table_size, 2045 (caddr_t *)&dma_maps->dma_table, 2046 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 2047 printf("%s:%d: unable to map table DMA for" 2048 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 2049 channel, drive, error); 2050 return (error); 2051 } 2052 2053 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 2054 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 2055 seg.ds_addr), DEBUG_PROBE); 2056 2057 /* Create and load table DMA map for this disk */ 2058 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 2059 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 2060 &dma_maps->dmamap_table)) != 0) { 2061 printf("%s:%d: unable to create table DMA map for " 2062 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 2063 channel, drive, error); 2064 return (error); 2065 } 2066 if ((error = bus_dmamap_load(sc->sc_dmat, 2067 dma_maps->dmamap_table, 2068 dma_maps->dma_table, 2069 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 2070 printf("%s:%d: unable to load table DMA map for " 2071 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 2072 channel, drive, error); 2073 return (error); 2074 } 2075 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 2076 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 2077 /* Create a xfer DMA map for this drive */ 2078 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 2079 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 2080 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2081 &dma_maps->dmamap_xfer)) != 0) { 2082 printf("%s:%d: unable to create xfer DMA map for " 2083 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 2084 channel, drive, error); 2085 return (error); 2086 } 2087 return (0); 2088 } 2089 2090 int 2091 pciide_dma_init(void *v, int channel, int drive, void *databuf, 2092 size_t datalen, int flags) 2093 { 2094 struct pciide_softc *sc = v; 2095 int error, seg; 2096 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2097 struct pciide_dma_maps *dma_maps = 2098 &sc->pciide_channels[channel].dma_maps[drive]; 2099 #ifndef BUS_DMA_RAW 2100 #define BUS_DMA_RAW 0 2101 #endif 2102 2103 error = bus_dmamap_load(sc->sc_dmat, 2104 dma_maps->dmamap_xfer, 2105 databuf, datalen, NULL, BUS_DMA_NOWAIT|BUS_DMA_RAW); 2106 if (error) { 2107 printf("%s:%d: unable to load xfer DMA map for " 2108 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 2109 channel, drive, error); 2110 return (error); 2111 } 2112 2113 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 2114 dma_maps->dmamap_xfer->dm_mapsize, 2115 (flags & WDC_DMA_READ) ? 2116 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2117 2118 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 2119 #ifdef DIAGNOSTIC 2120 /* A segment must not cross a 64k boundary */ 2121 { 2122 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 2123 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 2124 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 2125 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 2126 printf("pciide_dma: segment %d physical addr 0x%lx" 2127 " len 0x%lx not properly aligned\n", 2128 seg, phys, len); 2129 panic("pciide_dma: buf align"); 2130 } 2131 } 2132 #endif 2133 dma_maps->dma_table[seg].base_addr = 2134 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 2135 dma_maps->dma_table[seg].byte_count = 2136 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 2137 IDEDMA_BYTE_COUNT_MASK); 2138 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 2139 seg, letoh32(dma_maps->dma_table[seg].byte_count), 2140 letoh32(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 2141 2142 } 2143 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 2144 htole32(IDEDMA_BYTE_COUNT_EOT); 2145 2146 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 2147 dma_maps->dmamap_table->dm_mapsize, 2148 BUS_DMASYNC_PREWRITE); 2149 2150 /* Maps are ready. Start DMA function */ 2151 #ifdef DIAGNOSTIC 2152 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 2153 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 2154 dma_maps->dmamap_table->dm_segs[0].ds_addr); 2155 panic("pciide_dma_init: table align"); 2156 } 2157 #endif 2158 2159 /* Clear status bits */ 2160 PCIIDE_DMACTL_WRITE(sc, channel, PCIIDE_DMACTL_READ(sc, channel)); 2161 /* Write table addr */ 2162 PCIIDE_DMATBL_WRITE(sc, channel, 2163 dma_maps->dmamap_table->dm_segs[0].ds_addr); 2164 /* set read/write */ 2165 PCIIDE_DMACMD_WRITE(sc, channel, 2166 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 2167 /* remember flags */ 2168 dma_maps->dma_flags = flags; 2169 return (0); 2170 } 2171 2172 void 2173 pciide_dma_start(void *v, int channel, int drive) 2174 { 2175 struct pciide_softc *sc = v; 2176 2177 WDCDEBUG_PRINT(("pciide_dma_start\n"), DEBUG_XFERS); 2178 PCIIDE_DMACMD_WRITE(sc, channel, PCIIDE_DMACMD_READ(sc, channel) | 2179 IDEDMA_CMD_START); 2180 2181 sc->pciide_channels[channel].dma_in_progress = 1; 2182 } 2183 2184 int 2185 pciide_dma_finish(void *v, int channel, int drive, int force) 2186 { 2187 struct pciide_softc *sc = v; 2188 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2189 u_int8_t status; 2190 int error = 0; 2191 struct pciide_dma_maps *dma_maps = 2192 &sc->pciide_channels[channel].dma_maps[drive]; 2193 2194 status = PCIIDE_DMACTL_READ(sc, channel); 2195 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 2196 DEBUG_XFERS); 2197 if (status == 0xff) 2198 return (status); 2199 2200 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) { 2201 error = WDC_DMAST_NOIRQ; 2202 goto done; 2203 } 2204 2205 /* stop DMA channel */ 2206 PCIIDE_DMACMD_WRITE(sc, channel, 2207 ((dma_maps->dma_flags & WDC_DMA_READ) ? 2208 0x00 : IDEDMA_CMD_WRITE) | cp->idedma_cmd); 2209 2210 /* Unload the map of the data buffer */ 2211 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 2212 dma_maps->dmamap_xfer->dm_mapsize, 2213 (dma_maps->dma_flags & WDC_DMA_READ) ? 2214 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2215 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 2216 2217 /* Clear status bits */ 2218 PCIIDE_DMACTL_WRITE(sc, channel, status); 2219 2220 if ((status & IDEDMA_CTL_ERR) != 0) { 2221 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 2222 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 2223 error |= WDC_DMAST_ERR; 2224 } 2225 2226 if ((status & IDEDMA_CTL_INTR) == 0) { 2227 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 2228 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 2229 drive, status); 2230 error |= WDC_DMAST_NOIRQ; 2231 } 2232 2233 if ((status & IDEDMA_CTL_ACT) != 0) { 2234 /* data underrun, may be a valid condition for ATAPI */ 2235 error |= WDC_DMAST_UNDER; 2236 } 2237 2238 done: 2239 sc->pciide_channels[channel].dma_in_progress = 0; 2240 return (error); 2241 } 2242 2243 void 2244 pciide_irqack(struct channel_softc *chp) 2245 { 2246 struct pciide_channel *cp = (struct pciide_channel *)chp; 2247 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2248 int chan = chp->channel; 2249 2250 /* clear status bits in IDE DMA registers */ 2251 PCIIDE_DMACTL_WRITE(sc, chan, PCIIDE_DMACTL_READ(sc, chan)); 2252 } 2253 2254 /* some common code used by several chip_map */ 2255 int 2256 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 2257 { 2258 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2259 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2260 cp->name = PCIIDE_CHANNEL_NAME(channel); 2261 cp->wdc_channel.channel = channel; 2262 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2263 cp->wdc_channel.ch_queue = wdc_alloc_queue(); 2264 if (cp->wdc_channel.ch_queue == NULL) { 2265 printf("%s: %s " 2266 "cannot allocate channel queue", 2267 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2268 return (0); 2269 } 2270 cp->hw_ok = 1; 2271 2272 return (1); 2273 } 2274 2275 void 2276 pciide_chanfree(struct pciide_softc *sc, int channel) 2277 { 2278 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2279 if (cp->wdc_channel.ch_queue) 2280 wdc_free_queue(cp->wdc_channel.ch_queue); 2281 } 2282 2283 /* some common code used by several chip channel_map */ 2284 void 2285 pciide_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp, 2286 pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep, 2287 int (*pci_intr)(void *)) 2288 { 2289 struct channel_softc *wdc_cp = &cp->wdc_channel; 2290 2291 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 2292 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 2293 pci_intr); 2294 else 2295 cp->hw_ok = pciide_mapregs_compat(pa, cp, 2296 wdc_cp->channel, cmdsizep, ctlsizep); 2297 if (cp->hw_ok == 0) 2298 return; 2299 wdc_cp->data32iot = wdc_cp->cmd_iot; 2300 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 2301 wdcattach(wdc_cp); 2302 } 2303 2304 void 2305 pciide_unmap_chan(struct pciide_softc *sc, struct pciide_channel *cp, int flags) 2306 { 2307 struct channel_softc *wdc_cp = &cp->wdc_channel; 2308 2309 wdcdetach(wdc_cp, flags); 2310 2311 if (cp->compat != 0) 2312 pciide_unmapregs_compat(sc, cp); 2313 else 2314 pciide_unmapregs_native(sc, cp); 2315 } 2316 2317 /* 2318 * Generic code to call to know if a channel can be disabled. Return 1 2319 * if channel can be disabled, 0 if not 2320 */ 2321 int 2322 pciide_chan_candisable(struct pciide_channel *cp) 2323 { 2324 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2325 struct channel_softc *wdc_cp = &cp->wdc_channel; 2326 2327 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 2328 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 2329 printf("%s: %s disabled (no drives)\n", 2330 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2331 cp->hw_ok = 0; 2332 return (1); 2333 } 2334 return (0); 2335 } 2336 2337 /* 2338 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 2339 * Set hw_ok=0 on failure 2340 */ 2341 void 2342 pciide_map_compat_intr(struct pci_attach_args *pa, struct pciide_channel *cp, 2343 int compatchan, int interface) 2344 { 2345 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2346 struct channel_softc *wdc_cp = &cp->wdc_channel; 2347 2348 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 2349 return; 2350 2351 cp->compat = 1; 2352 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 2353 pa, compatchan, pciide_compat_intr, cp); 2354 if (cp->ih == NULL) { 2355 printf("%s: no compatibility interrupt for use by %s\n", 2356 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2357 cp->hw_ok = 0; 2358 } 2359 } 2360 2361 /* 2362 * generic code to unmap the compat intr if hw_ok=1 and it is a compat channel. 2363 * Set hw_ok=0 on failure 2364 */ 2365 void 2366 pciide_unmap_compat_intr(struct pci_attach_args *pa, struct pciide_channel *cp, 2367 int compatchan, int interface) 2368 { 2369 struct channel_softc *wdc_cp = &cp->wdc_channel; 2370 2371 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 2372 return; 2373 2374 pciide_machdep_compat_intr_disestablish(pa->pa_pc, cp->ih); 2375 } 2376 2377 void 2378 pciide_print_channels(int nchannels, pcireg_t interface) 2379 { 2380 int i; 2381 2382 for (i = 0; i < nchannels; i++) { 2383 printf(", %s %s to %s", PCIIDE_CHANNEL_NAME(i), 2384 (interface & PCIIDE_INTERFACE_SETTABLE(i)) ? 2385 "configured" : "wired", 2386 (interface & PCIIDE_INTERFACE_PCI(i)) ? "native-PCI" : 2387 "compatibility"); 2388 } 2389 2390 printf("\n"); 2391 } 2392 2393 void 2394 pciide_print_modes(struct pciide_channel *cp) 2395 { 2396 wdc_print_current_modes(&cp->wdc_channel); 2397 } 2398 2399 void 2400 default_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 2401 { 2402 struct pciide_channel *cp; 2403 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2404 pcireg_t csr; 2405 int channel, drive; 2406 struct ata_drive_datas *drvp; 2407 u_int8_t idedma_ctl; 2408 bus_size_t cmdsize, ctlsize; 2409 char *failreason; 2410 2411 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2412 printf(": DMA"); 2413 if (sc->sc_pp == &default_product_desc && 2414 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 2415 PCIIDE_OPTIONS_DMA) == 0) { 2416 printf(" (unsupported)"); 2417 sc->sc_dma_ok = 0; 2418 } else { 2419 pciide_mapreg_dma(sc, pa); 2420 if (sc->sc_dma_ok != 0) 2421 printf(", (partial support)"); 2422 } 2423 } else { 2424 printf(": no DMA"); 2425 sc->sc_dma_ok = 0; 2426 } 2427 if (sc->sc_dma_ok) { 2428 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2429 sc->sc_wdcdev.irqack = pciide_irqack; 2430 } 2431 sc->sc_wdcdev.PIO_cap = 0; 2432 sc->sc_wdcdev.DMA_cap = 0; 2433 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2434 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2435 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 2436 2437 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 2438 2439 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2440 cp = &sc->pciide_channels[channel]; 2441 if (pciide_chansetup(sc, channel, interface) == 0) 2442 continue; 2443 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 2444 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2445 &ctlsize, pciide_pci_intr); 2446 } else { 2447 cp->hw_ok = pciide_mapregs_compat(pa, cp, 2448 channel, &cmdsize, &ctlsize); 2449 } 2450 if (cp->hw_ok == 0) 2451 continue; 2452 /* 2453 * Check to see if something appears to be there. 2454 */ 2455 failreason = NULL; 2456 pciide_map_compat_intr(pa, cp, channel, interface); 2457 if (cp->hw_ok == 0) 2458 continue; 2459 if (!wdcprobe(&cp->wdc_channel)) { 2460 failreason = "not responding; disabled or no drives?"; 2461 goto next; 2462 } 2463 /* 2464 * Now, make sure it's actually attributable to this PCI IDE 2465 * channel by trying to access the channel again while the 2466 * PCI IDE controller's I/O space is disabled. (If the 2467 * channel no longer appears to be there, it belongs to 2468 * this controller.) YUCK! 2469 */ 2470 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 2471 PCI_COMMAND_STATUS_REG); 2472 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 2473 csr & ~PCI_COMMAND_IO_ENABLE); 2474 if (wdcprobe(&cp->wdc_channel)) 2475 failreason = "other hardware responding at addresses"; 2476 pci_conf_write(sc->sc_pc, sc->sc_tag, 2477 PCI_COMMAND_STATUS_REG, csr); 2478 next: 2479 if (failreason) { 2480 printf("%s: %s ignored (%s)\n", 2481 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2482 failreason); 2483 cp->hw_ok = 0; 2484 pciide_unmap_compat_intr(pa, cp, channel, interface); 2485 bus_space_unmap(cp->wdc_channel.cmd_iot, 2486 cp->wdc_channel.cmd_ioh, cmdsize); 2487 if (interface & PCIIDE_INTERFACE_PCI(channel)) 2488 bus_space_unmap(cp->wdc_channel.ctl_iot, 2489 cp->ctl_baseioh, ctlsize); 2490 else 2491 bus_space_unmap(cp->wdc_channel.ctl_iot, 2492 cp->wdc_channel.ctl_ioh, ctlsize); 2493 } 2494 if (cp->hw_ok) { 2495 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2496 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2497 wdcattach(&cp->wdc_channel); 2498 } 2499 } 2500 2501 if (sc->sc_dma_ok == 0) 2502 return; 2503 2504 /* Allocate DMA maps */ 2505 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2506 idedma_ctl = 0; 2507 cp = &sc->pciide_channels[channel]; 2508 for (drive = 0; drive < 2; drive++) { 2509 drvp = &cp->wdc_channel.ch_drive[drive]; 2510 /* If no drive, skip */ 2511 if ((drvp->drive_flags & DRIVE) == 0) 2512 continue; 2513 if ((drvp->drive_flags & DRIVE_DMA) == 0) 2514 continue; 2515 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 2516 /* Abort DMA setup */ 2517 printf("%s:%d:%d: cannot allocate DMA maps, " 2518 "using PIO transfers\n", 2519 sc->sc_wdcdev.sc_dev.dv_xname, 2520 channel, drive); 2521 drvp->drive_flags &= ~DRIVE_DMA; 2522 } 2523 printf("%s:%d:%d: using DMA data transfers\n", 2524 sc->sc_wdcdev.sc_dev.dv_xname, 2525 channel, drive); 2526 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2527 } 2528 if (idedma_ctl != 0) { 2529 /* Add software bits in status register */ 2530 PCIIDE_DMACTL_WRITE(sc, channel, idedma_ctl); 2531 } 2532 } 2533 } 2534 2535 void 2536 default_chip_unmap(struct pciide_softc *sc, int flags) 2537 { 2538 struct pciide_channel *cp; 2539 int channel; 2540 2541 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2542 cp = &sc->pciide_channels[channel]; 2543 pciide_unmap_chan(sc, cp, flags); 2544 pciide_chanfree(sc, channel); 2545 } 2546 2547 pciide_unmapreg_dma(sc); 2548 2549 if (sc->sc_cookie) 2550 free(sc->sc_cookie, M_DEVBUF, sc->sc_cookielen); 2551 } 2552 2553 void 2554 sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 2555 { 2556 struct pciide_channel *cp; 2557 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2558 int channel; 2559 bus_size_t cmdsize, ctlsize; 2560 2561 if (interface == 0) { 2562 WDCDEBUG_PRINT(("sata_chip_map interface == 0\n"), 2563 DEBUG_PROBE); 2564 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2565 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2566 } 2567 2568 printf(": DMA"); 2569 pciide_mapreg_dma(sc, pa); 2570 printf("\n"); 2571 2572 if (sc->sc_dma_ok) { 2573 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | 2574 WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2575 sc->sc_wdcdev.irqack = pciide_irqack; 2576 } 2577 sc->sc_wdcdev.PIO_cap = 4; 2578 sc->sc_wdcdev.DMA_cap = 2; 2579 sc->sc_wdcdev.UDMA_cap = 6; 2580 2581 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2582 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2583 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2584 WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA; 2585 sc->sc_wdcdev.set_modes = sata_setup_channel; 2586 sc->chip_unmap = default_chip_unmap; 2587 2588 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2589 cp = &sc->pciide_channels[channel]; 2590 if (pciide_chansetup(sc, channel, interface) == 0) 2591 continue; 2592 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2593 pciide_pci_intr); 2594 sata_setup_channel(&cp->wdc_channel); 2595 } 2596 } 2597 2598 void 2599 sata_setup_channel(struct channel_softc *chp) 2600 { 2601 struct ata_drive_datas *drvp; 2602 int drive; 2603 u_int32_t idedma_ctl; 2604 struct pciide_channel *cp = (struct pciide_channel *)chp; 2605 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2606 2607 /* setup DMA if needed */ 2608 pciide_channel_dma_setup(cp); 2609 2610 idedma_ctl = 0; 2611 2612 for (drive = 0; drive < 2; drive++) { 2613 drvp = &chp->ch_drive[drive]; 2614 /* If no drive, skip */ 2615 if ((drvp->drive_flags & DRIVE) == 0) 2616 continue; 2617 if (drvp->drive_flags & DRIVE_UDMA) { 2618 /* use Ultra/DMA */ 2619 drvp->drive_flags &= ~DRIVE_DMA; 2620 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2621 } else if (drvp->drive_flags & DRIVE_DMA) { 2622 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2623 } 2624 } 2625 2626 /* 2627 * Nothing to do to setup modes; it is meaningless in S-ATA 2628 * (but many S-ATA drives still want to get the SET_FEATURE 2629 * command). 2630 */ 2631 if (idedma_ctl != 0) { 2632 /* Add software bits in status register */ 2633 PCIIDE_DMACTL_WRITE(sc, chp->channel, idedma_ctl); 2634 } 2635 pciide_print_modes(cp); 2636 } 2637 2638 void 2639 piix_timing_debug(struct pciide_softc *sc) 2640 { 2641 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 2642 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 2643 DEBUG_PROBE); 2644 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE && 2645 sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_ISA) { 2646 WDCDEBUG_PRINT((", sidetim=0x%x", 2647 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 2648 DEBUG_PROBE); 2649 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2650 WDCDEBUG_PRINT((", udmareg 0x%x", 2651 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 2652 DEBUG_PROBE); 2653 } 2654 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 2655 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6321ESB_IDE || 2656 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 2657 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 2658 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 2659 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 2660 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CAM_IDE || 2661 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE || 2662 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 2663 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBL_IDE || 2664 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 2665 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 2666 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 2667 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801GB_IDE || 2668 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE || 2669 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82372FB_IDE) { 2670 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 2671 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 2672 DEBUG_PROBE); 2673 } 2674 } 2675 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 2676 } 2677 2678 void 2679 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 2680 { 2681 struct pciide_channel *cp; 2682 int channel; 2683 u_int32_t idetim; 2684 bus_size_t cmdsize, ctlsize; 2685 2686 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2687 2688 printf(": DMA"); 2689 pciide_mapreg_dma(sc, pa); 2690 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2691 WDC_CAPABILITY_MODE; 2692 if (sc->sc_dma_ok) { 2693 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2694 sc->sc_wdcdev.irqack = pciide_irqack; 2695 switch (sc->sc_pp->ide_product) { 2696 case PCI_PRODUCT_INTEL_6300ESB_IDE: 2697 case PCI_PRODUCT_INTEL_6321ESB_IDE: 2698 case PCI_PRODUCT_INTEL_82371AB_IDE: 2699 case PCI_PRODUCT_INTEL_82372FB_IDE: 2700 case PCI_PRODUCT_INTEL_82440MX_IDE: 2701 case PCI_PRODUCT_INTEL_82451NX: 2702 case PCI_PRODUCT_INTEL_82801AA_IDE: 2703 case PCI_PRODUCT_INTEL_82801AB_IDE: 2704 case PCI_PRODUCT_INTEL_82801BAM_IDE: 2705 case PCI_PRODUCT_INTEL_82801BA_IDE: 2706 case PCI_PRODUCT_INTEL_82801CAM_IDE: 2707 case PCI_PRODUCT_INTEL_82801CA_IDE: 2708 case PCI_PRODUCT_INTEL_82801DB_IDE: 2709 case PCI_PRODUCT_INTEL_82801DBL_IDE: 2710 case PCI_PRODUCT_INTEL_82801DBM_IDE: 2711 case PCI_PRODUCT_INTEL_82801EB_IDE: 2712 case PCI_PRODUCT_INTEL_82801FB_IDE: 2713 case PCI_PRODUCT_INTEL_82801GB_IDE: 2714 case PCI_PRODUCT_INTEL_82801HBM_IDE: 2715 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2716 break; 2717 } 2718 } 2719 sc->sc_wdcdev.PIO_cap = 4; 2720 sc->sc_wdcdev.DMA_cap = 2; 2721 switch (sc->sc_pp->ide_product) { 2722 case PCI_PRODUCT_INTEL_82801AA_IDE: 2723 case PCI_PRODUCT_INTEL_82372FB_IDE: 2724 sc->sc_wdcdev.UDMA_cap = 4; 2725 break; 2726 case PCI_PRODUCT_INTEL_6300ESB_IDE: 2727 case PCI_PRODUCT_INTEL_6321ESB_IDE: 2728 case PCI_PRODUCT_INTEL_82801BAM_IDE: 2729 case PCI_PRODUCT_INTEL_82801BA_IDE: 2730 case PCI_PRODUCT_INTEL_82801CAM_IDE: 2731 case PCI_PRODUCT_INTEL_82801CA_IDE: 2732 case PCI_PRODUCT_INTEL_82801DB_IDE: 2733 case PCI_PRODUCT_INTEL_82801DBL_IDE: 2734 case PCI_PRODUCT_INTEL_82801DBM_IDE: 2735 case PCI_PRODUCT_INTEL_82801EB_IDE: 2736 case PCI_PRODUCT_INTEL_82801FB_IDE: 2737 case PCI_PRODUCT_INTEL_82801GB_IDE: 2738 case PCI_PRODUCT_INTEL_82801HBM_IDE: 2739 sc->sc_wdcdev.UDMA_cap = 5; 2740 break; 2741 default: 2742 sc->sc_wdcdev.UDMA_cap = 2; 2743 break; 2744 } 2745 2746 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE || 2747 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_ISA) { 2748 sc->sc_wdcdev.set_modes = piix_setup_channel; 2749 } else { 2750 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 2751 } 2752 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2753 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2754 2755 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 2756 2757 piix_timing_debug(sc); 2758 2759 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2760 cp = &sc->pciide_channels[channel]; 2761 2762 if (pciide_chansetup(sc, channel, interface) == 0) 2763 continue; 2764 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 2765 if ((PIIX_IDETIM_READ(idetim, channel) & 2766 PIIX_IDETIM_IDE) == 0) { 2767 printf("%s: %s ignored (disabled)\n", 2768 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2769 cp->hw_ok = 0; 2770 continue; 2771 } 2772 pciide_map_compat_intr(pa, cp, channel, interface); 2773 if (cp->hw_ok == 0) 2774 continue; 2775 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2776 pciide_pci_intr); 2777 if (cp->hw_ok == 0) 2778 goto next; 2779 if (pciide_chan_candisable(cp)) { 2780 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 2781 channel); 2782 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 2783 idetim); 2784 } 2785 if (cp->hw_ok == 0) 2786 goto next; 2787 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 2788 next: 2789 if (cp->hw_ok == 0) 2790 pciide_unmap_compat_intr(pa, cp, channel, interface); 2791 } 2792 2793 piix_timing_debug(sc); 2794 } 2795 2796 void 2797 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 2798 { 2799 struct pciide_channel *cp; 2800 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2801 int channel; 2802 bus_size_t cmdsize, ctlsize; 2803 u_int8_t reg, ich = 0; 2804 2805 printf(": DMA"); 2806 pciide_mapreg_dma(sc, pa); 2807 2808 if (sc->sc_dma_ok) { 2809 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | 2810 WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2811 sc->sc_wdcdev.irqack = pciide_irqack; 2812 sc->sc_wdcdev.DMA_cap = 2; 2813 sc->sc_wdcdev.UDMA_cap = 6; 2814 } 2815 sc->sc_wdcdev.PIO_cap = 4; 2816 2817 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2818 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2819 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2820 WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA; 2821 sc->sc_wdcdev.set_modes = sata_setup_channel; 2822 2823 switch(sc->sc_pp->ide_product) { 2824 case PCI_PRODUCT_INTEL_6300ESB_SATA: 2825 case PCI_PRODUCT_INTEL_6300ESB_SATA2: 2826 case PCI_PRODUCT_INTEL_82801EB_SATA: 2827 case PCI_PRODUCT_INTEL_82801ER_SATA: 2828 ich = 5; 2829 break; 2830 case PCI_PRODUCT_INTEL_82801FB_SATA: 2831 case PCI_PRODUCT_INTEL_82801FR_SATA: 2832 case PCI_PRODUCT_INTEL_82801FBM_SATA: 2833 ich = 6; 2834 break; 2835 default: 2836 ich = 7; 2837 break; 2838 } 2839 2840 /* 2841 * Put the SATA portion of controllers that don't operate in combined 2842 * mode into native PCI modes so the maximum number of devices can be 2843 * used. Intel calls this "enhanced mode" 2844 */ 2845 if (ich == 5) { 2846 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP); 2847 if ((reg & ICH5_SATA_MAP_COMBINED) == 0) { 2848 reg = pciide_pci_read(pa->pa_pc, pa->pa_tag, 2849 ICH5_SATA_PI); 2850 reg |= ICH5_SATA_PI_PRI_NATIVE | 2851 ICH5_SATA_PI_SEC_NATIVE; 2852 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2853 ICH5_SATA_PI, reg); 2854 interface |= PCIIDE_INTERFACE_PCI(0) | 2855 PCIIDE_INTERFACE_PCI(1); 2856 } 2857 } else { 2858 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP) & 2859 ICH6_SATA_MAP_CMB_MASK; 2860 if (reg != ICH6_SATA_MAP_CMB_PRI && 2861 reg != ICH6_SATA_MAP_CMB_SEC) { 2862 reg = pciide_pci_read(pa->pa_pc, pa->pa_tag, 2863 ICH5_SATA_PI); 2864 reg |= ICH5_SATA_PI_PRI_NATIVE | 2865 ICH5_SATA_PI_SEC_NATIVE; 2866 2867 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2868 ICH5_SATA_PI, reg); 2869 interface |= PCIIDE_INTERFACE_PCI(0) | 2870 PCIIDE_INTERFACE_PCI(1); 2871 2872 /* 2873 * Ask for SATA IDE Mode, we don't need to do this 2874 * for the combined mode case as combined mode is 2875 * only allowed in IDE Mode 2876 */ 2877 if (ich >= 7) { 2878 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, 2879 ICH5_SATA_MAP) & ~ICH7_SATA_MAP_SMS_MASK; 2880 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2881 ICH5_SATA_MAP, reg); 2882 } 2883 } 2884 } 2885 2886 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 2887 2888 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2889 cp = &sc->pciide_channels[channel]; 2890 if (pciide_chansetup(sc, channel, interface) == 0) 2891 continue; 2892 2893 pciide_map_compat_intr(pa, cp, channel, interface); 2894 if (cp->hw_ok == 0) 2895 continue; 2896 2897 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2898 pciide_pci_intr); 2899 if (cp->hw_ok != 0) 2900 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 2901 2902 if (cp->hw_ok == 0) 2903 pciide_unmap_compat_intr(pa, cp, channel, interface); 2904 } 2905 } 2906 2907 void 2908 piix_setup_channel(struct channel_softc *chp) 2909 { 2910 u_int8_t mode[2], drive; 2911 u_int32_t oidetim, idetim, idedma_ctl; 2912 struct pciide_channel *cp = (struct pciide_channel *)chp; 2913 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2914 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 2915 2916 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 2917 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 2918 idedma_ctl = 0; 2919 2920 /* set up new idetim: Enable IDE registers decode */ 2921 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 2922 chp->channel); 2923 2924 /* setup DMA */ 2925 pciide_channel_dma_setup(cp); 2926 2927 /* 2928 * Here we have to mess up with drives mode: PIIX can't have 2929 * different timings for master and slave drives. 2930 * We need to find the best combination. 2931 */ 2932 2933 /* If both drives supports DMA, take the lower mode */ 2934 if ((drvp[0].drive_flags & DRIVE_DMA) && 2935 (drvp[1].drive_flags & DRIVE_DMA)) { 2936 mode[0] = mode[1] = 2937 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 2938 drvp[0].DMA_mode = mode[0]; 2939 drvp[1].DMA_mode = mode[1]; 2940 goto ok; 2941 } 2942 /* 2943 * If only one drive supports DMA, use its mode, and 2944 * put the other one in PIO mode 0 if mode not compatible 2945 */ 2946 if (drvp[0].drive_flags & DRIVE_DMA) { 2947 mode[0] = drvp[0].DMA_mode; 2948 mode[1] = drvp[1].PIO_mode; 2949 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 2950 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 2951 mode[1] = drvp[1].PIO_mode = 0; 2952 goto ok; 2953 } 2954 if (drvp[1].drive_flags & DRIVE_DMA) { 2955 mode[1] = drvp[1].DMA_mode; 2956 mode[0] = drvp[0].PIO_mode; 2957 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 2958 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 2959 mode[0] = drvp[0].PIO_mode = 0; 2960 goto ok; 2961 } 2962 /* 2963 * If both drives are not DMA, takes the lower mode, unless 2964 * one of them is PIO mode < 2 2965 */ 2966 if (drvp[0].PIO_mode < 2) { 2967 mode[0] = drvp[0].PIO_mode = 0; 2968 mode[1] = drvp[1].PIO_mode; 2969 } else if (drvp[1].PIO_mode < 2) { 2970 mode[1] = drvp[1].PIO_mode = 0; 2971 mode[0] = drvp[0].PIO_mode; 2972 } else { 2973 mode[0] = mode[1] = 2974 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 2975 drvp[0].PIO_mode = mode[0]; 2976 drvp[1].PIO_mode = mode[1]; 2977 } 2978 ok: /* The modes are setup */ 2979 for (drive = 0; drive < 2; drive++) { 2980 if (drvp[drive].drive_flags & DRIVE_DMA) { 2981 idetim |= piix_setup_idetim_timings( 2982 mode[drive], 1, chp->channel); 2983 goto end; 2984 } 2985 } 2986 /* If we are there, none of the drives are DMA */ 2987 if (mode[0] >= 2) 2988 idetim |= piix_setup_idetim_timings( 2989 mode[0], 0, chp->channel); 2990 else 2991 idetim |= piix_setup_idetim_timings( 2992 mode[1], 0, chp->channel); 2993 end: /* 2994 * timing mode is now set up in the controller. Enable 2995 * it per-drive 2996 */ 2997 for (drive = 0; drive < 2; drive++) { 2998 /* If no drive, skip */ 2999 if ((drvp[drive].drive_flags & DRIVE) == 0) 3000 continue; 3001 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 3002 if (drvp[drive].drive_flags & DRIVE_DMA) 3003 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3004 } 3005 if (idedma_ctl != 0) { 3006 /* Add software bits in status register */ 3007 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3008 IDEDMA_CTL(chp->channel), 3009 idedma_ctl); 3010 } 3011 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 3012 pciide_print_modes(cp); 3013 } 3014 3015 void 3016 piix3_4_setup_channel(struct channel_softc *chp) 3017 { 3018 struct ata_drive_datas *drvp; 3019 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 3020 struct pciide_channel *cp = (struct pciide_channel *)chp; 3021 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3022 int drive; 3023 int channel = chp->channel; 3024 3025 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 3026 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 3027 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 3028 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 3029 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 3030 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 3031 PIIX_SIDETIM_RTC_MASK(channel)); 3032 3033 idedma_ctl = 0; 3034 /* If channel disabled, no need to go further */ 3035 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 3036 return; 3037 /* set up new idetim: Enable IDE registers decode */ 3038 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 3039 3040 /* setup DMA if needed */ 3041 pciide_channel_dma_setup(cp); 3042 3043 for (drive = 0; drive < 2; drive++) { 3044 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 3045 PIIX_UDMATIM_SET(0x3, channel, drive)); 3046 drvp = &chp->ch_drive[drive]; 3047 /* If no drive, skip */ 3048 if ((drvp->drive_flags & DRIVE) == 0) 3049 continue; 3050 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 3051 (drvp->drive_flags & DRIVE_UDMA) == 0)) 3052 goto pio; 3053 3054 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 3055 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6321ESB_IDE || 3056 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 3057 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 3058 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 3059 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 3060 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CAM_IDE || 3061 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE || 3062 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 3063 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBL_IDE || 3064 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 3065 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 3066 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 3067 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801GB_IDE || 3068 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE || 3069 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82372FB_IDE) { 3070 ideconf |= PIIX_CONFIG_PINGPONG; 3071 } 3072 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 3073 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6321ESB_IDE || 3074 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 3075 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE|| 3076 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CAM_IDE|| 3077 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE || 3078 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 3079 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBL_IDE || 3080 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 3081 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 3082 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 3083 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801GB_IDE || 3084 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 3085 /* setup Ultra/100 */ 3086 if (drvp->UDMA_mode > 2 && 3087 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 3088 drvp->UDMA_mode = 2; 3089 if (drvp->UDMA_mode > 4) { 3090 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 3091 } else { 3092 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 3093 if (drvp->UDMA_mode > 2) { 3094 ideconf |= PIIX_CONFIG_UDMA66(channel, 3095 drive); 3096 } else { 3097 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 3098 drive); 3099 } 3100 } 3101 } 3102 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 3103 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82372FB_IDE) { 3104 /* setup Ultra/66 */ 3105 if (drvp->UDMA_mode > 2 && 3106 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 3107 drvp->UDMA_mode = 2; 3108 if (drvp->UDMA_mode > 2) 3109 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 3110 else 3111 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 3112 } 3113 3114 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3115 (drvp->drive_flags & DRIVE_UDMA)) { 3116 /* use Ultra/DMA */ 3117 drvp->drive_flags &= ~DRIVE_DMA; 3118 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 3119 udmareg |= PIIX_UDMATIM_SET( 3120 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 3121 } else { 3122 /* use Multiword DMA */ 3123 drvp->drive_flags &= ~DRIVE_UDMA; 3124 if (drive == 0) { 3125 idetim |= piix_setup_idetim_timings( 3126 drvp->DMA_mode, 1, channel); 3127 } else { 3128 sidetim |= piix_setup_sidetim_timings( 3129 drvp->DMA_mode, 1, channel); 3130 idetim = PIIX_IDETIM_SET(idetim, 3131 PIIX_IDETIM_SITRE, channel); 3132 } 3133 } 3134 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3135 3136 pio: /* use PIO mode */ 3137 idetim |= piix_setup_idetim_drvs(drvp); 3138 if (drive == 0) { 3139 idetim |= piix_setup_idetim_timings( 3140 drvp->PIO_mode, 0, channel); 3141 } else { 3142 sidetim |= piix_setup_sidetim_timings( 3143 drvp->PIO_mode, 0, channel); 3144 idetim = PIIX_IDETIM_SET(idetim, 3145 PIIX_IDETIM_SITRE, channel); 3146 } 3147 } 3148 if (idedma_ctl != 0) { 3149 /* Add software bits in status register */ 3150 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3151 IDEDMA_CTL(channel), 3152 idedma_ctl); 3153 } 3154 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 3155 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 3156 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 3157 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 3158 pciide_print_modes(cp); 3159 } 3160 3161 3162 /* setup ISP and RTC fields, based on mode */ 3163 u_int32_t 3164 piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 3165 { 3166 3167 if (dma) 3168 return (PIIX_IDETIM_SET(0, 3169 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 3170 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 3171 channel)); 3172 else 3173 return (PIIX_IDETIM_SET(0, 3174 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 3175 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 3176 channel)); 3177 } 3178 3179 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 3180 u_int32_t 3181 piix_setup_idetim_drvs(struct ata_drive_datas *drvp) 3182 { 3183 u_int32_t ret = 0; 3184 struct channel_softc *chp = drvp->chnl_softc; 3185 u_int8_t channel = chp->channel; 3186 u_int8_t drive = drvp->drive; 3187 3188 /* 3189 * If drive is using UDMA, timing setup is independent 3190 * so just check DMA and PIO here. 3191 */ 3192 if (drvp->drive_flags & DRIVE_DMA) { 3193 /* if mode = DMA mode 0, use compatible timings */ 3194 if ((drvp->drive_flags & DRIVE_DMA) && 3195 drvp->DMA_mode == 0) { 3196 drvp->PIO_mode = 0; 3197 return (ret); 3198 } 3199 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 3200 /* 3201 * PIO and DMA timings are the same, use fast timings for PIO 3202 * too, else use compat timings. 3203 */ 3204 if ((piix_isp_pio[drvp->PIO_mode] != 3205 piix_isp_dma[drvp->DMA_mode]) || 3206 (piix_rtc_pio[drvp->PIO_mode] != 3207 piix_rtc_dma[drvp->DMA_mode])) 3208 drvp->PIO_mode = 0; 3209 /* if PIO mode <= 2, use compat timings for PIO */ 3210 if (drvp->PIO_mode <= 2) { 3211 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 3212 channel); 3213 return (ret); 3214 } 3215 } 3216 3217 /* 3218 * Now setup PIO modes. If mode < 2, use compat timings. 3219 * Else enable fast timings. Enable IORDY and prefetch/post 3220 * if PIO mode >= 3. 3221 */ 3222 3223 if (drvp->PIO_mode < 2) 3224 return (ret); 3225 3226 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 3227 if (drvp->PIO_mode >= 3) { 3228 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 3229 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 3230 } 3231 return (ret); 3232 } 3233 3234 /* setup values in SIDETIM registers, based on mode */ 3235 u_int32_t 3236 piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 3237 { 3238 if (dma) 3239 return (PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 3240 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel)); 3241 else 3242 return (PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 3243 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel)); 3244 } 3245 3246 void 3247 amd756_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 3248 { 3249 struct pciide_channel *cp; 3250 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3251 int channel; 3252 pcireg_t chanenable; 3253 bus_size_t cmdsize, ctlsize; 3254 3255 printf(": DMA"); 3256 pciide_mapreg_dma(sc, pa); 3257 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3258 WDC_CAPABILITY_MODE; 3259 if (sc->sc_dma_ok) { 3260 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3261 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3262 sc->sc_wdcdev.irqack = pciide_irqack; 3263 } 3264 sc->sc_wdcdev.PIO_cap = 4; 3265 sc->sc_wdcdev.DMA_cap = 2; 3266 switch (sc->sc_pp->ide_product) { 3267 case PCI_PRODUCT_AMD_8111_IDE: 3268 sc->sc_wdcdev.UDMA_cap = 6; 3269 break; 3270 case PCI_PRODUCT_AMD_766_IDE: 3271 case PCI_PRODUCT_AMD_PBC768_IDE: 3272 sc->sc_wdcdev.UDMA_cap = 5; 3273 break; 3274 default: 3275 sc->sc_wdcdev.UDMA_cap = 4; 3276 break; 3277 } 3278 sc->sc_wdcdev.set_modes = amd756_setup_channel; 3279 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3280 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3281 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 3282 3283 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 3284 3285 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3286 cp = &sc->pciide_channels[channel]; 3287 if (pciide_chansetup(sc, channel, interface) == 0) 3288 continue; 3289 3290 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 3291 printf("%s: %s ignored (disabled)\n", 3292 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3293 cp->hw_ok = 0; 3294 continue; 3295 } 3296 pciide_map_compat_intr(pa, cp, channel, interface); 3297 if (cp->hw_ok == 0) 3298 continue; 3299 3300 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3301 pciide_pci_intr); 3302 3303 if (pciide_chan_candisable(cp)) { 3304 chanenable &= ~AMD756_CHAN_EN(channel); 3305 } 3306 if (cp->hw_ok == 0) { 3307 pciide_unmap_compat_intr(pa, cp, channel, interface); 3308 continue; 3309 } 3310 3311 amd756_setup_channel(&cp->wdc_channel); 3312 } 3313 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 3314 chanenable); 3315 return; 3316 } 3317 3318 void 3319 amd756_setup_channel(struct channel_softc *chp) 3320 { 3321 u_int32_t udmatim_reg, datatim_reg; 3322 u_int8_t idedma_ctl; 3323 int mode, drive; 3324 struct ata_drive_datas *drvp; 3325 struct pciide_channel *cp = (struct pciide_channel *)chp; 3326 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3327 pcireg_t chanenable; 3328 #ifndef PCIIDE_AMD756_ENABLEDMA 3329 int product = sc->sc_pp->ide_product; 3330 int rev = sc->sc_rev; 3331 #endif 3332 3333 idedma_ctl = 0; 3334 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 3335 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 3336 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 3337 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 3338 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, 3339 AMD756_CHANSTATUS_EN); 3340 3341 /* setup DMA if needed */ 3342 pciide_channel_dma_setup(cp); 3343 3344 for (drive = 0; drive < 2; drive++) { 3345 drvp = &chp->ch_drive[drive]; 3346 /* If no drive, skip */ 3347 if ((drvp->drive_flags & DRIVE) == 0) 3348 continue; 3349 /* add timing values, setup DMA if needed */ 3350 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 3351 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 3352 mode = drvp->PIO_mode; 3353 goto pio; 3354 } 3355 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3356 (drvp->drive_flags & DRIVE_UDMA)) { 3357 /* use Ultra/DMA */ 3358 drvp->drive_flags &= ~DRIVE_DMA; 3359 3360 /* Check cable */ 3361 if ((chanenable & AMD756_CABLE(chp->channel, 3362 drive)) == 0 && drvp->UDMA_mode > 2) { 3363 WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire " 3364 "cable not detected\n", drvp->drive_name, 3365 sc->sc_wdcdev.sc_dev.dv_xname, 3366 chp->channel, drive), DEBUG_PROBE); 3367 drvp->UDMA_mode = 2; 3368 } 3369 3370 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 3371 AMD756_UDMA_EN_MTH(chp->channel, drive) | 3372 AMD756_UDMA_TIME(chp->channel, drive, 3373 amd756_udma_tim[drvp->UDMA_mode]); 3374 /* can use PIO timings, MW DMA unused */ 3375 mode = drvp->PIO_mode; 3376 } else { 3377 /* use Multiword DMA, but only if revision is OK */ 3378 drvp->drive_flags &= ~DRIVE_UDMA; 3379 #ifndef PCIIDE_AMD756_ENABLEDMA 3380 /* 3381 * The workaround doesn't seem to be necessary 3382 * with all drives, so it can be disabled by 3383 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 3384 * triggered. 3385 */ 3386 if (AMD756_CHIPREV_DISABLEDMA(product, rev)) { 3387 printf("%s:%d:%d: multi-word DMA disabled due " 3388 "to chip revision\n", 3389 sc->sc_wdcdev.sc_dev.dv_xname, 3390 chp->channel, drive); 3391 mode = drvp->PIO_mode; 3392 drvp->drive_flags &= ~DRIVE_DMA; 3393 goto pio; 3394 } 3395 #endif 3396 /* mode = min(pio, dma+2) */ 3397 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 3398 mode = drvp->PIO_mode; 3399 else 3400 mode = drvp->DMA_mode + 2; 3401 } 3402 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3403 3404 pio: /* setup PIO mode */ 3405 if (mode <= 2) { 3406 drvp->DMA_mode = 0; 3407 drvp->PIO_mode = 0; 3408 mode = 0; 3409 } else { 3410 drvp->PIO_mode = mode; 3411 drvp->DMA_mode = mode - 2; 3412 } 3413 datatim_reg |= 3414 AMD756_DATATIM_PULSE(chp->channel, drive, 3415 amd756_pio_set[mode]) | 3416 AMD756_DATATIM_RECOV(chp->channel, drive, 3417 amd756_pio_rec[mode]); 3418 } 3419 if (idedma_ctl != 0) { 3420 /* Add software bits in status register */ 3421 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3422 IDEDMA_CTL(chp->channel), 3423 idedma_ctl); 3424 } 3425 pciide_print_modes(cp); 3426 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 3427 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 3428 } 3429 3430 void 3431 apollo_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 3432 { 3433 struct pciide_channel *cp; 3434 pcireg_t interface; 3435 int no_ideconf = 0, channel; 3436 u_int32_t ideconf; 3437 bus_size_t cmdsize, ctlsize; 3438 pcitag_t tag; 3439 pcireg_t id, class; 3440 3441 /* 3442 * Fake interface since VT6410 is claimed to be a ``RAID'' device. 3443 */ 3444 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3445 interface = PCI_INTERFACE(pa->pa_class); 3446 } else { 3447 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3448 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3449 } 3450 3451 switch (PCI_PRODUCT(pa->pa_id)) { 3452 case PCI_PRODUCT_VIATECH_VT6410: 3453 case PCI_PRODUCT_VIATECH_VT6415: 3454 no_ideconf = 1; 3455 /* FALLTHROUGH */ 3456 case PCI_PRODUCT_VIATECH_CX700_IDE: 3457 case PCI_PRODUCT_VIATECH_VX700_IDE: 3458 case PCI_PRODUCT_VIATECH_VX855_IDE: 3459 case PCI_PRODUCT_VIATECH_VX900_IDE: 3460 printf(": ATA133"); 3461 sc->sc_wdcdev.UDMA_cap = 6; 3462 break; 3463 default: 3464 /* 3465 * Determine the DMA capabilities by looking at the 3466 * ISA bridge. 3467 */ 3468 tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 3469 id = pci_conf_read(sc->sc_pc, tag, PCI_ID_REG); 3470 class = pci_conf_read(sc->sc_pc, tag, PCI_CLASS_REG); 3471 3472 /* 3473 * XXX On the VT8237, the ISA bridge is on a different 3474 * device. 3475 */ 3476 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE && 3477 pa->pa_device == 15) { 3478 tag = pci_make_tag(pa->pa_pc, pa->pa_bus, 17, 0); 3479 id = pci_conf_read(sc->sc_pc, tag, PCI_ID_REG); 3480 class = pci_conf_read(sc->sc_pc, tag, PCI_CLASS_REG); 3481 } 3482 3483 switch (PCI_PRODUCT(id)) { 3484 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 3485 if (PCI_REVISION(class) >= 0x02) { 3486 printf(": ATA33"); 3487 sc->sc_wdcdev.UDMA_cap = 2; 3488 } else { 3489 printf(": DMA"); 3490 sc->sc_wdcdev.UDMA_cap = 0; 3491 } 3492 break; 3493 case PCI_PRODUCT_VIATECH_VT82C596A: 3494 if (PCI_REVISION(class) >= 0x12) { 3495 printf(": ATA66"); 3496 sc->sc_wdcdev.UDMA_cap = 4; 3497 } else { 3498 printf(": ATA33"); 3499 sc->sc_wdcdev.UDMA_cap = 2; 3500 } 3501 break; 3502 3503 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 3504 if (PCI_REVISION(class) >= 0x40) { 3505 printf(": ATA100"); 3506 sc->sc_wdcdev.UDMA_cap = 5; 3507 } else { 3508 printf(": ATA66"); 3509 sc->sc_wdcdev.UDMA_cap = 4; 3510 } 3511 break; 3512 case PCI_PRODUCT_VIATECH_VT8231_ISA: 3513 case PCI_PRODUCT_VIATECH_VT8233_ISA: 3514 printf(": ATA100"); 3515 sc->sc_wdcdev.UDMA_cap = 5; 3516 break; 3517 case PCI_PRODUCT_VIATECH_VT8233A_ISA: 3518 case PCI_PRODUCT_VIATECH_VT8235_ISA: 3519 case PCI_PRODUCT_VIATECH_VT8237_ISA: 3520 printf(": ATA133"); 3521 sc->sc_wdcdev.UDMA_cap = 6; 3522 break; 3523 default: 3524 printf(": DMA"); 3525 sc->sc_wdcdev.UDMA_cap = 0; 3526 break; 3527 } 3528 break; 3529 } 3530 3531 pciide_mapreg_dma(sc, pa); 3532 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3533 WDC_CAPABILITY_MODE; 3534 if (sc->sc_dma_ok) { 3535 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3536 sc->sc_wdcdev.irqack = pciide_irqack; 3537 if (sc->sc_wdcdev.UDMA_cap > 0) 3538 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3539 } 3540 sc->sc_wdcdev.PIO_cap = 4; 3541 sc->sc_wdcdev.DMA_cap = 2; 3542 sc->sc_wdcdev.set_modes = apollo_setup_channel; 3543 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3544 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3545 3546 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 3547 3548 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 3549 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 3550 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 3551 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 3552 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 3553 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 3554 DEBUG_PROBE); 3555 3556 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3557 cp = &sc->pciide_channels[channel]; 3558 if (pciide_chansetup(sc, channel, interface) == 0) 3559 continue; 3560 3561 if (no_ideconf == 0) { 3562 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, 3563 APO_IDECONF); 3564 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 3565 printf("%s: %s ignored (disabled)\n", 3566 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3567 cp->hw_ok = 0; 3568 continue; 3569 } 3570 } 3571 pciide_map_compat_intr(pa, cp, channel, interface); 3572 if (cp->hw_ok == 0) 3573 continue; 3574 3575 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3576 pciide_pci_intr); 3577 if (cp->hw_ok == 0) { 3578 goto next; 3579 } 3580 if (pciide_chan_candisable(cp)) { 3581 if (no_ideconf == 0) { 3582 ideconf &= ~APO_IDECONF_EN(channel); 3583 pci_conf_write(sc->sc_pc, sc->sc_tag, 3584 APO_IDECONF, ideconf); 3585 } 3586 } 3587 3588 if (cp->hw_ok == 0) 3589 goto next; 3590 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 3591 next: 3592 if (cp->hw_ok == 0) 3593 pciide_unmap_compat_intr(pa, cp, channel, interface); 3594 } 3595 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 3596 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 3597 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 3598 } 3599 3600 void 3601 apollo_setup_channel(struct channel_softc *chp) 3602 { 3603 u_int32_t udmatim_reg, datatim_reg; 3604 u_int8_t idedma_ctl; 3605 int mode, drive; 3606 struct ata_drive_datas *drvp; 3607 struct pciide_channel *cp = (struct pciide_channel *)chp; 3608 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3609 3610 idedma_ctl = 0; 3611 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 3612 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 3613 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 3614 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 3615 3616 /* setup DMA if needed */ 3617 pciide_channel_dma_setup(cp); 3618 3619 /* 3620 * We can't mix Ultra/33 and Ultra/66 on the same channel, so 3621 * downgrade to Ultra/33 if needed 3622 */ 3623 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3624 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 3625 /* both drives UDMA */ 3626 if (chp->ch_drive[0].UDMA_mode > 2 && 3627 chp->ch_drive[1].UDMA_mode <= 2) { 3628 /* drive 0 Ultra/66, drive 1 Ultra/33 */ 3629 chp->ch_drive[0].UDMA_mode = 2; 3630 } else if (chp->ch_drive[1].UDMA_mode > 2 && 3631 chp->ch_drive[0].UDMA_mode <= 2) { 3632 /* drive 1 Ultra/66, drive 0 Ultra/33 */ 3633 chp->ch_drive[1].UDMA_mode = 2; 3634 } 3635 } 3636 3637 for (drive = 0; drive < 2; drive++) { 3638 drvp = &chp->ch_drive[drive]; 3639 /* If no drive, skip */ 3640 if ((drvp->drive_flags & DRIVE) == 0) 3641 continue; 3642 /* add timing values, setup DMA if needed */ 3643 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 3644 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 3645 mode = drvp->PIO_mode; 3646 goto pio; 3647 } 3648 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3649 (drvp->drive_flags & DRIVE_UDMA)) { 3650 /* use Ultra/DMA */ 3651 drvp->drive_flags &= ~DRIVE_DMA; 3652 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 3653 APO_UDMA_EN_MTH(chp->channel, drive); 3654 if (sc->sc_wdcdev.UDMA_cap == 6) { 3655 udmatim_reg |= APO_UDMA_TIME(chp->channel, 3656 drive, apollo_udma133_tim[drvp->UDMA_mode]); 3657 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 3658 /* 686b */ 3659 udmatim_reg |= APO_UDMA_TIME(chp->channel, 3660 drive, apollo_udma100_tim[drvp->UDMA_mode]); 3661 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 3662 /* 596b or 686a */ 3663 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 3664 udmatim_reg |= APO_UDMA_TIME(chp->channel, 3665 drive, apollo_udma66_tim[drvp->UDMA_mode]); 3666 } else { 3667 /* 596a or 586b */ 3668 udmatim_reg |= APO_UDMA_TIME(chp->channel, 3669 drive, apollo_udma33_tim[drvp->UDMA_mode]); 3670 } 3671 /* can use PIO timings, MW DMA unused */ 3672 mode = drvp->PIO_mode; 3673 } else { 3674 /* use Multiword DMA */ 3675 drvp->drive_flags &= ~DRIVE_UDMA; 3676 /* mode = min(pio, dma+2) */ 3677 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 3678 mode = drvp->PIO_mode; 3679 else 3680 mode = drvp->DMA_mode + 2; 3681 } 3682 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3683 3684 pio: /* setup PIO mode */ 3685 if (mode <= 2) { 3686 drvp->DMA_mode = 0; 3687 drvp->PIO_mode = 0; 3688 mode = 0; 3689 } else { 3690 drvp->PIO_mode = mode; 3691 drvp->DMA_mode = mode - 2; 3692 } 3693 datatim_reg |= 3694 APO_DATATIM_PULSE(chp->channel, drive, 3695 apollo_pio_set[mode]) | 3696 APO_DATATIM_RECOV(chp->channel, drive, 3697 apollo_pio_rec[mode]); 3698 } 3699 if (idedma_ctl != 0) { 3700 /* Add software bits in status register */ 3701 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3702 IDEDMA_CTL(chp->channel), 3703 idedma_ctl); 3704 } 3705 pciide_print_modes(cp); 3706 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 3707 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 3708 } 3709 3710 void 3711 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 3712 int channel) 3713 { 3714 struct pciide_channel *cp = &sc->pciide_channels[channel]; 3715 bus_size_t cmdsize, ctlsize; 3716 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 3717 pcireg_t interface; 3718 int one_channel; 3719 3720 /* 3721 * The 0648/0649 can be told to identify as a RAID controller. 3722 * In this case, we have to fake interface 3723 */ 3724 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 3725 interface = PCIIDE_INTERFACE_SETTABLE(0) | 3726 PCIIDE_INTERFACE_SETTABLE(1); 3727 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 3728 CMD_CONF_DSA1) 3729 interface |= PCIIDE_INTERFACE_PCI(0) | 3730 PCIIDE_INTERFACE_PCI(1); 3731 } else { 3732 interface = PCI_INTERFACE(pa->pa_class); 3733 } 3734 3735 sc->wdc_chanarray[channel] = &cp->wdc_channel; 3736 cp->name = PCIIDE_CHANNEL_NAME(channel); 3737 cp->wdc_channel.channel = channel; 3738 cp->wdc_channel.wdc = &sc->sc_wdcdev; 3739 3740 /* 3741 * Older CMD64X doesn't have independent channels 3742 */ 3743 switch (sc->sc_pp->ide_product) { 3744 case PCI_PRODUCT_CMDTECH_649: 3745 one_channel = 0; 3746 break; 3747 default: 3748 one_channel = 1; 3749 break; 3750 } 3751 3752 if (channel > 0 && one_channel) { 3753 cp->wdc_channel.ch_queue = 3754 sc->pciide_channels[0].wdc_channel.ch_queue; 3755 } else { 3756 cp->wdc_channel.ch_queue = wdc_alloc_queue(); 3757 } 3758 if (cp->wdc_channel.ch_queue == NULL) { 3759 printf( 3760 "%s: %s cannot allocate channel queue", 3761 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3762 return; 3763 } 3764 3765 /* 3766 * with a CMD PCI64x, if we get here, the first channel is enabled: 3767 * there's no way to disable the first channel without disabling 3768 * the whole device 3769 */ 3770 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 3771 printf("%s: %s ignored (disabled)\n", 3772 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3773 cp->hw_ok = 0; 3774 return; 3775 } 3776 cp->hw_ok = 1; 3777 pciide_map_compat_intr(pa, cp, channel, interface); 3778 if (cp->hw_ok == 0) 3779 return; 3780 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 3781 if (cp->hw_ok == 0) { 3782 pciide_unmap_compat_intr(pa, cp, channel, interface); 3783 return; 3784 } 3785 if (pciide_chan_candisable(cp)) { 3786 if (channel == 1) { 3787 ctrl &= ~CMD_CTRL_2PORT; 3788 pciide_pci_write(pa->pa_pc, pa->pa_tag, 3789 CMD_CTRL, ctrl); 3790 pciide_unmap_compat_intr(pa, cp, channel, interface); 3791 } 3792 } 3793 } 3794 3795 int 3796 cmd_pci_intr(void *arg) 3797 { 3798 struct pciide_softc *sc = arg; 3799 struct pciide_channel *cp; 3800 struct channel_softc *wdc_cp; 3801 int i, rv, crv; 3802 u_int32_t priirq, secirq; 3803 3804 rv = 0; 3805 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 3806 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 3807 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3808 cp = &sc->pciide_channels[i]; 3809 wdc_cp = &cp->wdc_channel; 3810 /* If a compat channel skip. */ 3811 if (cp->compat) 3812 continue; 3813 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 3814 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 3815 crv = wdcintr(wdc_cp); 3816 if (crv == 0) { 3817 #if 0 3818 printf("%s:%d: bogus intr\n", 3819 sc->sc_wdcdev.sc_dev.dv_xname, i); 3820 #endif 3821 } else 3822 rv = 1; 3823 } 3824 } 3825 return (rv); 3826 } 3827 3828 void 3829 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 3830 { 3831 int channel; 3832 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3833 3834 printf(": no DMA"); 3835 sc->sc_dma_ok = 0; 3836 3837 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3838 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3839 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 3840 3841 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 3842 3843 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3844 cmd_channel_map(pa, sc, channel); 3845 } 3846 } 3847 3848 void 3849 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 3850 { 3851 struct pciide_channel *cp; 3852 int channel; 3853 int rev = sc->sc_rev; 3854 pcireg_t interface; 3855 3856 /* 3857 * The 0648/0649 can be told to identify as a RAID controller. 3858 * In this case, we have to fake interface 3859 */ 3860 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 3861 interface = PCIIDE_INTERFACE_SETTABLE(0) | 3862 PCIIDE_INTERFACE_SETTABLE(1); 3863 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 3864 CMD_CONF_DSA1) 3865 interface |= PCIIDE_INTERFACE_PCI(0) | 3866 PCIIDE_INTERFACE_PCI(1); 3867 } else { 3868 interface = PCI_INTERFACE(pa->pa_class); 3869 } 3870 3871 printf(": DMA"); 3872 pciide_mapreg_dma(sc, pa); 3873 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3874 WDC_CAPABILITY_MODE; 3875 if (sc->sc_dma_ok) { 3876 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3877 switch (sc->sc_pp->ide_product) { 3878 case PCI_PRODUCT_CMDTECH_649: 3879 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3880 sc->sc_wdcdev.UDMA_cap = 5; 3881 sc->sc_wdcdev.irqack = cmd646_9_irqack; 3882 break; 3883 case PCI_PRODUCT_CMDTECH_648: 3884 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3885 sc->sc_wdcdev.UDMA_cap = 4; 3886 sc->sc_wdcdev.irqack = cmd646_9_irqack; 3887 break; 3888 case PCI_PRODUCT_CMDTECH_646: 3889 if (rev >= CMD0646U2_REV) { 3890 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3891 sc->sc_wdcdev.UDMA_cap = 2; 3892 } else if (rev >= CMD0646U_REV) { 3893 /* 3894 * Linux's driver claims that the 646U is broken 3895 * with UDMA. Only enable it if we know what we're 3896 * doing 3897 */ 3898 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 3899 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3900 sc->sc_wdcdev.UDMA_cap = 2; 3901 #endif 3902 /* explicitly disable UDMA */ 3903 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3904 CMD_UDMATIM(0), 0); 3905 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3906 CMD_UDMATIM(1), 0); 3907 } 3908 sc->sc_wdcdev.irqack = cmd646_9_irqack; 3909 break; 3910 default: 3911 sc->sc_wdcdev.irqack = pciide_irqack; 3912 } 3913 } 3914 3915 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3916 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3917 sc->sc_wdcdev.PIO_cap = 4; 3918 sc->sc_wdcdev.DMA_cap = 2; 3919 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 3920 3921 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 3922 3923 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 3924 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 3925 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 3926 DEBUG_PROBE); 3927 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3928 cp = &sc->pciide_channels[channel]; 3929 cmd_channel_map(pa, sc, channel); 3930 if (cp->hw_ok == 0) 3931 continue; 3932 cmd0643_9_setup_channel(&cp->wdc_channel); 3933 } 3934 /* 3935 * note - this also makes sure we clear the irq disable and reset 3936 * bits 3937 */ 3938 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 3939 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 3940 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 3941 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 3942 DEBUG_PROBE); 3943 } 3944 3945 void 3946 cmd0643_9_setup_channel(struct channel_softc *chp) 3947 { 3948 struct ata_drive_datas *drvp; 3949 u_int8_t tim; 3950 u_int32_t idedma_ctl, udma_reg; 3951 int drive; 3952 struct pciide_channel *cp = (struct pciide_channel *)chp; 3953 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3954 3955 idedma_ctl = 0; 3956 /* setup DMA if needed */ 3957 pciide_channel_dma_setup(cp); 3958 3959 for (drive = 0; drive < 2; drive++) { 3960 drvp = &chp->ch_drive[drive]; 3961 /* If no drive, skip */ 3962 if ((drvp->drive_flags & DRIVE) == 0) 3963 continue; 3964 /* add timing values, setup DMA if needed */ 3965 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 3966 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 3967 if (drvp->drive_flags & DRIVE_UDMA) { 3968 /* UltraDMA on a 646U2, 0648 or 0649 */ 3969 drvp->drive_flags &= ~DRIVE_DMA; 3970 udma_reg = pciide_pci_read(sc->sc_pc, 3971 sc->sc_tag, CMD_UDMATIM(chp->channel)); 3972 if (drvp->UDMA_mode > 2 && 3973 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3974 CMD_BICSR) & 3975 CMD_BICSR_80(chp->channel)) == 0) { 3976 WDCDEBUG_PRINT(("%s(%s:%d:%d): " 3977 "80-wire cable not detected\n", 3978 drvp->drive_name, 3979 sc->sc_wdcdev.sc_dev.dv_xname, 3980 chp->channel, drive), DEBUG_PROBE); 3981 drvp->UDMA_mode = 2; 3982 } 3983 if (drvp->UDMA_mode > 2) 3984 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 3985 else if (sc->sc_wdcdev.UDMA_cap > 2) 3986 udma_reg |= CMD_UDMATIM_UDMA33(drive); 3987 udma_reg |= CMD_UDMATIM_UDMA(drive); 3988 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 3989 CMD_UDMATIM_TIM_OFF(drive)); 3990 udma_reg |= 3991 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 3992 CMD_UDMATIM_TIM_OFF(drive)); 3993 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3994 CMD_UDMATIM(chp->channel), udma_reg); 3995 } else { 3996 /* 3997 * use Multiword DMA. 3998 * Timings will be used for both PIO and DMA, 3999 * so adjust DMA mode if needed 4000 * if we have a 0646U2/8/9, turn off UDMA 4001 */ 4002 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 4003 udma_reg = pciide_pci_read(sc->sc_pc, 4004 sc->sc_tag, 4005 CMD_UDMATIM(chp->channel)); 4006 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 4007 pciide_pci_write(sc->sc_pc, sc->sc_tag, 4008 CMD_UDMATIM(chp->channel), 4009 udma_reg); 4010 } 4011 if (drvp->PIO_mode >= 3 && 4012 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 4013 drvp->DMA_mode = drvp->PIO_mode - 2; 4014 } 4015 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 4016 } 4017 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4018 } 4019 pciide_pci_write(sc->sc_pc, sc->sc_tag, 4020 CMD_DATA_TIM(chp->channel, drive), tim); 4021 } 4022 if (idedma_ctl != 0) { 4023 /* Add software bits in status register */ 4024 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4025 IDEDMA_CTL(chp->channel), 4026 idedma_ctl); 4027 } 4028 pciide_print_modes(cp); 4029 #ifdef __sparc64__ 4030 /* 4031 * The Ultra 5 has a tendency to hang during reboot. This is due 4032 * to the PCI0646U asserting a PCI interrupt line when the chip 4033 * registers claim that it is not. Performing a reset at this 4034 * point appears to eliminate the symptoms. It is likely the 4035 * real cause is still lurking somewhere in the code. 4036 */ 4037 wdcreset(chp, SILENT); 4038 #endif /* __sparc64__ */ 4039 } 4040 4041 void 4042 cmd646_9_irqack(struct channel_softc *chp) 4043 { 4044 u_int32_t priirq, secirq; 4045 struct pciide_channel *cp = (struct pciide_channel *)chp; 4046 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4047 4048 if (chp->channel == 0) { 4049 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 4050 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 4051 } else { 4052 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 4053 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 4054 } 4055 pciide_irqack(chp); 4056 } 4057 4058 void 4059 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 4060 { 4061 struct pciide_channel *cp; 4062 int channel; 4063 4064 printf("\n%s: bus-master DMA support present", 4065 sc->sc_wdcdev.sc_dev.dv_xname); 4066 pciide_mapreg_dma(sc, pa); 4067 printf("\n"); 4068 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4069 WDC_CAPABILITY_MODE; 4070 if (sc->sc_dma_ok) { 4071 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4072 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 4073 sc->sc_wdcdev.UDMA_cap = 6; 4074 sc->sc_wdcdev.irqack = pciide_irqack; 4075 } 4076 4077 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4078 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4079 sc->sc_wdcdev.PIO_cap = 4; 4080 sc->sc_wdcdev.DMA_cap = 2; 4081 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 4082 4083 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 4084 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 4085 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 4086 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 4087 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4088 cp = &sc->pciide_channels[channel]; 4089 cmd680_channel_map(pa, sc, channel); 4090 if (cp->hw_ok == 0) 4091 continue; 4092 cmd680_setup_channel(&cp->wdc_channel); 4093 } 4094 } 4095 4096 void 4097 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 4098 int channel) 4099 { 4100 struct pciide_channel *cp = &sc->pciide_channels[channel]; 4101 bus_size_t cmdsize, ctlsize; 4102 int interface, i, reg; 4103 static const u_int8_t init_val[] = 4104 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 4105 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 4106 4107 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 4108 interface = PCIIDE_INTERFACE_SETTABLE(0) | 4109 PCIIDE_INTERFACE_SETTABLE(1); 4110 interface |= PCIIDE_INTERFACE_PCI(0) | 4111 PCIIDE_INTERFACE_PCI(1); 4112 } else { 4113 interface = PCI_INTERFACE(pa->pa_class); 4114 } 4115 4116 sc->wdc_chanarray[channel] = &cp->wdc_channel; 4117 cp->name = PCIIDE_CHANNEL_NAME(channel); 4118 cp->wdc_channel.channel = channel; 4119 cp->wdc_channel.wdc = &sc->sc_wdcdev; 4120 4121 cp->wdc_channel.ch_queue = wdc_alloc_queue(); 4122 if (cp->wdc_channel.ch_queue == NULL) { 4123 printf("%s %s: " 4124 "cannot allocate channel queue", 4125 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4126 return; 4127 } 4128 4129 /* XXX */ 4130 reg = 0xa2 + channel * 16; 4131 for (i = 0; i < sizeof(init_val); i++) 4132 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 4133 4134 printf("%s: %s %s to %s mode\n", 4135 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 4136 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 4137 "configured" : "wired", 4138 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 4139 "native-PCI" : "compatibility"); 4140 4141 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 4142 if (cp->hw_ok == 0) 4143 return; 4144 pciide_map_compat_intr(pa, cp, channel, interface); 4145 } 4146 4147 void 4148 cmd680_setup_channel(struct channel_softc *chp) 4149 { 4150 struct ata_drive_datas *drvp; 4151 u_int8_t mode, off, scsc; 4152 u_int16_t val; 4153 u_int32_t idedma_ctl; 4154 int drive; 4155 struct pciide_channel *cp = (struct pciide_channel *)chp; 4156 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4157 pci_chipset_tag_t pc = sc->sc_pc; 4158 pcitag_t pa = sc->sc_tag; 4159 static const u_int8_t udma2_tbl[] = 4160 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 4161 static const u_int8_t udma_tbl[] = 4162 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 4163 static const u_int16_t dma_tbl[] = 4164 { 0x2208, 0x10c2, 0x10c1 }; 4165 static const u_int16_t pio_tbl[] = 4166 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 4167 4168 idedma_ctl = 0; 4169 pciide_channel_dma_setup(cp); 4170 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 4171 4172 for (drive = 0; drive < 2; drive++) { 4173 drvp = &chp->ch_drive[drive]; 4174 /* If no drive, skip */ 4175 if ((drvp->drive_flags & DRIVE) == 0) 4176 continue; 4177 mode &= ~(0x03 << (drive * 4)); 4178 if (drvp->drive_flags & DRIVE_UDMA) { 4179 drvp->drive_flags &= ~DRIVE_DMA; 4180 off = 0xa0 + chp->channel * 16; 4181 if (drvp->UDMA_mode > 2 && 4182 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 4183 drvp->UDMA_mode = 2; 4184 scsc = pciide_pci_read(pc, pa, 0x8a); 4185 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 4186 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 4187 scsc = pciide_pci_read(pc, pa, 0x8a); 4188 if ((scsc & 0x30) == 0) 4189 drvp->UDMA_mode = 5; 4190 } 4191 mode |= 0x03 << (drive * 4); 4192 off = 0xac + chp->channel * 16 + drive * 2; 4193 val = pciide_pci_read(pc, pa, off) & ~0x3f; 4194 if (scsc & 0x30) 4195 val |= udma2_tbl[drvp->UDMA_mode]; 4196 else 4197 val |= udma_tbl[drvp->UDMA_mode]; 4198 pciide_pci_write(pc, pa, off, val); 4199 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4200 } else if (drvp->drive_flags & DRIVE_DMA) { 4201 mode |= 0x02 << (drive * 4); 4202 off = 0xa8 + chp->channel * 16 + drive * 2; 4203 val = dma_tbl[drvp->DMA_mode]; 4204 pciide_pci_write(pc, pa, off, val & 0xff); 4205 pciide_pci_write(pc, pa, off, val >> 8); 4206 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4207 } else { 4208 mode |= 0x01 << (drive * 4); 4209 off = 0xa4 + chp->channel * 16 + drive * 2; 4210 val = pio_tbl[drvp->PIO_mode]; 4211 pciide_pci_write(pc, pa, off, val & 0xff); 4212 pciide_pci_write(pc, pa, off, val >> 8); 4213 } 4214 } 4215 4216 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 4217 if (idedma_ctl != 0) { 4218 /* Add software bits in status register */ 4219 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4220 IDEDMA_CTL(chp->channel), 4221 idedma_ctl); 4222 } 4223 pciide_print_modes(cp); 4224 } 4225 4226 /* 4227 * When the Silicon Image 3112 retries a PCI memory read command, 4228 * it may retry it as a memory read multiple command under some 4229 * circumstances. This can totally confuse some PCI controllers, 4230 * so ensure that it will never do this by making sure that the 4231 * Read Threshold (FIFO Read Request Control) field of the FIFO 4232 * Valid Byte Count and Control registers for both channels (BA5 4233 * offset 0x40 and 0x44) are set to be at least as large as the 4234 * cacheline size register. 4235 */ 4236 void 4237 sii_fixup_cacheline(struct pciide_softc *sc, struct pci_attach_args *pa) 4238 { 4239 pcireg_t cls, reg40, reg44; 4240 4241 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 4242 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 4243 cls *= 4; 4244 if (cls > 224) { 4245 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 4246 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 4247 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 4248 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 4249 cls = 224; 4250 } 4251 if (cls < 32) 4252 cls = 32; 4253 cls = (cls + 31) / 32; 4254 reg40 = ba5_read_4(sc, 0x40); 4255 reg44 = ba5_read_4(sc, 0x44); 4256 if ((reg40 & 0x7) < cls) 4257 ba5_write_4(sc, 0x40, (reg40 & ~0x07) | cls); 4258 if ((reg44 & 0x7) < cls) 4259 ba5_write_4(sc, 0x44, (reg44 & ~0x07) | cls); 4260 } 4261 4262 void 4263 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 4264 { 4265 struct pciide_channel *cp; 4266 bus_size_t cmdsize, ctlsize; 4267 pcireg_t interface, scs_cmd, cfgctl; 4268 int channel; 4269 struct pciide_satalink *sl; 4270 4271 /* Allocate memory for private data */ 4272 sc->sc_cookielen = sizeof(*sl); 4273 sc->sc_cookie = malloc(sc->sc_cookielen, M_DEVBUF, M_NOWAIT | M_ZERO); 4274 sl = sc->sc_cookie; 4275 4276 sc->chip_unmap = default_chip_unmap; 4277 4278 #define SII3112_RESET_BITS \ 4279 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 4280 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 4281 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 4282 4283 /* 4284 * Reset everything and then unblock all of the interrupts. 4285 */ 4286 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 4287 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 4288 scs_cmd | SII3112_RESET_BITS); 4289 delay(50 * 1000); 4290 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 4291 scs_cmd & SCS_CMD_BA5_EN); 4292 delay(50 * 1000); 4293 4294 if (scs_cmd & SCS_CMD_BA5_EN) { 4295 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 4296 PCI_MAPREG_TYPE_MEM | 4297 PCI_MAPREG_MEM_TYPE_32BIT, 0, 4298 &sl->ba5_st, &sl->ba5_sh, 4299 NULL, NULL, 0) != 0) 4300 printf(": unable to map BA5 register space\n"); 4301 else 4302 sl->ba5_en = 1; 4303 } else { 4304 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 4305 SII3112_PCI_CFGCTL); 4306 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 4307 cfgctl | CFGCTL_BA5INDEN); 4308 } 4309 4310 printf(": DMA"); 4311 pciide_mapreg_dma(sc, pa); 4312 printf("\n"); 4313 4314 /* 4315 * Rev. <= 0x01 of the 3112 have a bug that can cause data 4316 * corruption if DMA transfers cross an 8K boundary. This is 4317 * apparently hard to tickle, but we'll go ahead and play it 4318 * safe. 4319 */ 4320 if (sc->sc_rev <= 0x01) { 4321 sc->sc_dma_maxsegsz = 8192; 4322 sc->sc_dma_boundary = 8192; 4323 } 4324 4325 sii_fixup_cacheline(sc, pa); 4326 4327 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 4328 sc->sc_wdcdev.PIO_cap = 4; 4329 if (sc->sc_dma_ok) { 4330 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4331 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4332 sc->sc_wdcdev.irqack = pciide_irqack; 4333 sc->sc_wdcdev.DMA_cap = 2; 4334 sc->sc_wdcdev.UDMA_cap = 6; 4335 } 4336 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 4337 4338 /* We can use SControl and SStatus to probe for drives. */ 4339 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 4340 4341 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4342 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4343 4344 /* 4345 * The 3112 either identifies itself as a RAID storage device 4346 * or a Misc storage device. Fake up the interface bits for 4347 * what our driver expects. 4348 */ 4349 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4350 interface = PCI_INTERFACE(pa->pa_class); 4351 } else { 4352 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4353 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4354 } 4355 4356 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4357 cp = &sc->pciide_channels[channel]; 4358 if (pciide_chansetup(sc, channel, interface) == 0) 4359 continue; 4360 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4361 pciide_pci_intr); 4362 if (cp->hw_ok == 0) 4363 continue; 4364 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 4365 } 4366 } 4367 4368 void 4369 sii3112_setup_channel(struct channel_softc *chp) 4370 { 4371 struct ata_drive_datas *drvp; 4372 int drive; 4373 u_int32_t idedma_ctl, dtm; 4374 struct pciide_channel *cp = (struct pciide_channel *)chp; 4375 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4376 4377 /* setup DMA if needed */ 4378 pciide_channel_dma_setup(cp); 4379 4380 idedma_ctl = 0; 4381 dtm = 0; 4382 4383 for (drive = 0; drive < 2; drive++) { 4384 drvp = &chp->ch_drive[drive]; 4385 /* If no drive, skip */ 4386 if ((drvp->drive_flags & DRIVE) == 0) 4387 continue; 4388 if (drvp->drive_flags & DRIVE_UDMA) { 4389 /* use Ultra/DMA */ 4390 drvp->drive_flags &= ~DRIVE_DMA; 4391 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4392 dtm |= DTM_IDEx_DMA; 4393 } else if (drvp->drive_flags & DRIVE_DMA) { 4394 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4395 dtm |= DTM_IDEx_DMA; 4396 } else { 4397 dtm |= DTM_IDEx_PIO; 4398 } 4399 } 4400 4401 /* 4402 * Nothing to do to setup modes; it is meaningless in S-ATA 4403 * (but many S-ATA drives still want to get the SET_FEATURE 4404 * command). 4405 */ 4406 if (idedma_ctl != 0) { 4407 /* Add software bits in status register */ 4408 PCIIDE_DMACTL_WRITE(sc, chp->channel, idedma_ctl); 4409 } 4410 BA5_WRITE_4(sc, chp->channel, ba5_IDE_DTM, dtm); 4411 pciide_print_modes(cp); 4412 } 4413 4414 void 4415 sii3112_drv_probe(struct channel_softc *chp) 4416 { 4417 struct pciide_channel *cp = (struct pciide_channel *)chp; 4418 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4419 uint32_t scontrol, sstatus; 4420 uint8_t scnt, sn, cl, ch; 4421 int s; 4422 4423 /* 4424 * The 3112 is a 2-port part, and only has one drive per channel 4425 * (each port emulates a master drive). 4426 * 4427 * The 3114 is similar, but has 4 channels. 4428 */ 4429 4430 /* 4431 * Request communication initialization sequence, any speed. 4432 * Performing this is the equivalent of an ATA Reset. 4433 */ 4434 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 4435 4436 /* 4437 * XXX We don't yet support SATA power management; disable all 4438 * power management state transitions. 4439 */ 4440 scontrol |= SControl_IPM_NONE; 4441 4442 BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); 4443 delay(50 * 1000); 4444 scontrol &= ~SControl_DET_INIT; 4445 BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); 4446 delay(50 * 1000); 4447 4448 sstatus = BA5_READ_4(sc, chp->channel, ba5_SStatus); 4449 #if 0 4450 printf("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 4451 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus, 4452 BA5_READ_4(sc, chp->channel, ba5_SControl)); 4453 #endif 4454 switch (sstatus & SStatus_DET_mask) { 4455 case SStatus_DET_NODEV: 4456 /* No device; be silent. */ 4457 break; 4458 4459 case SStatus_DET_DEV_NE: 4460 printf("%s: port %d: device connected, but " 4461 "communication not established\n", 4462 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 4463 break; 4464 4465 case SStatus_DET_OFFLINE: 4466 printf("%s: port %d: PHY offline\n", 4467 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 4468 break; 4469 4470 case SStatus_DET_DEV: 4471 /* 4472 * XXX ATAPI detection doesn't currently work. Don't 4473 * XXX know why. But, it's not like the standard method 4474 * XXX can detect an ATAPI device connected via a SATA/PATA 4475 * XXX bridge, so at least this is no worse. --thorpej 4476 */ 4477 if (chp->_vtbl != NULL) 4478 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (0 << 4)); 4479 else 4480 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 4481 wdr_sdh & _WDC_REGMASK, WDSD_IBM | (0 << 4)); 4482 delay(10); /* 400ns delay */ 4483 /* Save register contents. */ 4484 if (chp->_vtbl != NULL) { 4485 scnt = CHP_READ_REG(chp, wdr_seccnt); 4486 sn = CHP_READ_REG(chp, wdr_sector); 4487 cl = CHP_READ_REG(chp, wdr_cyl_lo); 4488 ch = CHP_READ_REG(chp, wdr_cyl_hi); 4489 } else { 4490 scnt = bus_space_read_1(chp->cmd_iot, 4491 chp->cmd_ioh, wdr_seccnt & _WDC_REGMASK); 4492 sn = bus_space_read_1(chp->cmd_iot, 4493 chp->cmd_ioh, wdr_sector & _WDC_REGMASK); 4494 cl = bus_space_read_1(chp->cmd_iot, 4495 chp->cmd_ioh, wdr_cyl_lo & _WDC_REGMASK); 4496 ch = bus_space_read_1(chp->cmd_iot, 4497 chp->cmd_ioh, wdr_cyl_hi & _WDC_REGMASK); 4498 } 4499 #if 0 4500 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 4501 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 4502 scnt, sn, cl, ch); 4503 #endif 4504 /* 4505 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 4506 * cases we get wrong values here, so ignore it. 4507 */ 4508 s = splbio(); 4509 if (cl == 0x14 && ch == 0xeb) 4510 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 4511 else 4512 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 4513 splx(s); 4514 4515 printf("%s: port %d", 4516 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 4517 switch ((sstatus & SStatus_SPD_mask) >> SStatus_SPD_shift) { 4518 case 1: 4519 printf(": 1.5Gb/s"); 4520 break; 4521 case 2: 4522 printf(": 3.0Gb/s"); 4523 break; 4524 } 4525 printf("\n"); 4526 break; 4527 4528 default: 4529 printf("%s: port %d: unknown SStatus: 0x%08x\n", 4530 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 4531 } 4532 } 4533 4534 void 4535 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 4536 { 4537 struct pciide_channel *cp; 4538 pcireg_t scs_cmd; 4539 pci_intr_handle_t intrhandle; 4540 const char *intrstr; 4541 int channel; 4542 struct pciide_satalink *sl; 4543 4544 /* Allocate memory for private data */ 4545 sc->sc_cookielen = sizeof(*sl); 4546 sc->sc_cookie = malloc(sc->sc_cookielen, M_DEVBUF, M_NOWAIT | M_ZERO); 4547 sl = sc->sc_cookie; 4548 4549 #define SII3114_RESET_BITS \ 4550 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 4551 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 4552 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 4553 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 4554 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 4555 4556 /* 4557 * Reset everything and then unblock all of the interrupts. 4558 */ 4559 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 4560 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 4561 scs_cmd | SII3114_RESET_BITS); 4562 delay(50 * 1000); 4563 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 4564 scs_cmd & SCS_CMD_M66EN); 4565 delay(50 * 1000); 4566 4567 /* 4568 * On the 3114, the BA5 register space is always enabled. In 4569 * order to use the 3114 in any sane way, we must use this BA5 4570 * register space, and so we consider it an error if we cannot 4571 * map it. 4572 * 4573 * As a consequence of using BA5, our register mapping is different 4574 * from a normal PCI IDE controller's, and so we are unable to use 4575 * most of the common PCI IDE register mapping functions. 4576 */ 4577 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 4578 PCI_MAPREG_TYPE_MEM | 4579 PCI_MAPREG_MEM_TYPE_32BIT, 0, 4580 &sl->ba5_st, &sl->ba5_sh, 4581 NULL, NULL, 0) != 0) { 4582 printf(": unable to map BA5 register space\n"); 4583 return; 4584 } 4585 sl->ba5_en = 1; 4586 4587 /* 4588 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 4589 * channel 2. This is required at all times for proper operation 4590 * when using the BA5 register space (otherwise interrupts from 4591 * all 4 channels won't work). 4592 */ 4593 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 4594 4595 printf(": DMA"); 4596 sii3114_mapreg_dma(sc, pa); 4597 printf("\n"); 4598 4599 sii_fixup_cacheline(sc, pa); 4600 4601 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 4602 sc->sc_wdcdev.PIO_cap = 4; 4603 if (sc->sc_dma_ok) { 4604 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4605 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4606 sc->sc_wdcdev.irqack = pciide_irqack; 4607 sc->sc_wdcdev.DMA_cap = 2; 4608 sc->sc_wdcdev.UDMA_cap = 6; 4609 } 4610 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 4611 4612 /* We can use SControl and SStatus to probe for drives. */ 4613 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 4614 4615 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4616 sc->sc_wdcdev.nchannels = 4; 4617 4618 /* Map and establish the interrupt handler. */ 4619 if (pci_intr_map(pa, &intrhandle) != 0) { 4620 printf("%s: couldn't map native-PCI interrupt\n", 4621 sc->sc_wdcdev.sc_dev.dv_xname); 4622 return; 4623 } 4624 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 4625 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 4626 /* XXX */ 4627 pciide_pci_intr, sc, 4628 sc->sc_wdcdev.sc_dev.dv_xname); 4629 if (sc->sc_pci_ih != NULL) { 4630 printf("%s: using %s for native-PCI interrupt\n", 4631 sc->sc_wdcdev.sc_dev.dv_xname, 4632 intrstr ? intrstr : "unknown interrupt"); 4633 } else { 4634 printf("%s: couldn't establish native-PCI interrupt", 4635 sc->sc_wdcdev.sc_dev.dv_xname); 4636 if (intrstr != NULL) 4637 printf(" at %s", intrstr); 4638 printf("\n"); 4639 return; 4640 } 4641 4642 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4643 cp = &sc->pciide_channels[channel]; 4644 if (sii3114_chansetup(sc, channel) == 0) 4645 continue; 4646 sii3114_mapchan(cp); 4647 if (cp->hw_ok == 0) 4648 continue; 4649 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 4650 } 4651 } 4652 4653 void 4654 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 4655 { 4656 int chan, reg; 4657 bus_size_t size; 4658 struct pciide_satalink *sl = sc->sc_cookie; 4659 4660 sc->sc_wdcdev.dma_arg = sc; 4661 sc->sc_wdcdev.dma_init = pciide_dma_init; 4662 sc->sc_wdcdev.dma_start = pciide_dma_start; 4663 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 4664 4665 /* 4666 * Slice off a subregion of BA5 for each of the channel's DMA 4667 * registers. 4668 */ 4669 4670 sc->sc_dma_iot = sl->ba5_st; 4671 for (chan = 0; chan < 4; chan++) { 4672 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 4673 size = 4; 4674 if (size > (IDEDMA_SCH_OFFSET - reg)) 4675 size = IDEDMA_SCH_OFFSET - reg; 4676 if (bus_space_subregion(sl->ba5_st, 4677 sl->ba5_sh, 4678 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 4679 size, &sl->regs[chan].dma_iohs[reg]) != 0) { 4680 sc->sc_dma_ok = 0; 4681 printf(": can't subregion offset " 4682 "%lu size %lu", 4683 (u_long) satalink_ba5_regmap[ 4684 chan].ba5_IDEDMA_CMD + reg, 4685 (u_long) size); 4686 return; 4687 } 4688 } 4689 } 4690 4691 sc->sc_dmacmd_read = sii3114_dmacmd_read; 4692 sc->sc_dmacmd_write = sii3114_dmacmd_write; 4693 sc->sc_dmactl_read = sii3114_dmactl_read; 4694 sc->sc_dmactl_write = sii3114_dmactl_write; 4695 sc->sc_dmatbl_write = sii3114_dmatbl_write; 4696 4697 /* DMA registers all set up! */ 4698 sc->sc_dmat = pa->pa_dmat; 4699 sc->sc_dma_ok = 1; 4700 } 4701 4702 int 4703 sii3114_chansetup(struct pciide_softc *sc, int channel) 4704 { 4705 static const char *channel_names[] = { 4706 "port 0", 4707 "port 1", 4708 "port 2", 4709 "port 3", 4710 }; 4711 struct pciide_channel *cp = &sc->pciide_channels[channel]; 4712 4713 sc->wdc_chanarray[channel] = &cp->wdc_channel; 4714 4715 /* 4716 * We must always keep the Interrupt Steering bit set in channel 2's 4717 * IDEDMA_CMD register. 4718 */ 4719 if (channel == 2) 4720 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 4721 4722 cp->name = channel_names[channel]; 4723 cp->wdc_channel.channel = channel; 4724 cp->wdc_channel.wdc = &sc->sc_wdcdev; 4725 cp->wdc_channel.ch_queue = wdc_alloc_queue(); 4726 if (cp->wdc_channel.ch_queue == NULL) { 4727 printf("%s %s channel: " 4728 "cannot allocate channel queue", 4729 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4730 return (0); 4731 } 4732 return (1); 4733 } 4734 4735 void 4736 sii3114_mapchan(struct pciide_channel *cp) 4737 { 4738 struct channel_softc *wdc_cp = &cp->wdc_channel; 4739 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4740 struct pciide_satalink *sl = sc->sc_cookie; 4741 int chan = wdc_cp->channel; 4742 int i; 4743 4744 cp->hw_ok = 0; 4745 cp->compat = 0; 4746 cp->ih = sc->sc_pci_ih; 4747 4748 sl->regs[chan].cmd_iot = sl->ba5_st; 4749 if (bus_space_subregion(sl->ba5_st, sl->ba5_sh, 4750 satalink_ba5_regmap[chan].ba5_IDE_TF0, 4751 9, &sl->regs[chan].cmd_baseioh) != 0) { 4752 printf("%s: couldn't subregion %s cmd base\n", 4753 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4754 return; 4755 } 4756 4757 sl->regs[chan].ctl_iot = sl->ba5_st; 4758 if (bus_space_subregion(sl->ba5_st, sl->ba5_sh, 4759 satalink_ba5_regmap[chan].ba5_IDE_TF8, 4760 1, &cp->ctl_baseioh) != 0) { 4761 printf("%s: couldn't subregion %s ctl base\n", 4762 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4763 return; 4764 } 4765 sl->regs[chan].ctl_ioh = cp->ctl_baseioh; 4766 4767 for (i = 0; i < WDC_NREG; i++) { 4768 if (bus_space_subregion(sl->regs[chan].cmd_iot, 4769 sl->regs[chan].cmd_baseioh, 4770 i, i == 0 ? 4 : 1, 4771 &sl->regs[chan].cmd_iohs[i]) != 0) { 4772 printf("%s: couldn't subregion %s channel " 4773 "cmd regs\n", 4774 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4775 return; 4776 } 4777 } 4778 sl->regs[chan].cmd_iohs[wdr_status & _WDC_REGMASK] = 4779 sl->regs[chan].cmd_iohs[wdr_command & _WDC_REGMASK]; 4780 sl->regs[chan].cmd_iohs[wdr_features & _WDC_REGMASK] = 4781 sl->regs[chan].cmd_iohs[wdr_error & _WDC_REGMASK]; 4782 wdc_cp->data32iot = wdc_cp->cmd_iot = sl->regs[chan].cmd_iot; 4783 wdc_cp->data32ioh = wdc_cp->cmd_ioh = sl->regs[chan].cmd_iohs[0]; 4784 wdc_cp->_vtbl = &wdc_sii3114_vtbl; 4785 wdcattach(wdc_cp); 4786 cp->hw_ok = 1; 4787 } 4788 4789 u_int8_t 4790 sii3114_read_reg(struct channel_softc *chp, enum wdc_regs reg) 4791 { 4792 struct pciide_channel *cp = (struct pciide_channel *)chp; 4793 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4794 struct pciide_satalink *sl = sc->sc_cookie; 4795 4796 if (reg & _WDC_AUX) 4797 return (bus_space_read_1(sl->regs[chp->channel].ctl_iot, 4798 sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK)); 4799 else 4800 return (bus_space_read_1(sl->regs[chp->channel].cmd_iot, 4801 sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0)); 4802 } 4803 4804 void 4805 sii3114_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val) 4806 { 4807 struct pciide_channel *cp = (struct pciide_channel *)chp; 4808 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4809 struct pciide_satalink *sl = sc->sc_cookie; 4810 4811 if (reg & _WDC_AUX) 4812 bus_space_write_1(sl->regs[chp->channel].ctl_iot, 4813 sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val); 4814 else 4815 bus_space_write_1(sl->regs[chp->channel].cmd_iot, 4816 sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 4817 0, val); 4818 } 4819 4820 u_int8_t 4821 sii3114_dmacmd_read(struct pciide_softc *sc, int chan) 4822 { 4823 struct pciide_satalink *sl = sc->sc_cookie; 4824 4825 return (bus_space_read_1(sc->sc_dma_iot, 4826 sl->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0)); 4827 } 4828 4829 void 4830 sii3114_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val) 4831 { 4832 struct pciide_satalink *sl = sc->sc_cookie; 4833 4834 bus_space_write_1(sc->sc_dma_iot, 4835 sl->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0, val); 4836 } 4837 4838 u_int8_t 4839 sii3114_dmactl_read(struct pciide_softc *sc, int chan) 4840 { 4841 struct pciide_satalink *sl = sc->sc_cookie; 4842 4843 return (bus_space_read_1(sc->sc_dma_iot, 4844 sl->regs[chan].dma_iohs[IDEDMA_CTL(0)], 0)); 4845 } 4846 4847 void 4848 sii3114_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val) 4849 { 4850 struct pciide_satalink *sl = sc->sc_cookie; 4851 4852 bus_space_write_1(sc->sc_dma_iot, 4853 sl->regs[chan].dma_iohs[IDEDMA_CTL(0)], 0, val); 4854 } 4855 4856 void 4857 sii3114_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val) 4858 { 4859 struct pciide_satalink *sl = sc->sc_cookie; 4860 4861 bus_space_write_4(sc->sc_dma_iot, 4862 sl->regs[chan].dma_iohs[IDEDMA_TBL(0)], 0, val); 4863 } 4864 4865 void 4866 cy693_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 4867 { 4868 struct pciide_channel *cp; 4869 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4870 bus_size_t cmdsize, ctlsize; 4871 struct pciide_cy *cy; 4872 4873 /* Allocate memory for private data */ 4874 sc->sc_cookielen = sizeof(*cy); 4875 sc->sc_cookie = malloc(sc->sc_cookielen, M_DEVBUF, M_NOWAIT | M_ZERO); 4876 cy = sc->sc_cookie; 4877 4878 /* 4879 * this chip has 2 PCI IDE functions, one for primary and one for 4880 * secondary. So we need to call pciide_mapregs_compat() with 4881 * the real channel 4882 */ 4883 if (pa->pa_function == 1) { 4884 cy->cy_compatchan = 0; 4885 } else if (pa->pa_function == 2) { 4886 cy->cy_compatchan = 1; 4887 } else { 4888 printf(": unexpected PCI function %d\n", pa->pa_function); 4889 return; 4890 } 4891 4892 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 4893 printf(": DMA"); 4894 pciide_mapreg_dma(sc, pa); 4895 } else { 4896 printf(": no DMA"); 4897 sc->sc_dma_ok = 0; 4898 } 4899 4900 cy->cy_handle = cy82c693_init(pa->pa_iot); 4901 if (cy->cy_handle == NULL) { 4902 printf(", (unable to map ctl registers)"); 4903 sc->sc_dma_ok = 0; 4904 } 4905 4906 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4907 WDC_CAPABILITY_MODE; 4908 if (sc->sc_dma_ok) { 4909 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4910 sc->sc_wdcdev.irqack = pciide_irqack; 4911 } 4912 sc->sc_wdcdev.PIO_cap = 4; 4913 sc->sc_wdcdev.DMA_cap = 2; 4914 sc->sc_wdcdev.set_modes = cy693_setup_channel; 4915 4916 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4917 sc->sc_wdcdev.nchannels = 1; 4918 4919 /* Only one channel for this chip; if we are here it's enabled */ 4920 cp = &sc->pciide_channels[0]; 4921 sc->wdc_chanarray[0] = &cp->wdc_channel; 4922 cp->name = PCIIDE_CHANNEL_NAME(0); 4923 cp->wdc_channel.channel = 0; 4924 cp->wdc_channel.wdc = &sc->sc_wdcdev; 4925 cp->wdc_channel.ch_queue = wdc_alloc_queue(); 4926 if (cp->wdc_channel.ch_queue == NULL) { 4927 printf(": cannot allocate channel queue\n"); 4928 return; 4929 } 4930 printf(", %s %s to ", PCIIDE_CHANNEL_NAME(0), 4931 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 4932 "configured" : "wired"); 4933 if (interface & PCIIDE_INTERFACE_PCI(0)) { 4934 printf("native-PCI\n"); 4935 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 4936 pciide_pci_intr); 4937 } else { 4938 printf("compatibility\n"); 4939 cp->hw_ok = pciide_mapregs_compat(pa, cp, cy->cy_compatchan, 4940 &cmdsize, &ctlsize); 4941 } 4942 4943 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4944 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4945 pciide_map_compat_intr(pa, cp, cy->cy_compatchan, interface); 4946 if (cp->hw_ok == 0) 4947 return; 4948 wdcattach(&cp->wdc_channel); 4949 if (pciide_chan_candisable(cp)) { 4950 pci_conf_write(sc->sc_pc, sc->sc_tag, 4951 PCI_COMMAND_STATUS_REG, 0); 4952 } 4953 if (cp->hw_ok == 0) { 4954 pciide_unmap_compat_intr(pa, cp, cy->cy_compatchan, 4955 interface); 4956 return; 4957 } 4958 4959 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 4960 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 4961 cy693_setup_channel(&cp->wdc_channel); 4962 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 4963 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 4964 } 4965 4966 void 4967 cy693_setup_channel(struct channel_softc *chp) 4968 { 4969 struct ata_drive_datas *drvp; 4970 int drive; 4971 u_int32_t cy_cmd_ctrl; 4972 u_int32_t idedma_ctl; 4973 struct pciide_channel *cp = (struct pciide_channel *)chp; 4974 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4975 int dma_mode = -1; 4976 struct pciide_cy *cy = sc->sc_cookie; 4977 4978 cy_cmd_ctrl = idedma_ctl = 0; 4979 4980 /* setup DMA if needed */ 4981 pciide_channel_dma_setup(cp); 4982 4983 for (drive = 0; drive < 2; drive++) { 4984 drvp = &chp->ch_drive[drive]; 4985 /* If no drive, skip */ 4986 if ((drvp->drive_flags & DRIVE) == 0) 4987 continue; 4988 /* add timing values, setup DMA if needed */ 4989 if (drvp->drive_flags & DRIVE_DMA) { 4990 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4991 /* use Multiword DMA */ 4992 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 4993 dma_mode = drvp->DMA_mode; 4994 } 4995 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 4996 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 4997 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 4998 CY_CMD_CTRL_IOW_REC_OFF(drive)); 4999 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 5000 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 5001 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 5002 CY_CMD_CTRL_IOR_REC_OFF(drive)); 5003 } 5004 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 5005 chp->ch_drive[0].DMA_mode = dma_mode; 5006 chp->ch_drive[1].DMA_mode = dma_mode; 5007 5008 if (dma_mode == -1) 5009 dma_mode = 0; 5010 5011 if (cy->cy_handle != NULL) { 5012 /* Note: `multiple' is implied. */ 5013 cy82c693_write(cy->cy_handle, 5014 (cy->cy_compatchan == 0) ? 5015 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 5016 } 5017 5018 pciide_print_modes(cp); 5019 5020 if (idedma_ctl != 0) { 5021 /* Add software bits in status register */ 5022 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5023 IDEDMA_CTL(chp->channel), idedma_ctl); 5024 } 5025 } 5026 5027 static struct sis_hostbr_type { 5028 u_int16_t id; 5029 u_int8_t rev; 5030 u_int8_t udma_mode; 5031 char *name; 5032 u_int8_t type; 5033 #define SIS_TYPE_NOUDMA 0 5034 #define SIS_TYPE_66 1 5035 #define SIS_TYPE_100OLD 2 5036 #define SIS_TYPE_100NEW 3 5037 #define SIS_TYPE_133OLD 4 5038 #define SIS_TYPE_133NEW 5 5039 #define SIS_TYPE_SOUTH 6 5040 } sis_hostbr_type[] = { 5041 /* Most infos here are from sos@freebsd.org */ 5042 {PCI_PRODUCT_SIS_530, 0x00, 4, "530", SIS_TYPE_66}, 5043 #if 0 5044 /* 5045 * controllers associated to a rev 0x2 530 Host to PCI Bridge 5046 * have problems with UDMA (info provided by Christos) 5047 */ 5048 {PCI_PRODUCT_SIS_530, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 5049 #endif 5050 {PCI_PRODUCT_SIS_540, 0x00, 4, "540", SIS_TYPE_66}, 5051 {PCI_PRODUCT_SIS_550, 0x00, 4, "550", SIS_TYPE_66}, 5052 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 5053 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 5054 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 5055 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 5056 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 5057 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 5058 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 5059 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 5060 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 5061 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 5062 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 5063 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 5064 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 5065 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 5066 {PCI_PRODUCT_SIS_661, 0x00, 6, "661", SIS_TYPE_SOUTH}, 5067 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 5068 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 5069 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 5070 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 5071 {PCI_PRODUCT_SIS_741, 0x00, 6, "741", SIS_TYPE_SOUTH}, 5072 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 5073 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 5074 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 5075 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 5076 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 5077 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 5078 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 5079 {PCI_PRODUCT_SIS_760, 0x00, 6, "760", SIS_TYPE_SOUTH}, 5080 /* 5081 * From sos@freebsd.org: the 0x961 ID will never be found in real world 5082 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 5083 */ 5084 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 5085 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 5086 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 5087 {PCI_PRODUCT_SIS_965, 0x00, 6, "965", SIS_TYPE_133NEW}, 5088 {PCI_PRODUCT_SIS_966, 0x00, 6, "966", SIS_TYPE_133NEW}, 5089 {PCI_PRODUCT_SIS_968, 0x00, 6, "968", SIS_TYPE_133NEW} 5090 }; 5091 5092 static struct sis_hostbr_type *sis_hostbr_type_match; 5093 5094 int 5095 sis_hostbr_match(struct pci_attach_args *pa) 5096 { 5097 int i; 5098 5099 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 5100 return (0); 5101 sis_hostbr_type_match = NULL; 5102 for (i = 0; 5103 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 5104 i++) { 5105 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 5106 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 5107 sis_hostbr_type_match = &sis_hostbr_type[i]; 5108 } 5109 return (sis_hostbr_type_match != NULL); 5110 } 5111 5112 int 5113 sis_south_match(struct pci_attach_args *pa) 5114 { 5115 return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 5116 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 5117 PCI_REVISION(pa->pa_class) >= 0x10); 5118 } 5119 5120 void 5121 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 5122 { 5123 struct pciide_channel *cp; 5124 int channel; 5125 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 5126 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 5127 int rev = sc->sc_rev; 5128 bus_size_t cmdsize, ctlsize; 5129 struct pciide_sis *sis; 5130 5131 /* Allocate memory for private data */ 5132 sc->sc_cookielen = sizeof(*sis); 5133 sc->sc_cookie = malloc(sc->sc_cookielen, M_DEVBUF, M_NOWAIT | M_ZERO); 5134 sis = sc->sc_cookie; 5135 5136 pci_find_device(NULL, sis_hostbr_match); 5137 5138 if (sis_hostbr_type_match) { 5139 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 5140 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 5141 pciide_pci_read(sc->sc_pc, sc->sc_tag, 5142 SIS_REG_57) & 0x7f); 5143 if (sc->sc_pp->ide_product == SIS_PRODUCT_5518) { 5144 sis->sis_type = SIS_TYPE_133NEW; 5145 sc->sc_wdcdev.UDMA_cap = 5146 sis_hostbr_type_match->udma_mode; 5147 } else { 5148 if (pci_find_device(NULL, sis_south_match)) { 5149 sis->sis_type = SIS_TYPE_133OLD; 5150 sc->sc_wdcdev.UDMA_cap = 5151 sis_hostbr_type_match->udma_mode; 5152 } else { 5153 sis->sis_type = SIS_TYPE_100NEW; 5154 sc->sc_wdcdev.UDMA_cap = 5155 sis_hostbr_type_match->udma_mode; 5156 } 5157 } 5158 } else { 5159 sis->sis_type = sis_hostbr_type_match->type; 5160 sc->sc_wdcdev.UDMA_cap = 5161 sis_hostbr_type_match->udma_mode; 5162 } 5163 printf(": %s", sis_hostbr_type_match->name); 5164 } else { 5165 printf(": 5597/5598"); 5166 if (rev >= 0xd0) { 5167 sc->sc_wdcdev.UDMA_cap = 2; 5168 sis->sis_type = SIS_TYPE_66; 5169 } else { 5170 sc->sc_wdcdev.UDMA_cap = 0; 5171 sis->sis_type = SIS_TYPE_NOUDMA; 5172 } 5173 } 5174 5175 printf(": DMA"); 5176 pciide_mapreg_dma(sc, pa); 5177 5178 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5179 WDC_CAPABILITY_MODE; 5180 if (sc->sc_dma_ok) { 5181 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 5182 sc->sc_wdcdev.irqack = pciide_irqack; 5183 if (sis->sis_type >= SIS_TYPE_66) 5184 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 5185 } 5186 5187 sc->sc_wdcdev.PIO_cap = 4; 5188 sc->sc_wdcdev.DMA_cap = 2; 5189 5190 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5191 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5192 switch (sis->sis_type) { 5193 case SIS_TYPE_NOUDMA: 5194 case SIS_TYPE_66: 5195 case SIS_TYPE_100OLD: 5196 sc->sc_wdcdev.set_modes = sis_setup_channel; 5197 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 5198 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 5199 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 5200 break; 5201 case SIS_TYPE_100NEW: 5202 case SIS_TYPE_133OLD: 5203 sc->sc_wdcdev.set_modes = sis_setup_channel; 5204 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 5205 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 5206 break; 5207 case SIS_TYPE_133NEW: 5208 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 5209 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 5210 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 5211 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 5212 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 5213 break; 5214 } 5215 5216 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 5217 5218 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5219 cp = &sc->pciide_channels[channel]; 5220 if (pciide_chansetup(sc, channel, interface) == 0) 5221 continue; 5222 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 5223 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 5224 printf("%s: %s ignored (disabled)\n", 5225 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 5226 cp->hw_ok = 0; 5227 continue; 5228 } 5229 pciide_map_compat_intr(pa, cp, channel, interface); 5230 if (cp->hw_ok == 0) 5231 continue; 5232 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5233 pciide_pci_intr); 5234 if (cp->hw_ok == 0) { 5235 pciide_unmap_compat_intr(pa, cp, channel, interface); 5236 continue; 5237 } 5238 if (pciide_chan_candisable(cp)) { 5239 if (channel == 0) 5240 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 5241 else 5242 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 5243 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 5244 sis_ctr0); 5245 } 5246 if (cp->hw_ok == 0) { 5247 pciide_unmap_compat_intr(pa, cp, channel, interface); 5248 continue; 5249 } 5250 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 5251 } 5252 } 5253 5254 void 5255 sis96x_setup_channel(struct channel_softc *chp) 5256 { 5257 struct ata_drive_datas *drvp; 5258 int drive; 5259 u_int32_t sis_tim; 5260 u_int32_t idedma_ctl; 5261 int regtim; 5262 struct pciide_channel *cp = (struct pciide_channel *)chp; 5263 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5264 5265 sis_tim = 0; 5266 idedma_ctl = 0; 5267 /* setup DMA if needed */ 5268 pciide_channel_dma_setup(cp); 5269 5270 for (drive = 0; drive < 2; drive++) { 5271 regtim = SIS_TIM133( 5272 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 5273 chp->channel, drive); 5274 drvp = &chp->ch_drive[drive]; 5275 /* If no drive, skip */ 5276 if ((drvp->drive_flags & DRIVE) == 0) 5277 continue; 5278 /* add timing values, setup DMA if needed */ 5279 if (drvp->drive_flags & DRIVE_UDMA) { 5280 /* use Ultra/DMA */ 5281 drvp->drive_flags &= ~DRIVE_DMA; 5282 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 5283 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 5284 if (drvp->UDMA_mode > 2) 5285 drvp->UDMA_mode = 2; 5286 } 5287 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 5288 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 5289 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5290 } else if (drvp->drive_flags & DRIVE_DMA) { 5291 /* 5292 * use Multiword DMA 5293 * Timings will be used for both PIO and DMA, 5294 * so adjust DMA mode if needed 5295 */ 5296 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 5297 drvp->PIO_mode = drvp->DMA_mode + 2; 5298 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 5299 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 5300 drvp->PIO_mode - 2 : 0; 5301 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 5302 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5303 } else { 5304 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 5305 } 5306 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 5307 "channel %d drive %d: 0x%x (reg 0x%x)\n", 5308 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 5309 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 5310 } 5311 if (idedma_ctl != 0) { 5312 /* Add software bits in status register */ 5313 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5314 IDEDMA_CTL(chp->channel), idedma_ctl); 5315 } 5316 pciide_print_modes(cp); 5317 } 5318 5319 void 5320 sis_setup_channel(struct channel_softc *chp) 5321 { 5322 struct ata_drive_datas *drvp; 5323 int drive; 5324 u_int32_t sis_tim; 5325 u_int32_t idedma_ctl; 5326 struct pciide_channel *cp = (struct pciide_channel *)chp; 5327 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5328 struct pciide_sis *sis = sc->sc_cookie; 5329 5330 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 5331 "channel %d 0x%x\n", chp->channel, 5332 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 5333 DEBUG_PROBE); 5334 sis_tim = 0; 5335 idedma_ctl = 0; 5336 /* setup DMA if needed */ 5337 pciide_channel_dma_setup(cp); 5338 5339 for (drive = 0; drive < 2; drive++) { 5340 drvp = &chp->ch_drive[drive]; 5341 /* If no drive, skip */ 5342 if ((drvp->drive_flags & DRIVE) == 0) 5343 continue; 5344 /* add timing values, setup DMA if needed */ 5345 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 5346 (drvp->drive_flags & DRIVE_UDMA) == 0) 5347 goto pio; 5348 5349 if (drvp->drive_flags & DRIVE_UDMA) { 5350 /* use Ultra/DMA */ 5351 drvp->drive_flags &= ~DRIVE_DMA; 5352 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 5353 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 5354 if (drvp->UDMA_mode > 2) 5355 drvp->UDMA_mode = 2; 5356 } 5357 switch (sis->sis_type) { 5358 case SIS_TYPE_66: 5359 case SIS_TYPE_100OLD: 5360 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 5361 SIS_TIM66_UDMA_TIME_OFF(drive); 5362 break; 5363 case SIS_TYPE_100NEW: 5364 sis_tim |= 5365 sis_udma100new_tim[drvp->UDMA_mode] << 5366 SIS_TIM100_UDMA_TIME_OFF(drive); 5367 break; 5368 case SIS_TYPE_133OLD: 5369 sis_tim |= 5370 sis_udma133old_tim[drvp->UDMA_mode] << 5371 SIS_TIM100_UDMA_TIME_OFF(drive); 5372 break; 5373 default: 5374 printf("unknown SiS IDE type %d\n", 5375 sis->sis_type); 5376 } 5377 } else { 5378 /* 5379 * use Multiword DMA 5380 * Timings will be used for both PIO and DMA, 5381 * so adjust DMA mode if needed 5382 */ 5383 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 5384 drvp->PIO_mode = drvp->DMA_mode + 2; 5385 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 5386 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 5387 drvp->PIO_mode - 2 : 0; 5388 if (drvp->DMA_mode == 0) 5389 drvp->PIO_mode = 0; 5390 } 5391 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5392 pio: switch (sis->sis_type) { 5393 case SIS_TYPE_NOUDMA: 5394 case SIS_TYPE_66: 5395 case SIS_TYPE_100OLD: 5396 sis_tim |= sis_pio_act[drvp->PIO_mode] << 5397 SIS_TIM66_ACT_OFF(drive); 5398 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 5399 SIS_TIM66_REC_OFF(drive); 5400 break; 5401 case SIS_TYPE_100NEW: 5402 case SIS_TYPE_133OLD: 5403 sis_tim |= sis_pio_act[drvp->PIO_mode] << 5404 SIS_TIM100_ACT_OFF(drive); 5405 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 5406 SIS_TIM100_REC_OFF(drive); 5407 break; 5408 default: 5409 printf("unknown SiS IDE type %d\n", 5410 sis->sis_type); 5411 } 5412 } 5413 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 5414 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 5415 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 5416 if (idedma_ctl != 0) { 5417 /* Add software bits in status register */ 5418 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5419 IDEDMA_CTL(chp->channel), idedma_ctl); 5420 } 5421 pciide_print_modes(cp); 5422 } 5423 5424 void 5425 natsemi_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 5426 { 5427 struct pciide_channel *cp; 5428 int channel; 5429 pcireg_t interface, ctl; 5430 bus_size_t cmdsize, ctlsize; 5431 5432 printf(": DMA"); 5433 pciide_mapreg_dma(sc, pa); 5434 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 5435 5436 if (sc->sc_dma_ok) { 5437 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 5438 sc->sc_wdcdev.irqack = natsemi_irqack; 5439 } 5440 5441 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CCBT, 0xb7); 5442 5443 /* 5444 * Mask off interrupts from both channels, appropriate channel(s) 5445 * will be unmasked later. 5446 */ 5447 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 5448 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) | 5449 NATSEMI_CHMASK(0) | NATSEMI_CHMASK(1)); 5450 5451 sc->sc_wdcdev.PIO_cap = 4; 5452 sc->sc_wdcdev.DMA_cap = 2; 5453 sc->sc_wdcdev.set_modes = natsemi_setup_channel; 5454 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5455 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5456 5457 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 5458 PCI_CLASS_REG)); 5459 interface &= ~PCIIDE_CHANSTATUS_EN; /* Reserved on PC87415 */ 5460 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 5461 5462 /* If we're in PCIIDE mode, unmask INTA, otherwise mask it. */ 5463 ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1); 5464 if (interface & (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1))) 5465 ctl &= ~NATSEMI_CTRL1_INTAMASK; 5466 else 5467 ctl |= NATSEMI_CTRL1_INTAMASK; 5468 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl); 5469 5470 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5471 cp = &sc->pciide_channels[channel]; 5472 if (pciide_chansetup(sc, channel, interface) == 0) 5473 continue; 5474 5475 pciide_map_compat_intr(pa, cp, channel, interface); 5476 if (cp->hw_ok == 0) 5477 continue; 5478 5479 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5480 natsemi_pci_intr); 5481 if (cp->hw_ok == 0) { 5482 pciide_unmap_compat_intr(pa, cp, channel, interface); 5483 continue; 5484 } 5485 natsemi_setup_channel(&cp->wdc_channel); 5486 } 5487 } 5488 5489 void 5490 natsemi_setup_channel(struct channel_softc *chp) 5491 { 5492 struct ata_drive_datas *drvp; 5493 int drive, ndrives = 0; 5494 u_int32_t idedma_ctl = 0; 5495 struct pciide_channel *cp = (struct pciide_channel *)chp; 5496 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5497 u_int8_t tim; 5498 5499 /* setup DMA if needed */ 5500 pciide_channel_dma_setup(cp); 5501 5502 for (drive = 0; drive < 2; drive++) { 5503 drvp = &chp->ch_drive[drive]; 5504 /* If no drive, skip */ 5505 if ((drvp->drive_flags & DRIVE) == 0) 5506 continue; 5507 5508 ndrives++; 5509 /* add timing values, setup DMA if needed */ 5510 if ((drvp->drive_flags & DRIVE_DMA) == 0) { 5511 tim = natsemi_pio_pulse[drvp->PIO_mode] | 5512 (natsemi_pio_recover[drvp->PIO_mode] << 4); 5513 } else { 5514 /* 5515 * use Multiword DMA 5516 * Timings will be used for both PIO and DMA, 5517 * so adjust DMA mode if needed 5518 */ 5519 if (drvp->PIO_mode >= 3 && 5520 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 5521 drvp->DMA_mode = drvp->PIO_mode - 2; 5522 } 5523 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5524 tim = natsemi_dma_pulse[drvp->DMA_mode] | 5525 (natsemi_dma_recover[drvp->DMA_mode] << 4); 5526 } 5527 5528 pciide_pci_write(sc->sc_pc, sc->sc_tag, 5529 NATSEMI_RTREG(chp->channel, drive), tim); 5530 pciide_pci_write(sc->sc_pc, sc->sc_tag, 5531 NATSEMI_WTREG(chp->channel, drive), tim); 5532 } 5533 if (idedma_ctl != 0) { 5534 /* Add software bits in status register */ 5535 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5536 IDEDMA_CTL(chp->channel), idedma_ctl); 5537 } 5538 if (ndrives > 0) { 5539 /* Unmask the channel if at least one drive is found */ 5540 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 5541 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) & 5542 ~(NATSEMI_CHMASK(chp->channel))); 5543 } 5544 5545 pciide_print_modes(cp); 5546 5547 /* Go ahead and ack interrupts generated during probe. */ 5548 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5549 IDEDMA_CTL(chp->channel), 5550 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5551 IDEDMA_CTL(chp->channel))); 5552 } 5553 5554 void 5555 natsemi_irqack(struct channel_softc *chp) 5556 { 5557 struct pciide_channel *cp = (struct pciide_channel *)chp; 5558 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5559 u_int8_t clr; 5560 5561 /* The "clear" bits are in the wrong register *sigh* */ 5562 clr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5563 IDEDMA_CMD(chp->channel)); 5564 clr |= bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5565 IDEDMA_CTL(chp->channel)) & 5566 (IDEDMA_CTL_ERR | IDEDMA_CTL_INTR); 5567 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5568 IDEDMA_CMD(chp->channel), clr); 5569 } 5570 5571 int 5572 natsemi_pci_intr(void *arg) 5573 { 5574 struct pciide_softc *sc = arg; 5575 struct pciide_channel *cp; 5576 struct channel_softc *wdc_cp; 5577 int i, rv, crv; 5578 u_int8_t msk; 5579 5580 rv = 0; 5581 msk = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2); 5582 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5583 cp = &sc->pciide_channels[i]; 5584 wdc_cp = &cp->wdc_channel; 5585 5586 /* If a compat channel skip. */ 5587 if (cp->compat) 5588 continue; 5589 5590 /* If this channel is masked, skip it. */ 5591 if (msk & NATSEMI_CHMASK(i)) 5592 continue; 5593 5594 if (pciide_intr_flag(cp) == 0) 5595 continue; 5596 5597 crv = wdcintr(wdc_cp); 5598 if (crv == 0) 5599 ; /* leave rv alone */ 5600 else if (crv == 1) 5601 rv = 1; /* claim the intr */ 5602 else if (rv == 0) /* crv should be -1 in this case */ 5603 rv = crv; /* if we've done no better, take it */ 5604 } 5605 return (rv); 5606 } 5607 5608 void 5609 ns_scx200_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 5610 { 5611 struct pciide_channel *cp; 5612 int channel; 5613 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 5614 bus_size_t cmdsize, ctlsize; 5615 5616 printf(": DMA"); 5617 pciide_mapreg_dma(sc, pa); 5618 5619 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5620 WDC_CAPABILITY_MODE; 5621 if (sc->sc_dma_ok) { 5622 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5623 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5624 sc->sc_wdcdev.irqack = pciide_irqack; 5625 } 5626 sc->sc_wdcdev.PIO_cap = 4; 5627 sc->sc_wdcdev.DMA_cap = 2; 5628 sc->sc_wdcdev.UDMA_cap = 2; 5629 5630 sc->sc_wdcdev.set_modes = ns_scx200_setup_channel; 5631 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5632 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5633 5634 /* 5635 * Soekris net4801 errata 0003: 5636 * 5637 * The SC1100 built in busmaster IDE controller is pretty standard, 5638 * but have two bugs: data transfers need to be dword aligned and 5639 * it cannot do an exact 64Kbyte data transfer. 5640 * 5641 * Assume that reducing maximum segment size by one page 5642 * will be enough, and restrict boundary too for extra certainty. 5643 */ 5644 if (sc->sc_pp->ide_product == PCI_PRODUCT_NS_SCX200_IDE) { 5645 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX - PAGE_SIZE; 5646 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_MAX - PAGE_SIZE; 5647 } 5648 5649 /* 5650 * This chip seems to be unable to do one-sector transfers 5651 * using DMA. 5652 */ 5653 sc->sc_wdcdev.quirks = WDC_QUIRK_NOSHORTDMA; 5654 5655 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 5656 5657 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5658 cp = &sc->pciide_channels[channel]; 5659 if (pciide_chansetup(sc, channel, interface) == 0) 5660 continue; 5661 pciide_map_compat_intr(pa, cp, channel, interface); 5662 if (cp->hw_ok == 0) 5663 continue; 5664 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5665 pciide_pci_intr); 5666 if (cp->hw_ok == 0) { 5667 pciide_unmap_compat_intr(pa, cp, channel, interface); 5668 continue; 5669 } 5670 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 5671 } 5672 } 5673 5674 void 5675 ns_scx200_setup_channel(struct channel_softc *chp) 5676 { 5677 struct ata_drive_datas *drvp; 5678 int drive, mode; 5679 u_int32_t idedma_ctl; 5680 struct pciide_channel *cp = (struct pciide_channel*)chp; 5681 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5682 int channel = chp->channel; 5683 int pioformat; 5684 pcireg_t piotim, dmatim; 5685 5686 /* Setup DMA if needed */ 5687 pciide_channel_dma_setup(cp); 5688 5689 idedma_ctl = 0; 5690 5691 pioformat = (pci_conf_read(sc->sc_pc, sc->sc_tag, 5692 SCx200_TIM_DMA(0, 0)) >> SCx200_PIOFORMAT_SHIFT) & 0x01; 5693 WDCDEBUG_PRINT(("%s: pio format %d\n", __func__, pioformat), 5694 DEBUG_PROBE); 5695 5696 /* Per channel settings */ 5697 for (drive = 0; drive < 2; drive++) { 5698 drvp = &chp->ch_drive[drive]; 5699 5700 /* If no drive, skip */ 5701 if ((drvp->drive_flags & DRIVE) == 0) 5702 continue; 5703 5704 piotim = pci_conf_read(sc->sc_pc, sc->sc_tag, 5705 SCx200_TIM_PIO(channel, drive)); 5706 dmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 5707 SCx200_TIM_DMA(channel, drive)); 5708 WDCDEBUG_PRINT(("%s:%d:%d: piotim=0x%x, dmatim=0x%x\n", 5709 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, 5710 piotim, dmatim), DEBUG_PROBE); 5711 5712 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 5713 (drvp->drive_flags & DRIVE_UDMA) != 0) { 5714 /* Setup UltraDMA mode */ 5715 drvp->drive_flags &= ~DRIVE_DMA; 5716 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5717 dmatim = scx200_udma33[drvp->UDMA_mode]; 5718 mode = drvp->PIO_mode; 5719 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 5720 (drvp->drive_flags & DRIVE_DMA) != 0) { 5721 /* Setup multiword DMA mode */ 5722 drvp->drive_flags &= ~DRIVE_UDMA; 5723 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5724 dmatim = scx200_dma33[drvp->DMA_mode]; 5725 5726 /* mode = min(pio, dma + 2) */ 5727 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 5728 mode = drvp->PIO_mode; 5729 else 5730 mode = drvp->DMA_mode + 2; 5731 } else { 5732 mode = drvp->PIO_mode; 5733 } 5734 5735 /* Setup PIO mode */ 5736 drvp->PIO_mode = mode; 5737 if (mode < 2) 5738 drvp->DMA_mode = 0; 5739 else 5740 drvp->DMA_mode = mode - 2; 5741 5742 piotim = scx200_pio33[pioformat][drvp->PIO_mode]; 5743 5744 WDCDEBUG_PRINT(("%s:%d:%d: new piotim=0x%x, dmatim=0x%x\n", 5745 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, 5746 piotim, dmatim), DEBUG_PROBE); 5747 5748 pci_conf_write(sc->sc_pc, sc->sc_tag, 5749 SCx200_TIM_PIO(channel, drive), piotim); 5750 pci_conf_write(sc->sc_pc, sc->sc_tag, 5751 SCx200_TIM_DMA(channel, drive), dmatim); 5752 } 5753 5754 if (idedma_ctl != 0) { 5755 /* Add software bits in status register */ 5756 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5757 IDEDMA_CTL(channel), idedma_ctl); 5758 } 5759 5760 pciide_print_modes(cp); 5761 } 5762 5763 void 5764 acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 5765 { 5766 struct pciide_channel *cp; 5767 int channel; 5768 pcireg_t cr, interface; 5769 bus_size_t cmdsize, ctlsize; 5770 int rev = sc->sc_rev; 5771 5772 printf(": DMA"); 5773 pciide_mapreg_dma(sc, pa); 5774 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5775 WDC_CAPABILITY_MODE; 5776 5777 if (sc->sc_dma_ok) { 5778 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 5779 if (rev >= 0x20) { 5780 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 5781 if (rev >= 0xC4) 5782 sc->sc_wdcdev.UDMA_cap = 5; 5783 else if (rev >= 0xC2) 5784 sc->sc_wdcdev.UDMA_cap = 4; 5785 else 5786 sc->sc_wdcdev.UDMA_cap = 2; 5787 } 5788 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5789 sc->sc_wdcdev.irqack = pciide_irqack; 5790 if (rev <= 0xC4) 5791 sc->sc_wdcdev.dma_init = acer_dma_init; 5792 } 5793 5794 sc->sc_wdcdev.PIO_cap = 4; 5795 sc->sc_wdcdev.DMA_cap = 2; 5796 sc->sc_wdcdev.set_modes = acer_setup_channel; 5797 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5798 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5799 5800 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 5801 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 5802 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 5803 5804 /* Enable "microsoft register bits" R/W. */ 5805 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 5806 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 5807 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 5808 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 5809 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 5810 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 5811 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 5812 ~ACER_CHANSTATUSREGS_RO); 5813 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 5814 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 5815 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 5816 /* Don't use cr, re-read the real register content instead */ 5817 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 5818 PCI_CLASS_REG)); 5819 5820 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 5821 5822 /* From linux: enable "Cable Detection" */ 5823 if (rev >= 0xC2) 5824 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 5825 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 5826 | ACER_0x4B_CDETECT); 5827 5828 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5829 cp = &sc->pciide_channels[channel]; 5830 if (pciide_chansetup(sc, channel, interface) == 0) 5831 continue; 5832 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 5833 printf("%s: %s ignored (disabled)\n", 5834 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 5835 cp->hw_ok = 0; 5836 continue; 5837 } 5838 pciide_map_compat_intr(pa, cp, channel, interface); 5839 if (cp->hw_ok == 0) 5840 continue; 5841 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5842 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 5843 if (cp->hw_ok == 0) { 5844 pciide_unmap_compat_intr(pa, cp, channel, interface); 5845 continue; 5846 } 5847 if (pciide_chan_candisable(cp)) { 5848 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 5849 pci_conf_write(sc->sc_pc, sc->sc_tag, 5850 PCI_CLASS_REG, cr); 5851 } 5852 if (cp->hw_ok == 0) { 5853 pciide_unmap_compat_intr(pa, cp, channel, interface); 5854 continue; 5855 } 5856 acer_setup_channel(&cp->wdc_channel); 5857 } 5858 } 5859 5860 void 5861 acer_setup_channel(struct channel_softc *chp) 5862 { 5863 struct ata_drive_datas *drvp; 5864 int drive; 5865 u_int32_t acer_fifo_udma; 5866 u_int32_t idedma_ctl; 5867 struct pciide_channel *cp = (struct pciide_channel *)chp; 5868 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5869 5870 idedma_ctl = 0; 5871 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 5872 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 5873 acer_fifo_udma), DEBUG_PROBE); 5874 /* setup DMA if needed */ 5875 pciide_channel_dma_setup(cp); 5876 5877 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 5878 DRIVE_UDMA) { /* check 80 pins cable */ 5879 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 5880 ACER_0x4A_80PIN(chp->channel)) { 5881 WDCDEBUG_PRINT(("%s:%d: 80-wire cable not detected\n", 5882 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel), 5883 DEBUG_PROBE); 5884 if (chp->ch_drive[0].UDMA_mode > 2) 5885 chp->ch_drive[0].UDMA_mode = 2; 5886 if (chp->ch_drive[1].UDMA_mode > 2) 5887 chp->ch_drive[1].UDMA_mode = 2; 5888 } 5889 } 5890 5891 for (drive = 0; drive < 2; drive++) { 5892 drvp = &chp->ch_drive[drive]; 5893 /* If no drive, skip */ 5894 if ((drvp->drive_flags & DRIVE) == 0) 5895 continue; 5896 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 5897 "channel %d drive %d 0x%x\n", chp->channel, drive, 5898 pciide_pci_read(sc->sc_pc, sc->sc_tag, 5899 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 5900 /* clear FIFO/DMA mode */ 5901 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 5902 ACER_UDMA_EN(chp->channel, drive) | 5903 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 5904 5905 /* add timing values, setup DMA if needed */ 5906 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 5907 (drvp->drive_flags & DRIVE_UDMA) == 0) { 5908 acer_fifo_udma |= 5909 ACER_FTH_OPL(chp->channel, drive, 0x1); 5910 goto pio; 5911 } 5912 5913 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 5914 if (drvp->drive_flags & DRIVE_UDMA) { 5915 /* use Ultra/DMA */ 5916 drvp->drive_flags &= ~DRIVE_DMA; 5917 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 5918 acer_fifo_udma |= 5919 ACER_UDMA_TIM(chp->channel, drive, 5920 acer_udma[drvp->UDMA_mode]); 5921 /* XXX disable if one drive < UDMA3 ? */ 5922 if (drvp->UDMA_mode >= 3) { 5923 pciide_pci_write(sc->sc_pc, sc->sc_tag, 5924 ACER_0x4B, 5925 pciide_pci_read(sc->sc_pc, sc->sc_tag, 5926 ACER_0x4B) | ACER_0x4B_UDMA66); 5927 } 5928 } else { 5929 /* 5930 * use Multiword DMA 5931 * Timings will be used for both PIO and DMA, 5932 * so adjust DMA mode if needed 5933 */ 5934 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 5935 drvp->PIO_mode = drvp->DMA_mode + 2; 5936 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 5937 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 5938 drvp->PIO_mode - 2 : 0; 5939 if (drvp->DMA_mode == 0) 5940 drvp->PIO_mode = 0; 5941 } 5942 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5943 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 5944 ACER_IDETIM(chp->channel, drive), 5945 acer_pio[drvp->PIO_mode]); 5946 } 5947 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 5948 acer_fifo_udma), DEBUG_PROBE); 5949 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 5950 if (idedma_ctl != 0) { 5951 /* Add software bits in status register */ 5952 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5953 IDEDMA_CTL(chp->channel), idedma_ctl); 5954 } 5955 pciide_print_modes(cp); 5956 } 5957 5958 int 5959 acer_pci_intr(void *arg) 5960 { 5961 struct pciide_softc *sc = arg; 5962 struct pciide_channel *cp; 5963 struct channel_softc *wdc_cp; 5964 int i, rv, crv; 5965 u_int32_t chids; 5966 5967 rv = 0; 5968 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 5969 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5970 cp = &sc->pciide_channels[i]; 5971 wdc_cp = &cp->wdc_channel; 5972 /* If a compat channel skip. */ 5973 if (cp->compat) 5974 continue; 5975 if (chids & ACER_CHIDS_INT(i)) { 5976 crv = wdcintr(wdc_cp); 5977 if (crv == 0) 5978 printf("%s:%d: bogus intr\n", 5979 sc->sc_wdcdev.sc_dev.dv_xname, i); 5980 else 5981 rv = 1; 5982 } 5983 } 5984 return (rv); 5985 } 5986 5987 int 5988 acer_dma_init(void *v, int channel, int drive, void *databuf, 5989 size_t datalen, int flags) 5990 { 5991 /* Use PIO for LBA48 transfers. */ 5992 if (flags & WDC_DMA_LBA48) 5993 return (EINVAL); 5994 5995 return (pciide_dma_init(v, channel, drive, databuf, datalen, flags)); 5996 } 5997 5998 void 5999 hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 6000 { 6001 struct pciide_channel *cp; 6002 int i, compatchan, revision; 6003 pcireg_t interface; 6004 bus_size_t cmdsize, ctlsize; 6005 6006 revision = sc->sc_rev; 6007 6008 /* 6009 * when the chip is in native mode it identifies itself as a 6010 * 'misc mass storage'. Fake interface in this case. 6011 */ 6012 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 6013 interface = PCI_INTERFACE(pa->pa_class); 6014 } else { 6015 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 6016 PCIIDE_INTERFACE_PCI(0); 6017 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 6018 (revision == HPT370_REV || revision == HPT370A_REV || 6019 revision == HPT372_REV)) || 6020 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 6021 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 6022 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 6023 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 6024 interface |= PCIIDE_INTERFACE_PCI(1); 6025 } 6026 6027 printf(": DMA"); 6028 pciide_mapreg_dma(sc, pa); 6029 printf("\n"); 6030 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 6031 WDC_CAPABILITY_MODE; 6032 if (sc->sc_dma_ok) { 6033 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 6034 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 6035 sc->sc_wdcdev.irqack = pciide_irqack; 6036 } 6037 sc->sc_wdcdev.PIO_cap = 4; 6038 sc->sc_wdcdev.DMA_cap = 2; 6039 6040 sc->sc_wdcdev.set_modes = hpt_setup_channel; 6041 sc->sc_wdcdev.channels = sc->wdc_chanarray; 6042 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 6043 revision == HPT366_REV) { 6044 sc->sc_wdcdev.UDMA_cap = 4; 6045 /* 6046 * The 366 has 2 PCI IDE functions, one for primary and one 6047 * for secondary. So we need to call pciide_mapregs_compat() 6048 * with the real channel 6049 */ 6050 if (pa->pa_function == 0) { 6051 compatchan = 0; 6052 } else if (pa->pa_function == 1) { 6053 compatchan = 1; 6054 } else { 6055 printf("%s: unexpected PCI function %d\n", 6056 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 6057 return; 6058 } 6059 sc->sc_wdcdev.nchannels = 1; 6060 } else { 6061 sc->sc_wdcdev.nchannels = 2; 6062 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 6063 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 6064 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 6065 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 6066 sc->sc_wdcdev.UDMA_cap = 6; 6067 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 6068 if (revision == HPT372_REV) 6069 sc->sc_wdcdev.UDMA_cap = 6; 6070 else 6071 sc->sc_wdcdev.UDMA_cap = 5; 6072 } 6073 } 6074 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 6075 cp = &sc->pciide_channels[i]; 6076 compatchan = 0; 6077 if (sc->sc_wdcdev.nchannels > 1) { 6078 compatchan = i; 6079 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 6080 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 6081 printf("%s: %s ignored (disabled)\n", 6082 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 6083 cp->hw_ok = 0; 6084 continue; 6085 } 6086 } 6087 if (pciide_chansetup(sc, i, interface) == 0) 6088 continue; 6089 if (interface & PCIIDE_INTERFACE_PCI(i)) { 6090 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 6091 &ctlsize, hpt_pci_intr); 6092 } else { 6093 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 6094 &cmdsize, &ctlsize); 6095 } 6096 if (cp->hw_ok == 0) 6097 return; 6098 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 6099 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 6100 wdcattach(&cp->wdc_channel); 6101 hpt_setup_channel(&cp->wdc_channel); 6102 } 6103 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 6104 (revision == HPT370_REV || revision == HPT370A_REV || 6105 revision == HPT372_REV)) || 6106 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 6107 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 6108 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 6109 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 6110 /* 6111 * Turn off fast interrupts 6112 */ 6113 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(0), 6114 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(0)) & 6115 ~(HPT370_CTRL2_FASTIRQ | HPT370_CTRL2_HIRQ)); 6116 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(1), 6117 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(1)) & 6118 ~(HPT370_CTRL2_FASTIRQ | HPT370_CTRL2_HIRQ)); 6119 6120 /* 6121 * HPT370 and higher has a bit to disable interrupts, 6122 * make sure to clear it 6123 */ 6124 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 6125 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 6126 ~HPT_CSEL_IRQDIS); 6127 } 6128 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 6129 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 6130 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 6131 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 6132 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 6133 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 6134 revision == HPT372_REV)) 6135 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 6136 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 6137 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 6138 6139 return; 6140 } 6141 6142 void 6143 hpt_setup_channel(struct channel_softc *chp) 6144 { 6145 struct ata_drive_datas *drvp; 6146 int drive; 6147 int cable; 6148 u_int32_t before, after; 6149 u_int32_t idedma_ctl; 6150 struct pciide_channel *cp = (struct pciide_channel *)chp; 6151 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6152 int revision = sc->sc_rev; 6153 u_int32_t *tim_pio, *tim_dma, *tim_udma; 6154 6155 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 6156 6157 /* setup DMA if needed */ 6158 pciide_channel_dma_setup(cp); 6159 6160 idedma_ctl = 0; 6161 6162 switch (sc->sc_pp->ide_product) { 6163 case PCI_PRODUCT_TRIONES_HPT366: 6164 if (revision == HPT370_REV || 6165 revision == HPT370A_REV) { 6166 tim_pio = hpt370_pio; 6167 tim_dma = hpt370_dma; 6168 tim_udma = hpt370_udma; 6169 } else if (revision == HPT372_REV) { 6170 tim_pio = hpt372_pio; 6171 tim_dma = hpt372_dma; 6172 tim_udma = hpt372_udma; 6173 } else { 6174 tim_pio = hpt366_pio; 6175 tim_dma = hpt366_dma; 6176 tim_udma = hpt366_udma; 6177 } 6178 break; 6179 case PCI_PRODUCT_TRIONES_HPT372A: 6180 case PCI_PRODUCT_TRIONES_HPT302: 6181 case PCI_PRODUCT_TRIONES_HPT371: 6182 tim_pio = hpt372_pio; 6183 tim_dma = hpt372_dma; 6184 tim_udma = hpt372_udma; 6185 break; 6186 case PCI_PRODUCT_TRIONES_HPT374: 6187 tim_pio = hpt374_pio; 6188 tim_dma = hpt374_dma; 6189 tim_udma = hpt374_udma; 6190 break; 6191 default: 6192 printf("%s: no known timing values\n", 6193 sc->sc_wdcdev.sc_dev.dv_xname); 6194 goto end; 6195 } 6196 6197 /* Per drive settings */ 6198 for (drive = 0; drive < 2; drive++) { 6199 drvp = &chp->ch_drive[drive]; 6200 /* If no drive, skip */ 6201 if ((drvp->drive_flags & DRIVE) == 0) 6202 continue; 6203 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 6204 HPT_IDETIM(chp->channel, drive)); 6205 6206 /* add timing values, setup DMA if needed */ 6207 if (drvp->drive_flags & DRIVE_UDMA) { 6208 /* use Ultra/DMA */ 6209 drvp->drive_flags &= ~DRIVE_DMA; 6210 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 6211 drvp->UDMA_mode > 2) { 6212 WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire " 6213 "cable not detected\n", drvp->drive_name, 6214 sc->sc_wdcdev.sc_dev.dv_xname, 6215 chp->channel, drive), DEBUG_PROBE); 6216 drvp->UDMA_mode = 2; 6217 } 6218 after = tim_udma[drvp->UDMA_mode]; 6219 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 6220 } else if (drvp->drive_flags & DRIVE_DMA) { 6221 /* 6222 * use Multiword DMA. 6223 * Timings will be used for both PIO and DMA, so adjust 6224 * DMA mode if needed 6225 */ 6226 if (drvp->PIO_mode >= 3 && 6227 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 6228 drvp->DMA_mode = drvp->PIO_mode - 2; 6229 } 6230 after = tim_dma[drvp->DMA_mode]; 6231 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 6232 } else { 6233 /* PIO only */ 6234 after = tim_pio[drvp->PIO_mode]; 6235 } 6236 pci_conf_write(sc->sc_pc, sc->sc_tag, 6237 HPT_IDETIM(chp->channel, drive), after); 6238 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 6239 "(BIOS 0x%08x)\n", sc->sc_wdcdev.sc_dev.dv_xname, 6240 after, before), DEBUG_PROBE); 6241 } 6242 end: 6243 if (idedma_ctl != 0) { 6244 /* Add software bits in status register */ 6245 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6246 IDEDMA_CTL(chp->channel), idedma_ctl); 6247 } 6248 pciide_print_modes(cp); 6249 } 6250 6251 int 6252 hpt_pci_intr(void *arg) 6253 { 6254 struct pciide_softc *sc = arg; 6255 struct pciide_channel *cp; 6256 struct channel_softc *wdc_cp; 6257 int rv = 0; 6258 int dmastat, i, crv; 6259 6260 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 6261 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6262 IDEDMA_CTL(i)); 6263 if((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 6264 IDEDMA_CTL_INTR) 6265 continue; 6266 cp = &sc->pciide_channels[i]; 6267 wdc_cp = &cp->wdc_channel; 6268 crv = wdcintr(wdc_cp); 6269 if (crv == 0) { 6270 printf("%s:%d: bogus intr\n", 6271 sc->sc_wdcdev.sc_dev.dv_xname, i); 6272 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6273 IDEDMA_CTL(i), dmastat); 6274 } else 6275 rv = 1; 6276 } 6277 return (rv); 6278 } 6279 6280 /* Macros to test product */ 6281 #define PDC_IS_262(sc) \ 6282 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || \ 6283 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 6284 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267) 6285 #define PDC_IS_265(sc) \ 6286 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 6287 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 6288 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 6289 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268R || \ 6290 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 6291 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 6292 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 6293 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 6294 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 6295 #define PDC_IS_268(sc) \ 6296 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 6297 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268R || \ 6298 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 6299 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 6300 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 6301 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 6302 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 6303 #define PDC_IS_269(sc) \ 6304 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 6305 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 6306 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 6307 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 6308 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 6309 6310 u_int8_t 6311 pdc268_config_read(struct channel_softc *chp, int index) 6312 { 6313 struct pciide_channel *cp = (struct pciide_channel *)chp; 6314 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6315 int channel = chp->channel; 6316 6317 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6318 PDC268_INDEX(channel), index); 6319 return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6320 PDC268_DATA(channel))); 6321 } 6322 6323 void 6324 pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 6325 { 6326 struct pciide_channel *cp; 6327 int channel; 6328 pcireg_t interface, st, mode; 6329 bus_size_t cmdsize, ctlsize; 6330 6331 if (!PDC_IS_268(sc)) { 6332 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 6333 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 6334 st), DEBUG_PROBE); 6335 } 6336 6337 /* turn off RAID mode */ 6338 if (!PDC_IS_268(sc)) 6339 st &= ~PDC2xx_STATE_IDERAID; 6340 6341 /* 6342 * can't rely on the PCI_CLASS_REG content if the chip was in raid 6343 * mode. We have to fake interface 6344 */ 6345 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 6346 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 6347 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 6348 6349 printf(": DMA"); 6350 pciide_mapreg_dma(sc, pa); 6351 6352 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 6353 WDC_CAPABILITY_MODE; 6354 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20246 || 6355 PDC_IS_262(sc)) 6356 sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_ATAPI_DMA; 6357 if (sc->sc_dma_ok) { 6358 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 6359 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 6360 sc->sc_wdcdev.irqack = pciide_irqack; 6361 } 6362 sc->sc_wdcdev.PIO_cap = 4; 6363 sc->sc_wdcdev.DMA_cap = 2; 6364 if (PDC_IS_269(sc)) 6365 sc->sc_wdcdev.UDMA_cap = 6; 6366 else if (PDC_IS_265(sc)) 6367 sc->sc_wdcdev.UDMA_cap = 5; 6368 else if (PDC_IS_262(sc)) 6369 sc->sc_wdcdev.UDMA_cap = 4; 6370 else 6371 sc->sc_wdcdev.UDMA_cap = 2; 6372 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 6373 pdc20268_setup_channel : pdc202xx_setup_channel; 6374 sc->sc_wdcdev.channels = sc->wdc_chanarray; 6375 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 6376 6377 if (PDC_IS_262(sc)) { 6378 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 6379 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 6380 } 6381 6382 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 6383 if (!PDC_IS_268(sc)) { 6384 /* setup failsafe defaults */ 6385 mode = 0; 6386 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 6387 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 6388 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 6389 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 6390 for (channel = 0; 6391 channel < sc->sc_wdcdev.nchannels; 6392 channel++) { 6393 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 6394 "drive 0 initial timings 0x%x, now 0x%x\n", 6395 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 6396 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 6397 DEBUG_PROBE); 6398 pci_conf_write(sc->sc_pc, sc->sc_tag, 6399 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 6400 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 6401 "drive 1 initial timings 0x%x, now 0x%x\n", 6402 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 6403 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 6404 pci_conf_write(sc->sc_pc, sc->sc_tag, 6405 PDC2xx_TIM(channel, 1), mode); 6406 } 6407 6408 mode = PDC2xx_SCR_DMA; 6409 if (PDC_IS_262(sc)) { 6410 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 6411 } else { 6412 /* the BIOS set it up this way */ 6413 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 6414 } 6415 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 6416 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 6417 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 6418 "now 0x%x\n", 6419 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 6420 PDC2xx_SCR), 6421 mode), DEBUG_PROBE); 6422 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 6423 PDC2xx_SCR, mode); 6424 6425 /* controller initial state register is OK even without BIOS */ 6426 /* Set DMA mode to IDE DMA compatibility */ 6427 mode = 6428 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 6429 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 6430 DEBUG_PROBE); 6431 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 6432 mode | 0x1); 6433 mode = 6434 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 6435 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 6436 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 6437 mode | 0x1); 6438 } 6439 6440 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 6441 cp = &sc->pciide_channels[channel]; 6442 if (pciide_chansetup(sc, channel, interface) == 0) 6443 continue; 6444 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 6445 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 6446 printf("%s: %s ignored (disabled)\n", 6447 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 6448 cp->hw_ok = 0; 6449 continue; 6450 } 6451 pciide_map_compat_intr(pa, cp, channel, interface); 6452 if (cp->hw_ok == 0) 6453 continue; 6454 if (PDC_IS_265(sc)) 6455 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 6456 pdc20265_pci_intr); 6457 else 6458 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 6459 pdc202xx_pci_intr); 6460 if (cp->hw_ok == 0) { 6461 pciide_unmap_compat_intr(pa, cp, channel, interface); 6462 continue; 6463 } 6464 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) { 6465 st &= ~(PDC_IS_262(sc) ? 6466 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 6467 pciide_unmap_compat_intr(pa, cp, channel, interface); 6468 } 6469 if (PDC_IS_268(sc)) 6470 pdc20268_setup_channel(&cp->wdc_channel); 6471 else 6472 pdc202xx_setup_channel(&cp->wdc_channel); 6473 } 6474 if (!PDC_IS_268(sc)) { 6475 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 6476 "0x%x\n", st), DEBUG_PROBE); 6477 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 6478 } 6479 return; 6480 } 6481 6482 void 6483 pdc202xx_setup_channel(struct channel_softc *chp) 6484 { 6485 struct ata_drive_datas *drvp; 6486 int drive; 6487 pcireg_t mode, st; 6488 u_int32_t idedma_ctl, scr, atapi; 6489 struct pciide_channel *cp = (struct pciide_channel *)chp; 6490 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6491 int channel = chp->channel; 6492 6493 /* setup DMA if needed */ 6494 pciide_channel_dma_setup(cp); 6495 6496 idedma_ctl = 0; 6497 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 6498 sc->sc_wdcdev.sc_dev.dv_xname, 6499 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 6500 DEBUG_PROBE); 6501 6502 /* Per channel settings */ 6503 if (PDC_IS_262(sc)) { 6504 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6505 PDC262_U66); 6506 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 6507 /* Check cable */ 6508 if ((st & PDC262_STATE_80P(channel)) != 0 && 6509 ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 6510 chp->ch_drive[0].UDMA_mode > 2) || 6511 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 6512 chp->ch_drive[1].UDMA_mode > 2))) { 6513 WDCDEBUG_PRINT(("%s:%d: 80-wire cable not detected\n", 6514 sc->sc_wdcdev.sc_dev.dv_xname, channel), 6515 DEBUG_PROBE); 6516 if (chp->ch_drive[0].UDMA_mode > 2) 6517 chp->ch_drive[0].UDMA_mode = 2; 6518 if (chp->ch_drive[1].UDMA_mode > 2) 6519 chp->ch_drive[1].UDMA_mode = 2; 6520 } 6521 /* Trim UDMA mode */ 6522 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 6523 chp->ch_drive[0].UDMA_mode <= 2) || 6524 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 6525 chp->ch_drive[1].UDMA_mode <= 2)) { 6526 if (chp->ch_drive[0].UDMA_mode > 2) 6527 chp->ch_drive[0].UDMA_mode = 2; 6528 if (chp->ch_drive[1].UDMA_mode > 2) 6529 chp->ch_drive[1].UDMA_mode = 2; 6530 } 6531 /* Set U66 if needed */ 6532 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 6533 chp->ch_drive[0].UDMA_mode > 2) || 6534 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 6535 chp->ch_drive[1].UDMA_mode > 2)) 6536 scr |= PDC262_U66_EN(channel); 6537 else 6538 scr &= ~PDC262_U66_EN(channel); 6539 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6540 PDC262_U66, scr); 6541 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 6542 sc->sc_wdcdev.sc_dev.dv_xname, channel, 6543 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 6544 PDC262_ATAPI(channel))), DEBUG_PROBE); 6545 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 6546 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 6547 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 6548 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 6549 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 6550 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 6551 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 6552 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 6553 atapi = 0; 6554 else 6555 atapi = PDC262_ATAPI_UDMA; 6556 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 6557 PDC262_ATAPI(channel), atapi); 6558 } 6559 } 6560 for (drive = 0; drive < 2; drive++) { 6561 drvp = &chp->ch_drive[drive]; 6562 /* If no drive, skip */ 6563 if ((drvp->drive_flags & DRIVE) == 0) 6564 continue; 6565 mode = 0; 6566 if (drvp->drive_flags & DRIVE_UDMA) { 6567 /* use Ultra/DMA */ 6568 drvp->drive_flags &= ~DRIVE_DMA; 6569 mode = PDC2xx_TIM_SET_MB(mode, 6570 pdc2xx_udma_mb[drvp->UDMA_mode]); 6571 mode = PDC2xx_TIM_SET_MC(mode, 6572 pdc2xx_udma_mc[drvp->UDMA_mode]); 6573 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 6574 } else if (drvp->drive_flags & DRIVE_DMA) { 6575 mode = PDC2xx_TIM_SET_MB(mode, 6576 pdc2xx_dma_mb[drvp->DMA_mode]); 6577 mode = PDC2xx_TIM_SET_MC(mode, 6578 pdc2xx_dma_mc[drvp->DMA_mode]); 6579 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 6580 } else { 6581 mode = PDC2xx_TIM_SET_MB(mode, 6582 pdc2xx_dma_mb[0]); 6583 mode = PDC2xx_TIM_SET_MC(mode, 6584 pdc2xx_dma_mc[0]); 6585 } 6586 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 6587 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 6588 if (drvp->drive_flags & DRIVE_ATA) 6589 mode |= PDC2xx_TIM_PRE; 6590 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 6591 if (drvp->PIO_mode >= 3) { 6592 mode |= PDC2xx_TIM_IORDY; 6593 if (drive == 0) 6594 mode |= PDC2xx_TIM_IORDYp; 6595 } 6596 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 6597 "timings 0x%x\n", 6598 sc->sc_wdcdev.sc_dev.dv_xname, 6599 chp->channel, drive, mode), DEBUG_PROBE); 6600 pci_conf_write(sc->sc_pc, sc->sc_tag, 6601 PDC2xx_TIM(chp->channel, drive), mode); 6602 } 6603 if (idedma_ctl != 0) { 6604 /* Add software bits in status register */ 6605 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6606 IDEDMA_CTL(channel), idedma_ctl); 6607 } 6608 pciide_print_modes(cp); 6609 } 6610 6611 void 6612 pdc20268_setup_channel(struct channel_softc *chp) 6613 { 6614 struct ata_drive_datas *drvp; 6615 int drive, cable; 6616 u_int32_t idedma_ctl; 6617 struct pciide_channel *cp = (struct pciide_channel *)chp; 6618 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6619 int channel = chp->channel; 6620 6621 /* check 80 pins cable */ 6622 cable = pdc268_config_read(chp, 0x0b) & PDC268_CABLE; 6623 6624 /* setup DMA if needed */ 6625 pciide_channel_dma_setup(cp); 6626 6627 idedma_ctl = 0; 6628 6629 for (drive = 0; drive < 2; drive++) { 6630 drvp = &chp->ch_drive[drive]; 6631 /* If no drive, skip */ 6632 if ((drvp->drive_flags & DRIVE) == 0) 6633 continue; 6634 if (drvp->drive_flags & DRIVE_UDMA) { 6635 /* use Ultra/DMA */ 6636 drvp->drive_flags &= ~DRIVE_DMA; 6637 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 6638 if (cable && drvp->UDMA_mode > 2) { 6639 WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire " 6640 "cable not detected\n", drvp->drive_name, 6641 sc->sc_wdcdev.sc_dev.dv_xname, 6642 channel, drive), DEBUG_PROBE); 6643 drvp->UDMA_mode = 2; 6644 } 6645 } else if (drvp->drive_flags & DRIVE_DMA) { 6646 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 6647 } 6648 } 6649 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 6650 if (idedma_ctl != 0) { 6651 /* Add software bits in status register */ 6652 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6653 IDEDMA_CTL(channel), idedma_ctl); 6654 } 6655 pciide_print_modes(cp); 6656 } 6657 6658 int 6659 pdc202xx_pci_intr(void *arg) 6660 { 6661 struct pciide_softc *sc = arg; 6662 struct pciide_channel *cp; 6663 struct channel_softc *wdc_cp; 6664 int i, rv, crv; 6665 u_int32_t scr; 6666 6667 rv = 0; 6668 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 6669 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 6670 cp = &sc->pciide_channels[i]; 6671 wdc_cp = &cp->wdc_channel; 6672 /* If a compat channel skip. */ 6673 if (cp->compat) 6674 continue; 6675 if (scr & PDC2xx_SCR_INT(i)) { 6676 crv = wdcintr(wdc_cp); 6677 if (crv == 0) 6678 printf("%s:%d: bogus intr (reg 0x%x)\n", 6679 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 6680 else 6681 rv = 1; 6682 } 6683 } 6684 return (rv); 6685 } 6686 6687 int 6688 pdc20265_pci_intr(void *arg) 6689 { 6690 struct pciide_softc *sc = arg; 6691 struct pciide_channel *cp; 6692 struct channel_softc *wdc_cp; 6693 int i, rv, crv; 6694 u_int32_t dmastat; 6695 6696 rv = 0; 6697 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 6698 cp = &sc->pciide_channels[i]; 6699 wdc_cp = &cp->wdc_channel; 6700 /* If a compat channel skip. */ 6701 if (cp->compat) 6702 continue; 6703 6704 /* 6705 * In case of shared IRQ check that the interrupt 6706 * was actually generated by this channel. 6707 * Only check the channel that is enabled. 6708 */ 6709 if (cp->hw_ok && PDC_IS_268(sc)) { 6710 if ((pdc268_config_read(wdc_cp, 6711 0x0b) & PDC268_INTR) == 0) 6712 continue; 6713 } 6714 6715 /* 6716 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 6717 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 6718 * So use it instead (requires 2 reg reads instead of 1, 6719 * but we can't do it another way). 6720 */ 6721 dmastat = bus_space_read_1(sc->sc_dma_iot, 6722 sc->sc_dma_ioh, IDEDMA_CTL(i)); 6723 if ((dmastat & IDEDMA_CTL_INTR) == 0) 6724 continue; 6725 6726 crv = wdcintr(wdc_cp); 6727 if (crv == 0) 6728 printf("%s:%d: bogus intr\n", 6729 sc->sc_wdcdev.sc_dev.dv_xname, i); 6730 else 6731 rv = 1; 6732 } 6733 return (rv); 6734 } 6735 6736 void 6737 pdc20262_dma_start(void *v, int channel, int drive) 6738 { 6739 struct pciide_softc *sc = v; 6740 struct pciide_dma_maps *dma_maps = 6741 &sc->pciide_channels[channel].dma_maps[drive]; 6742 u_int8_t clock; 6743 u_int32_t count; 6744 6745 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 6746 clock = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6747 PDC262_U66); 6748 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6749 PDC262_U66, clock | PDC262_U66_EN(channel)); 6750 count = dma_maps->dmamap_xfer->dm_mapsize >> 1; 6751 count |= dma_maps->dma_flags & WDC_DMA_READ ? 6752 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 6753 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 6754 PDC262_ATAPI(channel), count); 6755 } 6756 6757 pciide_dma_start(v, channel, drive); 6758 } 6759 6760 int 6761 pdc20262_dma_finish(void *v, int channel, int drive, int force) 6762 { 6763 struct pciide_softc *sc = v; 6764 struct pciide_dma_maps *dma_maps = 6765 &sc->pciide_channels[channel].dma_maps[drive]; 6766 u_int8_t clock; 6767 6768 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 6769 clock = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6770 PDC262_U66); 6771 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6772 PDC262_U66, clock & ~PDC262_U66_EN(channel)); 6773 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 6774 PDC262_ATAPI(channel), 0); 6775 } 6776 6777 return (pciide_dma_finish(v, channel, drive, force)); 6778 } 6779 6780 void 6781 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 6782 { 6783 struct pciide_channel *cp; 6784 struct channel_softc *wdc_cp; 6785 struct pciide_pdcsata *ps; 6786 int channel, i; 6787 bus_size_t dmasize; 6788 pci_intr_handle_t intrhandle; 6789 const char *intrstr; 6790 6791 /* Allocate memory for private data */ 6792 sc->sc_cookielen = sizeof(*ps); 6793 sc->sc_cookie = malloc(sc->sc_cookielen, M_DEVBUF, M_NOWAIT | M_ZERO); 6794 ps = sc->sc_cookie; 6795 6796 /* 6797 * Promise SATA controllers have 3 or 4 channels, 6798 * the usual IDE registers are mapped in I/O space, with offsets. 6799 */ 6800 if (pci_intr_map(pa, &intrhandle) != 0) { 6801 printf(": couldn't map interrupt\n"); 6802 return; 6803 } 6804 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 6805 6806 switch (sc->sc_pp->ide_product) { 6807 case PCI_PRODUCT_PROMISE_PDC20318: 6808 case PCI_PRODUCT_PROMISE_PDC20319: 6809 case PCI_PRODUCT_PROMISE_PDC20371: 6810 case PCI_PRODUCT_PROMISE_PDC20375: 6811 case PCI_PRODUCT_PROMISE_PDC20376: 6812 case PCI_PRODUCT_PROMISE_PDC20377: 6813 case PCI_PRODUCT_PROMISE_PDC20378: 6814 case PCI_PRODUCT_PROMISE_PDC20379: 6815 default: 6816 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 6817 intrhandle, IPL_BIO, pdc203xx_pci_intr, sc, 6818 sc->sc_wdcdev.sc_dev.dv_xname); 6819 break; 6820 6821 case PCI_PRODUCT_PROMISE_PDC40518: 6822 case PCI_PRODUCT_PROMISE_PDC40519: 6823 case PCI_PRODUCT_PROMISE_PDC40718: 6824 case PCI_PRODUCT_PROMISE_PDC40719: 6825 case PCI_PRODUCT_PROMISE_PDC40779: 6826 case PCI_PRODUCT_PROMISE_PDC20571: 6827 case PCI_PRODUCT_PROMISE_PDC20575: 6828 case PCI_PRODUCT_PROMISE_PDC20579: 6829 case PCI_PRODUCT_PROMISE_PDC20771: 6830 case PCI_PRODUCT_PROMISE_PDC20775: 6831 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 6832 intrhandle, IPL_BIO, pdc205xx_pci_intr, sc, 6833 sc->sc_wdcdev.sc_dev.dv_xname); 6834 break; 6835 } 6836 6837 if (sc->sc_pci_ih == NULL) { 6838 printf(": couldn't establish native-PCI interrupt"); 6839 if (intrstr != NULL) 6840 printf(" at %s", intrstr); 6841 printf("\n"); 6842 return; 6843 } 6844 6845 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 6846 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 6847 &sc->sc_dma_ioh, NULL, &dmasize, 0) == 0); 6848 if (!sc->sc_dma_ok) { 6849 printf(": couldn't map bus-master DMA registers\n"); 6850 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 6851 return; 6852 } 6853 6854 sc->sc_dmat = pa->pa_dmat; 6855 6856 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 6857 PCI_MAPREG_MEM_TYPE_32BIT, 0, &ps->ba5_st, 6858 &ps->ba5_sh, NULL, NULL, 0) != 0) { 6859 printf(": couldn't map IDE registers\n"); 6860 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 6861 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 6862 return; 6863 } 6864 6865 printf(": DMA\n"); 6866 6867 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 6868 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 6869 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 6870 sc->sc_wdcdev.irqack = pdc203xx_irqack; 6871 sc->sc_wdcdev.PIO_cap = 4; 6872 sc->sc_wdcdev.DMA_cap = 2; 6873 sc->sc_wdcdev.UDMA_cap = 6; 6874 sc->sc_wdcdev.set_modes = pdc203xx_setup_channel; 6875 sc->sc_wdcdev.channels = sc->wdc_chanarray; 6876 6877 switch (sc->sc_pp->ide_product) { 6878 case PCI_PRODUCT_PROMISE_PDC20318: 6879 case PCI_PRODUCT_PROMISE_PDC20319: 6880 case PCI_PRODUCT_PROMISE_PDC20371: 6881 case PCI_PRODUCT_PROMISE_PDC20375: 6882 case PCI_PRODUCT_PROMISE_PDC20376: 6883 case PCI_PRODUCT_PROMISE_PDC20377: 6884 case PCI_PRODUCT_PROMISE_PDC20378: 6885 case PCI_PRODUCT_PROMISE_PDC20379: 6886 default: 6887 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x06c, 0x00ff0033); 6888 sc->sc_wdcdev.nchannels = 6889 (bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x48) & 0x02) ? 6890 PDC203xx_NCHANNELS : 3; 6891 break; 6892 6893 case PCI_PRODUCT_PROMISE_PDC40518: 6894 case PCI_PRODUCT_PROMISE_PDC40519: 6895 case PCI_PRODUCT_PROMISE_PDC40718: 6896 case PCI_PRODUCT_PROMISE_PDC40719: 6897 case PCI_PRODUCT_PROMISE_PDC40779: 6898 case PCI_PRODUCT_PROMISE_PDC20571: 6899 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x60, 0x00ff00ff); 6900 sc->sc_wdcdev.nchannels = PDC40718_NCHANNELS; 6901 6902 sc->sc_wdcdev.reset = pdc205xx_do_reset; 6903 sc->sc_wdcdev.drv_probe = pdc205xx_drv_probe; 6904 6905 break; 6906 case PCI_PRODUCT_PROMISE_PDC20575: 6907 case PCI_PRODUCT_PROMISE_PDC20579: 6908 case PCI_PRODUCT_PROMISE_PDC20771: 6909 case PCI_PRODUCT_PROMISE_PDC20775: 6910 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x60, 0x00ff00ff); 6911 sc->sc_wdcdev.nchannels = PDC20575_NCHANNELS; 6912 6913 sc->sc_wdcdev.reset = pdc205xx_do_reset; 6914 sc->sc_wdcdev.drv_probe = pdc205xx_drv_probe; 6915 6916 break; 6917 } 6918 6919 sc->sc_wdcdev.dma_arg = sc; 6920 sc->sc_wdcdev.dma_init = pciide_dma_init; 6921 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 6922 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 6923 6924 for (channel = 0; channel < sc->sc_wdcdev.nchannels; 6925 channel++) { 6926 cp = &sc->pciide_channels[channel]; 6927 sc->wdc_chanarray[channel] = &cp->wdc_channel; 6928 6929 cp->ih = sc->sc_pci_ih; 6930 cp->name = NULL; 6931 cp->wdc_channel.channel = channel; 6932 cp->wdc_channel.wdc = &sc->sc_wdcdev; 6933 cp->wdc_channel.ch_queue = wdc_alloc_queue(); 6934 if (cp->wdc_channel.ch_queue == NULL) { 6935 printf("%s: channel %d: " 6936 "cannot allocate channel queue\n", 6937 sc->sc_wdcdev.sc_dev.dv_xname, channel); 6938 continue; 6939 } 6940 wdc_cp = &cp->wdc_channel; 6941 6942 ps->regs[channel].ctl_iot = ps->ba5_st; 6943 ps->regs[channel].cmd_iot = ps->ba5_st; 6944 6945 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh, 6946 0x0238 + (channel << 7), 1, 6947 &ps->regs[channel].ctl_ioh) != 0) { 6948 printf("%s: couldn't map channel %d ctl regs\n", 6949 sc->sc_wdcdev.sc_dev.dv_xname, 6950 channel); 6951 continue; 6952 } 6953 for (i = 0; i < WDC_NREG; i++) { 6954 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh, 6955 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 6956 &ps->regs[channel].cmd_iohs[i]) != 0) { 6957 printf("%s: couldn't map channel %d cmd " 6958 "regs\n", 6959 sc->sc_wdcdev.sc_dev.dv_xname, 6960 channel); 6961 goto loop_end; 6962 } 6963 } 6964 ps->regs[channel].cmd_iohs[wdr_status & _WDC_REGMASK] = 6965 ps->regs[channel].cmd_iohs[wdr_command & _WDC_REGMASK]; 6966 ps->regs[channel].cmd_iohs[wdr_features & _WDC_REGMASK] = 6967 ps->regs[channel].cmd_iohs[wdr_error & _WDC_REGMASK]; 6968 wdc_cp->data32iot = wdc_cp->cmd_iot = 6969 ps->regs[channel].cmd_iot; 6970 wdc_cp->data32ioh = wdc_cp->cmd_ioh = 6971 ps->regs[channel].cmd_iohs[0]; 6972 wdc_cp->_vtbl = &wdc_pdc203xx_vtbl; 6973 6974 /* 6975 * Subregion de busmaster registers. They're spread all over 6976 * the controller's register space :(. They are also 4 bytes 6977 * sized, with some specific extensions in the extra bits. 6978 * It also seems that the IDEDMA_CTL register isn't available. 6979 */ 6980 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh, 6981 0x260 + (channel << 7), 1, 6982 &ps->regs[channel].dma_iohs[IDEDMA_CMD(0)]) != 0) { 6983 printf("%s channel %d: can't subregion DMA " 6984 "registers\n", 6985 sc->sc_wdcdev.sc_dev.dv_xname, channel); 6986 continue; 6987 } 6988 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh, 6989 0x244 + (channel << 7), 4, 6990 &ps->regs[channel].dma_iohs[IDEDMA_TBL(0)]) != 0) { 6991 printf("%s channel %d: can't subregion DMA " 6992 "registers\n", 6993 sc->sc_wdcdev.sc_dev.dv_xname, channel); 6994 continue; 6995 } 6996 6997 wdcattach(wdc_cp); 6998 bus_space_write_4(sc->sc_dma_iot, 6999 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0, 7000 (bus_space_read_4(sc->sc_dma_iot, 7001 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 7002 0) & ~0x00003f9f) | (channel + 1)); 7003 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 7004 (channel + 1) << 2, 0x00000001); 7005 7006 pdc203xx_setup_channel(&cp->wdc_channel); 7007 7008 loop_end: ; 7009 } 7010 7011 printf("%s: using %s for native-PCI interrupt\n", 7012 sc->sc_wdcdev.sc_dev.dv_xname, 7013 intrstr ? intrstr : "unknown interrupt"); 7014 } 7015 7016 void 7017 pdc203xx_setup_channel(struct channel_softc *chp) 7018 { 7019 struct ata_drive_datas *drvp; 7020 struct pciide_channel *cp = (struct pciide_channel *)chp; 7021 int drive, s; 7022 7023 pciide_channel_dma_setup(cp); 7024 7025 for (drive = 0; drive < 2; drive++) { 7026 drvp = &chp->ch_drive[drive]; 7027 if ((drvp->drive_flags & DRIVE) == 0) 7028 continue; 7029 if (drvp->drive_flags & DRIVE_UDMA) { 7030 s = splbio(); 7031 drvp->drive_flags &= ~DRIVE_DMA; 7032 splx(s); 7033 } 7034 } 7035 pciide_print_modes(cp); 7036 } 7037 7038 int 7039 pdc203xx_pci_intr(void *arg) 7040 { 7041 struct pciide_softc *sc = arg; 7042 struct pciide_channel *cp; 7043 struct channel_softc *wdc_cp; 7044 struct pciide_pdcsata *ps = sc->sc_cookie; 7045 int i, rv, crv; 7046 u_int32_t scr; 7047 7048 rv = 0; 7049 scr = bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x00040); 7050 7051 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 7052 cp = &sc->pciide_channels[i]; 7053 wdc_cp = &cp->wdc_channel; 7054 if (scr & (1 << (i + 1))) { 7055 crv = wdcintr(wdc_cp); 7056 if (crv == 0) { 7057 printf("%s:%d: bogus intr (reg 0x%x)\n", 7058 sc->sc_wdcdev.sc_dev.dv_xname, 7059 i, scr); 7060 } else 7061 rv = 1; 7062 } 7063 } 7064 7065 return (rv); 7066 } 7067 7068 int 7069 pdc205xx_pci_intr(void *arg) 7070 { 7071 struct pciide_softc *sc = arg; 7072 struct pciide_channel *cp; 7073 struct channel_softc *wdc_cp; 7074 struct pciide_pdcsata *ps = sc->sc_cookie; 7075 int i, rv, crv; 7076 u_int32_t scr, status; 7077 7078 rv = 0; 7079 scr = bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x40); 7080 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x40, scr & 0x0000ffff); 7081 7082 status = bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x60); 7083 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x60, status & 0x000000ff); 7084 7085 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 7086 cp = &sc->pciide_channels[i]; 7087 wdc_cp = &cp->wdc_channel; 7088 if (scr & (1 << (i + 1))) { 7089 crv = wdcintr(wdc_cp); 7090 if (crv == 0) { 7091 printf("%s:%d: bogus intr (reg 0x%x)\n", 7092 sc->sc_wdcdev.sc_dev.dv_xname, 7093 i, scr); 7094 } else 7095 rv = 1; 7096 } 7097 } 7098 return rv; 7099 } 7100 7101 void 7102 pdc203xx_irqack(struct channel_softc *chp) 7103 { 7104 struct pciide_channel *cp = (struct pciide_channel *)chp; 7105 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7106 struct pciide_pdcsata *ps = sc->sc_cookie; 7107 int chan = chp->channel; 7108 7109 bus_space_write_4(sc->sc_dma_iot, 7110 ps->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0, 7111 (bus_space_read_4(sc->sc_dma_iot, 7112 ps->regs[chan].dma_iohs[IDEDMA_CMD(0)], 7113 0) & ~0x00003f9f) | (chan + 1)); 7114 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 7115 (chan + 1) << 2, 0x00000001); 7116 } 7117 7118 void 7119 pdc203xx_dma_start(void *v, int channel, int drive) 7120 { 7121 struct pciide_softc *sc = v; 7122 struct pciide_channel *cp = &sc->pciide_channels[channel]; 7123 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 7124 struct pciide_pdcsata *ps = sc->sc_cookie; 7125 7126 /* Write table address */ 7127 bus_space_write_4(sc->sc_dma_iot, 7128 ps->regs[channel].dma_iohs[IDEDMA_TBL(0)], 0, 7129 dma_maps->dmamap_table->dm_segs[0].ds_addr); 7130 7131 /* Start DMA engine */ 7132 bus_space_write_4(sc->sc_dma_iot, 7133 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0, 7134 (bus_space_read_4(sc->sc_dma_iot, 7135 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 7136 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 7137 } 7138 7139 int 7140 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 7141 { 7142 struct pciide_softc *sc = v; 7143 struct pciide_channel *cp = &sc->pciide_channels[channel]; 7144 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 7145 struct pciide_pdcsata *ps = sc->sc_cookie; 7146 7147 /* Stop DMA channel */ 7148 bus_space_write_4(sc->sc_dma_iot, 7149 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0, 7150 (bus_space_read_4(sc->sc_dma_iot, 7151 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 7152 0) & ~0x80)); 7153 7154 /* Unload the map of the data buffer */ 7155 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 7156 dma_maps->dmamap_xfer->dm_mapsize, 7157 (dma_maps->dma_flags & WDC_DMA_READ) ? 7158 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 7159 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 7160 7161 return (0); 7162 } 7163 7164 u_int8_t 7165 pdc203xx_read_reg(struct channel_softc *chp, enum wdc_regs reg) 7166 { 7167 struct pciide_channel *cp = (struct pciide_channel *)chp; 7168 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7169 struct pciide_pdcsata *ps = sc->sc_cookie; 7170 u_int8_t val; 7171 7172 if (reg & _WDC_AUX) { 7173 return (bus_space_read_1(ps->regs[chp->channel].ctl_iot, 7174 ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK)); 7175 } else { 7176 val = bus_space_read_1(ps->regs[chp->channel].cmd_iot, 7177 ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0); 7178 return (val); 7179 } 7180 } 7181 7182 void 7183 pdc203xx_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val) 7184 { 7185 struct pciide_channel *cp = (struct pciide_channel *)chp; 7186 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7187 struct pciide_pdcsata *ps = sc->sc_cookie; 7188 7189 if (reg & _WDC_AUX) 7190 bus_space_write_1(ps->regs[chp->channel].ctl_iot, 7191 ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val); 7192 else 7193 bus_space_write_1(ps->regs[chp->channel].cmd_iot, 7194 ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 7195 0, val); 7196 } 7197 7198 void 7199 pdc205xx_do_reset(struct channel_softc *chp) 7200 { 7201 struct pciide_channel *cp = (struct pciide_channel *)chp; 7202 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7203 struct pciide_pdcsata *ps = sc->sc_cookie; 7204 u_int32_t scontrol; 7205 7206 wdc_do_reset(chp); 7207 7208 /* reset SATA */ 7209 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 7210 SCONTROL_WRITE(ps, chp->channel, scontrol); 7211 delay(50*1000); 7212 7213 scontrol &= ~SControl_DET_INIT; 7214 SCONTROL_WRITE(ps, chp->channel, scontrol); 7215 delay(50*1000); 7216 } 7217 7218 void 7219 pdc205xx_drv_probe(struct channel_softc *chp) 7220 { 7221 struct pciide_channel *cp = (struct pciide_channel *)chp; 7222 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7223 struct pciide_pdcsata *ps = sc->sc_cookie; 7224 bus_space_handle_t *iohs; 7225 u_int32_t scontrol, sstatus; 7226 u_int16_t scnt, sn, cl, ch; 7227 int s; 7228 7229 SCONTROL_WRITE(ps, chp->channel, 0); 7230 delay(50*1000); 7231 7232 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 7233 SCONTROL_WRITE(ps,chp->channel,scontrol); 7234 delay(50*1000); 7235 7236 scontrol &= ~SControl_DET_INIT; 7237 SCONTROL_WRITE(ps,chp->channel,scontrol); 7238 delay(50*1000); 7239 7240 sstatus = SSTATUS_READ(ps,chp->channel); 7241 7242 switch (sstatus & SStatus_DET_mask) { 7243 case SStatus_DET_NODEV: 7244 /* No Device; be silent. */ 7245 break; 7246 7247 case SStatus_DET_DEV_NE: 7248 printf("%s: port %d: device connected, but " 7249 "communication not established\n", 7250 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 7251 break; 7252 7253 case SStatus_DET_OFFLINE: 7254 printf("%s: port %d: PHY offline\n", 7255 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 7256 break; 7257 7258 case SStatus_DET_DEV: 7259 iohs = ps->regs[chp->channel].cmd_iohs; 7260 bus_space_write_1(chp->cmd_iot, iohs[wdr_sdh], 0, 7261 WDSD_IBM); 7262 delay(10); /* 400ns delay */ 7263 scnt = bus_space_read_2(chp->cmd_iot, iohs[wdr_seccnt], 0); 7264 sn = bus_space_read_2(chp->cmd_iot, iohs[wdr_sector], 0); 7265 cl = bus_space_read_2(chp->cmd_iot, iohs[wdr_cyl_lo], 0); 7266 ch = bus_space_read_2(chp->cmd_iot, iohs[wdr_cyl_hi], 0); 7267 #if 0 7268 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 7269 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 7270 scnt, sn, cl, ch); 7271 #endif 7272 /* 7273 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 7274 * cases we get wrong values here, so ignore it. 7275 */ 7276 s = splbio(); 7277 if (cl == 0x14 && ch == 0xeb) 7278 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 7279 else 7280 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 7281 splx(s); 7282 #if 0 7283 printf("%s: port %d", 7284 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 7285 switch ((sstatus & SStatus_SPD_mask) >> SStatus_SPD_shift) { 7286 case 1: 7287 printf(": 1.5Gb/s"); 7288 break; 7289 case 2: 7290 printf(": 3.0Gb/s"); 7291 break; 7292 } 7293 printf("\n"); 7294 #endif 7295 break; 7296 7297 default: 7298 printf("%s: port %d: unknown SStatus: 0x%08x\n", 7299 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 7300 } 7301 } 7302 7303 void 7304 serverworks_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 7305 { 7306 struct pciide_channel *cp; 7307 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 7308 pcitag_t pcib_tag; 7309 int channel; 7310 bus_size_t cmdsize, ctlsize; 7311 7312 printf(": DMA"); 7313 pciide_mapreg_dma(sc, pa); 7314 printf("\n"); 7315 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 7316 WDC_CAPABILITY_MODE; 7317 7318 if (sc->sc_dma_ok) { 7319 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 7320 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 7321 sc->sc_wdcdev.irqack = pciide_irqack; 7322 } 7323 sc->sc_wdcdev.PIO_cap = 4; 7324 sc->sc_wdcdev.DMA_cap = 2; 7325 switch (sc->sc_pp->ide_product) { 7326 case PCI_PRODUCT_RCC_OSB4_IDE: 7327 sc->sc_wdcdev.UDMA_cap = 2; 7328 break; 7329 case PCI_PRODUCT_RCC_CSB5_IDE: 7330 if (sc->sc_rev < 0x92) 7331 sc->sc_wdcdev.UDMA_cap = 4; 7332 else 7333 sc->sc_wdcdev.UDMA_cap = 5; 7334 break; 7335 case PCI_PRODUCT_RCC_CSB6_IDE: 7336 sc->sc_wdcdev.UDMA_cap = 4; 7337 break; 7338 case PCI_PRODUCT_RCC_CSB6_RAID_IDE: 7339 case PCI_PRODUCT_RCC_HT_1000_IDE: 7340 sc->sc_wdcdev.UDMA_cap = 5; 7341 break; 7342 } 7343 7344 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 7345 sc->sc_wdcdev.channels = sc->wdc_chanarray; 7346 sc->sc_wdcdev.nchannels = 7347 (sc->sc_pp->ide_product == PCI_PRODUCT_RCC_CSB6_IDE ? 1 : 2); 7348 7349 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 7350 cp = &sc->pciide_channels[channel]; 7351 if (pciide_chansetup(sc, channel, interface) == 0) 7352 continue; 7353 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 7354 serverworks_pci_intr); 7355 if (cp->hw_ok == 0) 7356 return; 7357 pciide_map_compat_intr(pa, cp, channel, interface); 7358 if (cp->hw_ok == 0) 7359 return; 7360 serverworks_setup_channel(&cp->wdc_channel); 7361 } 7362 7363 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 7364 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 7365 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 7366 } 7367 7368 void 7369 serverworks_setup_channel(struct channel_softc *chp) 7370 { 7371 struct ata_drive_datas *drvp; 7372 struct pciide_channel *cp = (struct pciide_channel *)chp; 7373 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7374 int channel = chp->channel; 7375 int drive, unit; 7376 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 7377 u_int32_t idedma_ctl; 7378 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 7379 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 7380 7381 /* setup DMA if needed */ 7382 pciide_channel_dma_setup(cp); 7383 7384 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 7385 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 7386 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 7387 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 7388 7389 pio_time &= ~(0xffff << (16 * channel)); 7390 dma_time &= ~(0xffff << (16 * channel)); 7391 pio_mode &= ~(0xff << (8 * channel + 16)); 7392 udma_mode &= ~(0xff << (8 * channel + 16)); 7393 udma_mode &= ~(3 << (2 * channel)); 7394 7395 idedma_ctl = 0; 7396 7397 /* Per drive settings */ 7398 for (drive = 0; drive < 2; drive++) { 7399 drvp = &chp->ch_drive[drive]; 7400 /* If no drive, skip */ 7401 if ((drvp->drive_flags & DRIVE) == 0) 7402 continue; 7403 unit = drive + 2 * channel; 7404 /* add timing values, setup DMA if needed */ 7405 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 7406 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 7407 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 7408 (drvp->drive_flags & DRIVE_UDMA)) { 7409 /* use Ultra/DMA, check for 80-pin cable */ 7410 if (sc->sc_rev <= 0x92 && drvp->UDMA_mode > 2 && 7411 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 7412 PCI_SUBSYS_ID_REG)) & 7413 (1 << (14 + channel))) == 0) { 7414 WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire " 7415 "cable not detected\n", drvp->drive_name, 7416 sc->sc_wdcdev.sc_dev.dv_xname, 7417 channel, drive), DEBUG_PROBE); 7418 drvp->UDMA_mode = 2; 7419 } 7420 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 7421 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 7422 udma_mode |= 1 << unit; 7423 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 7424 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 7425 (drvp->drive_flags & DRIVE_DMA)) { 7426 /* use Multiword DMA */ 7427 drvp->drive_flags &= ~DRIVE_UDMA; 7428 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 7429 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 7430 } else { 7431 /* PIO only */ 7432 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 7433 } 7434 } 7435 7436 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 7437 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 7438 if (sc->sc_pp->ide_product != PCI_PRODUCT_RCC_OSB4_IDE) 7439 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 7440 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 7441 7442 if (idedma_ctl != 0) { 7443 /* Add software bits in status register */ 7444 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7445 IDEDMA_CTL(channel), idedma_ctl); 7446 } 7447 pciide_print_modes(cp); 7448 } 7449 7450 int 7451 serverworks_pci_intr(void *arg) 7452 { 7453 struct pciide_softc *sc = arg; 7454 struct pciide_channel *cp; 7455 struct channel_softc *wdc_cp; 7456 int rv = 0; 7457 int dmastat, i, crv; 7458 7459 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 7460 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7461 IDEDMA_CTL(i)); 7462 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 7463 IDEDMA_CTL_INTR) 7464 continue; 7465 cp = &sc->pciide_channels[i]; 7466 wdc_cp = &cp->wdc_channel; 7467 crv = wdcintr(wdc_cp); 7468 if (crv == 0) { 7469 printf("%s:%d: bogus intr\n", 7470 sc->sc_wdcdev.sc_dev.dv_xname, i); 7471 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7472 IDEDMA_CTL(i), dmastat); 7473 } else 7474 rv = 1; 7475 } 7476 return (rv); 7477 } 7478 7479 void 7480 svwsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 7481 { 7482 struct pciide_channel *cp; 7483 pci_intr_handle_t intrhandle; 7484 const char *intrstr; 7485 int channel; 7486 struct pciide_svwsata *ss; 7487 7488 /* Allocate memory for private data */ 7489 sc->sc_cookielen = sizeof(*ss); 7490 sc->sc_cookie = malloc(sc->sc_cookielen, M_DEVBUF, M_NOWAIT | M_ZERO); 7491 ss = sc->sc_cookie; 7492 7493 /* The 4-port version has a dummy second function. */ 7494 if (pci_conf_read(sc->sc_pc, sc->sc_tag, 7495 PCI_MAPREG_START + 0x14) == 0) { 7496 printf("\n"); 7497 return; 7498 } 7499 7500 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 7501 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 7502 &ss->ba5_st, &ss->ba5_sh, NULL, NULL, 0) != 0) { 7503 printf(": unable to map BA5 register space\n"); 7504 return; 7505 } 7506 7507 printf(": DMA"); 7508 svwsata_mapreg_dma(sc, pa); 7509 printf("\n"); 7510 7511 if (sc->sc_dma_ok) { 7512 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | 7513 WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 7514 sc->sc_wdcdev.irqack = pciide_irqack; 7515 } 7516 sc->sc_wdcdev.PIO_cap = 4; 7517 sc->sc_wdcdev.DMA_cap = 2; 7518 sc->sc_wdcdev.UDMA_cap = 6; 7519 7520 sc->sc_wdcdev.channels = sc->wdc_chanarray; 7521 sc->sc_wdcdev.nchannels = 4; 7522 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 7523 WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA; 7524 sc->sc_wdcdev.set_modes = sata_setup_channel; 7525 7526 /* We can use SControl and SStatus to probe for drives. */ 7527 sc->sc_wdcdev.drv_probe = svwsata_drv_probe; 7528 7529 /* Map and establish the interrupt handler. */ 7530 if(pci_intr_map(pa, &intrhandle) != 0) { 7531 printf("%s: couldn't map native-PCI interrupt\n", 7532 sc->sc_wdcdev.sc_dev.dv_xname); 7533 return; 7534 } 7535 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 7536 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 7537 pciide_pci_intr, sc, sc->sc_wdcdev.sc_dev.dv_xname); 7538 if (sc->sc_pci_ih != NULL) { 7539 printf("%s: using %s for native-PCI interrupt\n", 7540 sc->sc_wdcdev.sc_dev.dv_xname, 7541 intrstr ? intrstr : "unknown interrupt"); 7542 } else { 7543 printf("%s: couldn't establish native-PCI interrupt", 7544 sc->sc_wdcdev.sc_dev.dv_xname); 7545 if (intrstr != NULL) 7546 printf(" at %s", intrstr); 7547 printf("\n"); 7548 return; 7549 } 7550 7551 switch (sc->sc_pp->ide_product) { 7552 case PCI_PRODUCT_RCC_K2_SATA: 7553 bus_space_write_4(ss->ba5_st, ss->ba5_sh, SVWSATA_SICR1, 7554 bus_space_read_4(ss->ba5_st, ss->ba5_sh, SVWSATA_SICR1) 7555 & ~0x00040000); 7556 bus_space_write_4(ss->ba5_st, ss->ba5_sh, 7557 SVWSATA_SIM, 0); 7558 break; 7559 } 7560 7561 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 7562 cp = &sc->pciide_channels[channel]; 7563 if (pciide_chansetup(sc, channel, 0) == 0) 7564 continue; 7565 svwsata_mapchan(cp); 7566 sata_setup_channel(&cp->wdc_channel); 7567 } 7568 } 7569 7570 void 7571 svwsata_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 7572 { 7573 struct pciide_svwsata *ss = sc->sc_cookie; 7574 7575 sc->sc_wdcdev.dma_arg = sc; 7576 sc->sc_wdcdev.dma_init = pciide_dma_init; 7577 sc->sc_wdcdev.dma_start = pciide_dma_start; 7578 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 7579 7580 /* XXX */ 7581 sc->sc_dma_iot = ss->ba5_st; 7582 sc->sc_dma_ioh = ss->ba5_sh; 7583 7584 sc->sc_dmacmd_read = svwsata_dmacmd_read; 7585 sc->sc_dmacmd_write = svwsata_dmacmd_write; 7586 sc->sc_dmactl_read = svwsata_dmactl_read; 7587 sc->sc_dmactl_write = svwsata_dmactl_write; 7588 sc->sc_dmatbl_write = svwsata_dmatbl_write; 7589 7590 /* DMA registers all set up! */ 7591 sc->sc_dmat = pa->pa_dmat; 7592 sc->sc_dma_ok = 1; 7593 } 7594 7595 u_int8_t 7596 svwsata_dmacmd_read(struct pciide_softc *sc, int chan) 7597 { 7598 return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7599 (chan << 8) + SVWSATA_DMA + IDEDMA_CMD(0))); 7600 } 7601 7602 void 7603 svwsata_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val) 7604 { 7605 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7606 (chan << 8) + SVWSATA_DMA + IDEDMA_CMD(0), val); 7607 } 7608 7609 u_int8_t 7610 svwsata_dmactl_read(struct pciide_softc *sc, int chan) 7611 { 7612 return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7613 (chan << 8) + SVWSATA_DMA + IDEDMA_CTL(0))); 7614 } 7615 7616 void 7617 svwsata_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val) 7618 { 7619 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7620 (chan << 8) + SVWSATA_DMA + IDEDMA_CTL(0), val); 7621 } 7622 7623 void 7624 svwsata_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val) 7625 { 7626 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 7627 (chan << 8) + SVWSATA_DMA + IDEDMA_TBL(0), val); 7628 } 7629 7630 void 7631 svwsata_mapchan(struct pciide_channel *cp) 7632 { 7633 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7634 struct channel_softc *wdc_cp = &cp->wdc_channel; 7635 struct pciide_svwsata *ss = sc->sc_cookie; 7636 7637 cp->compat = 0; 7638 cp->ih = sc->sc_pci_ih; 7639 7640 if (bus_space_subregion(ss->ba5_st, ss->ba5_sh, 7641 (wdc_cp->channel << 8) + SVWSATA_TF0, 7642 SVWSATA_TF8 - SVWSATA_TF0, &wdc_cp->cmd_ioh) != 0) { 7643 printf("%s: couldn't map %s cmd regs\n", 7644 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 7645 return; 7646 } 7647 if (bus_space_subregion(ss->ba5_st, ss->ba5_sh, 7648 (wdc_cp->channel << 8) + SVWSATA_TF8, 4, 7649 &wdc_cp->ctl_ioh) != 0) { 7650 printf("%s: couldn't map %s ctl regs\n", 7651 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 7652 return; 7653 } 7654 wdc_cp->cmd_iot = wdc_cp->ctl_iot = ss->ba5_st; 7655 wdc_cp->_vtbl = &wdc_svwsata_vtbl; 7656 wdc_cp->ch_flags |= WDCF_DMA_BEFORE_CMD; 7657 wdcattach(wdc_cp); 7658 } 7659 7660 void 7661 svwsata_drv_probe(struct channel_softc *chp) 7662 { 7663 struct pciide_channel *cp = (struct pciide_channel *)chp; 7664 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7665 struct pciide_svwsata *ss = sc->sc_cookie; 7666 int channel = chp->channel; 7667 uint32_t scontrol, sstatus; 7668 uint8_t scnt, sn, cl, ch; 7669 int s; 7670 7671 /* 7672 * Request communication initialization sequence, any speed. 7673 * Performing this is the equivalent of an ATA Reset. 7674 */ 7675 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 7676 7677 /* 7678 * XXX We don't yet support SATA power management; disable all 7679 * power management state transitions. 7680 */ 7681 scontrol |= SControl_IPM_NONE; 7682 7683 bus_space_write_4(ss->ba5_st, ss->ba5_sh, 7684 (channel << 8) + SVWSATA_SCONTROL, scontrol); 7685 delay(50 * 1000); 7686 scontrol &= ~SControl_DET_INIT; 7687 bus_space_write_4(ss->ba5_st, ss->ba5_sh, 7688 (channel << 8) + SVWSATA_SCONTROL, scontrol); 7689 delay(100 * 1000); 7690 7691 sstatus = bus_space_read_4(ss->ba5_st, ss->ba5_sh, 7692 (channel << 8) + SVWSATA_SSTATUS); 7693 #if 0 7694 printf("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 7695 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus, 7696 bus_space_read_4(ss->ba5_st, ss->ba5_sh, 7697 (channel << 8) + SVWSATA_SSTATUS)); 7698 #endif 7699 switch (sstatus & SStatus_DET_mask) { 7700 case SStatus_DET_NODEV: 7701 /* No device; be silent. */ 7702 break; 7703 7704 case SStatus_DET_DEV_NE: 7705 printf("%s: port %d: device connected, but " 7706 "communication not established\n", 7707 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 7708 break; 7709 7710 case SStatus_DET_OFFLINE: 7711 printf("%s: port %d: PHY offline\n", 7712 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 7713 break; 7714 7715 case SStatus_DET_DEV: 7716 /* 7717 * XXX ATAPI detection doesn't currently work. Don't 7718 * XXX know why. But, it's not like the standard method 7719 * XXX can detect an ATAPI device connected via a SATA/PATA 7720 * XXX bridge, so at least this is no worse. --thorpej 7721 */ 7722 if (chp->_vtbl != NULL) 7723 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (0 << 4)); 7724 else 7725 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 7726 wdr_sdh & _WDC_REGMASK, WDSD_IBM | (0 << 4)); 7727 delay(10); /* 400ns delay */ 7728 /* Save register contents. */ 7729 if (chp->_vtbl != NULL) { 7730 scnt = CHP_READ_REG(chp, wdr_seccnt); 7731 sn = CHP_READ_REG(chp, wdr_sector); 7732 cl = CHP_READ_REG(chp, wdr_cyl_lo); 7733 ch = CHP_READ_REG(chp, wdr_cyl_hi); 7734 } else { 7735 scnt = bus_space_read_1(chp->cmd_iot, 7736 chp->cmd_ioh, wdr_seccnt & _WDC_REGMASK); 7737 sn = bus_space_read_1(chp->cmd_iot, 7738 chp->cmd_ioh, wdr_sector & _WDC_REGMASK); 7739 cl = bus_space_read_1(chp->cmd_iot, 7740 chp->cmd_ioh, wdr_cyl_lo & _WDC_REGMASK); 7741 ch = bus_space_read_1(chp->cmd_iot, 7742 chp->cmd_ioh, wdr_cyl_hi & _WDC_REGMASK); 7743 } 7744 #if 0 7745 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 7746 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 7747 scnt, sn, cl, ch); 7748 #endif 7749 /* 7750 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 7751 * cases we get wrong values here, so ignore it. 7752 */ 7753 s = splbio(); 7754 if (cl == 0x14 && ch == 0xeb) 7755 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 7756 else 7757 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 7758 splx(s); 7759 7760 printf("%s: port %d", 7761 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 7762 switch ((sstatus & SStatus_SPD_mask) >> SStatus_SPD_shift) { 7763 case 1: 7764 printf(": 1.5Gb/s"); 7765 break; 7766 case 2: 7767 printf(": 3.0Gb/s"); 7768 break; 7769 } 7770 printf("\n"); 7771 break; 7772 7773 default: 7774 printf("%s: port %d: unknown SStatus: 0x%08x\n", 7775 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 7776 } 7777 } 7778 7779 u_int8_t 7780 svwsata_read_reg(struct channel_softc *chp, enum wdc_regs reg) 7781 { 7782 if (reg & _WDC_AUX) { 7783 return (bus_space_read_4(chp->ctl_iot, chp->ctl_ioh, 7784 (reg & _WDC_REGMASK) << 2)); 7785 } else { 7786 return (bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 7787 (reg & _WDC_REGMASK) << 2)); 7788 } 7789 } 7790 7791 void 7792 svwsata_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val) 7793 { 7794 if (reg & _WDC_AUX) { 7795 bus_space_write_4(chp->ctl_iot, chp->ctl_ioh, 7796 (reg & _WDC_REGMASK) << 2, val); 7797 } else { 7798 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 7799 (reg & _WDC_REGMASK) << 2, val); 7800 } 7801 } 7802 7803 void 7804 svwsata_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int16_t val) 7805 { 7806 if (reg & _WDC_AUX) { 7807 bus_space_write_4(chp->ctl_iot, chp->ctl_ioh, 7808 (reg & _WDC_REGMASK) << 2, val); 7809 } else { 7810 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 7811 (reg & _WDC_REGMASK) << 2, val); 7812 } 7813 } 7814 7815 #define ACARD_IS_850(sc) \ 7816 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 7817 7818 void 7819 acard_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 7820 { 7821 struct pciide_channel *cp; 7822 int i; 7823 pcireg_t interface; 7824 bus_size_t cmdsize, ctlsize; 7825 7826 /* 7827 * when the chip is in native mode it identifies itself as a 7828 * 'misc mass storage'. Fake interface in this case. 7829 */ 7830 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 7831 interface = PCI_INTERFACE(pa->pa_class); 7832 } else { 7833 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 7834 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 7835 } 7836 7837 printf(": DMA"); 7838 pciide_mapreg_dma(sc, pa); 7839 printf("\n"); 7840 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 7841 WDC_CAPABILITY_MODE; 7842 7843 if (sc->sc_dma_ok) { 7844 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 7845 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 7846 sc->sc_wdcdev.irqack = pciide_irqack; 7847 } 7848 sc->sc_wdcdev.PIO_cap = 4; 7849 sc->sc_wdcdev.DMA_cap = 2; 7850 switch (sc->sc_pp->ide_product) { 7851 case PCI_PRODUCT_ACARD_ATP850U: 7852 sc->sc_wdcdev.UDMA_cap = 2; 7853 break; 7854 case PCI_PRODUCT_ACARD_ATP860: 7855 case PCI_PRODUCT_ACARD_ATP860A: 7856 sc->sc_wdcdev.UDMA_cap = 4; 7857 break; 7858 case PCI_PRODUCT_ACARD_ATP865A: 7859 case PCI_PRODUCT_ACARD_ATP865R: 7860 sc->sc_wdcdev.UDMA_cap = 6; 7861 break; 7862 } 7863 7864 sc->sc_wdcdev.set_modes = acard_setup_channel; 7865 sc->sc_wdcdev.channels = sc->wdc_chanarray; 7866 sc->sc_wdcdev.nchannels = 2; 7867 7868 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 7869 cp = &sc->pciide_channels[i]; 7870 if (pciide_chansetup(sc, i, interface) == 0) 7871 continue; 7872 if (interface & PCIIDE_INTERFACE_PCI(i)) { 7873 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 7874 &ctlsize, pciide_pci_intr); 7875 } else { 7876 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 7877 &cmdsize, &ctlsize); 7878 } 7879 if (cp->hw_ok == 0) 7880 return; 7881 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 7882 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 7883 wdcattach(&cp->wdc_channel); 7884 acard_setup_channel(&cp->wdc_channel); 7885 } 7886 if (!ACARD_IS_850(sc)) { 7887 u_int32_t reg; 7888 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 7889 reg &= ~ATP860_CTRL_INT; 7890 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 7891 } 7892 } 7893 7894 void 7895 acard_setup_channel(struct channel_softc *chp) 7896 { 7897 struct ata_drive_datas *drvp; 7898 struct pciide_channel *cp = (struct pciide_channel *)chp; 7899 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7900 int channel = chp->channel; 7901 int drive; 7902 u_int32_t idetime, udma_mode; 7903 u_int32_t idedma_ctl; 7904 7905 /* setup DMA if needed */ 7906 pciide_channel_dma_setup(cp); 7907 7908 if (ACARD_IS_850(sc)) { 7909 idetime = 0; 7910 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 7911 udma_mode &= ~ATP850_UDMA_MASK(channel); 7912 } else { 7913 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 7914 idetime &= ~ATP860_SETTIME_MASK(channel); 7915 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 7916 udma_mode &= ~ATP860_UDMA_MASK(channel); 7917 } 7918 7919 idedma_ctl = 0; 7920 7921 /* Per drive settings */ 7922 for (drive = 0; drive < 2; drive++) { 7923 drvp = &chp->ch_drive[drive]; 7924 /* If no drive, skip */ 7925 if ((drvp->drive_flags & DRIVE) == 0) 7926 continue; 7927 /* add timing values, setup DMA if needed */ 7928 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 7929 (drvp->drive_flags & DRIVE_UDMA)) { 7930 /* use Ultra/DMA */ 7931 if (ACARD_IS_850(sc)) { 7932 idetime |= ATP850_SETTIME(drive, 7933 acard_act_udma[drvp->UDMA_mode], 7934 acard_rec_udma[drvp->UDMA_mode]); 7935 udma_mode |= ATP850_UDMA_MODE(channel, drive, 7936 acard_udma_conf[drvp->UDMA_mode]); 7937 } else { 7938 idetime |= ATP860_SETTIME(channel, drive, 7939 acard_act_udma[drvp->UDMA_mode], 7940 acard_rec_udma[drvp->UDMA_mode]); 7941 udma_mode |= ATP860_UDMA_MODE(channel, drive, 7942 acard_udma_conf[drvp->UDMA_mode]); 7943 } 7944 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 7945 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 7946 (drvp->drive_flags & DRIVE_DMA)) { 7947 /* use Multiword DMA */ 7948 drvp->drive_flags &= ~DRIVE_UDMA; 7949 if (ACARD_IS_850(sc)) { 7950 idetime |= ATP850_SETTIME(drive, 7951 acard_act_dma[drvp->DMA_mode], 7952 acard_rec_dma[drvp->DMA_mode]); 7953 } else { 7954 idetime |= ATP860_SETTIME(channel, drive, 7955 acard_act_dma[drvp->DMA_mode], 7956 acard_rec_dma[drvp->DMA_mode]); 7957 } 7958 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 7959 } else { 7960 /* PIO only */ 7961 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 7962 if (ACARD_IS_850(sc)) { 7963 idetime |= ATP850_SETTIME(drive, 7964 acard_act_pio[drvp->PIO_mode], 7965 acard_rec_pio[drvp->PIO_mode]); 7966 } else { 7967 idetime |= ATP860_SETTIME(channel, drive, 7968 acard_act_pio[drvp->PIO_mode], 7969 acard_rec_pio[drvp->PIO_mode]); 7970 } 7971 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 7972 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) | 7973 ATP8x0_CTRL_EN(channel)); 7974 } 7975 } 7976 7977 if (idedma_ctl != 0) { 7978 /* Add software bits in status register */ 7979 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7980 IDEDMA_CTL(channel), idedma_ctl); 7981 } 7982 pciide_print_modes(cp); 7983 7984 if (ACARD_IS_850(sc)) { 7985 pci_conf_write(sc->sc_pc, sc->sc_tag, 7986 ATP850_IDETIME(channel), idetime); 7987 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 7988 } else { 7989 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 7990 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 7991 } 7992 } 7993 7994 void 7995 nforce_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 7996 { 7997 struct pciide_channel *cp; 7998 int channel; 7999 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 8000 bus_size_t cmdsize, ctlsize; 8001 u_int32_t conf; 8002 8003 conf = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_CONF); 8004 WDCDEBUG_PRINT(("%s: conf register 0x%x\n", 8005 sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE); 8006 8007 printf(": DMA"); 8008 pciide_mapreg_dma(sc, pa); 8009 8010 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8011 WDC_CAPABILITY_MODE; 8012 if (sc->sc_dma_ok) { 8013 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8014 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8015 sc->sc_wdcdev.irqack = pciide_irqack; 8016 } 8017 sc->sc_wdcdev.PIO_cap = 4; 8018 sc->sc_wdcdev.DMA_cap = 2; 8019 switch (sc->sc_pp->ide_product) { 8020 case PCI_PRODUCT_NVIDIA_NFORCE_IDE: 8021 sc->sc_wdcdev.UDMA_cap = 5; 8022 break; 8023 default: 8024 sc->sc_wdcdev.UDMA_cap = 6; 8025 } 8026 sc->sc_wdcdev.set_modes = nforce_setup_channel; 8027 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8028 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 8029 8030 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 8031 8032 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8033 cp = &sc->pciide_channels[channel]; 8034 8035 if (pciide_chansetup(sc, channel, interface) == 0) 8036 continue; 8037 8038 if ((conf & NFORCE_CHAN_EN(channel)) == 0) { 8039 printf("%s: %s ignored (disabled)\n", 8040 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 8041 cp->hw_ok = 0; 8042 continue; 8043 } 8044 8045 pciide_map_compat_intr(pa, cp, channel, interface); 8046 if (cp->hw_ok == 0) 8047 continue; 8048 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8049 nforce_pci_intr); 8050 if (cp->hw_ok == 0) { 8051 pciide_unmap_compat_intr(pa, cp, channel, interface); 8052 continue; 8053 } 8054 8055 if (pciide_chan_candisable(cp)) { 8056 conf &= ~NFORCE_CHAN_EN(channel); 8057 pciide_unmap_compat_intr(pa, cp, channel, interface); 8058 continue; 8059 } 8060 8061 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 8062 } 8063 WDCDEBUG_PRINT(("%s: new conf register 0x%x\n", 8064 sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE); 8065 pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_CONF, conf); 8066 } 8067 8068 void 8069 nforce_setup_channel(struct channel_softc *chp) 8070 { 8071 struct ata_drive_datas *drvp; 8072 int drive, mode; 8073 u_int32_t idedma_ctl; 8074 struct pciide_channel *cp = (struct pciide_channel *)chp; 8075 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 8076 int channel = chp->channel; 8077 u_int32_t conf, piodmatim, piotim, udmatim; 8078 8079 conf = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_CONF); 8080 piodmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_PIODMATIM); 8081 piotim = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_PIOTIM); 8082 udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_UDMATIM); 8083 WDCDEBUG_PRINT(("%s: %s old timing values: piodmatim=0x%x, " 8084 "piotim=0x%x, udmatim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, 8085 cp->name, piodmatim, piotim, udmatim), DEBUG_PROBE); 8086 8087 /* Setup DMA if needed */ 8088 pciide_channel_dma_setup(cp); 8089 8090 /* Clear all bits for this channel */ 8091 idedma_ctl = 0; 8092 piodmatim &= ~NFORCE_PIODMATIM_MASK(channel); 8093 udmatim &= ~NFORCE_UDMATIM_MASK(channel); 8094 8095 /* Per channel settings */ 8096 for (drive = 0; drive < 2; drive++) { 8097 drvp = &chp->ch_drive[drive]; 8098 8099 /* If no drive, skip */ 8100 if ((drvp->drive_flags & DRIVE) == 0) 8101 continue; 8102 8103 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 8104 (drvp->drive_flags & DRIVE_UDMA) != 0) { 8105 /* Setup UltraDMA mode */ 8106 drvp->drive_flags &= ~DRIVE_DMA; 8107 8108 udmatim |= NFORCE_UDMATIM_SET(channel, drive, 8109 nforce_udma[drvp->UDMA_mode]) | 8110 NFORCE_UDMA_EN(channel, drive) | 8111 NFORCE_UDMA_ENM(channel, drive); 8112 8113 mode = drvp->PIO_mode; 8114 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 8115 (drvp->drive_flags & DRIVE_DMA) != 0) { 8116 /* Setup multiword DMA mode */ 8117 drvp->drive_flags &= ~DRIVE_UDMA; 8118 8119 /* mode = min(pio, dma + 2) */ 8120 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 8121 mode = drvp->PIO_mode; 8122 else 8123 mode = drvp->DMA_mode + 2; 8124 } else { 8125 mode = drvp->PIO_mode; 8126 goto pio; 8127 } 8128 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 8129 8130 pio: 8131 /* Setup PIO mode */ 8132 if (mode <= 2) { 8133 drvp->DMA_mode = 0; 8134 drvp->PIO_mode = 0; 8135 mode = 0; 8136 } else { 8137 drvp->PIO_mode = mode; 8138 drvp->DMA_mode = mode - 2; 8139 } 8140 piodmatim |= NFORCE_PIODMATIM_SET(channel, drive, 8141 nforce_pio[mode]); 8142 } 8143 8144 if (idedma_ctl != 0) { 8145 /* Add software bits in status register */ 8146 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 8147 IDEDMA_CTL(channel), idedma_ctl); 8148 } 8149 8150 WDCDEBUG_PRINT(("%s: %s new timing values: piodmatim=0x%x, " 8151 "piotim=0x%x, udmatim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, 8152 cp->name, piodmatim, piotim, udmatim), DEBUG_PROBE); 8153 pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_PIODMATIM, piodmatim); 8154 pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_UDMATIM, udmatim); 8155 8156 pciide_print_modes(cp); 8157 } 8158 8159 int 8160 nforce_pci_intr(void *arg) 8161 { 8162 struct pciide_softc *sc = arg; 8163 struct pciide_channel *cp; 8164 struct channel_softc *wdc_cp; 8165 int i, rv, crv; 8166 u_int32_t dmastat; 8167 8168 rv = 0; 8169 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 8170 cp = &sc->pciide_channels[i]; 8171 wdc_cp = &cp->wdc_channel; 8172 8173 /* Skip compat channel */ 8174 if (cp->compat) 8175 continue; 8176 8177 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 8178 IDEDMA_CTL(i)); 8179 if ((dmastat & IDEDMA_CTL_INTR) == 0) 8180 continue; 8181 8182 crv = wdcintr(wdc_cp); 8183 if (crv == 0) 8184 printf("%s:%d: bogus intr\n", 8185 sc->sc_wdcdev.sc_dev.dv_xname, i); 8186 else 8187 rv = 1; 8188 } 8189 return (rv); 8190 } 8191 8192 void 8193 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 8194 { 8195 struct pciide_channel *cp; 8196 bus_size_t cmdsize, ctlsize; 8197 pcireg_t interface; 8198 int channel; 8199 8200 printf(": DMA"); 8201 #ifdef PCIIDE_I31244_DISABLEDMA 8202 if (sc->sc_rev == 0) { 8203 printf(" disabled due to rev. 0"); 8204 sc->sc_dma_ok = 0; 8205 } else 8206 #endif 8207 pciide_mapreg_dma(sc, pa); 8208 printf("\n"); 8209 8210 /* 8211 * XXX Configure LEDs to show activity. 8212 */ 8213 8214 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8215 WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA; 8216 sc->sc_wdcdev.PIO_cap = 4; 8217 if (sc->sc_dma_ok) { 8218 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8219 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8220 sc->sc_wdcdev.irqack = pciide_irqack; 8221 sc->sc_wdcdev.DMA_cap = 2; 8222 sc->sc_wdcdev.UDMA_cap = 6; 8223 } 8224 sc->sc_wdcdev.set_modes = sata_setup_channel; 8225 8226 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8227 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 8228 8229 interface = PCI_INTERFACE(pa->pa_class); 8230 8231 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8232 cp = &sc->pciide_channels[channel]; 8233 if (pciide_chansetup(sc, channel, interface) == 0) 8234 continue; 8235 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8236 pciide_pci_intr); 8237 if (cp->hw_ok == 0) 8238 continue; 8239 pciide_map_compat_intr(pa, cp, channel, interface); 8240 sata_setup_channel(&cp->wdc_channel); 8241 } 8242 } 8243 8244 void 8245 ite_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 8246 { 8247 struct pciide_channel *cp; 8248 int channel; 8249 pcireg_t interface; 8250 bus_size_t cmdsize, ctlsize; 8251 pcireg_t cfg, modectl; 8252 8253 /* 8254 * Fake interface since IT8212F is claimed to be a ``RAID'' device. 8255 */ 8256 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 8257 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 8258 8259 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG); 8260 modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE); 8261 WDCDEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n", 8262 sc->sc_wdcdev.sc_dev.dv_xname, cfg & IT_CFG_MASK, 8263 modectl & IT_MODE_MASK), DEBUG_PROBE); 8264 8265 printf(": DMA"); 8266 pciide_mapreg_dma(sc, pa); 8267 8268 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8269 WDC_CAPABILITY_MODE; 8270 if (sc->sc_dma_ok) { 8271 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8272 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8273 sc->sc_wdcdev.irqack = pciide_irqack; 8274 } 8275 sc->sc_wdcdev.PIO_cap = 4; 8276 sc->sc_wdcdev.DMA_cap = 2; 8277 sc->sc_wdcdev.UDMA_cap = 6; 8278 8279 sc->sc_wdcdev.set_modes = ite_setup_channel; 8280 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8281 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 8282 8283 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 8284 8285 /* Disable RAID */ 8286 modectl &= ~IT_MODE_RAID1; 8287 /* Disable CPU firmware mode */ 8288 modectl &= ~IT_MODE_CPU; 8289 8290 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_MODE, modectl); 8291 8292 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8293 cp = &sc->pciide_channels[channel]; 8294 8295 if (pciide_chansetup(sc, channel, interface) == 0) 8296 continue; 8297 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8298 pciide_pci_intr); 8299 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 8300 } 8301 8302 /* Re-read configuration registers after channels setup */ 8303 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG); 8304 modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE); 8305 WDCDEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n", 8306 sc->sc_wdcdev.sc_dev.dv_xname, cfg & IT_CFG_MASK, 8307 modectl & IT_MODE_MASK), DEBUG_PROBE); 8308 } 8309 8310 void 8311 ite_setup_channel(struct channel_softc *chp) 8312 { 8313 struct ata_drive_datas *drvp; 8314 int drive, mode; 8315 u_int32_t idedma_ctl; 8316 struct pciide_channel *cp = (struct pciide_channel *)chp; 8317 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 8318 int channel = chp->channel; 8319 pcireg_t cfg, modectl; 8320 pcireg_t tim; 8321 8322 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG); 8323 modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE); 8324 tim = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_TIM(channel)); 8325 WDCDEBUG_PRINT(("%s:%d: tim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, 8326 channel, tim), DEBUG_PROBE); 8327 8328 /* Setup DMA if needed */ 8329 pciide_channel_dma_setup(cp); 8330 8331 /* Clear all bits for this channel */ 8332 idedma_ctl = 0; 8333 8334 /* Per channel settings */ 8335 for (drive = 0; drive < 2; drive++) { 8336 drvp = &chp->ch_drive[drive]; 8337 8338 /* If no drive, skip */ 8339 if ((drvp->drive_flags & DRIVE) == 0) 8340 continue; 8341 8342 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 8343 (drvp->drive_flags & DRIVE_UDMA) != 0) { 8344 /* Setup UltraDMA mode */ 8345 drvp->drive_flags &= ~DRIVE_DMA; 8346 modectl &= ~IT_MODE_DMA(channel, drive); 8347 8348 #if 0 8349 /* Check cable, works only in CPU firmware mode */ 8350 if (drvp->UDMA_mode > 2 && 8351 (cfg & IT_CFG_CABLE(channel, drive)) == 0) { 8352 WDCDEBUG_PRINT(("%s(%s:%d:%d): " 8353 "80-wire cable not detected\n", 8354 drvp->drive_name, 8355 sc->sc_wdcdev.sc_dev.dv_xname, 8356 channel, drive), DEBUG_PROBE); 8357 drvp->UDMA_mode = 2; 8358 } 8359 #endif 8360 8361 if (drvp->UDMA_mode >= 5) 8362 tim |= IT_TIM_UDMA5(drive); 8363 else 8364 tim &= ~IT_TIM_UDMA5(drive); 8365 8366 mode = drvp->PIO_mode; 8367 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 8368 (drvp->drive_flags & DRIVE_DMA) != 0) { 8369 /* Setup multiword DMA mode */ 8370 drvp->drive_flags &= ~DRIVE_UDMA; 8371 modectl |= IT_MODE_DMA(channel, drive); 8372 8373 /* mode = min(pio, dma + 2) */ 8374 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 8375 mode = drvp->PIO_mode; 8376 else 8377 mode = drvp->DMA_mode + 2; 8378 } else { 8379 mode = drvp->PIO_mode; 8380 goto pio; 8381 } 8382 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 8383 8384 pio: 8385 /* Setup PIO mode */ 8386 if (mode <= 2) { 8387 drvp->DMA_mode = 0; 8388 drvp->PIO_mode = 0; 8389 mode = 0; 8390 } else { 8391 drvp->PIO_mode = mode; 8392 drvp->DMA_mode = mode - 2; 8393 } 8394 8395 /* Enable IORDY if PIO mode >= 3 */ 8396 if (drvp->PIO_mode >= 3) 8397 cfg |= IT_CFG_IORDY(channel); 8398 } 8399 8400 WDCDEBUG_PRINT(("%s: tim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, 8401 tim), DEBUG_PROBE); 8402 8403 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_CFG, cfg); 8404 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_MODE, modectl); 8405 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_TIM(channel), tim); 8406 8407 if (idedma_ctl != 0) { 8408 /* Add software bits in status register */ 8409 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 8410 IDEDMA_CTL(channel), idedma_ctl); 8411 } 8412 8413 pciide_print_modes(cp); 8414 } 8415 8416 void 8417 ixp_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 8418 { 8419 struct pciide_channel *cp; 8420 int channel; 8421 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 8422 bus_size_t cmdsize, ctlsize; 8423 8424 printf(": DMA"); 8425 pciide_mapreg_dma(sc, pa); 8426 8427 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8428 WDC_CAPABILITY_MODE; 8429 if (sc->sc_dma_ok) { 8430 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8431 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8432 sc->sc_wdcdev.irqack = pciide_irqack; 8433 } 8434 sc->sc_wdcdev.PIO_cap = 4; 8435 sc->sc_wdcdev.DMA_cap = 2; 8436 sc->sc_wdcdev.UDMA_cap = 6; 8437 8438 sc->sc_wdcdev.set_modes = ixp_setup_channel; 8439 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8440 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 8441 8442 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 8443 8444 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8445 cp = &sc->pciide_channels[channel]; 8446 if (pciide_chansetup(sc, channel, interface) == 0) 8447 continue; 8448 pciide_map_compat_intr(pa, cp, channel, interface); 8449 if (cp->hw_ok == 0) 8450 continue; 8451 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8452 pciide_pci_intr); 8453 if (cp->hw_ok == 0) { 8454 pciide_unmap_compat_intr(pa, cp, channel, interface); 8455 continue; 8456 } 8457 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 8458 } 8459 } 8460 8461 void 8462 ixp_setup_channel(struct channel_softc *chp) 8463 { 8464 struct ata_drive_datas *drvp; 8465 int drive, mode; 8466 u_int32_t idedma_ctl; 8467 struct pciide_channel *cp = (struct pciide_channel*)chp; 8468 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 8469 int channel = chp->channel; 8470 pcireg_t udma, mdma_timing, pio, pio_timing; 8471 8472 pio_timing = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_PIO_TIMING); 8473 pio = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_PIO_CTL); 8474 mdma_timing = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_MDMA_TIMING); 8475 udma = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_UDMA_CTL); 8476 8477 /* Setup DMA if needed */ 8478 pciide_channel_dma_setup(cp); 8479 8480 idedma_ctl = 0; 8481 8482 /* Per channel settings */ 8483 for (drive = 0; drive < 2; drive++) { 8484 drvp = &chp->ch_drive[drive]; 8485 8486 /* If no drive, skip */ 8487 if ((drvp->drive_flags & DRIVE) == 0) 8488 continue; 8489 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 8490 (drvp->drive_flags & DRIVE_UDMA) != 0) { 8491 /* Setup UltraDMA mode */ 8492 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 8493 IXP_UDMA_ENABLE(udma, chp->channel, drive); 8494 IXP_SET_MODE(udma, chp->channel, drive, 8495 drvp->UDMA_mode); 8496 mode = drvp->PIO_mode; 8497 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 8498 (drvp->drive_flags & DRIVE_DMA) != 0) { 8499 /* Setup multiword DMA mode */ 8500 drvp->drive_flags &= ~DRIVE_UDMA; 8501 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 8502 IXP_UDMA_DISABLE(udma, chp->channel, drive); 8503 IXP_SET_TIMING(mdma_timing, chp->channel, drive, 8504 ixp_mdma_timings[drvp->DMA_mode]); 8505 8506 /* mode = min(pio, dma + 2) */ 8507 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 8508 mode = drvp->PIO_mode; 8509 else 8510 mode = drvp->DMA_mode + 2; 8511 } else { 8512 mode = drvp->PIO_mode; 8513 } 8514 8515 /* Setup PIO mode */ 8516 drvp->PIO_mode = mode; 8517 if (mode < 2) 8518 drvp->DMA_mode = 0; 8519 else 8520 drvp->DMA_mode = mode - 2; 8521 /* 8522 * Set PIO mode and timings 8523 * Linux driver avoids PIO mode 1, let's do it too. 8524 */ 8525 if (drvp->PIO_mode == 1) 8526 drvp->PIO_mode = 0; 8527 8528 IXP_SET_MODE(pio, chp->channel, drive, drvp->PIO_mode); 8529 IXP_SET_TIMING(pio_timing, chp->channel, drive, 8530 ixp_pio_timings[drvp->PIO_mode]); 8531 } 8532 8533 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_UDMA_CTL, udma); 8534 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_MDMA_TIMING, mdma_timing); 8535 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_PIO_CTL, pio); 8536 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_PIO_TIMING, pio_timing); 8537 8538 if (idedma_ctl != 0) { 8539 /* Add software bits in status register */ 8540 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 8541 IDEDMA_CTL(channel), idedma_ctl); 8542 } 8543 8544 pciide_print_modes(cp); 8545 } 8546 8547 void 8548 jmicron_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 8549 { 8550 struct pciide_channel *cp; 8551 int channel; 8552 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 8553 bus_size_t cmdsize, ctlsize; 8554 u_int32_t conf; 8555 8556 conf = pci_conf_read(sc->sc_pc, sc->sc_tag, JMICRON_CONF); 8557 WDCDEBUG_PRINT(("%s: conf register 0x%x\n", 8558 sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE); 8559 8560 printf(": DMA"); 8561 pciide_mapreg_dma(sc, pa); 8562 8563 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8564 WDC_CAPABILITY_MODE; 8565 if (sc->sc_dma_ok) { 8566 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8567 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8568 sc->sc_wdcdev.irqack = pciide_irqack; 8569 } 8570 sc->sc_wdcdev.PIO_cap = 4; 8571 sc->sc_wdcdev.DMA_cap = 2; 8572 sc->sc_wdcdev.UDMA_cap = 6; 8573 sc->sc_wdcdev.set_modes = jmicron_setup_channel; 8574 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8575 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 8576 8577 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 8578 8579 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8580 cp = &sc->pciide_channels[channel]; 8581 8582 if (pciide_chansetup(sc, channel, interface) == 0) 8583 continue; 8584 8585 #if 0 8586 if ((conf & JMICRON_CHAN_EN(channel)) == 0) { 8587 printf("%s: %s ignored (disabled)\n", 8588 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 8589 cp->hw_ok = 0; 8590 continue; 8591 } 8592 #endif 8593 8594 pciide_map_compat_intr(pa, cp, channel, interface); 8595 if (cp->hw_ok == 0) 8596 continue; 8597 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8598 pciide_pci_intr); 8599 if (cp->hw_ok == 0) { 8600 pciide_unmap_compat_intr(pa, cp, channel, interface); 8601 continue; 8602 } 8603 8604 if (pciide_chan_candisable(cp)) { 8605 conf &= ~JMICRON_CHAN_EN(channel); 8606 pciide_unmap_compat_intr(pa, cp, channel, interface); 8607 continue; 8608 } 8609 8610 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 8611 } 8612 WDCDEBUG_PRINT(("%s: new conf register 0x%x\n", 8613 sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE); 8614 pci_conf_write(sc->sc_pc, sc->sc_tag, JMICRON_CONF, conf); 8615 } 8616 8617 void 8618 jmicron_setup_channel(struct channel_softc *chp) 8619 { 8620 struct ata_drive_datas *drvp; 8621 int drive, mode; 8622 u_int32_t idedma_ctl; 8623 struct pciide_channel *cp = (struct pciide_channel *)chp; 8624 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 8625 int channel = chp->channel; 8626 u_int32_t conf; 8627 8628 conf = pci_conf_read(sc->sc_pc, sc->sc_tag, JMICRON_CONF); 8629 8630 /* Setup DMA if needed */ 8631 pciide_channel_dma_setup(cp); 8632 8633 /* Clear all bits for this channel */ 8634 idedma_ctl = 0; 8635 8636 /* Per channel settings */ 8637 for (drive = 0; drive < 2; drive++) { 8638 drvp = &chp->ch_drive[drive]; 8639 8640 /* If no drive, skip */ 8641 if ((drvp->drive_flags & DRIVE) == 0) 8642 continue; 8643 8644 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 8645 (drvp->drive_flags & DRIVE_UDMA) != 0) { 8646 /* Setup UltraDMA mode */ 8647 drvp->drive_flags &= ~DRIVE_DMA; 8648 8649 /* see if cable is up to scratch */ 8650 if ((conf & JMICRON_CONF_40PIN) && 8651 (drvp->UDMA_mode > 2)) 8652 drvp->UDMA_mode = 2; 8653 8654 mode = drvp->PIO_mode; 8655 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 8656 (drvp->drive_flags & DRIVE_DMA) != 0) { 8657 /* Setup multiword DMA mode */ 8658 drvp->drive_flags &= ~DRIVE_UDMA; 8659 8660 /* mode = min(pio, dma + 2) */ 8661 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 8662 mode = drvp->PIO_mode; 8663 else 8664 mode = drvp->DMA_mode + 2; 8665 } else { 8666 mode = drvp->PIO_mode; 8667 goto pio; 8668 } 8669 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 8670 8671 pio: 8672 /* Setup PIO mode */ 8673 if (mode <= 2) { 8674 drvp->DMA_mode = 0; 8675 drvp->PIO_mode = 0; 8676 } else { 8677 drvp->PIO_mode = mode; 8678 drvp->DMA_mode = mode - 2; 8679 } 8680 } 8681 8682 if (idedma_ctl != 0) { 8683 /* Add software bits in status register */ 8684 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 8685 IDEDMA_CTL(channel), idedma_ctl); 8686 } 8687 8688 pciide_print_modes(cp); 8689 } 8690 8691 void 8692 phison_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 8693 { 8694 struct pciide_channel *cp; 8695 int channel; 8696 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 8697 bus_size_t cmdsize, ctlsize; 8698 8699 sc->chip_unmap = default_chip_unmap; 8700 8701 printf(": DMA"); 8702 pciide_mapreg_dma(sc, pa); 8703 8704 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8705 WDC_CAPABILITY_MODE; 8706 if (sc->sc_dma_ok) { 8707 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8708 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8709 sc->sc_wdcdev.irqack = pciide_irqack; 8710 } 8711 sc->sc_wdcdev.PIO_cap = 4; 8712 sc->sc_wdcdev.DMA_cap = 2; 8713 sc->sc_wdcdev.UDMA_cap = 5; 8714 sc->sc_wdcdev.set_modes = phison_setup_channel; 8715 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8716 sc->sc_wdcdev.nchannels = 1; 8717 8718 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 8719 8720 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8721 cp = &sc->pciide_channels[channel]; 8722 8723 if (pciide_chansetup(sc, channel, interface) == 0) 8724 continue; 8725 8726 pciide_map_compat_intr(pa, cp, channel, interface); 8727 if (cp->hw_ok == 0) 8728 continue; 8729 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8730 pciide_pci_intr); 8731 if (cp->hw_ok == 0) { 8732 pciide_unmap_compat_intr(pa, cp, channel, interface); 8733 continue; 8734 } 8735 8736 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 8737 } 8738 } 8739 8740 void 8741 phison_setup_channel(struct channel_softc *chp) 8742 { 8743 struct ata_drive_datas *drvp; 8744 int drive, mode; 8745 u_int32_t idedma_ctl; 8746 struct pciide_channel *cp = (struct pciide_channel *)chp; 8747 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 8748 int channel = chp->channel; 8749 8750 /* Setup DMA if needed */ 8751 pciide_channel_dma_setup(cp); 8752 8753 /* Clear all bits for this channel */ 8754 idedma_ctl = 0; 8755 8756 /* Per channel settings */ 8757 for (drive = 0; drive < 2; drive++) { 8758 drvp = &chp->ch_drive[drive]; 8759 8760 /* If no drive, skip */ 8761 if ((drvp->drive_flags & DRIVE) == 0) 8762 continue; 8763 8764 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 8765 (drvp->drive_flags & DRIVE_UDMA) != 0) { 8766 /* Setup UltraDMA mode */ 8767 drvp->drive_flags &= ~DRIVE_DMA; 8768 mode = drvp->PIO_mode; 8769 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 8770 (drvp->drive_flags & DRIVE_DMA) != 0) { 8771 /* Setup multiword DMA mode */ 8772 drvp->drive_flags &= ~DRIVE_UDMA; 8773 8774 /* mode = min(pio, dma + 2) */ 8775 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 8776 mode = drvp->PIO_mode; 8777 else 8778 mode = drvp->DMA_mode + 2; 8779 } else { 8780 mode = drvp->PIO_mode; 8781 goto pio; 8782 } 8783 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 8784 8785 pio: 8786 /* Setup PIO mode */ 8787 if (mode <= 2) { 8788 drvp->DMA_mode = 0; 8789 drvp->PIO_mode = 0; 8790 } else { 8791 drvp->PIO_mode = mode; 8792 drvp->DMA_mode = mode - 2; 8793 } 8794 } 8795 8796 if (idedma_ctl != 0) { 8797 /* Add software bits in status register */ 8798 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 8799 IDEDMA_CTL(channel), idedma_ctl); 8800 } 8801 8802 pciide_print_modes(cp); 8803 } 8804 8805 void 8806 sch_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 8807 { 8808 struct pciide_channel *cp; 8809 int channel; 8810 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 8811 bus_size_t cmdsize, ctlsize; 8812 8813 printf(": DMA"); 8814 pciide_mapreg_dma(sc, pa); 8815 8816 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8817 WDC_CAPABILITY_MODE; 8818 if (sc->sc_dma_ok) { 8819 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8820 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8821 sc->sc_wdcdev.irqack = pciide_irqack; 8822 } 8823 sc->sc_wdcdev.PIO_cap = 4; 8824 sc->sc_wdcdev.DMA_cap = 2; 8825 sc->sc_wdcdev.UDMA_cap = 5; 8826 sc->sc_wdcdev.set_modes = sch_setup_channel; 8827 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8828 sc->sc_wdcdev.nchannels = 1; 8829 8830 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 8831 8832 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8833 cp = &sc->pciide_channels[channel]; 8834 8835 if (pciide_chansetup(sc, channel, interface) == 0) 8836 continue; 8837 8838 pciide_map_compat_intr(pa, cp, channel, interface); 8839 if (cp->hw_ok == 0) 8840 continue; 8841 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8842 pciide_pci_intr); 8843 if (cp->hw_ok == 0) { 8844 pciide_unmap_compat_intr(pa, cp, channel, interface); 8845 continue; 8846 } 8847 8848 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 8849 } 8850 } 8851 8852 void 8853 sch_setup_channel(struct channel_softc *chp) 8854 { 8855 struct ata_drive_datas *drvp; 8856 int drive, mode; 8857 u_int32_t tim, timaddr; 8858 struct pciide_channel *cp = (struct pciide_channel *)chp; 8859 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 8860 8861 /* Setup DMA if needed */ 8862 pciide_channel_dma_setup(cp); 8863 8864 /* Per channel settings */ 8865 for (drive = 0; drive < 2; drive++) { 8866 drvp = &chp->ch_drive[drive]; 8867 8868 /* If no drive, skip */ 8869 if ((drvp->drive_flags & DRIVE) == 0) 8870 continue; 8871 8872 timaddr = (drive == 0) ? SCH_D0TIM : SCH_D1TIM; 8873 tim = pci_conf_read(sc->sc_pc, sc->sc_tag, timaddr); 8874 tim &= ~SCH_TIM_MASK; 8875 8876 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 8877 (drvp->drive_flags & DRIVE_UDMA) != 0) { 8878 /* Setup UltraDMA mode */ 8879 drvp->drive_flags &= ~DRIVE_DMA; 8880 8881 mode = drvp->PIO_mode; 8882 tim |= (drvp->UDMA_mode << 16) | SCH_TIM_SYNCDMA; 8883 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 8884 (drvp->drive_flags & DRIVE_DMA) != 0) { 8885 /* Setup multiword DMA mode */ 8886 drvp->drive_flags &= ~DRIVE_UDMA; 8887 8888 tim &= ~SCH_TIM_SYNCDMA; 8889 8890 /* mode = min(pio, dma + 2) */ 8891 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 8892 mode = drvp->PIO_mode; 8893 else 8894 mode = drvp->DMA_mode + 2; 8895 } else { 8896 mode = drvp->PIO_mode; 8897 goto pio; 8898 } 8899 8900 pio: 8901 /* Setup PIO mode */ 8902 if (mode <= 2) { 8903 drvp->DMA_mode = 0; 8904 drvp->PIO_mode = 0; 8905 } else { 8906 drvp->PIO_mode = mode; 8907 drvp->DMA_mode = mode - 2; 8908 } 8909 tim |= (drvp->DMA_mode << 8) | (drvp->PIO_mode); 8910 pci_conf_write(sc->sc_pc, sc->sc_tag, timaddr, tim); 8911 } 8912 8913 pciide_print_modes(cp); 8914 } 8915 8916 void 8917 rdc_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 8918 { 8919 struct pciide_channel *cp; 8920 int channel; 8921 u_int32_t patr; 8922 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 8923 bus_size_t cmdsize, ctlsize; 8924 8925 printf(": DMA"); 8926 pciide_mapreg_dma(sc, pa); 8927 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 8928 if (sc->sc_dma_ok) { 8929 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | 8930 WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 8931 sc->sc_wdcdev.irqack = pciide_irqack; 8932 sc->sc_wdcdev.dma_init = pciide_dma_init; 8933 } 8934 sc->sc_wdcdev.PIO_cap = 4; 8935 sc->sc_wdcdev.DMA_cap = 2; 8936 sc->sc_wdcdev.UDMA_cap = 5; 8937 sc->sc_wdcdev.set_modes = rdc_setup_channel; 8938 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8939 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 8940 8941 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 8942 8943 WDCDEBUG_PRINT(("rdc_chip_map: old PATR=0x%x, " 8944 "PSD1ATR=0x%x, UDCCR=0x%x, IIOCR=0x%x\n", 8945 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR), 8946 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR), 8947 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR), 8948 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)), 8949 DEBUG_PROBE); 8950 8951 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8952 cp = &sc->pciide_channels[channel]; 8953 8954 if (pciide_chansetup(sc, channel, interface) == 0) 8955 continue; 8956 patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR); 8957 if ((patr & RDCIDE_PATR_EN(channel)) == 0) { 8958 printf("%s: %s ignored (disabled)\n", 8959 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 8960 cp->hw_ok = 0; 8961 continue; 8962 } 8963 pciide_map_compat_intr(pa, cp, channel, interface); 8964 if (cp->hw_ok == 0) 8965 continue; 8966 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8967 pciide_pci_intr); 8968 if (cp->hw_ok == 0) 8969 goto next; 8970 if (pciide_chan_candisable(cp)) { 8971 patr &= ~RDCIDE_PATR_EN(channel); 8972 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR, 8973 patr); 8974 } 8975 if (cp->hw_ok == 0) 8976 goto next; 8977 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 8978 next: 8979 if (cp->hw_ok == 0) 8980 pciide_unmap_compat_intr(pa, cp, channel, interface); 8981 } 8982 8983 WDCDEBUG_PRINT(("rdc_chip_map: PATR=0x%x, " 8984 "PSD1ATR=0x%x, UDCCR=0x%x, IIOCR=0x%x\n", 8985 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR), 8986 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR), 8987 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR), 8988 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)), 8989 DEBUG_PROBE); 8990 } 8991 8992 void 8993 rdc_setup_channel(struct channel_softc *chp) 8994 { 8995 u_int8_t drive; 8996 u_int32_t patr, psd1atr, udccr, iiocr; 8997 struct pciide_channel *cp = (struct pciide_channel *)chp; 8998 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 8999 struct ata_drive_datas *drvp; 9000 9001 patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR); 9002 psd1atr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR); 9003 udccr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR); 9004 iiocr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR); 9005 9006 /* setup DMA */ 9007 pciide_channel_dma_setup(cp); 9008 9009 /* clear modes */ 9010 patr = patr & (RDCIDE_PATR_EN(0) | RDCIDE_PATR_EN(1)); 9011 psd1atr &= ~RDCIDE_PSD1ATR_SETUP_MASK(chp->channel); 9012 psd1atr &= ~RDCIDE_PSD1ATR_HOLD_MASK(chp->channel); 9013 for (drive = 0; drive < 2; drive++) { 9014 udccr &= ~RDCIDE_UDCCR_EN(chp->channel, drive); 9015 udccr &= ~RDCIDE_UDCCR_TIM_MASK(chp->channel, drive); 9016 iiocr &= ~RDCIDE_IIOCR_CLK_MASK(chp->channel, drive); 9017 } 9018 /* now setup modes */ 9019 for (drive = 0; drive < 2; drive++) { 9020 drvp = &cp->wdc_channel.ch_drive[drive]; 9021 if ((drvp->drive_flags & DRIVE) == 0) 9022 continue; 9023 if (drvp->drive_flags & DRIVE_ATAPI) 9024 patr |= RDCIDE_PATR_ATA(chp->channel, drive); 9025 if (drive == 0) { 9026 patr |= RDCIDE_PATR_SETUP(rdcide_setup[drvp->PIO_mode], 9027 chp->channel); 9028 patr |= RDCIDE_PATR_HOLD(rdcide_hold[drvp->PIO_mode], 9029 chp->channel); 9030 } else { 9031 patr |= RDCIDE_PATR_DEV1_TEN(chp->channel); 9032 psd1atr |= RDCIDE_PSD1ATR_SETUP( 9033 rdcide_setup[drvp->PIO_mode], 9034 chp->channel); 9035 psd1atr |= RDCIDE_PSD1ATR_HOLD( 9036 rdcide_hold[drvp->PIO_mode], 9037 chp->channel); 9038 } 9039 if (drvp->PIO_mode > 0) { 9040 patr |= RDCIDE_PATR_FTIM(chp->channel, drive); 9041 patr |= RDCIDE_PATR_IORDY(chp->channel, drive); 9042 } 9043 if (drvp->drive_flags & DRIVE_DMA) 9044 patr |= RDCIDE_PATR_DMAEN(chp->channel, drive); 9045 if ((drvp->drive_flags & DRIVE_UDMA) == 0) 9046 continue; 9047 9048 if ((iiocr & RDCIDE_IIOCR_CABLE(chp->channel, drive)) == 0 9049 && drvp->UDMA_mode > 2) 9050 drvp->UDMA_mode = 2; 9051 udccr |= RDCIDE_UDCCR_EN(chp->channel, drive); 9052 udccr |= RDCIDE_UDCCR_TIM(rdcide_udmatim[drvp->UDMA_mode], 9053 chp->channel, drive); 9054 iiocr |= RDCIDE_IIOCR_CLK(rdcide_udmaclk[drvp->UDMA_mode], 9055 chp->channel, drive); 9056 } 9057 9058 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR, patr); 9059 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR, psd1atr); 9060 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR, udccr); 9061 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR, iiocr); 9062 } 9063