1 /* $OpenBSD: pcireg.h,v 1.36 2009/05/28 15:41:48 damien Exp $ */ 2 /* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43 /* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46 #define PCI_ID_REG 0x00 47 48 typedef u_int16_t pci_vendor_id_t; 49 typedef u_int16_t pci_product_id_t; 50 51 #define PCI_VENDOR_SHIFT 0 52 #define PCI_VENDOR_MASK 0xffff 53 #define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56 #define PCI_PRODUCT_SHIFT 16 57 #define PCI_PRODUCT_MASK 0xffff 58 #define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61 #define PCI_ID_CODE(vid,pid) \ 62 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 63 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) 64 65 /* 66 * Command and status register. 67 */ 68 #define PCI_COMMAND_STATUS_REG 0x04 69 70 #define PCI_COMMAND_IO_ENABLE 0x00000001 71 #define PCI_COMMAND_MEM_ENABLE 0x00000002 72 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 73 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 74 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 75 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 76 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 77 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 78 #define PCI_COMMAND_SERR_ENABLE 0x00000100 79 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 80 #define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 81 82 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 83 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 84 #define PCI_STATUS_UDF_SUPPORT 0x00400000 85 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 86 #define PCI_STATUS_PARITY_ERROR 0x01000000 87 #define PCI_STATUS_DEVSEL_FAST 0x00000000 88 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 89 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 90 #define PCI_STATUS_DEVSEL_MASK 0x06000000 91 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 92 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 93 #define PCI_STATUS_MASTER_ABORT 0x20000000 94 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 95 #define PCI_STATUS_PARITY_DETECT 0x80000000 96 97 #define PCI_COMMAND_STATUS_BITS \ 98 ("\020\01IO\02MEM\03MASTER\04SPECIAL\05INVALIDATE\06PALETTE\07PARITY"\ 99 "\010STEPPING\011SERR\012BACKTOBACK\025CAPLIST\026CLK66\027UDF"\ 100 "\030BACK2BACK_STAT\031PARITY_STAT\032DEVSEL_MEDIUM\033DEVSEL_SLOW"\ 101 "\034TARGET_TARGET_ABORT\035MASTER_TARGET_ABORT\036MASTER_ABORT"\ 102 "\037SPECIAL_ERROR\040PARITY_DETECT") 103 /* 104 * PCI Class and Revision Register; defines type and revision of device. 105 */ 106 #define PCI_CLASS_REG 0x08 107 108 typedef u_int8_t pci_class_t; 109 typedef u_int8_t pci_subclass_t; 110 typedef u_int8_t pci_interface_t; 111 typedef u_int8_t pci_revision_t; 112 113 #define PCI_CLASS_SHIFT 24 114 #define PCI_CLASS_MASK 0xff 115 #define PCI_CLASS(cr) \ 116 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 117 118 #define PCI_SUBCLASS_SHIFT 16 119 #define PCI_SUBCLASS_MASK 0xff 120 #define PCI_SUBCLASS(cr) \ 121 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 122 123 #define PCI_INTERFACE_SHIFT 8 124 #define PCI_INTERFACE_MASK 0xff 125 #define PCI_INTERFACE(cr) \ 126 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 127 128 #define PCI_REVISION_SHIFT 0 129 #define PCI_REVISION_MASK 0xff 130 #define PCI_REVISION(cr) \ 131 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 132 133 /* base classes */ 134 #define PCI_CLASS_PREHISTORIC 0x00 135 #define PCI_CLASS_MASS_STORAGE 0x01 136 #define PCI_CLASS_NETWORK 0x02 137 #define PCI_CLASS_DISPLAY 0x03 138 #define PCI_CLASS_MULTIMEDIA 0x04 139 #define PCI_CLASS_MEMORY 0x05 140 #define PCI_CLASS_BRIDGE 0x06 141 #define PCI_CLASS_COMMUNICATIONS 0x07 142 #define PCI_CLASS_SYSTEM 0x08 143 #define PCI_CLASS_INPUT 0x09 144 #define PCI_CLASS_DOCK 0x0a 145 #define PCI_CLASS_PROCESSOR 0x0b 146 #define PCI_CLASS_SERIALBUS 0x0c 147 #define PCI_CLASS_WIRELESS 0x0d 148 #define PCI_CLASS_I2O 0x0e 149 #define PCI_CLASS_SATCOM 0x0f 150 #define PCI_CLASS_CRYPTO 0x10 151 #define PCI_CLASS_DASP 0x11 152 #define PCI_CLASS_UNDEFINED 0xff 153 154 /* 0x00 prehistoric subclasses */ 155 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 156 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 157 158 /* 0x01 mass storage subclasses */ 159 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 160 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 161 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 162 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 163 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 164 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 165 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 166 #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 167 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 168 169 /* 0x02 network subclasses */ 170 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 171 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 172 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 173 #define PCI_SUBCLASS_NETWORK_ATM 0x03 174 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 175 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 176 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 177 #define PCI_SUBCLASS_NETWORK_MISC 0x80 178 179 /* 0x03 display subclasses */ 180 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 181 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 182 #define PCI_SUBCLASS_DISPLAY_3D 0x02 183 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 184 185 /* 0x04 multimedia subclasses */ 186 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 187 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 188 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 189 #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 190 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 191 192 /* 0x05 memory subclasses */ 193 #define PCI_SUBCLASS_MEMORY_RAM 0x00 194 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 195 #define PCI_SUBCLASS_MEMORY_MISC 0x80 196 197 /* 0x06 bridge subclasses */ 198 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 199 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 200 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 201 #define PCI_SUBCLASS_BRIDGE_MC 0x03 202 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 203 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 204 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 205 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 206 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 207 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 208 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 209 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 210 211 /* 0x07 communications subclasses */ 212 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 213 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 214 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 215 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 216 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 217 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 218 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 219 220 /* 0x08 system subclasses */ 221 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 222 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 223 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 224 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 225 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 226 #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 227 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 228 229 /* 0x09 input subclasses */ 230 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 231 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 232 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 233 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 234 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 235 #define PCI_SUBCLASS_INPUT_MISC 0x80 236 237 /* 0x0a dock subclasses */ 238 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 239 #define PCI_SUBCLASS_DOCK_MISC 0x80 240 241 /* 0x0b processor subclasses */ 242 #define PCI_SUBCLASS_PROCESSOR_386 0x00 243 #define PCI_SUBCLASS_PROCESSOR_486 0x01 244 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 245 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 246 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 247 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 248 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 249 250 /* 0x0c serial bus subclasses */ 251 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 252 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 253 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 254 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 255 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 256 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 257 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 258 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 259 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 260 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 261 262 /* 0x0d wireless subclasses */ 263 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 264 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 265 #define PCI_SUBCLASS_WIRELESS_RF 0x10 266 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 267 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 268 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 269 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 270 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 271 272 /* 0x0e I2O (Intelligent I/O) subclasses */ 273 #define PCI_SUBCLASS_I2O_STANDARD 0x00 274 275 /* 0x0f satellite communication subclasses */ 276 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 277 #define PCI_SUBCLASS_SATCOM_TV 0x01 278 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 279 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 280 #define PCI_SUBCLASS_SATCOM_DATA 0x04 281 282 /* 0x10 encryption/decryption subclasses */ 283 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 284 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 285 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 286 287 /* 0x11 data acquisition and signal processing subclasses */ 288 #define PCI_SUBCLASS_DASP_DPIO 0x00 289 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 290 #define PCI_SUBCLASS_DASP_SYNC 0x10 291 #define PCI_SUBCLASS_DASP_MGMT 0x20 292 #define PCI_SUBCLASS_DASP_MISC 0x80 293 294 /* 295 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 296 */ 297 #define PCI_BHLC_REG 0x0c 298 299 #define PCI_BIST_SHIFT 24 300 #define PCI_BIST_MASK 0xff 301 #define PCI_BIST(bhlcr) \ 302 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 303 304 #define PCI_HDRTYPE_SHIFT 16 305 #define PCI_HDRTYPE_MASK 0xff 306 #define PCI_HDRTYPE(bhlcr) \ 307 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 308 309 #define PCI_HDRTYPE_TYPE(bhlcr) \ 310 (PCI_HDRTYPE(bhlcr) & 0x7f) 311 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 312 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 313 314 #define PCI_LATTIMER_SHIFT 8 315 #define PCI_LATTIMER_MASK 0xff 316 #define PCI_LATTIMER(bhlcr) \ 317 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 318 319 #define PCI_CACHELINE_SHIFT 0 320 #define PCI_CACHELINE_MASK 0xff 321 #define PCI_CACHELINE(bhlcr) \ 322 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 323 324 /* config registers for header type 0 devices */ 325 326 #define PCI_MAPS 0x10 327 #define PCI_CARDBUSCIS 0x28 328 #define PCI_SUBVEND_0 0x2c 329 #define PCI_SUBDEV_0 0x2e 330 #define PCI_INTLINE 0x3c 331 #define PCI_INTPIN 0x3d 332 #define PCI_MINGNT 0x3e 333 #define PCI_MAXLAT 0x3f 334 335 /* config registers for header type 1 devices */ 336 337 #define PCI_SECSTAT_1 0 /**/ 338 339 #define PCI_PRIBUS_1 0x18 340 #define PCI_SECBUS_1 0x19 341 #define PCI_SUBBUS_1 0x1a 342 #define PCI_SECLAT_1 0x1b 343 344 #define PCI_IOBASEL_1 0x1c 345 #define PCI_IOLIMITL_1 0x1d 346 #define PCI_IOBASEH_1 0 /**/ 347 #define PCI_IOLIMITH_1 0 /**/ 348 349 #define PCI_MEMBASE_1 0x20 350 #define PCI_MEMLIMIT_1 0x22 351 352 #define PCI_PMBASEL_1 0x24 353 #define PCI_PMLIMITL_1 0x26 354 #define PCI_PMBASEH_1 0 /**/ 355 #define PCI_PMLIMITH_1 0 /**/ 356 357 #define PCI_BRIDGECTL_1 0 /**/ 358 359 #define PCI_SUBVEND_1 0x34 360 #define PCI_SUBDEV_1 0x36 361 362 /* config registers for header type 2 devices */ 363 364 #define PCI_SECSTAT_2 0x16 365 366 #define PCI_PRIBUS_2 0x18 367 #define PCI_SECBUS_2 0x19 368 #define PCI_SUBBUS_2 0x1a 369 #define PCI_SECLAT_2 0x1b 370 371 #define PCI_MEMBASE0_2 0x1c 372 #define PCI_MEMLIMIT0_2 0x20 373 #define PCI_MEMBASE1_2 0x24 374 #define PCI_MEMLIMIT1_2 0x28 375 #define PCI_IOBASE0_2 0x2c 376 #define PCI_IOLIMIT0_2 0x30 377 #define PCI_IOBASE1_2 0x34 378 #define PCI_IOLIMIT1_2 0x38 379 380 #define PCI_BRIDGECTL_2 0x3e 381 382 #define PCI_SUBVEND_2 0x40 383 #define PCI_SUBDEV_2 0x42 384 385 #define PCI_PCCARDIF_2 0x44 386 387 /* 388 * Mapping registers 389 */ 390 #define PCI_MAPREG_START 0x10 391 #define PCI_MAPREG_END 0x28 392 #define PCI_MAPREG_PPB_END 0x18 393 #define PCI_MAPREG_PCB_END 0x14 394 395 #define PCI_MAPREG_TYPE(mr) \ 396 ((mr) & PCI_MAPREG_TYPE_MASK) 397 #define PCI_MAPREG_TYPE_MASK 0x00000001 398 399 #define PCI_MAPREG_TYPE_MEM 0x00000000 400 #define PCI_MAPREG_TYPE_IO 0x00000001 401 402 #define PCI_MAPREG_MEM_TYPE(mr) \ 403 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 404 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 405 406 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 407 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 408 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 409 410 #define _PCI_MAPREG_TYPEBITS(reg) \ 411 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 412 reg & PCI_MAPREG_TYPE_MASK : \ 413 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 414 415 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 416 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 417 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 418 419 #define PCI_MAPREG_MEM_ADDR(mr) \ 420 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 421 #define PCI_MAPREG_MEM_SIZE(mr) \ 422 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 423 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 424 425 #define PCI_MAPREG_MEM64_ADDR(mr) \ 426 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 427 #define PCI_MAPREG_MEM64_SIZE(mr) \ 428 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 429 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 430 431 #define PCI_MAPREG_IO_ADDR(mr) \ 432 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 433 #define PCI_MAPREG_IO_SIZE(mr) \ 434 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 435 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 436 437 /* 438 * Cardbus CIS pointer (PCI rev. 2.1) 439 */ 440 #define PCI_CARDBUS_CIS_REG 0x28 441 442 /* 443 * Subsystem identification register; contains a vendor ID and a device ID. 444 * Types/macros for PCI_ID_REG apply. 445 * (PCI rev. 2.1) 446 */ 447 #define PCI_SUBSYS_ID_REG 0x2c 448 449 /* 450 * Expansion ROM Base Address register 451 * (PCI rev. 2.0) 452 */ 453 #define PCI_ROM_REG 0x30 454 455 #define PCI_ROM_ENABLE 0x00000001 456 #define PCI_ROM_ADDR_MASK 0xfffff800 457 #define PCI_ROM_ADDR(mr) \ 458 ((mr) & PCI_ROM_ADDR_MASK) 459 #define PCI_ROM_SIZE(mr) \ 460 (PCI_ROM_ADDR(mr) & -PCI_ROM_ADDR(mr)) 461 462 /* 463 * capabilities link list (PCI rev. 2.2) 464 */ 465 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 466 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 467 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 468 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 469 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 470 471 #define PCI_CAP_RESERVED 0x00 472 #define PCI_CAP_PWRMGMT 0x01 473 #define PCI_CAP_AGP 0x02 474 #define PCI_CAP_VPD 0x03 475 #define PCI_CAP_SLOTID 0x04 476 #define PCI_CAP_MSI 0x05 477 #define PCI_CAP_CPCI_HOTSWAP 0x06 478 #define PCI_CAP_PCIX 0x07 479 #define PCI_CAP_LDT 0x08 480 #define PCI_CAP_VENDSPEC 0x09 481 #define PCI_CAP_DEBUGPORT 0x0a 482 #define PCI_CAP_CPCI_RSRCCTL 0x0b 483 #define PCI_CAP_HOTPLUG 0x0c 484 #define PCI_CAP_AGP8 0x0e 485 #define PCI_CAP_SECURE 0x0f 486 #define PCI_CAP_PCIEXPRESS 0x10 487 #define PCI_CAP_MSIX 0x11 488 489 /* 490 * Vital Product Data; access via capability pointer (PCI rev 2.2). 491 */ 492 #define PCI_VPD_ADDRESS_MASK 0x7fff 493 #define PCI_VPD_ADDRESS_SHIFT 16 494 #define PCI_VPD_ADDRESS(ofs) \ 495 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 496 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 497 #define PCI_VPD_OPFLAG 0x80000000 498 499 /* 500 * Power Management Control Status Register; access via capability pointer. 501 */ 502 #define PCI_PMCSR 0x04 503 #define PCI_PMCSR_STATE_MASK 0x03 504 #define PCI_PMCSR_STATE_D0 0x00 505 #define PCI_PMCSR_STATE_D1 0x01 506 #define PCI_PMCSR_STATE_D2 0x02 507 #define PCI_PMCSR_STATE_D3 0x03 508 509 /* 510 * PCI Express; access via capability pointer. 511 */ 512 #define PCI_PCIE_XCAP 0x00 513 #define PCI_PCIE_XCAP_SI 0x01000000 514 #define PCI_PCIE_DCAP 0x04 515 #define PCI_PCIE_DCSR 0x08 516 #define PCI_PCIE_DCSR_ENA_NO_SNOOP 0x00000800 517 #define PCI_PCIE_LCAP 0x0c 518 #define PCI_PCIE_LCSR 0x10 519 #define PCI_PCIE_LCSR_ASPM_L0S 0x00000001 520 #define PCI_PCIE_LCSR_ASPM_L1 0x00000002 521 #define PCI_PCIE_SLCAP 0x14 522 #define PCI_PCIE_SLCAP_ABP 0x00000001 523 #define PCI_PCIE_SLCAP_PCP 0x00000002 524 #define PCI_PCIE_SLCAP_MSP 0x00000004 525 #define PCI_PCIE_SLCAP_AIP 0x00000008 526 #define PCI_PCIE_SLCAP_PIP 0x00000010 527 #define PCI_PCIE_SLCAP_HPS 0x00000020 528 #define PCI_PCIE_SLCAP_HPC 0x00000040 529 #define PCI_PCIE_SLCSR 0x18 530 #define PCI_PCIE_SLCSR_ABE 0x00000001 531 #define PCI_PCIE_SLCSR_PFE 0x00000002 532 #define PCI_PCIE_SLCSR_MSE 0x00000004 533 #define PCI_PCIE_SLCSR_PDE 0x00000008 534 #define PCI_PCIE_SLCSR_CCE 0x00000010 535 #define PCI_PCIE_SLCSR_HPE 0x00000020 536 #define PCI_PCIE_SLCSR_ABP 0x00010000 537 #define PCI_PCIE_SLCSR_PFD 0x00020000 538 #define PCI_PCIE_SLCSR_MSC 0x00040000 539 #define PCI_PCIE_SLCSR_PDC 0x00080000 540 #define PCI_PCIE_SLCSR_CC 0x00100000 541 #define PCI_PCIE_SLCSR_MS 0x00200000 542 #define PCI_PCIE_SLCSR_PDS 0x00400000 543 #define PCI_PCIE_SLCSR_LACS 0x01000000 544 #define PCI_PCIE_RCSR 0x1c 545 546 /* 547 * Interrupt Configuration Register; contains interrupt pin and line. 548 */ 549 #define PCI_INTERRUPT_REG 0x3c 550 551 typedef u_int8_t pci_intr_pin_t; 552 typedef u_int8_t pci_intr_line_t; 553 554 #define PCI_INTERRUPT_PIN_SHIFT 8 555 #define PCI_INTERRUPT_PIN_MASK 0xff 556 #define PCI_INTERRUPT_PIN(icr) \ 557 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 558 559 #define PCI_INTERRUPT_LINE_SHIFT 0 560 #define PCI_INTERRUPT_LINE_MASK 0xff 561 #define PCI_INTERRUPT_LINE(icr) \ 562 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 563 564 #define PCI_MIN_GNT_SHIFT 16 565 #define PCI_MIN_GNT_MASK 0xff 566 #define PCI_MIN_GNT(icr) \ 567 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 568 569 #define PCI_MAX_LAT_SHIFT 24 570 #define PCI_MAX_LAT_MASK 0xff 571 #define PCI_MAX_LAT(icr) \ 572 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 573 574 #define PCI_INTERRUPT_PIN_NONE 0x00 575 #define PCI_INTERRUPT_PIN_A 0x01 576 #define PCI_INTERRUPT_PIN_B 0x02 577 #define PCI_INTERRUPT_PIN_C 0x03 578 #define PCI_INTERRUPT_PIN_D 0x04 579 #define PCI_INTERRUPT_PIN_MAX 0x04 580 581 /* 582 * Vital Product Data resource tags. 583 */ 584 struct pci_vpd_smallres { 585 uint8_t vpdres_byte0; /* length of data + tag */ 586 /* Actual data. */ 587 } __packed; 588 589 struct pci_vpd_largeres { 590 uint8_t vpdres_byte0; 591 uint8_t vpdres_len_lsb; /* length of data only */ 592 uint8_t vpdres_len_msb; 593 /* Actual data. */ 594 } __packed; 595 596 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 597 598 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 599 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 600 601 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 602 603 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 604 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 605 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 606 607 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 608 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 609 610 struct pci_vpd { 611 uint8_t vpd_key0; 612 uint8_t vpd_key1; 613 uint8_t vpd_len; /* length of data only */ 614 /* Actual data. */ 615 } __packed; 616 617 /* 618 * Recommended VPD fields: 619 * 620 * PN Part number of assembly 621 * FN FRU part number 622 * EC EC level of assembly 623 * MN Manufacture ID 624 * SN Serial Number 625 * 626 * Conditionally recommended VPD fields: 627 * 628 * LI Load ID 629 * RL ROM Level 630 * RM Alterable ROM Level 631 * NA Network Address 632 * DD Device Driver Level 633 * DG Diagnostic Level 634 * LL Loadable Microcode Level 635 * VI Vendor ID/Device ID 636 * FU Function Number 637 * SI Subsystem Vendor ID/Subsystem ID 638 * 639 * Additional VPD fields: 640 * 641 * Z0-ZZ User/Product Specific 642 */ 643 644 #endif /* _DEV_PCI_PCIREG_H_ */ 645