1 /* $OpenBSD: pcscp.c,v 1.17 2010/06/28 18:31:02 krw Exp $ */ 2 /* $NetBSD: pcscp.c,v 1.26 2003/10/19 10:25:42 tsutsui Exp $ */ 3 4 /*- 5 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center; Izumi Tsutsui. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 36 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 37 * 38 * Technical manual available at 39 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/buf.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #include <scsi/scsi_all.h> 51 #include <scsi/scsiconf.h> 52 #include <scsi/scsi_message.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #include <dev/ic/ncr53c9xreg.h> 59 #include <dev/ic/ncr53c9xvar.h> 60 61 #include <dev/pci/pcscpreg.h> 62 63 #define IO_MAP_REG 0x10 64 65 struct pcscp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 68 bus_space_tag_t sc_st; /* bus space tag */ 69 bus_space_handle_t sc_sh; /* bus space handle */ 70 void *sc_ih; /* interrupt cookie */ 71 72 bus_dma_tag_t sc_dmat; /* DMA tag */ 73 74 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 75 76 u_int32_t *sc_mdladdr; /* MDL array */ 77 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 78 79 int sc_active; /* DMA state */ 80 int sc_datain; /* DMA Data Direction */ 81 size_t sc_dmasize; /* DMA size */ 82 char **sc_dmaaddr; /* DMA address */ 83 size_t *sc_dmalen; /* DMA length */ 84 }; 85 86 #define READ_DMAREG(sc, reg) \ 87 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 88 #define WRITE_DMAREG(sc, reg, var) \ 89 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 90 91 #define PCSCP_READ_REG(sc, reg) \ 92 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2) 93 #define PCSCP_WRITE_REG(sc, reg, val) \ 94 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) 95 96 int pcscp_match(struct device *, void *, void *); 97 void pcscp_attach(struct device *, struct device *, void *); 98 99 struct cfattach pcscp_ca = { 100 sizeof(struct pcscp_softc), pcscp_match, pcscp_attach 101 }; 102 103 struct cfdriver pcscp_cd = { 104 NULL, "pcscp", DV_DULL 105 }; 106 107 /* 108 * Functions and the switch for the MI code. 109 */ 110 111 u_char pcscp_read_reg(struct ncr53c9x_softc *, int); 112 void pcscp_write_reg(struct ncr53c9x_softc *, int, u_char); 113 int pcscp_dma_isintr(struct ncr53c9x_softc *); 114 void pcscp_dma_reset(struct ncr53c9x_softc *); 115 int pcscp_dma_intr(struct ncr53c9x_softc *); 116 int pcscp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 117 size_t *, int, size_t *); 118 void pcscp_dma_go(struct ncr53c9x_softc *); 119 void pcscp_dma_stop(struct ncr53c9x_softc *); 120 int pcscp_dma_isactive(struct ncr53c9x_softc *); 121 122 struct scsi_adapter pcscp_adapter = { 123 ncr53c9x_scsi_cmd, /* cmd */ 124 scsi_minphys, /* scsi_minphys */ 125 0, /* open */ 126 0, /* close */ 127 }; 128 129 struct ncr53c9x_glue pcscp_glue = { 130 pcscp_read_reg, 131 pcscp_write_reg, 132 pcscp_dma_isintr, 133 pcscp_dma_reset, 134 pcscp_dma_intr, 135 pcscp_dma_setup, 136 pcscp_dma_go, 137 pcscp_dma_stop, 138 pcscp_dma_isactive, 139 NULL, /* gl_clear_latched_intr */ 140 }; 141 142 int 143 pcscp_match(struct device *parent, void *match, void *aux) 144 { 145 struct pci_attach_args *pa = aux; 146 147 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 148 return 0; 149 150 switch (PCI_PRODUCT(pa->pa_id)) { 151 case PCI_PRODUCT_AMD_PCSCSI_PCI: 152 return 1; 153 } 154 return 0; 155 } 156 157 /* 158 * Attach this instance, and then all the sub-devices 159 */ 160 void 161 pcscp_attach(struct device *parent, struct device *self, void *aux) 162 { 163 struct pci_attach_args *pa = aux; 164 struct pcscp_softc *esc = (void *)self; 165 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 166 bus_space_tag_t iot; 167 bus_space_handle_t ioh; 168 pci_intr_handle_t ih; 169 const char *intrstr; 170 bus_dma_segment_t seg; 171 int error, rseg; 172 173 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 174 &iot, &ioh, NULL, NULL, NULL)) { 175 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 176 return; 177 } 178 179 sc->sc_glue = &pcscp_glue; 180 181 esc->sc_st = iot; 182 esc->sc_sh = ioh; 183 esc->sc_dmat = pa->pa_dmat; 184 185 /* 186 * XXX More of this should be in ncr53c9x_attach(), but 187 * XXX should we really poke around the chip that much in 188 * XXX the MI code? Think about this more... 189 */ 190 191 /* 192 * Set up static configuration info. 193 */ 194 195 /* 196 * XXX should read configuration from EEPROM? 197 * 198 * MI ncr53c9x driver does not support configuration 199 * per each target device, though... 200 */ 201 sc->sc_id = 7; 202 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 203 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 204 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 205 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 206 sc->sc_rev = NCR_VARIANT_AM53C974; 207 sc->sc_features = NCR_F_FASTSCSI; 208 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 209 sc->sc_freq = 40; /* MHz */ 210 211 /* 212 * XXX minsync and maxxfer _should_ be set up in MI code, 213 * XXX but it appears to have some dependency on what sort 214 * XXX of DMA we're hooked up to, etc. 215 */ 216 217 /* 218 * This is the value used to start sync negotiations 219 * Note that the NCR register "SYNCTP" is programmed 220 * in "clocks per byte", and has a minimum value of 4. 221 * The SCSI period used in negotiation is one-fourth 222 * of the time (in nanoseconds) needed to transfer one byte. 223 * Since the chip's clock is given in MHz, we have the following 224 * formula: 4 * period = (1000 / freq) * 4 225 */ 226 227 sc->sc_minsync = 1000 / sc->sc_freq; 228 229 /* Really no limit, but since we want to fit into the TCR... */ 230 sc->sc_maxxfer = 16 * 1024 * 1024; 231 232 /* 233 * Create the DMA maps for the data transfers. 234 */ 235 236 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 237 #define MDL_SEG_OFFSET 0x0FFF 238 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 239 240 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE, 241 MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 242 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 243 return; 244 } 245 246 /* 247 * Allocate and map memory for the MDL. 248 */ 249 250 if ((error = bus_dmamem_alloc(esc->sc_dmat, 251 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 252 BUS_DMA_NOWAIT)) != 0) { 253 printf("%s: unable to allocate memory for the MDL, " 254 "error = %d\n", sc->sc_dev.dv_xname, error); 255 goto fail_0; 256 } 257 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 258 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 259 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 260 printf("%s: unable to map the MDL memory, error = %d\n", 261 sc->sc_dev.dv_xname, error); 262 goto fail_1; 263 } 264 if ((error = bus_dmamap_create(esc->sc_dmat, 265 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 266 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 267 printf("%s: unable to map_create for the MDL, error = %d\n", 268 sc->sc_dev.dv_xname, error); 269 goto fail_2; 270 } 271 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 272 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 273 NULL, BUS_DMA_NOWAIT)) != 0) { 274 printf("%s: unable to load for the MDL, error = %d\n", 275 sc->sc_dev.dv_xname, error); 276 goto fail_3; 277 } 278 279 /* map and establish interrupt */ 280 if (pci_intr_map(pa, &ih)) { 281 printf(": couldn't map interrupt\n"); 282 goto fail_4; 283 } 284 285 intrstr = pci_intr_string(pa->pa_pc, ih); 286 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 287 ncr53c9x_intr, esc, sc->sc_dev.dv_xname); 288 if (esc->sc_ih == NULL) { 289 printf(": couldn't establish interrupt"); 290 if (intrstr != NULL) 291 printf(" at %s", intrstr); 292 printf("\n"); 293 goto fail_4; 294 } 295 if (intrstr != NULL) 296 printf(": %s\n", intrstr); 297 298 /* Do the common parts of attachment. */ 299 printf("%s", sc->sc_dev.dv_xname); 300 301 ncr53c9x_attach(sc, &pcscp_adapter); 302 303 /* Turn on target selection using the `dma' method */ 304 sc->sc_features |= NCR_F_DMASELECT; 305 306 return; 307 308 fail_4: 309 bus_dmamap_unload(esc->sc_dmat, esc->sc_mdldmap); 310 fail_3: 311 bus_dmamap_destroy(esc->sc_dmat, esc->sc_mdldmap); 312 fail_2: 313 bus_dmamem_unmap(esc->sc_dmat, (caddr_t)esc->sc_mdldmap, 314 sizeof(uint32_t) * MDL_SIZE); 315 fail_1: 316 bus_dmamem_free(esc->sc_dmat, &seg, rseg); 317 fail_0: 318 bus_dmamap_destroy(esc->sc_dmat, esc->sc_xfermap); 319 } 320 321 /* 322 * Glue functions. 323 */ 324 325 u_char 326 pcscp_read_reg(struct ncr53c9x_softc *sc, int reg) 327 { 328 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 329 330 return PCSCP_READ_REG(esc, reg); 331 } 332 333 void 334 pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 335 { 336 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 337 338 PCSCP_WRITE_REG(esc, reg, v); 339 } 340 341 int 342 pcscp_dma_isintr(struct ncr53c9x_softc *sc) 343 { 344 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 345 346 return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0; 347 } 348 349 void 350 pcscp_dma_reset(struct ncr53c9x_softc *sc) 351 { 352 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 353 354 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 355 356 esc->sc_active = 0; 357 } 358 359 int 360 pcscp_dma_intr(struct ncr53c9x_softc *sc) 361 { 362 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 363 int trans, resid, i; 364 bus_dmamap_t dmap = esc->sc_xfermap; 365 int datain = esc->sc_datain; 366 u_int32_t dmastat; 367 char *p = NULL; 368 369 dmastat = READ_DMAREG(esc, DMA_STAT); 370 371 if (dmastat & DMASTAT_ERR) { 372 /* XXX not tested... */ 373 WRITE_DMAREG(esc, DMA_CMD, 374 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 375 376 printf("%s: error: DMA error detected; Aborting.\n", 377 sc->sc_dev.dv_xname); 378 bus_dmamap_unload(esc->sc_dmat, dmap); 379 return -1; 380 } 381 382 if (dmastat & DMASTAT_ABT) { 383 /* XXX What should be done? */ 384 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 385 WRITE_DMAREG(esc, DMA_CMD, 386 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 387 esc->sc_active = 0; 388 return 0; 389 } 390 391 #ifdef DIAGNOSTIC 392 /* This is an "assertion" :) */ 393 if (esc->sc_active == 0) 394 panic("pcscp dmaintr: DMA wasn't active"); 395 #endif 396 397 /* DMA has stopped */ 398 399 esc->sc_active = 0; 400 401 if (esc->sc_dmasize == 0) { 402 /* A "Transfer Pad" operation completed */ 403 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 404 PCSCP_READ_REG(esc, NCR_TCL) | 405 (PCSCP_READ_REG(esc, NCR_TCM) << 8), 406 PCSCP_READ_REG(esc, NCR_TCL), 407 PCSCP_READ_REG(esc, NCR_TCM))); 408 return 0; 409 } 410 411 resid = 0; 412 /* 413 * If a transfer onto the SCSI bus gets interrupted by the device 414 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 415 * as residual since the ESP counter registers get decremented as 416 * bytes are clocked into the FIFO. 417 */ 418 if (!datain && 419 (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 420 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 421 } 422 423 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 424 /* 425 * `Terminal count' is off, so read the residue 426 * out of the ESP counter registers. 427 */ 428 if (datain) { 429 resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 430 while (resid > 1) 431 resid = 432 PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 433 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 434 (datain ? DMACMD_DIR : 0)); 435 436 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 437 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 438 break; 439 440 /* See the below comments... */ 441 if (resid) 442 p = *esc->sc_dmaaddr; 443 } 444 445 resid += PCSCP_READ_REG(esc, NCR_TCL) | 446 (PCSCP_READ_REG(esc, NCR_TCM) << 8) | 447 (PCSCP_READ_REG(esc, NCR_TCH) << 16); 448 } else { 449 while ((dmastat & DMASTAT_DONE) == 0) 450 dmastat = READ_DMAREG(esc, DMA_STAT); 451 } 452 453 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 454 455 /* sync MDL */ 456 bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap, 457 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE); 458 /* sync transfer buffer */ 459 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 460 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 461 bus_dmamap_unload(esc->sc_dmat, dmap); 462 463 trans = esc->sc_dmasize - resid; 464 465 /* 466 * From the technical manual notes: 467 * 468 * `In some odd byte conditions, one residual byte will be left 469 * in the SCSI FIFO, and the FIFO flags will never count to 0. 470 * When this happens, the residual byte should be retrieved 471 * via PIO following completion of the BLAST operation.' 472 */ 473 474 if (p) { 475 p += trans; 476 *p = PCSCP_READ_REG(esc, NCR_FIFO); 477 trans++; 478 } 479 480 if (trans < 0) { /* transferred < 0 ? */ 481 #if 0 482 /* 483 * This situation can happen in perfectly normal operation 484 * if the ESP is reselected while using DMA to select 485 * another target. As such, don't print the warning. 486 */ 487 printf("%s: xfer (%d) > req (%d)\n", 488 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 489 #endif 490 trans = esc->sc_dmasize; 491 } 492 493 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 494 PCSCP_READ_REG(esc, NCR_TCL), 495 PCSCP_READ_REG(esc, NCR_TCM), 496 PCSCP_READ_REG(esc, NCR_TCH), 497 trans, resid)); 498 499 *esc->sc_dmalen -= trans; 500 *esc->sc_dmaaddr += trans; 501 502 return 0; 503 } 504 505 int 506 pcscp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 507 int datain, size_t *dmasize) 508 { 509 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 510 bus_dmamap_t dmap = esc->sc_xfermap; 511 u_int32_t *mdl; 512 int error, nseg, seg; 513 bus_addr_t s_offset, s_addr; 514 515 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 516 517 esc->sc_dmaaddr = addr; 518 esc->sc_dmalen = len; 519 esc->sc_dmasize = *dmasize; 520 esc->sc_datain = datain; 521 522 #ifdef DIAGNOSTIC 523 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 524 panic("pcscp: transfer size too large"); 525 #endif 526 527 /* 528 * No need to set up DMA in `Transfer Pad' operation. 529 * (case of *dmasize == 0) 530 */ 531 if (*dmasize == 0) 532 return 0; 533 534 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 535 *esc->sc_dmalen, NULL, 536 ((sc->sc_nexus->xs->flags & SCSI_NOSLEEP) ? 537 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 538 ((sc->sc_nexus->xs->flags & SCSI_DATA_IN) ? 539 BUS_DMA_READ : BUS_DMA_WRITE)); 540 if (error) { 541 printf("%s: unable to load dmamap, error = %d\n", 542 sc->sc_dev.dv_xname, error); 543 return error; 544 } 545 546 /* set transfer length */ 547 WRITE_DMAREG(esc, DMA_STC, *dmasize); 548 549 /* set up MDL */ 550 mdl = esc->sc_mdladdr; 551 nseg = dmap->dm_nsegs; 552 553 /* the first segment is possibly not aligned with 4k MDL boundary */ 554 s_addr = dmap->dm_segs[0].ds_addr; 555 s_offset = s_addr & MDL_SEG_OFFSET; 556 s_addr -= s_offset; 557 558 /* set the first MDL and offset */ 559 WRITE_DMAREG(esc, DMA_SPA, s_offset); 560 *mdl++ = htole32(s_addr); 561 562 /* the rest dmamap segments are aligned with 4k boundary */ 563 for (seg = 1; seg < nseg; seg++) 564 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr); 565 566 return 0; 567 } 568 569 void 570 pcscp_dma_go(struct ncr53c9x_softc *sc) 571 { 572 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 573 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 574 int datain = esc->sc_datain; 575 576 /* No DMA transfer in Transfer Pad operation */ 577 if (esc->sc_dmasize == 0) 578 return; 579 580 /* sync transfer buffer */ 581 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 582 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 583 584 /* sync MDL */ 585 bus_dmamap_sync(esc->sc_dmat, mdldmap, 586 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 587 588 /* set Starting MDL Address */ 589 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 590 591 /* set DMA command register bits */ 592 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 593 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 594 /* DMACMD_INTE | */ 595 (datain ? DMACMD_DIR : 0)); 596 597 /* issue DMA start command */ 598 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 599 /* DMACMD_INTE | */ 600 (datain ? DMACMD_DIR : 0)); 601 602 esc->sc_active = 1; 603 } 604 605 void 606 pcscp_dma_stop(struct ncr53c9x_softc *sc) 607 { 608 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 609 610 /* dma stop */ 611 /* XXX What should we do here ? */ 612 WRITE_DMAREG(esc, DMA_CMD, 613 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 614 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfermap); 615 616 esc->sc_active = 0; 617 } 618 619 int 620 pcscp_dma_isactive(struct ncr53c9x_softc *sc) 621 { 622 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 623 624 /* XXX should check esc->sc_active? */ 625 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 626 return 1; 627 return 0; 628 } 629