1 /* $OpenBSD: pcscp.c,v 1.3 2001/06/12 15:40:33 niklas Exp $ */ 2 /* $NetBSD: pcscp.c,v 1.11 2000/11/14 18:42:58 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center; Izumi Tsutsui. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 43 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 44 * 45 * Technical manual available at 46 * http://www.amd.com/products/npd/techdocs/techdocs.html 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/buf.h> 53 54 #include <machine/bus.h> 55 #include <machine/intr.h> 56 #include <machine/endian.h> 57 58 #include <scsi/scsi_all.h> 59 #include <scsi/scsiconf.h> 60 #include <scsi/scsi_message.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <dev/pci/pcscpreg.h> 70 71 #define IO_MAP_REG 0x10 72 #define MEM_MAP_REG 0x14 73 74 struct pcscp_softc { 75 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 76 77 bus_space_tag_t sc_st; /* bus space tag */ 78 bus_space_handle_t sc_sh; /* bus space handle */ 79 void *sc_ih; /* interrupt cookie */ 80 81 bus_dma_tag_t sc_dmat; /* DMA tag */ 82 83 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 84 85 u_int32_t *sc_mdladdr; /* MDL array */ 86 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 87 88 int sc_active; /* DMA state */ 89 int sc_datain; /* DMA Data Direction */ 90 size_t sc_dmasize; /* DMA size */ 91 char **sc_dmaaddr; /* DMA address */ 92 size_t *sc_dmalen; /* DMA length */ 93 }; 94 95 #define READ_DMAREG(sc, reg) \ 96 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 97 #define WRITE_DMAREG(sc, reg, var) \ 98 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 99 100 /* don't have to use MI defines in MD code... */ 101 #undef NCR_READ_REG 102 #define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg)) 103 #undef NCR_WRITE_REG 104 #define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val)) 105 106 int pcscp_match __P((struct device *, void *, void *)); 107 void pcscp_attach __P((struct device *, struct device *, void *)); 108 109 struct cfattach pcscp_ca = { 110 sizeof(struct pcscp_softc), pcscp_match, pcscp_attach 111 }; 112 113 struct cfdriver pcscp_cd = { 114 NULL, "pcscp", DV_DULL 115 }; 116 117 /* 118 * Functions and the switch for the MI code. 119 */ 120 121 u_char pcscp_read_reg __P((struct ncr53c9x_softc *, int)); 122 void pcscp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 123 int pcscp_dma_isintr __P((struct ncr53c9x_softc *)); 124 void pcscp_dma_reset __P((struct ncr53c9x_softc *)); 125 int pcscp_dma_intr __P((struct ncr53c9x_softc *)); 126 int pcscp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 127 size_t *, int, size_t *)); 128 void pcscp_dma_go __P((struct ncr53c9x_softc *)); 129 void pcscp_dma_stop __P((struct ncr53c9x_softc *)); 130 int pcscp_dma_isactive __P((struct ncr53c9x_softc *)); 131 132 struct scsi_adapter pcscp_adapter = { 133 ncr53c9x_scsi_cmd, /* cmd */ 134 minphys, /* minphys */ 135 0, /* open */ 136 0, /* close */ 137 }; 138 139 struct ncr53c9x_glue pcscp_glue = { 140 pcscp_read_reg, 141 pcscp_write_reg, 142 pcscp_dma_isintr, 143 pcscp_dma_reset, 144 pcscp_dma_intr, 145 pcscp_dma_setup, 146 pcscp_dma_go, 147 pcscp_dma_stop, 148 pcscp_dma_isactive, 149 NULL, /* gl_clear_latched_intr */ 150 }; 151 152 int 153 pcscp_match(parent, match, aux) 154 struct device *parent; 155 void *match, *aux; 156 { 157 struct pci_attach_args *pa = aux; 158 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 159 return 0; 160 161 switch (PCI_PRODUCT(pa->pa_id)) { 162 case PCI_PRODUCT_AMD_PCSCSI_PCI: 163 #if 0 164 case PCI_PRODUCT_AMD_PCNETS_PCI: 165 #endif 166 return 1; 167 } 168 return 0; 169 } 170 171 /* 172 * Attach this instance, and then all the sub-devices 173 */ 174 void 175 pcscp_attach(parent, self, aux) 176 struct device *parent, *self; 177 void *aux; 178 { 179 struct pci_attach_args *pa = aux; 180 struct pcscp_softc *esc = (void *)self; 181 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 182 bus_space_tag_t st, iot, memt; 183 bus_space_handle_t sh, ioh, memh; 184 int ioh_valid, memh_valid; 185 pci_intr_handle_t ih; 186 const char *intrstr; 187 pcireg_t csr; 188 bus_dma_segment_t seg; 189 int error, rseg; 190 191 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 192 &iot, &ioh, NULL, NULL, 0) == 0); 193 #if 0 /* XXX cannot use memory map? */ 194 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 195 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 196 &memt, &memh, NULL, NULL, 0) == 0); 197 #else 198 memh_valid = 0; 199 #endif 200 201 if (memh_valid) { 202 st = memt; 203 sh = memh; 204 } else if (ioh_valid) { 205 st = iot; 206 sh = ioh; 207 } else { 208 printf(": unable to map registers\n"); 209 return; 210 } 211 212 sc->sc_glue = &pcscp_glue; 213 214 esc->sc_st = st; 215 esc->sc_sh = sh; 216 esc->sc_dmat = pa->pa_dmat; 217 218 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 219 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 220 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 221 222 /* 223 * XXX More of this should be in ncr53c9x_attach(), but 224 * XXX should we really poke around the chip that much in 225 * XXX the MI code? Think about this more... 226 */ 227 228 /* 229 * Set up static configuration info. 230 */ 231 232 /* 233 * XXX should read configuration from EEPROM? 234 * 235 * MI ncr53c9x driver does not support configuration 236 * per each target device, though... 237 */ 238 sc->sc_id = 7; 239 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 240 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 241 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 242 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 243 sc->sc_rev = NCR_VARIANT_AM53C974; 244 sc->sc_features = NCR_F_FASTSCSI; 245 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 246 sc->sc_freq = 40; /* MHz */ 247 248 /* 249 * XXX minsync and maxxfer _should_ be set up in MI code, 250 * XXX but it appears to have some dependency on what sort 251 * XXX of DMA we're hooked up to, etc. 252 */ 253 254 /* 255 * This is the value used to start sync negotiations 256 * Note that the NCR register "SYNCTP" is programmed 257 * in "clocks per byte", and has a minimum value of 4. 258 * The SCSI period used in negotiation is one-fourth 259 * of the time (in nanoseconds) needed to transfer one byte. 260 * Since the chip's clock is given in MHz, we have the following 261 * formula: 4 * period = (1000 / freq) * 4 262 */ 263 264 sc->sc_minsync = 1000 / sc->sc_freq; 265 266 /* Really no limit, but since we want to fit into the TCR... */ 267 sc->sc_maxxfer = 16 * 1024 * 1024; 268 269 /* map and establish interrupt */ 270 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 271 pa->pa_intrline, &ih)) { 272 printf(": couldn't map interrupt\n"); 273 return; 274 } 275 276 intrstr = pci_intr_string(pa->pa_pc, ih); 277 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 278 ncr53c9x_intr, esc, sc->sc_dev.dv_xname); 279 if (esc->sc_ih == NULL) { 280 printf(": couldn't establish interrupt"); 281 if (intrstr != NULL) 282 printf(" at %s", intrstr); 283 printf("\n"); 284 return; 285 } 286 if (intrstr != NULL) 287 printf(": %s\n", intrstr); 288 289 /* 290 * Create the DMA maps for the data transfers. 291 */ 292 293 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 294 #define MDL_SEG_OFFSET 0x0FFF 295 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 296 297 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0, 298 BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 299 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 300 return; 301 } 302 303 /* 304 * Allocate and map memory for the MDL. 305 */ 306 307 if ((error = bus_dmamem_alloc(esc->sc_dmat, 308 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 309 BUS_DMA_NOWAIT)) != 0) { 310 printf("%s: unable to allocate memory for the MDL, " 311 "error = %d\n", sc->sc_dev.dv_xname, error); 312 return; 313 } 314 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 315 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 316 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 317 printf("%s: unable to map the MDL memory, error = %d\n", 318 sc->sc_dev.dv_xname, error); 319 return; 320 } 321 if ((error = bus_dmamap_create(esc->sc_dmat, 322 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 323 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 324 printf("%s: unable to map_create for the MDL, error = %d\n", 325 sc->sc_dev.dv_xname, error); 326 return; 327 } 328 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 329 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 330 NULL, BUS_DMA_NOWAIT)) != 0) { 331 printf("%s: unable to load for the MDL, error = %d\n", 332 sc->sc_dev.dv_xname, error); 333 return; 334 } 335 336 /* Do the common parts of attachment. */ 337 printf("%s", sc->sc_dev.dv_xname); 338 339 ncr53c9x_attach(sc, &pcscp_adapter, NULL); 340 341 /* Turn on target selection using the `dma' method */ 342 ncr53c9x_dmaselect = 1; 343 } 344 345 /* 346 * Glue functions. 347 */ 348 349 u_char 350 pcscp_read_reg(sc, reg) 351 struct ncr53c9x_softc *sc; 352 int reg; 353 { 354 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 355 356 return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2); 357 } 358 359 void 360 pcscp_write_reg(sc, reg, v) 361 struct ncr53c9x_softc *sc; 362 int reg; 363 u_char v; 364 { 365 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 366 367 bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v); 368 } 369 370 int 371 pcscp_dma_isintr(sc) 372 struct ncr53c9x_softc *sc; 373 { 374 375 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 376 } 377 378 void 379 pcscp_dma_reset(sc) 380 struct ncr53c9x_softc *sc; 381 { 382 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 383 384 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 385 386 esc->sc_active = 0; 387 } 388 389 int 390 pcscp_dma_intr(sc) 391 struct ncr53c9x_softc *sc; 392 { 393 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 394 int trans, resid, i; 395 bus_dmamap_t dmap = esc->sc_xfermap; 396 int datain = esc->sc_datain; 397 u_int32_t dmastat; 398 char *p = NULL; 399 400 dmastat = READ_DMAREG(esc, DMA_STAT); 401 402 if (dmastat & DMASTAT_ERR) { 403 /* XXX not tested... */ 404 WRITE_DMAREG(esc, DMA_CMD, 405 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 406 407 printf("%s: error: DMA error detected; Aborting.\n", 408 sc->sc_dev.dv_xname); 409 bus_dmamap_unload(esc->sc_dmat, dmap); 410 return -1; 411 } 412 413 if (dmastat & DMASTAT_ABT) { 414 /* XXX What should be done? */ 415 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 416 WRITE_DMAREG(esc, DMA_CMD, 417 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 418 esc->sc_active = 0; 419 return 0; 420 } 421 422 /* This is an "assertion" :) */ 423 if (esc->sc_active == 0) 424 panic("pcscp dmaintr: DMA wasn't active"); 425 426 /* DMA has stopped */ 427 428 esc->sc_active = 0; 429 430 if (esc->sc_dmasize == 0) { 431 /* A "Transfer Pad" operation completed */ 432 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 433 NCR_READ_REG(sc, NCR_TCL) | 434 (NCR_READ_REG(sc, NCR_TCM) << 8), 435 NCR_READ_REG(sc, NCR_TCL), 436 NCR_READ_REG(sc, NCR_TCM))); 437 return 0; 438 } 439 440 resid = 0; 441 /* 442 * If a transfer onto the SCSI bus gets interrupted by the device 443 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 444 * as residual since the ESP counter registers get decremented as 445 * bytes are clocked into the FIFO. 446 */ 447 if (!datain && 448 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 449 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 450 } 451 452 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 453 /* 454 * `Terminal count' is off, so read the residue 455 * out of the ESP counter registers. 456 */ 457 if (datain) { 458 resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 459 while (resid > 1) 460 resid = 461 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 462 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 463 (datain ? DMACMD_DIR : 0)); 464 465 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 466 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 467 break; 468 469 /* See the below comments... */ 470 if (resid) 471 p = *esc->sc_dmaaddr; 472 } 473 474 resid += (NCR_READ_REG(sc, NCR_TCL) | 475 (NCR_READ_REG(sc, NCR_TCM) << 8) | 476 ((sc->sc_cfg2 & NCRCFG2_FE) 477 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 478 479 if (resid == 0 && esc->sc_dmasize == 65536 && 480 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 481 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 482 resid = 65536; 483 } else { 484 while((dmastat & DMASTAT_DONE) == 0) 485 dmastat = READ_DMAREG(esc, DMA_STAT); 486 } 487 488 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 489 490 bus_dmamap_sync(esc->sc_dmat, dmap, 491 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 492 bus_dmamap_unload(esc->sc_dmat, dmap); 493 494 trans = esc->sc_dmasize - resid; 495 496 /* 497 * From the technical manual notes: 498 * 499 * `In some odd byte conditions, one residual byte will be left 500 * in the SCSI FIFO, and the FIFO flags will never count to 0. 501 * When this happens, the residual byte should be retrieved 502 * via PIO following completion of the BLAST operation.' 503 */ 504 505 if (p) { 506 p += trans; 507 *p = NCR_READ_REG(sc, NCR_FIFO); 508 trans++; 509 } 510 511 if (trans < 0) { /* transferred < 0 ? */ 512 #if 0 513 /* 514 * This situation can happen in perfectly normal operation 515 * if the ESP is reselected while using DMA to select 516 * another target. As such, don't print the warning. 517 */ 518 printf("%s: xfer (%d) > req (%d)\n", 519 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 520 #endif 521 trans = esc->sc_dmasize; 522 } 523 524 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 525 NCR_READ_REG(sc, NCR_TCL), 526 NCR_READ_REG(sc, NCR_TCM), 527 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 528 trans, resid)); 529 530 *esc->sc_dmalen -= trans; 531 *esc->sc_dmaaddr += trans; 532 533 return 0; 534 } 535 536 int 537 pcscp_dma_setup(sc, addr, len, datain, dmasize) 538 struct ncr53c9x_softc *sc; 539 caddr_t *addr; 540 size_t *len; 541 int datain; 542 size_t *dmasize; 543 { 544 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 545 bus_dmamap_t dmap = esc->sc_xfermap; 546 u_int32_t *mdl; 547 int error, nseg, seg; 548 bus_addr_t s_offset, s_addr; 549 long rest, count; 550 551 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 552 553 esc->sc_dmaaddr = addr; 554 esc->sc_dmalen = len; 555 esc->sc_dmasize = *dmasize; 556 esc->sc_datain = datain; 557 558 #ifdef DIAGNOSTIC 559 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 560 panic("pcscp: transfer size too large"); 561 #endif 562 563 /* 564 * No need to set up DMA in `Transfer Pad' operation. 565 * (case of *dmasize == 0) 566 */ 567 if (*dmasize == 0) 568 return 0; 569 570 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 571 *esc->sc_dmalen, NULL, 572 sc->sc_nexus->xs->flags & SCSI_NOSLEEP ? 573 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 574 if (error) { 575 printf("%s: unable to load dmamap, error = %d\n", 576 sc->sc_dev.dv_xname, error); 577 return error; 578 } 579 580 /* set transfer length */ 581 WRITE_DMAREG(esc, DMA_STC, *dmasize); 582 583 /* set up MDL */ 584 mdl = esc->sc_mdladdr; 585 nseg = dmap->dm_nsegs; 586 587 /* the first segment is possibly not aligned with 4k MDL boundary */ 588 count = dmap->dm_segs[0].ds_len; 589 s_addr = dmap->dm_segs[0].ds_addr; 590 s_offset = s_addr & MDL_SEG_OFFSET; 591 s_addr -= s_offset; 592 rest = MDL_SEG_SIZE - s_offset; 593 594 /* set the first MDL and offset */ 595 WRITE_DMAREG(esc, DMA_SPA, s_offset); 596 *mdl++ = htole32(s_addr); 597 count -= rest; 598 599 /* rests of the first dmamap segment */ 600 while (count > 0) { 601 s_addr += MDL_SEG_SIZE; 602 *mdl++ = htole32(s_addr); 603 count -= MDL_SEG_SIZE; 604 } 605 606 /* the rest dmamap segments are aligned with 4k boundary */ 607 for (seg = 1; seg < nseg; seg++) { 608 count = dmap->dm_segs[seg].ds_len; 609 s_addr = dmap->dm_segs[seg].ds_addr; 610 611 /* first 4kbyte of each dmamap segment */ 612 *mdl++ = htole32(s_addr); 613 count -= MDL_SEG_SIZE; 614 615 /* trailing contiguous 4k frames of each dmamap segments */ 616 while (count > 0) { 617 s_addr += MDL_SEG_SIZE; 618 *mdl++ = htole32(s_addr); 619 count -= MDL_SEG_SIZE; 620 } 621 } 622 623 return 0; 624 } 625 626 void 627 pcscp_dma_go(sc) 628 struct ncr53c9x_softc *sc; 629 { 630 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 631 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 632 int datain = esc->sc_datain; 633 634 /* No DMA transfer in Transfer Pad operation */ 635 if (esc->sc_dmasize == 0) 636 return; 637 638 /* sync transfer buffer */ 639 bus_dmamap_sync(esc->sc_dmat, dmap, 640 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 641 642 /* sync MDL */ 643 bus_dmamap_sync(esc->sc_dmat, mdldmap, 644 BUS_DMASYNC_PREWRITE); 645 646 /* set Starting MDL Address */ 647 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 648 649 /* set DMA command register bits */ 650 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 651 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 652 /* DMACMD_INTE | */ 653 (datain ? DMACMD_DIR : 0)); 654 655 /* issue DMA start command */ 656 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 657 /* DMACMD_INTE | */ 658 (datain ? DMACMD_DIR : 0)); 659 660 esc->sc_active = 1; 661 } 662 663 void 664 pcscp_dma_stop(sc) 665 struct ncr53c9x_softc *sc; 666 { 667 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 668 669 /* dma stop */ 670 /* XXX What should we do here ? */ 671 WRITE_DMAREG(esc, DMA_CMD, 672 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 673 674 esc->sc_active = 0; 675 } 676 677 int 678 pcscp_dma_isactive(sc) 679 struct ncr53c9x_softc *sc; 680 { 681 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 682 683 /* XXX should check esc->sc_active? */ 684 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 685 return 1; 686 return 0; 687 } 688