1 /* $OpenBSD: pcscp.c,v 1.19 2014/01/18 22:33:59 dlg Exp $ */ 2 /* $NetBSD: pcscp.c,v 1.26 2003/10/19 10:25:42 tsutsui Exp $ */ 3 4 /*- 5 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center; Izumi Tsutsui. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 36 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 37 * 38 * Technical manual available at 39 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/buf.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #include <scsi/scsi_all.h> 51 #include <scsi/scsiconf.h> 52 #include <scsi/scsi_message.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #include <dev/ic/ncr53c9xreg.h> 59 #include <dev/ic/ncr53c9xvar.h> 60 61 #include <dev/pci/pcscpreg.h> 62 63 #define IO_MAP_REG 0x10 64 65 struct pcscp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 68 bus_space_tag_t sc_st; /* bus space tag */ 69 bus_space_handle_t sc_sh; /* bus space handle */ 70 void *sc_ih; /* interrupt cookie */ 71 72 bus_dma_tag_t sc_dmat; /* DMA tag */ 73 74 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 75 76 u_int32_t *sc_mdladdr; /* MDL array */ 77 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 78 79 int sc_active; /* DMA state */ 80 int sc_datain; /* DMA Data Direction */ 81 size_t sc_dmasize; /* DMA size */ 82 char **sc_dmaaddr; /* DMA address */ 83 size_t *sc_dmalen; /* DMA length */ 84 }; 85 86 #define READ_DMAREG(sc, reg) \ 87 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 88 #define WRITE_DMAREG(sc, reg, var) \ 89 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 90 91 #define PCSCP_READ_REG(sc, reg) \ 92 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2) 93 #define PCSCP_WRITE_REG(sc, reg, val) \ 94 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) 95 96 int pcscp_match(struct device *, void *, void *); 97 void pcscp_attach(struct device *, struct device *, void *); 98 99 struct cfattach pcscp_ca = { 100 sizeof(struct pcscp_softc), pcscp_match, pcscp_attach 101 }; 102 103 struct cfdriver pcscp_cd = { 104 NULL, "pcscp", DV_DULL 105 }; 106 107 /* 108 * Functions and the switch for the MI code. 109 */ 110 111 u_char pcscp_read_reg(struct ncr53c9x_softc *, int); 112 void pcscp_write_reg(struct ncr53c9x_softc *, int, u_char); 113 int pcscp_dma_isintr(struct ncr53c9x_softc *); 114 void pcscp_dma_reset(struct ncr53c9x_softc *); 115 int pcscp_dma_intr(struct ncr53c9x_softc *); 116 int pcscp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 117 size_t *, int, size_t *); 118 void pcscp_dma_go(struct ncr53c9x_softc *); 119 void pcscp_dma_stop(struct ncr53c9x_softc *); 120 int pcscp_dma_isactive(struct ncr53c9x_softc *); 121 122 struct ncr53c9x_glue pcscp_glue = { 123 pcscp_read_reg, 124 pcscp_write_reg, 125 pcscp_dma_isintr, 126 pcscp_dma_reset, 127 pcscp_dma_intr, 128 pcscp_dma_setup, 129 pcscp_dma_go, 130 pcscp_dma_stop, 131 pcscp_dma_isactive, 132 NULL, /* gl_clear_latched_intr */ 133 }; 134 135 int 136 pcscp_match(struct device *parent, void *match, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 140 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 141 return 0; 142 143 switch (PCI_PRODUCT(pa->pa_id)) { 144 case PCI_PRODUCT_AMD_PCSCSI_PCI: 145 return 1; 146 } 147 return 0; 148 } 149 150 /* 151 * Attach this instance, and then all the sub-devices 152 */ 153 void 154 pcscp_attach(struct device *parent, struct device *self, void *aux) 155 { 156 struct pci_attach_args *pa = aux; 157 struct pcscp_softc *esc = (void *)self; 158 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 159 bus_space_tag_t iot; 160 bus_space_handle_t ioh; 161 pci_intr_handle_t ih; 162 const char *intrstr; 163 bus_dma_segment_t seg; 164 int error, rseg; 165 166 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 167 &iot, &ioh, NULL, NULL, 0)) { 168 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 169 return; 170 } 171 172 sc->sc_glue = &pcscp_glue; 173 174 esc->sc_st = iot; 175 esc->sc_sh = ioh; 176 esc->sc_dmat = pa->pa_dmat; 177 178 /* 179 * XXX More of this should be in ncr53c9x_attach(), but 180 * XXX should we really poke around the chip that much in 181 * XXX the MI code? Think about this more... 182 */ 183 184 /* 185 * Set up static configuration info. 186 */ 187 188 /* 189 * XXX should read configuration from EEPROM? 190 * 191 * MI ncr53c9x driver does not support configuration 192 * per each target device, though... 193 */ 194 sc->sc_id = 7; 195 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 196 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 197 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 198 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 199 sc->sc_rev = NCR_VARIANT_AM53C974; 200 sc->sc_features = NCR_F_FASTSCSI; 201 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 202 sc->sc_freq = 40; /* MHz */ 203 204 /* 205 * XXX minsync and maxxfer _should_ be set up in MI code, 206 * XXX but it appears to have some dependency on what sort 207 * XXX of DMA we're hooked up to, etc. 208 */ 209 210 /* 211 * This is the value used to start sync negotiations 212 * Note that the NCR register "SYNCTP" is programmed 213 * in "clocks per byte", and has a minimum value of 4. 214 * The SCSI period used in negotiation is one-fourth 215 * of the time (in nanoseconds) needed to transfer one byte. 216 * Since the chip's clock is given in MHz, we have the following 217 * formula: 4 * period = (1000 / freq) * 4 218 */ 219 220 sc->sc_minsync = 1000 / sc->sc_freq; 221 222 /* Really no limit, but since we want to fit into the TCR... */ 223 sc->sc_maxxfer = 16 * 1024 * 1024; 224 225 /* 226 * Create the DMA maps for the data transfers. 227 */ 228 229 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 230 #define MDL_SEG_OFFSET 0x0FFF 231 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 232 233 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE, 234 MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 235 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 236 return; 237 } 238 239 /* 240 * Allocate and map memory for the MDL. 241 */ 242 243 if ((error = bus_dmamem_alloc(esc->sc_dmat, 244 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 245 BUS_DMA_NOWAIT)) != 0) { 246 printf("%s: unable to allocate memory for the MDL, " 247 "error = %d\n", sc->sc_dev.dv_xname, error); 248 goto fail_0; 249 } 250 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 251 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 252 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 253 printf("%s: unable to map the MDL memory, error = %d\n", 254 sc->sc_dev.dv_xname, error); 255 goto fail_1; 256 } 257 if ((error = bus_dmamap_create(esc->sc_dmat, 258 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 259 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 260 printf("%s: unable to map_create for the MDL, error = %d\n", 261 sc->sc_dev.dv_xname, error); 262 goto fail_2; 263 } 264 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 265 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 266 NULL, BUS_DMA_NOWAIT)) != 0) { 267 printf("%s: unable to load for the MDL, error = %d\n", 268 sc->sc_dev.dv_xname, error); 269 goto fail_3; 270 } 271 272 /* map and establish interrupt */ 273 if (pci_intr_map(pa, &ih)) { 274 printf(": couldn't map interrupt\n"); 275 goto fail_4; 276 } 277 278 intrstr = pci_intr_string(pa->pa_pc, ih); 279 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 280 ncr53c9x_intr, esc, sc->sc_dev.dv_xname); 281 if (esc->sc_ih == NULL) { 282 printf(": couldn't establish interrupt"); 283 if (intrstr != NULL) 284 printf(" at %s", intrstr); 285 printf("\n"); 286 goto fail_4; 287 } 288 if (intrstr != NULL) 289 printf(": %s\n", intrstr); 290 291 /* Do the common parts of attachment. */ 292 printf("%s", sc->sc_dev.dv_xname); 293 294 ncr53c9x_attach(sc); 295 296 /* Turn on target selection using the `dma' method */ 297 sc->sc_features |= NCR_F_DMASELECT; 298 299 return; 300 301 fail_4: 302 bus_dmamap_unload(esc->sc_dmat, esc->sc_mdldmap); 303 fail_3: 304 bus_dmamap_destroy(esc->sc_dmat, esc->sc_mdldmap); 305 fail_2: 306 bus_dmamem_unmap(esc->sc_dmat, (caddr_t)esc->sc_mdldmap, 307 sizeof(uint32_t) * MDL_SIZE); 308 fail_1: 309 bus_dmamem_free(esc->sc_dmat, &seg, rseg); 310 fail_0: 311 bus_dmamap_destroy(esc->sc_dmat, esc->sc_xfermap); 312 } 313 314 /* 315 * Glue functions. 316 */ 317 318 u_char 319 pcscp_read_reg(struct ncr53c9x_softc *sc, int reg) 320 { 321 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 322 323 return PCSCP_READ_REG(esc, reg); 324 } 325 326 void 327 pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 328 { 329 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 330 331 PCSCP_WRITE_REG(esc, reg, v); 332 } 333 334 int 335 pcscp_dma_isintr(struct ncr53c9x_softc *sc) 336 { 337 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 338 339 return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0; 340 } 341 342 void 343 pcscp_dma_reset(struct ncr53c9x_softc *sc) 344 { 345 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 346 347 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 348 349 esc->sc_active = 0; 350 } 351 352 int 353 pcscp_dma_intr(struct ncr53c9x_softc *sc) 354 { 355 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 356 int trans, resid, i; 357 bus_dmamap_t dmap = esc->sc_xfermap; 358 int datain = esc->sc_datain; 359 u_int32_t dmastat; 360 char *p = NULL; 361 362 dmastat = READ_DMAREG(esc, DMA_STAT); 363 364 if (dmastat & DMASTAT_ERR) { 365 /* XXX not tested... */ 366 WRITE_DMAREG(esc, DMA_CMD, 367 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 368 369 printf("%s: error: DMA error detected; Aborting.\n", 370 sc->sc_dev.dv_xname); 371 bus_dmamap_unload(esc->sc_dmat, dmap); 372 return -1; 373 } 374 375 if (dmastat & DMASTAT_ABT) { 376 /* XXX What should be done? */ 377 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 378 WRITE_DMAREG(esc, DMA_CMD, 379 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 380 esc->sc_active = 0; 381 return 0; 382 } 383 384 #ifdef DIAGNOSTIC 385 /* This is an "assertion" :) */ 386 if (esc->sc_active == 0) 387 panic("pcscp dmaintr: DMA wasn't active"); 388 #endif 389 390 /* DMA has stopped */ 391 392 esc->sc_active = 0; 393 394 if (esc->sc_dmasize == 0) { 395 /* A "Transfer Pad" operation completed */ 396 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 397 PCSCP_READ_REG(esc, NCR_TCL) | 398 (PCSCP_READ_REG(esc, NCR_TCM) << 8), 399 PCSCP_READ_REG(esc, NCR_TCL), 400 PCSCP_READ_REG(esc, NCR_TCM))); 401 return 0; 402 } 403 404 resid = 0; 405 /* 406 * If a transfer onto the SCSI bus gets interrupted by the device 407 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 408 * as residual since the ESP counter registers get decremented as 409 * bytes are clocked into the FIFO. 410 */ 411 if (!datain && 412 (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 413 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 414 } 415 416 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 417 /* 418 * `Terminal count' is off, so read the residue 419 * out of the ESP counter registers. 420 */ 421 if (datain) { 422 resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 423 while (resid > 1) 424 resid = 425 PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 426 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 427 (datain ? DMACMD_DIR : 0)); 428 429 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 430 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 431 break; 432 433 /* See the below comments... */ 434 if (resid) 435 p = *esc->sc_dmaaddr; 436 } 437 438 resid += PCSCP_READ_REG(esc, NCR_TCL) | 439 (PCSCP_READ_REG(esc, NCR_TCM) << 8) | 440 (PCSCP_READ_REG(esc, NCR_TCH) << 16); 441 } else { 442 while ((dmastat & DMASTAT_DONE) == 0) 443 dmastat = READ_DMAREG(esc, DMA_STAT); 444 } 445 446 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 447 448 /* sync MDL */ 449 bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap, 450 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE); 451 /* sync transfer buffer */ 452 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 453 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 454 bus_dmamap_unload(esc->sc_dmat, dmap); 455 456 trans = esc->sc_dmasize - resid; 457 458 /* 459 * From the technical manual notes: 460 * 461 * `In some odd byte conditions, one residual byte will be left 462 * in the SCSI FIFO, and the FIFO flags will never count to 0. 463 * When this happens, the residual byte should be retrieved 464 * via PIO following completion of the BLAST operation.' 465 */ 466 467 if (p) { 468 p += trans; 469 *p = PCSCP_READ_REG(esc, NCR_FIFO); 470 trans++; 471 } 472 473 if (trans < 0) { /* transferred < 0 ? */ 474 #if 0 475 /* 476 * This situation can happen in perfectly normal operation 477 * if the ESP is reselected while using DMA to select 478 * another target. As such, don't print the warning. 479 */ 480 printf("%s: xfer (%d) > req (%d)\n", 481 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 482 #endif 483 trans = esc->sc_dmasize; 484 } 485 486 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 487 PCSCP_READ_REG(esc, NCR_TCL), 488 PCSCP_READ_REG(esc, NCR_TCM), 489 PCSCP_READ_REG(esc, NCR_TCH), 490 trans, resid)); 491 492 *esc->sc_dmalen -= trans; 493 *esc->sc_dmaaddr += trans; 494 495 return 0; 496 } 497 498 int 499 pcscp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 500 int datain, size_t *dmasize) 501 { 502 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 503 bus_dmamap_t dmap = esc->sc_xfermap; 504 u_int32_t *mdl; 505 int error, nseg, seg; 506 bus_addr_t s_offset, s_addr; 507 508 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 509 510 esc->sc_dmaaddr = addr; 511 esc->sc_dmalen = len; 512 esc->sc_dmasize = *dmasize; 513 esc->sc_datain = datain; 514 515 #ifdef DIAGNOSTIC 516 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 517 panic("pcscp: transfer size too large"); 518 #endif 519 520 /* 521 * No need to set up DMA in `Transfer Pad' operation. 522 * (case of *dmasize == 0) 523 */ 524 if (*dmasize == 0) 525 return 0; 526 527 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 528 *esc->sc_dmalen, NULL, 529 ((sc->sc_nexus->xs->flags & SCSI_NOSLEEP) ? 530 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 531 ((sc->sc_nexus->xs->flags & SCSI_DATA_IN) ? 532 BUS_DMA_READ : BUS_DMA_WRITE)); 533 if (error) { 534 printf("%s: unable to load dmamap, error = %d\n", 535 sc->sc_dev.dv_xname, error); 536 return error; 537 } 538 539 /* set transfer length */ 540 WRITE_DMAREG(esc, DMA_STC, *dmasize); 541 542 /* set up MDL */ 543 mdl = esc->sc_mdladdr; 544 nseg = dmap->dm_nsegs; 545 546 /* the first segment is possibly not aligned with 4k MDL boundary */ 547 s_addr = dmap->dm_segs[0].ds_addr; 548 s_offset = s_addr & MDL_SEG_OFFSET; 549 s_addr -= s_offset; 550 551 /* set the first MDL and offset */ 552 WRITE_DMAREG(esc, DMA_SPA, s_offset); 553 *mdl++ = htole32(s_addr); 554 555 /* the rest dmamap segments are aligned with 4k boundary */ 556 for (seg = 1; seg < nseg; seg++) 557 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr); 558 559 return 0; 560 } 561 562 void 563 pcscp_dma_go(struct ncr53c9x_softc *sc) 564 { 565 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 566 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 567 int datain = esc->sc_datain; 568 569 /* No DMA transfer in Transfer Pad operation */ 570 if (esc->sc_dmasize == 0) 571 return; 572 573 /* sync transfer buffer */ 574 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 575 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 576 577 /* sync MDL */ 578 bus_dmamap_sync(esc->sc_dmat, mdldmap, 579 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 580 581 /* set Starting MDL Address */ 582 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 583 584 /* set DMA command register bits */ 585 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 586 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 587 /* DMACMD_INTE | */ 588 (datain ? DMACMD_DIR : 0)); 589 590 /* issue DMA start command */ 591 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 592 /* DMACMD_INTE | */ 593 (datain ? DMACMD_DIR : 0)); 594 595 esc->sc_active = 1; 596 } 597 598 void 599 pcscp_dma_stop(struct ncr53c9x_softc *sc) 600 { 601 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 602 603 /* dma stop */ 604 /* XXX What should we do here ? */ 605 WRITE_DMAREG(esc, DMA_CMD, 606 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 607 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfermap); 608 609 esc->sc_active = 0; 610 } 611 612 int 613 pcscp_dma_isactive(struct ncr53c9x_softc *sc) 614 { 615 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 616 617 /* XXX should check esc->sc_active? */ 618 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 619 return 1; 620 return 0; 621 } 622