1 /* $OpenBSD: ppb.c,v 1.68 2019/04/23 19:37:35 patrick Exp $ */ 2 /* $NetBSD: ppb.c,v 1.16 1997/06/06 23:48:05 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Christopher G. Demetriou 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/task.h> 38 #include <sys/timeout.h> 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/ppbreg.h> 44 45 #ifndef PCI_IO_START 46 #define PCI_IO_START 0 47 #endif 48 49 #ifndef PCI_IO_END 50 #define PCI_IO_END 0xffffffff 51 #endif 52 53 #ifndef PCI_MEM_START 54 #define PCI_MEM_START 0 55 #endif 56 57 #ifndef PCI_MEM_END 58 #define PCI_MEM_END 0xffffffff 59 #endif 60 61 #define PPB_EXNAMLEN 32 62 63 struct ppb_softc { 64 struct device sc_dev; /* generic device glue */ 65 pci_chipset_tag_t sc_pc; /* our PCI chipset... */ 66 pcitag_t sc_tag; /* ...and tag. */ 67 pci_intr_handle_t sc_ih[4]; 68 void *sc_intrhand; 69 struct extent *sc_parent_busex; 70 struct extent *sc_busex; 71 struct extent *sc_ioex; 72 struct extent *sc_memex; 73 struct extent *sc_pmemex; 74 struct device *sc_psc; 75 int sc_cap_off; 76 struct task sc_insert_task; 77 struct task sc_rescan_task; 78 struct task sc_remove_task; 79 struct timeout sc_to; 80 81 u_long sc_busnum; 82 u_long sc_busrange; 83 84 bus_addr_t sc_iobase, sc_iolimit; 85 bus_addr_t sc_membase, sc_memlimit; 86 bus_addr_t sc_pmembase, sc_pmemlimit; 87 88 pcireg_t sc_csr; 89 pcireg_t sc_bhlcr; 90 pcireg_t sc_bir; 91 pcireg_t sc_bcr; 92 pcireg_t sc_int; 93 pcireg_t sc_slcsr; 94 pcireg_t sc_msi_mc; 95 pcireg_t sc_msi_ma; 96 pcireg_t sc_msi_mau32; 97 pcireg_t sc_msi_md; 98 int sc_pmcsr_state; 99 }; 100 101 int ppbmatch(struct device *, void *, void *); 102 void ppbattach(struct device *, struct device *, void *); 103 int ppbdetach(struct device *self, int flags); 104 int ppbactivate(struct device *self, int act); 105 106 struct cfattach ppb_ca = { 107 sizeof(struct ppb_softc), ppbmatch, ppbattach, ppbdetach, ppbactivate 108 }; 109 110 struct cfdriver ppb_cd = { 111 NULL, "ppb", DV_DULL 112 }; 113 114 void ppb_alloc_busrange(struct ppb_softc *, struct pci_attach_args *, 115 pcireg_t *); 116 void ppb_alloc_resources(struct ppb_softc *, struct pci_attach_args *); 117 int ppb_intr(void *); 118 void ppb_hotplug_insert(void *); 119 void ppb_hotplug_insert_finish(void *); 120 void ppb_hotplug_rescan(void *); 121 void ppb_hotplug_remove(void *); 122 int ppbprint(void *, const char *pnp); 123 124 int 125 ppbmatch(struct device *parent, void *match, void *aux) 126 { 127 struct pci_attach_args *pa = aux; 128 129 /* 130 * This device is mislabeled. It is not a PCI bridge. 131 */ 132 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH && 133 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT82C586_PWR) 134 return (0); 135 /* 136 * Check the ID register to see that it's a PCI bridge. 137 * If it is, we assume that we can deal with it; it _should_ 138 * work in a standardized way... 139 */ 140 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 141 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI) 142 return (1); 143 144 return (0); 145 } 146 147 void 148 ppbattach(struct device *parent, struct device *self, void *aux) 149 { 150 struct ppb_softc *sc = (struct ppb_softc *)self; 151 struct pci_attach_args *pa = aux; 152 pci_chipset_tag_t pc = pa->pa_pc; 153 struct pcibus_attach_args pba; 154 pci_interface_t interface; 155 pci_intr_handle_t ih; 156 pcireg_t busdata, reg, blr; 157 char *name; 158 int sec, sub; 159 int pin; 160 161 sc->sc_pc = pc; 162 sc->sc_tag = pa->pa_tag; 163 164 busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO); 165 166 /* 167 * When the bus number isn't configured, try to allocate one 168 * ourselves. 169 */ 170 if (busdata == 0 && pa->pa_busex) 171 ppb_alloc_busrange(sc, pa, &busdata); 172 173 /* 174 * When the bus number still isn't set correctly, give up. 175 */ 176 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 177 printf(": not configured by system firmware\n"); 178 return; 179 } 180 181 #if 0 182 /* 183 * XXX can't do this, because we're not given our bus number 184 * (we shouldn't need it), and because we've no way to 185 * decompose our tag. 186 */ 187 /* sanity check. */ 188 if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata)) 189 panic("ppbattach: bus in tag (%d) != bus in reg (%d)", 190 pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata)); 191 #endif 192 193 sec = PPB_BUSINFO_SECONDARY(busdata); 194 sub = PPB_BUSINFO_SUBORDINATE(busdata); 195 if (sub > sec) { 196 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 197 if (name) { 198 snprintf(name, PPB_EXNAMLEN, "%s pcibus", sc->sc_dev.dv_xname); 199 sc->sc_busex = extent_create(name, 0, 0xff, 200 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 201 extent_free(sc->sc_busex, sec + 1, 202 sub - sec, EX_NOWAIT); 203 } 204 } 205 206 /* Check for PCI Express capabilities and setup hotplug support. */ 207 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 208 &sc->sc_cap_off, ®) && (reg & PCI_PCIE_XCAP_SI)) { 209 task_set(&sc->sc_insert_task, ppb_hotplug_insert, sc); 210 task_set(&sc->sc_rescan_task, ppb_hotplug_rescan, sc); 211 task_set(&sc->sc_remove_task, ppb_hotplug_remove, sc); 212 timeout_set(&sc->sc_to, ppb_hotplug_insert_finish, sc); 213 214 #ifdef __i386__ 215 if (pci_intr_map(pa, &ih) == 0) 216 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO, 217 ppb_intr, sc, self->dv_xname); 218 #else 219 if (pci_intr_map_msi(pa, &ih) == 0 || 220 pci_intr_map(pa, &ih) == 0) 221 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO, 222 ppb_intr, sc, self->dv_xname); 223 #endif 224 225 if (sc->sc_intrhand) { 226 printf(": %s", pci_intr_string(pc, ih)); 227 228 /* Enable hotplug interrupt. */ 229 reg = pci_conf_read(pc, pa->pa_tag, 230 sc->sc_cap_off + PCI_PCIE_SLCSR); 231 reg |= (PCI_PCIE_SLCSR_HPE | PCI_PCIE_SLCSR_PDE); 232 pci_conf_write(pc, pa->pa_tag, 233 sc->sc_cap_off + PCI_PCIE_SLCSR, reg); 234 } 235 } 236 237 printf("\n"); 238 239 interface = PCI_INTERFACE(pa->pa_class); 240 241 /* 242 * The Intel 82801BAM Hub-to-PCI can decode subtractively but 243 * doesn't advertise itself as such. 244 */ 245 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 246 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BA_HPB || 247 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BAM_HPB)) 248 interface = PPB_INTERFACE_SUBTRACTIVE; 249 250 if (interface != PPB_INTERFACE_SUBTRACTIVE) 251 ppb_alloc_resources(sc, pa); 252 253 for (pin = PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_D; pin++) { 254 pa->pa_intrpin = pa->pa_rawintrpin = pin; 255 pa->pa_intrline = 0; 256 pci_intr_map(pa, &sc->sc_ih[pin - PCI_INTERRUPT_PIN_A]); 257 } 258 259 /* 260 * The UltraSPARC-IIi APB doesn't implement the standard 261 * address range registers. 262 */ 263 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 264 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_SIMBA) 265 goto attach; 266 267 /* Figure out the I/O address range of the bridge. */ 268 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IOSTATUS); 269 sc->sc_iobase = (blr & 0x000000f0) << 8; 270 sc->sc_iolimit = (blr & 0x000f000) | 0x00000fff; 271 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IO_HI); 272 sc->sc_iobase |= (blr & 0x0000ffff) << 16; 273 sc->sc_iolimit |= (blr & 0xffff0000); 274 if (sc->sc_iolimit > sc->sc_iobase) { 275 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 276 if (name) { 277 snprintf(name, PPB_EXNAMLEN, "%s pciio", sc->sc_dev.dv_xname); 278 sc->sc_ioex = extent_create(name, 0, 0xffffffff, 279 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 280 extent_free(sc->sc_ioex, sc->sc_iobase, 281 sc->sc_iolimit - sc->sc_iobase + 1, EX_NOWAIT); 282 } 283 } 284 285 /* Figure out the memory mapped I/O address range of the bridge. */ 286 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_MEM); 287 sc->sc_membase = (blr & 0x0000fff0) << 16; 288 sc->sc_memlimit = (blr & 0xfff00000) | 0x000fffff; 289 if (sc->sc_memlimit > sc->sc_membase) { 290 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 291 if (name) { 292 snprintf(name, PPB_EXNAMLEN, "%s pcimem", sc->sc_dev.dv_xname); 293 sc->sc_memex = extent_create(name, 0, (u_long)-1L, 294 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 295 extent_free(sc->sc_memex, sc->sc_membase, 296 sc->sc_memlimit - sc->sc_membase + 1, 297 EX_NOWAIT); 298 } 299 } 300 301 /* Figure out the prefetchable MMI/O address range of the bridge. */ 302 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFMEM); 303 sc->sc_pmembase = (blr & 0x0000fff0) << 16; 304 sc->sc_pmemlimit = (blr & 0xfff00000) | 0x000fffff; 305 #ifdef __LP64__ 306 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFBASE_HI32); 307 sc->sc_pmembase |= ((uint64_t)blr) << 32; 308 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFLIM_HI32); 309 sc->sc_pmemlimit |= ((uint64_t)blr) << 32; 310 #endif 311 if (sc->sc_pmemlimit > sc->sc_pmembase) { 312 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 313 if (name) { 314 snprintf(name, PPB_EXNAMLEN, "%s pcipmem", sc->sc_dev.dv_xname); 315 sc->sc_pmemex = extent_create(name, 0, (u_long)-1L, 316 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 317 extent_free(sc->sc_pmemex, sc->sc_pmembase, 318 sc->sc_pmemlimit - sc->sc_pmembase + 1, 319 EX_NOWAIT); 320 } 321 } 322 323 if (interface == PPB_INTERFACE_SUBTRACTIVE) { 324 if (sc->sc_ioex == NULL) 325 sc->sc_ioex = pa->pa_ioex; 326 if (sc->sc_memex == NULL) 327 sc->sc_memex = pa->pa_memex; 328 } 329 330 attach: 331 /* 332 * Attach the PCI bus that hangs off of it. 333 * 334 * XXX Don't pass-through Memory Read Multiple. Should we? 335 * XXX Consult the spec... 336 */ 337 bzero(&pba, sizeof(pba)); 338 pba.pba_busname = "pci"; 339 pba.pba_iot = pa->pa_iot; 340 pba.pba_memt = pa->pa_memt; 341 pba.pba_dmat = pa->pa_dmat; 342 pba.pba_pc = pc; 343 pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY; 344 pba.pba_busex = sc->sc_busex; 345 pba.pba_ioex = sc->sc_ioex; 346 pba.pba_memex = sc->sc_memex; 347 pba.pba_pmemex = sc->sc_pmemex; 348 pba.pba_domain = pa->pa_domain; 349 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 350 pba.pba_bridgeih = sc->sc_ih; 351 pba.pba_bridgetag = &sc->sc_tag; 352 pba.pba_intrswiz = pa->pa_intrswiz; 353 pba.pba_intrtag = pa->pa_intrtag; 354 355 sc->sc_psc = config_found(self, &pba, ppbprint); 356 } 357 358 int 359 ppbdetach(struct device *self, int flags) 360 { 361 struct ppb_softc *sc = (struct ppb_softc *)self; 362 char *name; 363 int rv; 364 365 if (sc->sc_intrhand) 366 pci_intr_disestablish(sc->sc_pc, sc->sc_intrhand); 367 368 rv = config_detach_children(self, flags); 369 370 if (sc->sc_busex) { 371 name = sc->sc_busex->ex_name; 372 extent_destroy(sc->sc_busex); 373 free(name, M_DEVBUF, PPB_EXNAMLEN); 374 } 375 376 if (sc->sc_ioex) { 377 name = sc->sc_ioex->ex_name; 378 extent_destroy(sc->sc_ioex); 379 free(name, M_DEVBUF, PPB_EXNAMLEN); 380 } 381 382 if (sc->sc_memex) { 383 name = sc->sc_memex->ex_name; 384 extent_destroy(sc->sc_memex); 385 free(name, M_DEVBUF, PPB_EXNAMLEN); 386 } 387 388 if (sc->sc_pmemex) { 389 name = sc->sc_pmemex->ex_name; 390 extent_destroy(sc->sc_pmemex); 391 free(name, M_DEVBUF, PPB_EXNAMLEN); 392 } 393 394 if (sc->sc_parent_busex) 395 extent_free(sc->sc_parent_busex, sc->sc_busnum, 396 sc->sc_busrange, EX_NOWAIT); 397 398 return (rv); 399 } 400 401 int 402 ppbactivate(struct device *self, int act) 403 { 404 struct ppb_softc *sc = (void *)self; 405 pci_chipset_tag_t pc = sc->sc_pc; 406 pcitag_t tag = sc->sc_tag; 407 pcireg_t blr, reg; 408 int off, rv = 0; 409 410 switch (act) { 411 case DVACT_SUSPEND: 412 rv = config_activate_children(self, act); 413 414 /* Save registers that may get lost. */ 415 sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 416 sc->sc_bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 417 sc->sc_bir = pci_conf_read(pc, tag, PPB_REG_BUSINFO); 418 sc->sc_bcr = pci_conf_read(pc, tag, PPB_REG_BRIDGECONTROL); 419 sc->sc_int = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 420 if (sc->sc_cap_off) 421 sc->sc_slcsr = pci_conf_read(pc, tag, 422 sc->sc_cap_off + PCI_PCIE_SLCSR); 423 424 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) { 425 sc->sc_msi_ma = pci_conf_read(pc, tag, 426 off + PCI_MSI_MA); 427 if (reg & PCI_MSI_MC_C64) { 428 sc->sc_msi_mau32 = pci_conf_read(pc, tag, 429 off + PCI_MSI_MAU32); 430 sc->sc_msi_md = pci_conf_read(pc, tag, 431 off + PCI_MSI_MD64); 432 } else { 433 sc->sc_msi_md = pci_conf_read(pc, tag, 434 off + PCI_MSI_MD32); 435 } 436 sc->sc_msi_mc = reg; 437 } 438 break; 439 case DVACT_RESUME: 440 if (pci_dopm) { 441 /* Restore power. */ 442 pci_set_powerstate(pc, tag, sc->sc_pmcsr_state); 443 } 444 445 /* Restore the registers saved above. */ 446 pci_conf_write(pc, tag, PCI_BHLC_REG, sc->sc_bhlcr); 447 pci_conf_write(pc, tag, PPB_REG_BUSINFO, sc->sc_bir); 448 pci_conf_write(pc, tag, PPB_REG_BRIDGECONTROL, sc->sc_bcr); 449 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, sc->sc_int); 450 if (sc->sc_cap_off) 451 pci_conf_write(pc, tag, 452 sc->sc_cap_off + PCI_PCIE_SLCSR, sc->sc_slcsr); 453 454 /* Restore I/O window. */ 455 blr = pci_conf_read(pc, tag, PPB_REG_IOSTATUS); 456 blr &= 0xffff0000; 457 blr |= sc->sc_iolimit & PPB_IO_MASK; 458 blr |= (sc->sc_iobase >> PPB_IO_SHIFT); 459 pci_conf_write(pc, tag, PPB_REG_IOSTATUS, blr); 460 blr = (sc->sc_iobase & 0xffff0000) >> 16; 461 blr |= sc->sc_iolimit & 0xffff0000; 462 pci_conf_write(pc, tag, PPB_REG_IO_HI, blr); 463 464 /* Restore memory mapped I/O window. */ 465 blr = sc->sc_memlimit & PPB_MEM_MASK; 466 blr |= (sc->sc_membase >> PPB_MEM_SHIFT); 467 pci_conf_write(pc, tag, PPB_REG_MEM, blr); 468 469 /* Restore prefetchable MMI/O window. */ 470 blr = sc->sc_pmemlimit & PPB_MEM_MASK; 471 blr |= ((sc->sc_pmembase & PPB_MEM_MASK) >> PPB_MEM_SHIFT); 472 pci_conf_write(pc, tag, PPB_REG_PREFMEM, blr); 473 #ifdef __LP64__ 474 pci_conf_write(pc, tag, PPB_REG_PREFBASE_HI32, 475 sc->sc_pmembase >> 32); 476 pci_conf_write(pc, tag, PPB_REG_PREFLIM_HI32, 477 sc->sc_pmemlimit >> 32); 478 #endif 479 480 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) { 481 pci_conf_write(pc, tag, off + PCI_MSI_MA, 482 sc->sc_msi_ma); 483 if (reg & PCI_MSI_MC_C64) { 484 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 485 sc->sc_msi_mau32); 486 pci_conf_write(pc, tag, off + PCI_MSI_MD64, 487 sc->sc_msi_md); 488 } else { 489 pci_conf_write(pc, tag, off + PCI_MSI_MD32, 490 sc->sc_msi_md); 491 } 492 pci_conf_write(pc, tag, off + PCI_MSI_MC, 493 sc->sc_msi_mc); 494 } 495 496 /* 497 * Restore command register last to avoid exposing 498 * uninitialised windows. 499 */ 500 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 501 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 502 (reg & 0xffff0000) | (sc->sc_csr & 0x0000ffff)); 503 504 rv = config_activate_children(self, act); 505 break; 506 case DVACT_POWERDOWN: 507 rv = config_activate_children(self, act); 508 509 if (pci_dopm) { 510 /* 511 * Place the bridge into the lowest possible 512 * power state. 513 */ 514 sc->sc_pmcsr_state = pci_get_powerstate(pc, tag); 515 pci_set_powerstate(pc, tag, 516 pci_min_powerstate(pc, tag)); 517 } 518 break; 519 default: 520 rv = config_activate_children(self, act); 521 break; 522 } 523 return (rv); 524 } 525 526 void 527 ppb_alloc_busrange(struct ppb_softc *sc, struct pci_attach_args *pa, 528 pcireg_t *busdata) 529 { 530 pci_chipset_tag_t pc = sc->sc_pc; 531 u_long busnum, busrange; 532 533 for (busrange = 16; busrange > 0; busrange >>= 1) { 534 if (extent_alloc(pa->pa_busex, busrange, 1, 0, 0, 535 EX_NOWAIT, &busnum)) 536 continue; 537 sc->sc_parent_busex = pa->pa_busex; 538 sc->sc_busnum = busnum; 539 sc->sc_busrange = busrange; 540 *busdata |= pa->pa_bus; 541 *busdata |= (busnum << 8); 542 *busdata |= ((busnum + busrange - 1) << 16); 543 pci_conf_write(pc, pa->pa_tag, PPB_REG_BUSINFO, *busdata); 544 return; 545 } 546 } 547 548 void 549 ppb_alloc_resources(struct ppb_softc *sc, struct pci_attach_args *pa) 550 { 551 pci_chipset_tag_t pc = sc->sc_pc; 552 pcireg_t id, busdata, blr, bhlcr, type, csr; 553 pcireg_t addr, mask; 554 pcitag_t tag; 555 int bus, dev; 556 int reg, reg_start, reg_end, reg_rom; 557 int io_count = 0; 558 int mem_count = 0; 559 bus_addr_t start, end; 560 u_long base, size; 561 562 if (pa->pa_memex == NULL) 563 return; 564 565 busdata = pci_conf_read(pc, sc->sc_tag, PPB_REG_BUSINFO); 566 bus = PPB_BUSINFO_SECONDARY(busdata); 567 if (bus == 0) 568 return; 569 570 /* 571 * Count number of devices. If there are no devices behind 572 * this bridge, there's no point in allocating any address 573 * space. 574 */ 575 for (dev = 0; dev < pci_bus_maxdevs(pc, bus); dev++) { 576 tag = pci_make_tag(pc, bus, dev, 0); 577 id = pci_conf_read(pc, tag, PCI_ID_REG); 578 579 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID || 580 PCI_VENDOR(id) == 0) 581 continue; 582 583 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 584 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 585 case 0: 586 reg_start = PCI_MAPREG_START; 587 reg_end = PCI_MAPREG_END; 588 reg_rom = PCI_ROM_REG; 589 break; 590 case 1: /* PCI-PCI bridge */ 591 reg_start = PCI_MAPREG_START; 592 reg_end = PCI_MAPREG_PPB_END; 593 reg_rom = 0; /* 0x38 */ 594 io_count++; 595 mem_count++; 596 break; 597 case 2: /* PCI-Cardbus bridge */ 598 reg_start = PCI_MAPREG_START; 599 reg_end = PCI_MAPREG_PCB_END; 600 reg_rom = 0; 601 io_count++; 602 mem_count++; 603 break; 604 default: 605 return; 606 } 607 608 for (reg = reg_start; reg < reg_end; reg += 4) { 609 if (pci_mapreg_probe(pc, tag, reg, &type) == 0) 610 continue; 611 612 if (type == PCI_MAPREG_TYPE_IO) 613 io_count++; 614 else 615 mem_count++; 616 } 617 618 if (reg_rom != 0) { 619 addr = pci_conf_read(pc, tag, reg_rom); 620 pci_conf_write(pc, tag, reg_rom, ~PCI_ROM_ENABLE); 621 mask = pci_conf_read(pc, tag, reg_rom); 622 pci_conf_write(pc, tag, reg_rom, addr); 623 if (PCI_ROM_SIZE(mask)) 624 mem_count++; 625 } 626 } 627 628 csr = pci_conf_read(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 629 630 /* 631 * Get the bridge in a consistent state. If memory mapped I/O or 632 * port I/O is disabled, disabled the associated windows as well. 633 */ 634 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 635 pci_conf_write(pc, sc->sc_tag, PPB_REG_MEM, 0x0000ffff); 636 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFMEM, 0x0000ffff); 637 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFBASE_HI32, 0); 638 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFLIM_HI32, 0); 639 } 640 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) { 641 pci_conf_write(pc, sc->sc_tag, PPB_REG_IOSTATUS, 0x000000ff); 642 pci_conf_write(pc, sc->sc_tag, PPB_REG_IO_HI, 0x0000ffff); 643 } 644 645 /* Allocate I/O address space if necessary. */ 646 if (io_count > 0 && pa->pa_ioex) { 647 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IOSTATUS); 648 sc->sc_iobase = (blr << PPB_IO_SHIFT) & PPB_IO_MASK; 649 sc->sc_iolimit = (blr & PPB_IO_MASK) | 0x00000fff; 650 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IO_HI); 651 sc->sc_iobase |= (blr & 0x0000ffff) << 16; 652 sc->sc_iolimit |= (blr & 0xffff0000); 653 if (sc->sc_iolimit < sc->sc_iobase || sc->sc_iobase == 0) { 654 start = max(PCI_IO_START, pa->pa_ioex->ex_start); 655 end = min(PCI_IO_END, pa->pa_ioex->ex_end); 656 for (size = 0x2000; size >= PPB_IO_MIN; size >>= 1) 657 if (extent_alloc_subregion(pa->pa_ioex, start, 658 end, size, size, 0, 0, 0, &base) == 0) 659 break; 660 if (size >= PPB_IO_MIN) { 661 sc->sc_iobase = base; 662 sc->sc_iolimit = base + size - 1; 663 blr = pci_conf_read(pc, sc->sc_tag, 664 PPB_REG_IOSTATUS); 665 blr &= 0xffff0000; 666 blr |= sc->sc_iolimit & PPB_IO_MASK; 667 blr |= (sc->sc_iobase >> PPB_IO_SHIFT); 668 pci_conf_write(pc, sc->sc_tag, 669 PPB_REG_IOSTATUS, blr); 670 blr = (sc->sc_iobase & 0xffff0000) >> 16; 671 blr |= sc->sc_iolimit & 0xffff0000; 672 pci_conf_write(pc, sc->sc_tag, 673 PPB_REG_IO_HI, blr); 674 675 csr |= PCI_COMMAND_IO_ENABLE; 676 } 677 } 678 } 679 680 /* Allocate memory mapped I/O address space if necessary. */ 681 if (mem_count > 0 && pa->pa_memex) { 682 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_MEM); 683 sc->sc_membase = (blr << PPB_MEM_SHIFT) & PPB_MEM_MASK; 684 sc->sc_memlimit = (blr & PPB_MEM_MASK) | 0x000fffff; 685 if (sc->sc_memlimit < sc->sc_membase || sc->sc_membase == 0) { 686 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 687 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 688 for (size = 0x2000000; size >= PPB_MEM_MIN; size >>= 1) 689 if (extent_alloc_subregion(pa->pa_memex, start, 690 end, size, size, 0, 0, 0, &base) == 0) 691 break; 692 if (size >= PPB_MEM_MIN) { 693 sc->sc_membase = base; 694 sc->sc_memlimit = base + size - 1; 695 blr = sc->sc_memlimit & PPB_MEM_MASK; 696 blr |= (sc->sc_membase >> PPB_MEM_SHIFT); 697 pci_conf_write(pc, sc->sc_tag, 698 PPB_REG_MEM, blr); 699 700 csr |= PCI_COMMAND_MEM_ENABLE; 701 } 702 } 703 } 704 705 /* Enable bus master. */ 706 csr |= PCI_COMMAND_MASTER_ENABLE; 707 708 pci_conf_write(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr); 709 } 710 711 int 712 ppb_intr(void *arg) 713 { 714 struct ppb_softc *sc = arg; 715 pcireg_t reg; 716 717 /* 718 * XXX ignore hotplug events while in autoconf. On some 719 * machines with onboard re(4), we get a bogus hotplug remove 720 * event when we reset that device. Ignoring that event makes 721 * sure we will not try to forcibly detach re(4) when it isn't 722 * ready to deal with that. 723 */ 724 if (cold) 725 return (0); 726 727 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 728 sc->sc_cap_off + PCI_PCIE_SLCSR); 729 if (reg & PCI_PCIE_SLCSR_PDC) { 730 if (reg & PCI_PCIE_SLCSR_PDS) 731 task_add(systq, &sc->sc_insert_task); 732 else 733 task_add(systq, &sc->sc_remove_task); 734 735 /* Clear interrupts. */ 736 pci_conf_write(sc->sc_pc, sc->sc_tag, 737 sc->sc_cap_off + PCI_PCIE_SLCSR, reg); 738 return (1); 739 } 740 741 return (0); 742 } 743 744 #ifdef PCI_MACHDEP_ENUMERATE_BUS 745 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 746 #else 747 extern int pci_enumerate_bus(struct pci_softc *, 748 int (*)(struct pci_attach_args *), struct pci_attach_args *); 749 #endif 750 751 void 752 ppb_hotplug_insert(void *xsc) 753 { 754 struct ppb_softc *sc = xsc; 755 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 756 757 if (!LIST_EMPTY(&psc->sc_devs)) 758 return; 759 760 /* XXX Powerup the card. */ 761 762 /* XXX Turn on LEDs. */ 763 764 /* Wait a second for things to settle. */ 765 timeout_add_sec(&sc->sc_to, 1); 766 } 767 768 void 769 ppb_hotplug_insert_finish(void *arg) 770 { 771 struct ppb_softc *sc = arg; 772 773 task_add(systq, &sc->sc_rescan_task); 774 } 775 776 void 777 ppb_hotplug_rescan(void *xsc) 778 { 779 struct ppb_softc *sc = xsc; 780 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 781 782 if (psc) 783 pci_enumerate_bus(psc, NULL, NULL); 784 } 785 786 void 787 ppb_hotplug_remove(void *xsc) 788 { 789 struct ppb_softc *sc = xsc; 790 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 791 792 if (psc) { 793 pci_detach_devices(psc, DETACH_FORCE); 794 795 /* 796 * XXX Allocate the entire window with EX_CONFLICTOK 797 * such that we can easily free it. 798 */ 799 if (sc->sc_ioex != NULL) { 800 extent_alloc_region(sc->sc_ioex, sc->sc_iobase, 801 sc->sc_iolimit - sc->sc_iobase + 1, 802 EX_NOWAIT | EX_CONFLICTOK); 803 extent_free(sc->sc_ioex, sc->sc_iobase, 804 sc->sc_iolimit - sc->sc_iobase + 1, EX_NOWAIT); 805 } 806 807 if (sc->sc_memex != NULL) { 808 extent_alloc_region(sc->sc_memex, sc->sc_membase, 809 sc->sc_memlimit - sc->sc_membase + 1, 810 EX_NOWAIT | EX_CONFLICTOK); 811 extent_free(sc->sc_memex, sc->sc_membase, 812 sc->sc_memlimit - sc->sc_membase + 1, EX_NOWAIT); 813 } 814 815 if (sc->sc_pmemex != NULL) { 816 extent_alloc_region(sc->sc_pmemex, sc->sc_pmembase, 817 sc->sc_pmemlimit - sc->sc_pmembase + 1, 818 EX_NOWAIT | EX_CONFLICTOK); 819 extent_free(sc->sc_pmemex, sc->sc_pmembase, 820 sc->sc_pmemlimit - sc->sc_pmembase + 1, EX_NOWAIT); 821 } 822 } 823 } 824 825 int 826 ppbprint(void *aux, const char *pnp) 827 { 828 struct pcibus_attach_args *pba = aux; 829 830 /* only PCIs can attach to PPBs; easy. */ 831 if (pnp) 832 printf("pci at %s", pnp); 833 printf(" bus %d", pba->pba_bus); 834 return (UNCONF); 835 } 836