1 /* $OpenBSD: ppb.c,v 1.72 2023/04/13 15:07:43 miod Exp $ */ 2 /* $NetBSD: ppb.c,v 1.16 1997/06/06 23:48:05 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Christopher G. Demetriou 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/task.h> 38 #include <sys/timeout.h> 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/ppbreg.h> 44 45 #ifdef __HAVE_FDT 46 #include <machine/fdt.h> 47 #include <dev/ofw/openfirm.h> 48 #endif 49 50 #ifndef PCI_IO_START 51 #define PCI_IO_START 0 52 #endif 53 54 #ifndef PCI_IO_END 55 #define PCI_IO_END 0xffffffff 56 #endif 57 58 #ifndef PCI_MEM_START 59 #define PCI_MEM_START 0 60 #endif 61 62 #ifndef PCI_MEM_END 63 #define PCI_MEM_END 0xffffffff 64 #endif 65 66 #define PPB_EXNAMLEN 32 67 68 struct ppb_softc { 69 struct device sc_dev; /* generic device glue */ 70 pci_chipset_tag_t sc_pc; /* our PCI chipset... */ 71 pcitag_t sc_tag; /* ...and tag. */ 72 pci_intr_handle_t sc_ih[4]; 73 void *sc_intrhand; 74 struct extent *sc_parent_busex; 75 struct extent *sc_busex; 76 struct extent *sc_ioex; 77 struct extent *sc_memex; 78 struct extent *sc_pmemex; 79 struct device *sc_psc; 80 int sc_cap_off; 81 struct task sc_insert_task; 82 struct task sc_rescan_task; 83 struct task sc_remove_task; 84 struct timeout sc_to; 85 86 u_long sc_busnum; 87 u_long sc_busrange; 88 89 bus_addr_t sc_iobase, sc_iolimit; 90 bus_addr_t sc_membase, sc_memlimit; 91 bus_addr_t sc_pmembase, sc_pmemlimit; 92 93 pcireg_t sc_csr; 94 pcireg_t sc_bhlcr; 95 pcireg_t sc_bir; 96 pcireg_t sc_bcr; 97 pcireg_t sc_int; 98 pcireg_t sc_slcsr; 99 pcireg_t sc_msi_mc; 100 pcireg_t sc_msi_ma; 101 pcireg_t sc_msi_mau32; 102 pcireg_t sc_msi_md; 103 int sc_pmcsr_state; 104 }; 105 106 int ppbmatch(struct device *, void *, void *); 107 void ppbattach(struct device *, struct device *, void *); 108 int ppbdetach(struct device *self, int flags); 109 int ppbactivate(struct device *self, int act); 110 111 const struct cfattach ppb_ca = { 112 sizeof(struct ppb_softc), ppbmatch, ppbattach, ppbdetach, ppbactivate 113 }; 114 115 struct cfdriver ppb_cd = { 116 NULL, "ppb", DV_DULL 117 }; 118 119 void ppb_alloc_busrange(struct ppb_softc *, struct pci_attach_args *, 120 pcireg_t *); 121 void ppb_alloc_resources(struct ppb_softc *, struct pci_attach_args *); 122 int ppb_intr(void *); 123 void ppb_hotplug_insert(void *); 124 void ppb_hotplug_insert_finish(void *); 125 void ppb_hotplug_rescan(void *); 126 void ppb_hotplug_remove(void *); 127 int ppbprint(void *, const char *pnp); 128 129 int 130 ppbmatch(struct device *parent, void *match, void *aux) 131 { 132 struct pci_attach_args *pa = aux; 133 134 /* 135 * This device is mislabeled. It is not a PCI bridge. 136 */ 137 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH && 138 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT82C586_PWR) 139 return (0); 140 /* 141 * Check the ID register to see that it's a PCI bridge. 142 * If it is, we assume that we can deal with it; it _should_ 143 * work in a standardized way... 144 */ 145 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 146 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI) 147 return (1); 148 149 return (0); 150 } 151 152 void 153 ppbattach(struct device *parent, struct device *self, void *aux) 154 { 155 struct ppb_softc *sc = (struct ppb_softc *)self; 156 struct pci_attach_args *pa = aux; 157 pci_chipset_tag_t pc = pa->pa_pc; 158 struct pcibus_attach_args pba; 159 pci_interface_t interface; 160 pci_intr_handle_t ih; 161 pcireg_t busdata, reg, blr; 162 char *name; 163 int sec, sub; 164 int pin; 165 166 sc->sc_pc = pc; 167 sc->sc_tag = pa->pa_tag; 168 169 busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO); 170 171 /* 172 * When the bus number isn't configured, try to allocate one 173 * ourselves. 174 */ 175 if (busdata == 0 && pa->pa_busex) 176 ppb_alloc_busrange(sc, pa, &busdata); 177 178 /* 179 * When the bus number still isn't set correctly, give up. 180 */ 181 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 182 printf(": not configured by system firmware\n"); 183 return; 184 } 185 186 #if 0 187 /* 188 * XXX can't do this, because we're not given our bus number 189 * (we shouldn't need it), and because we've no way to 190 * decompose our tag. 191 */ 192 /* sanity check. */ 193 if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata)) 194 panic("ppbattach: bus in tag (%d) != bus in reg (%d)", 195 pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata)); 196 #endif 197 198 sec = PPB_BUSINFO_SECONDARY(busdata); 199 sub = PPB_BUSINFO_SUBORDINATE(busdata); 200 if (sub > sec) { 201 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 202 if (name) { 203 snprintf(name, PPB_EXNAMLEN, "%s pcibus", sc->sc_dev.dv_xname); 204 sc->sc_busex = extent_create(name, 0, 0xff, 205 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 206 extent_free(sc->sc_busex, sec + 1, 207 sub - sec, EX_NOWAIT); 208 } 209 } 210 211 sc->sc_parent_busex = pa->pa_busex; 212 sc->sc_busnum = sec; 213 sc->sc_busrange = sub - sec + 1; 214 215 /* Check for PCI Express capabilities and setup hotplug support. */ 216 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 217 &sc->sc_cap_off, ®) && (reg & PCI_PCIE_XCAP_SI)) { 218 task_set(&sc->sc_insert_task, ppb_hotplug_insert, sc); 219 task_set(&sc->sc_rescan_task, ppb_hotplug_rescan, sc); 220 task_set(&sc->sc_remove_task, ppb_hotplug_remove, sc); 221 timeout_set(&sc->sc_to, ppb_hotplug_insert_finish, sc); 222 223 #ifdef __i386__ 224 if (pci_intr_map(pa, &ih) == 0) 225 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO, 226 ppb_intr, sc, self->dv_xname); 227 #else 228 if (pci_intr_map_msi(pa, &ih) == 0 || 229 pci_intr_map(pa, &ih) == 0) 230 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_BIO, 231 ppb_intr, sc, self->dv_xname); 232 #endif 233 234 if (sc->sc_intrhand) { 235 printf(": %s", pci_intr_string(pc, ih)); 236 237 /* Enable hotplug interrupt. */ 238 reg = pci_conf_read(pc, pa->pa_tag, 239 sc->sc_cap_off + PCI_PCIE_SLCSR); 240 reg |= (PCI_PCIE_SLCSR_HPE | PCI_PCIE_SLCSR_PDE); 241 pci_conf_write(pc, pa->pa_tag, 242 sc->sc_cap_off + PCI_PCIE_SLCSR, reg); 243 } 244 } 245 246 printf("\n"); 247 248 interface = PCI_INTERFACE(pa->pa_class); 249 250 /* 251 * The Intel 82801BAM Hub-to-PCI can decode subtractively but 252 * doesn't advertise itself as such. 253 */ 254 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 255 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BA_HPB || 256 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801BAM_HPB)) 257 interface = PPB_INTERFACE_SUBTRACTIVE; 258 259 if (interface != PPB_INTERFACE_SUBTRACTIVE) 260 ppb_alloc_resources(sc, pa); 261 262 for (pin = PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_D; pin++) { 263 pa->pa_intrpin = pa->pa_rawintrpin = pin; 264 pa->pa_intrline = 0; 265 pci_intr_map(pa, &sc->sc_ih[pin - PCI_INTERRUPT_PIN_A]); 266 } 267 268 /* 269 * The UltraSPARC-IIi APB doesn't implement the standard 270 * address range registers. 271 */ 272 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 273 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_SIMBA) 274 goto attach; 275 276 /* Figure out the I/O address range of the bridge. */ 277 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IOSTATUS); 278 sc->sc_iobase = (blr & 0x000000f0) << 8; 279 sc->sc_iolimit = (blr & 0x000f000) | 0x00000fff; 280 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_IO_HI); 281 sc->sc_iobase |= (blr & 0x0000ffff) << 16; 282 sc->sc_iolimit |= (blr & 0xffff0000); 283 if (sc->sc_iolimit > sc->sc_iobase) { 284 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 285 if (name) { 286 snprintf(name, PPB_EXNAMLEN, "%s pciio", sc->sc_dev.dv_xname); 287 sc->sc_ioex = extent_create(name, 0, 0xffffffff, 288 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 289 extent_free(sc->sc_ioex, sc->sc_iobase, 290 sc->sc_iolimit - sc->sc_iobase + 1, EX_NOWAIT); 291 } 292 } 293 294 /* Figure out the memory mapped I/O address range of the bridge. */ 295 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_MEM); 296 sc->sc_membase = (blr & 0x0000fff0) << 16; 297 sc->sc_memlimit = (blr & 0xfff00000) | 0x000fffff; 298 if (sc->sc_memlimit > sc->sc_membase) { 299 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 300 if (name) { 301 snprintf(name, PPB_EXNAMLEN, "%s pcimem", sc->sc_dev.dv_xname); 302 sc->sc_memex = extent_create(name, 0, (u_long)-1L, 303 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 304 extent_free(sc->sc_memex, sc->sc_membase, 305 sc->sc_memlimit - sc->sc_membase + 1, 306 EX_NOWAIT); 307 } 308 } 309 310 /* Figure out the prefetchable MMI/O address range of the bridge. */ 311 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFMEM); 312 sc->sc_pmembase = (blr & 0x0000fff0) << 16; 313 sc->sc_pmemlimit = (blr & 0xfff00000) | 0x000fffff; 314 #ifdef __LP64__ 315 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFBASE_HI32); 316 sc->sc_pmembase |= ((uint64_t)blr) << 32; 317 blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFLIM_HI32); 318 sc->sc_pmemlimit |= ((uint64_t)blr) << 32; 319 #endif 320 if (sc->sc_pmemlimit > sc->sc_pmembase) { 321 name = malloc(PPB_EXNAMLEN, M_DEVBUF, M_NOWAIT); 322 if (name) { 323 snprintf(name, PPB_EXNAMLEN, "%s pcipmem", sc->sc_dev.dv_xname); 324 sc->sc_pmemex = extent_create(name, 0, (u_long)-1L, 325 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 326 extent_free(sc->sc_pmemex, sc->sc_pmembase, 327 sc->sc_pmemlimit - sc->sc_pmembase + 1, 328 EX_NOWAIT); 329 } 330 } 331 332 if (interface == PPB_INTERFACE_SUBTRACTIVE) { 333 if (sc->sc_ioex == NULL) 334 sc->sc_ioex = pa->pa_ioex; 335 if (sc->sc_memex == NULL) 336 sc->sc_memex = pa->pa_memex; 337 } 338 339 attach: 340 /* 341 * Attach the PCI bus that hangs off of it. 342 * 343 * XXX Don't pass-through Memory Read Multiple. Should we? 344 * XXX Consult the spec... 345 */ 346 bzero(&pba, sizeof(pba)); 347 pba.pba_busname = "pci"; 348 pba.pba_iot = pa->pa_iot; 349 pba.pba_memt = pa->pa_memt; 350 pba.pba_dmat = pa->pa_dmat; 351 pba.pba_pc = pc; 352 pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY; 353 pba.pba_busex = sc->sc_busex; 354 pba.pba_ioex = sc->sc_ioex; 355 pba.pba_memex = sc->sc_memex; 356 pba.pba_pmemex = sc->sc_pmemex; 357 pba.pba_domain = pa->pa_domain; 358 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 359 pba.pba_bridgeih = sc->sc_ih; 360 pba.pba_bridgetag = &sc->sc_tag; 361 pba.pba_intrswiz = pa->pa_intrswiz; 362 pba.pba_intrtag = pa->pa_intrtag; 363 364 sc->sc_psc = config_found(self, &pba, ppbprint); 365 } 366 367 int 368 ppbdetach(struct device *self, int flags) 369 { 370 struct ppb_softc *sc = (struct ppb_softc *)self; 371 char *name; 372 int rv; 373 374 if (sc->sc_intrhand) 375 pci_intr_disestablish(sc->sc_pc, sc->sc_intrhand); 376 377 rv = config_detach_children(self, flags); 378 379 if (sc->sc_busex) { 380 name = sc->sc_busex->ex_name; 381 extent_destroy(sc->sc_busex); 382 free(name, M_DEVBUF, PPB_EXNAMLEN); 383 } 384 385 if (sc->sc_ioex) { 386 name = sc->sc_ioex->ex_name; 387 extent_destroy(sc->sc_ioex); 388 free(name, M_DEVBUF, PPB_EXNAMLEN); 389 } 390 391 if (sc->sc_memex) { 392 name = sc->sc_memex->ex_name; 393 extent_destroy(sc->sc_memex); 394 free(name, M_DEVBUF, PPB_EXNAMLEN); 395 } 396 397 if (sc->sc_pmemex) { 398 name = sc->sc_pmemex->ex_name; 399 extent_destroy(sc->sc_pmemex); 400 free(name, M_DEVBUF, PPB_EXNAMLEN); 401 } 402 403 if (sc->sc_parent_busex && sc->sc_busrange > 0) 404 extent_free(sc->sc_parent_busex, sc->sc_busnum, 405 sc->sc_busrange, EX_NOWAIT); 406 407 return (rv); 408 } 409 410 int 411 ppbactivate(struct device *self, int act) 412 { 413 struct ppb_softc *sc = (void *)self; 414 pci_chipset_tag_t pc = sc->sc_pc; 415 pcitag_t tag = sc->sc_tag; 416 pcireg_t blr, reg; 417 int off, rv = 0; 418 419 switch (act) { 420 case DVACT_SUSPEND: 421 rv = config_activate_children(self, act); 422 423 /* Save registers that may get lost. */ 424 sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 425 sc->sc_bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 426 sc->sc_bir = pci_conf_read(pc, tag, PPB_REG_BUSINFO); 427 sc->sc_bcr = pci_conf_read(pc, tag, PPB_REG_BRIDGECONTROL); 428 sc->sc_int = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 429 if (sc->sc_cap_off) 430 sc->sc_slcsr = pci_conf_read(pc, tag, 431 sc->sc_cap_off + PCI_PCIE_SLCSR); 432 433 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) { 434 sc->sc_msi_ma = pci_conf_read(pc, tag, 435 off + PCI_MSI_MA); 436 if (reg & PCI_MSI_MC_C64) { 437 sc->sc_msi_mau32 = pci_conf_read(pc, tag, 438 off + PCI_MSI_MAU32); 439 sc->sc_msi_md = pci_conf_read(pc, tag, 440 off + PCI_MSI_MD64); 441 } else { 442 sc->sc_msi_md = pci_conf_read(pc, tag, 443 off + PCI_MSI_MD32); 444 } 445 sc->sc_msi_mc = reg; 446 } 447 break; 448 case DVACT_RESUME: 449 if (pci_dopm) { 450 /* Restore power. */ 451 pci_set_powerstate(pc, tag, sc->sc_pmcsr_state); 452 } 453 454 /* Restore the registers saved above. */ 455 pci_conf_write(pc, tag, PCI_BHLC_REG, sc->sc_bhlcr); 456 pci_conf_write(pc, tag, PPB_REG_BUSINFO, sc->sc_bir); 457 pci_conf_write(pc, tag, PPB_REG_BRIDGECONTROL, sc->sc_bcr); 458 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, sc->sc_int); 459 if (sc->sc_cap_off) 460 pci_conf_write(pc, tag, 461 sc->sc_cap_off + PCI_PCIE_SLCSR, sc->sc_slcsr); 462 463 /* Restore I/O window. */ 464 blr = pci_conf_read(pc, tag, PPB_REG_IOSTATUS); 465 blr &= 0xffff0000; 466 blr |= sc->sc_iolimit & PPB_IO_MASK; 467 blr |= (sc->sc_iobase >> PPB_IO_SHIFT); 468 pci_conf_write(pc, tag, PPB_REG_IOSTATUS, blr); 469 blr = (sc->sc_iobase & 0xffff0000) >> 16; 470 blr |= sc->sc_iolimit & 0xffff0000; 471 pci_conf_write(pc, tag, PPB_REG_IO_HI, blr); 472 473 /* Restore memory mapped I/O window. */ 474 blr = sc->sc_memlimit & PPB_MEM_MASK; 475 blr |= (sc->sc_membase >> PPB_MEM_SHIFT); 476 pci_conf_write(pc, tag, PPB_REG_MEM, blr); 477 478 /* Restore prefetchable MMI/O window. */ 479 blr = sc->sc_pmemlimit & PPB_MEM_MASK; 480 blr |= ((sc->sc_pmembase & PPB_MEM_MASK) >> PPB_MEM_SHIFT); 481 pci_conf_write(pc, tag, PPB_REG_PREFMEM, blr); 482 #ifdef __LP64__ 483 pci_conf_write(pc, tag, PPB_REG_PREFBASE_HI32, 484 sc->sc_pmembase >> 32); 485 pci_conf_write(pc, tag, PPB_REG_PREFLIM_HI32, 486 sc->sc_pmemlimit >> 32); 487 #endif 488 489 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) { 490 pci_conf_write(pc, tag, off + PCI_MSI_MA, 491 sc->sc_msi_ma); 492 if (reg & PCI_MSI_MC_C64) { 493 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 494 sc->sc_msi_mau32); 495 pci_conf_write(pc, tag, off + PCI_MSI_MD64, 496 sc->sc_msi_md); 497 } else { 498 pci_conf_write(pc, tag, off + PCI_MSI_MD32, 499 sc->sc_msi_md); 500 } 501 pci_conf_write(pc, tag, off + PCI_MSI_MC, 502 sc->sc_msi_mc); 503 } 504 505 /* 506 * Restore command register last to avoid exposing 507 * uninitialised windows. 508 */ 509 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 510 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 511 (reg & 0xffff0000) | (sc->sc_csr & 0x0000ffff)); 512 513 rv = config_activate_children(self, act); 514 break; 515 case DVACT_POWERDOWN: 516 rv = config_activate_children(self, act); 517 518 if (pci_dopm) { 519 /* 520 * Place the bridge into the lowest possible 521 * power state. 522 */ 523 sc->sc_pmcsr_state = pci_get_powerstate(pc, tag); 524 pci_set_powerstate(pc, tag, 525 pci_min_powerstate(pc, tag)); 526 } 527 break; 528 default: 529 rv = config_activate_children(self, act); 530 break; 531 } 532 return (rv); 533 } 534 535 void 536 ppb_alloc_busrange(struct ppb_softc *sc, struct pci_attach_args *pa, 537 pcireg_t *busdata) 538 { 539 pci_chipset_tag_t pc = sc->sc_pc; 540 u_long busnum, busrange = 0; 541 542 #ifdef __HAVE_FDT 543 int node = PCITAG_NODE(pa->pa_tag); 544 uint32_t bus_range[2]; 545 546 if (node && OF_getpropintarray(node, "bus-range", bus_range, 547 sizeof(bus_range)) == sizeof(bus_range)) { 548 if (extent_alloc_region(pa->pa_busex, bus_range[0], 549 bus_range[1] - bus_range[0] + 1, EX_NOWAIT) == 0) { 550 busnum = bus_range[0]; 551 busrange = bus_range[1] - bus_range[0] + 1; 552 } 553 } 554 #endif 555 556 if (busrange == 0) { 557 for (busrange = 16; busrange > 0; busrange >>= 1) { 558 if (extent_alloc(pa->pa_busex, busrange, 1, 0, 0, 559 EX_NOWAIT, &busnum) == 0) 560 break; 561 } 562 } 563 564 if (busrange > 0) { 565 *busdata |= pa->pa_bus; 566 *busdata |= (busnum << 8); 567 *busdata |= ((busnum + busrange - 1) << 16); 568 pci_conf_write(pc, pa->pa_tag, PPB_REG_BUSINFO, *busdata); 569 } 570 } 571 572 void 573 ppb_alloc_resources(struct ppb_softc *sc, struct pci_attach_args *pa) 574 { 575 pci_chipset_tag_t pc = sc->sc_pc; 576 pcireg_t id, busdata, blr, bhlcr, type, csr; 577 pcireg_t addr, mask; 578 pcitag_t tag; 579 int bus, dev; 580 int reg, reg_start, reg_end, reg_rom; 581 int io_count = 0; 582 int mem_count = 0; 583 bus_addr_t start, end; 584 u_long base, size; 585 586 if (pa->pa_memex == NULL) 587 return; 588 589 busdata = pci_conf_read(pc, sc->sc_tag, PPB_REG_BUSINFO); 590 bus = PPB_BUSINFO_SECONDARY(busdata); 591 if (bus == 0) 592 return; 593 594 /* 595 * Count number of devices. If there are no devices behind 596 * this bridge, there's no point in allocating any address 597 * space. 598 */ 599 for (dev = 0; dev < pci_bus_maxdevs(pc, bus); dev++) { 600 tag = pci_make_tag(pc, bus, dev, 0); 601 id = pci_conf_read(pc, tag, PCI_ID_REG); 602 603 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID || 604 PCI_VENDOR(id) == 0) 605 continue; 606 607 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 608 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 609 case 0: 610 reg_start = PCI_MAPREG_START; 611 reg_end = PCI_MAPREG_END; 612 reg_rom = PCI_ROM_REG; 613 break; 614 case 1: /* PCI-PCI bridge */ 615 reg_start = PCI_MAPREG_START; 616 reg_end = PCI_MAPREG_PPB_END; 617 reg_rom = 0; /* 0x38 */ 618 io_count++; 619 mem_count++; 620 break; 621 case 2: /* PCI-Cardbus bridge */ 622 reg_start = PCI_MAPREG_START; 623 reg_end = PCI_MAPREG_PCB_END; 624 reg_rom = 0; 625 io_count++; 626 mem_count++; 627 break; 628 default: 629 return; 630 } 631 632 for (reg = reg_start; reg < reg_end; reg += 4) { 633 if (pci_mapreg_probe(pc, tag, reg, &type) == 0) 634 continue; 635 636 if (type == PCI_MAPREG_TYPE_IO) 637 io_count++; 638 else 639 mem_count++; 640 641 if (type == (PCI_MAPREG_TYPE_MEM | 642 PCI_MAPREG_MEM_TYPE_64BIT)) 643 reg += 4; 644 } 645 646 if (reg_rom != 0) { 647 addr = pci_conf_read(pc, tag, reg_rom); 648 pci_conf_write(pc, tag, reg_rom, ~PCI_ROM_ENABLE); 649 mask = pci_conf_read(pc, tag, reg_rom); 650 pci_conf_write(pc, tag, reg_rom, addr); 651 if (PCI_ROM_SIZE(mask)) 652 mem_count++; 653 } 654 } 655 656 csr = pci_conf_read(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 657 658 /* 659 * Get the bridge in a consistent state. If memory mapped I/O or 660 * port I/O is disabled, disabled the associated windows as well. 661 */ 662 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 663 pci_conf_write(pc, sc->sc_tag, PPB_REG_MEM, 0x0000ffff); 664 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFMEM, 0x0000ffff); 665 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFBASE_HI32, 0); 666 pci_conf_write(pc, sc->sc_tag, PPB_REG_PREFLIM_HI32, 0); 667 } 668 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) { 669 pci_conf_write(pc, sc->sc_tag, PPB_REG_IOSTATUS, 0x000000ff); 670 pci_conf_write(pc, sc->sc_tag, PPB_REG_IO_HI, 0x0000ffff); 671 } 672 673 /* Allocate I/O address space if necessary. */ 674 if (io_count > 0 && pa->pa_ioex) { 675 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IOSTATUS); 676 sc->sc_iobase = (blr << PPB_IO_SHIFT) & PPB_IO_MASK; 677 sc->sc_iolimit = (blr & PPB_IO_MASK) | 0x00000fff; 678 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_IO_HI); 679 sc->sc_iobase |= (blr & 0x0000ffff) << 16; 680 sc->sc_iolimit |= (blr & 0xffff0000); 681 if (sc->sc_iolimit < sc->sc_iobase || sc->sc_iobase == 0) { 682 start = max(PCI_IO_START, pa->pa_ioex->ex_start); 683 end = min(PCI_IO_END, pa->pa_ioex->ex_end); 684 for (size = 0x2000; size >= PPB_IO_MIN; size >>= 1) 685 if (extent_alloc_subregion(pa->pa_ioex, start, 686 end, size, size, 0, 0, 0, &base) == 0) 687 break; 688 if (size >= PPB_IO_MIN) { 689 sc->sc_iobase = base; 690 sc->sc_iolimit = base + size - 1; 691 blr = pci_conf_read(pc, sc->sc_tag, 692 PPB_REG_IOSTATUS); 693 blr &= 0xffff0000; 694 blr |= sc->sc_iolimit & PPB_IO_MASK; 695 blr |= (sc->sc_iobase >> PPB_IO_SHIFT); 696 pci_conf_write(pc, sc->sc_tag, 697 PPB_REG_IOSTATUS, blr); 698 blr = (sc->sc_iobase & 0xffff0000) >> 16; 699 blr |= sc->sc_iolimit & 0xffff0000; 700 pci_conf_write(pc, sc->sc_tag, 701 PPB_REG_IO_HI, blr); 702 703 csr |= PCI_COMMAND_IO_ENABLE; 704 } 705 } 706 } 707 708 /* Allocate memory mapped I/O address space if necessary. */ 709 if (mem_count > 0 && pa->pa_memex) { 710 blr = pci_conf_read(pc, sc->sc_tag, PPB_REG_MEM); 711 sc->sc_membase = (blr << PPB_MEM_SHIFT) & PPB_MEM_MASK; 712 sc->sc_memlimit = (blr & PPB_MEM_MASK) | 0x000fffff; 713 if (sc->sc_memlimit < sc->sc_membase || sc->sc_membase == 0) { 714 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 715 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 716 for (size = 0x2000000; size >= PPB_MEM_MIN; size >>= 1) 717 if (extent_alloc_subregion(pa->pa_memex, start, 718 end, size, size, 0, 0, 0, &base) == 0) 719 break; 720 if (size >= PPB_MEM_MIN) { 721 sc->sc_membase = base; 722 sc->sc_memlimit = base + size - 1; 723 blr = sc->sc_memlimit & PPB_MEM_MASK; 724 blr |= (sc->sc_membase >> PPB_MEM_SHIFT); 725 pci_conf_write(pc, sc->sc_tag, 726 PPB_REG_MEM, blr); 727 728 csr |= PCI_COMMAND_MEM_ENABLE; 729 } 730 } 731 } 732 733 /* Enable bus master. */ 734 csr |= PCI_COMMAND_MASTER_ENABLE; 735 736 pci_conf_write(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr); 737 } 738 739 int 740 ppb_intr(void *arg) 741 { 742 struct ppb_softc *sc = arg; 743 pcireg_t reg; 744 745 /* 746 * XXX ignore hotplug events while in autoconf. On some 747 * machines with onboard re(4), we get a bogus hotplug remove 748 * event when we reset that device. Ignoring that event makes 749 * sure we will not try to forcibly detach re(4) when it isn't 750 * ready to deal with that. 751 */ 752 if (cold) 753 return (0); 754 755 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 756 sc->sc_cap_off + PCI_PCIE_SLCSR); 757 if (reg & PCI_PCIE_SLCSR_PDC) { 758 if (reg & PCI_PCIE_SLCSR_PDS) 759 task_add(systq, &sc->sc_insert_task); 760 else 761 task_add(systq, &sc->sc_remove_task); 762 763 /* Clear interrupts. */ 764 pci_conf_write(sc->sc_pc, sc->sc_tag, 765 sc->sc_cap_off + PCI_PCIE_SLCSR, reg); 766 return (1); 767 } 768 769 return (0); 770 } 771 772 #ifdef PCI_MACHDEP_ENUMERATE_BUS 773 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 774 #else 775 extern int pci_enumerate_bus(struct pci_softc *, 776 int (*)(struct pci_attach_args *), struct pci_attach_args *); 777 #endif 778 779 void 780 ppb_hotplug_insert(void *xsc) 781 { 782 struct ppb_softc *sc = xsc; 783 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 784 785 if (!LIST_EMPTY(&psc->sc_devs)) 786 return; 787 788 /* XXX Powerup the card. */ 789 790 /* XXX Turn on LEDs. */ 791 792 /* Wait a second for things to settle. */ 793 timeout_add_sec(&sc->sc_to, 1); 794 } 795 796 void 797 ppb_hotplug_insert_finish(void *arg) 798 { 799 struct ppb_softc *sc = arg; 800 801 task_add(systq, &sc->sc_rescan_task); 802 } 803 804 void 805 ppb_hotplug_rescan(void *xsc) 806 { 807 struct ppb_softc *sc = xsc; 808 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 809 810 if (psc) 811 pci_enumerate_bus(psc, NULL, NULL); 812 } 813 814 void 815 ppb_hotplug_remove(void *xsc) 816 { 817 struct ppb_softc *sc = xsc; 818 struct pci_softc *psc = (struct pci_softc *)sc->sc_psc; 819 820 if (psc) { 821 pci_detach_devices(psc, DETACH_FORCE); 822 823 /* 824 * XXX Allocate the entire window with EX_CONFLICTOK 825 * such that we can easily free it. 826 */ 827 if (sc->sc_ioex != NULL) { 828 extent_alloc_region(sc->sc_ioex, sc->sc_iobase, 829 sc->sc_iolimit - sc->sc_iobase + 1, 830 EX_NOWAIT | EX_CONFLICTOK); 831 extent_free(sc->sc_ioex, sc->sc_iobase, 832 sc->sc_iolimit - sc->sc_iobase + 1, EX_NOWAIT); 833 } 834 835 if (sc->sc_memex != NULL) { 836 extent_alloc_region(sc->sc_memex, sc->sc_membase, 837 sc->sc_memlimit - sc->sc_membase + 1, 838 EX_NOWAIT | EX_CONFLICTOK); 839 extent_free(sc->sc_memex, sc->sc_membase, 840 sc->sc_memlimit - sc->sc_membase + 1, EX_NOWAIT); 841 } 842 843 if (sc->sc_pmemex != NULL) { 844 extent_alloc_region(sc->sc_pmemex, sc->sc_pmembase, 845 sc->sc_pmemlimit - sc->sc_pmembase + 1, 846 EX_NOWAIT | EX_CONFLICTOK); 847 extent_free(sc->sc_pmemex, sc->sc_pmembase, 848 sc->sc_pmemlimit - sc->sc_pmembase + 1, EX_NOWAIT); 849 } 850 } 851 } 852 853 int 854 ppbprint(void *aux, const char *pnp) 855 { 856 struct pcibus_attach_args *pba = aux; 857 858 /* only PCIs can attach to PPBs; easy. */ 859 if (pnp) 860 printf("pci at %s", pnp); 861 printf(" bus %d", pba->pba_bus); 862 return (UNCONF); 863 } 864