1 /* $OpenBSD: tga.c,v 1.36 2011/04/07 15:30:16 miod Exp $ */ 2 /* $NetBSD: tga.c,v 1.40 2002/03/13 15:05:18 ad Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/conf.h> 36 #include <sys/malloc.h> 37 #include <sys/buf.h> 38 #include <sys/ioctl.h> 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/tgareg.h> 47 #include <dev/pci/tgavar.h> 48 #include <dev/ic/bt485reg.h> 49 #include <dev/ic/bt485var.h> 50 #include <dev/ic/bt463reg.h> 51 #include <dev/ic/bt463var.h> 52 #include <dev/ic/ibm561var.h> 53 54 #include <dev/wscons/wsconsio.h> 55 #include <dev/rasops/rasops.h> 56 #include <dev/wsfont/wsfont.h> 57 58 #if defined(__alpha__) || defined(__mips__) 59 #include <uvm/uvm_extern.h> 60 #endif 61 62 #ifdef __alpha__ 63 #include <machine/pte.h> 64 #endif 65 #ifdef __mips__ 66 #include <mips/pte.h> 67 #endif 68 69 int tgamatch(struct device *, struct cfdata *, void *); 70 void tgaattach(struct device *, struct device *, void *); 71 int tgaprint(void *, const char *); 72 73 struct cfdriver tga_cd = { 74 NULL, "tga", DV_DULL 75 }; 76 77 struct cfattach tga_ca = { 78 sizeof(struct tga_softc), (cfmatch_t)tgamatch, tgaattach, 79 }; 80 81 int tga_identify(struct tga_devconfig *); 82 const struct tga_conf *tga_getconf(int); 83 void tga_getdevconfig(bus_space_tag_t memt, pci_chipset_tag_t pc, 84 pcitag_t tag, struct tga_devconfig *dc); 85 unsigned tga_getdotclock(struct tga_devconfig *dc); 86 87 struct tga_devconfig tga_console_dc; 88 89 int tga_ioctl(void *, u_long, caddr_t, int, struct proc *); 90 paddr_t tga_mmap(void *, off_t, int); 91 int tga_copyrows(void *, int, int, int); 92 int tga_copycols(void *, int, int, int, int); 93 int tga_alloc_screen(void *, const struct wsscreen_descr *, 94 void **, int *, int *, long *); 95 void tga_free_screen(void *, void *); 96 int tga_show_screen(void *, void *, int, 97 void (*) (void *, int, int), void *); 98 void tga_burner(void *, u_int, u_int); 99 int tga_rop(struct rasops_info *, int, int, int, int, 100 struct rasops_info *, int, int); 101 int tga_rop_vtov(struct rasops_info *, int, int, int, 102 int, struct rasops_info *, int, int ); 103 int tga_putchar(void *c, int row, int col, u_int uc, long attr); 104 int tga_eraserows(void *, int, int, long); 105 int tga_erasecols(void *, int, int, int, long); 106 void tga2_init(struct tga_devconfig *); 107 108 void tga_config_interrupts(struct device *); 109 110 /* RAMDAC interface functions */ 111 int tga_sched_update(void *, void (*)(void *)); 112 void tga_ramdac_wr(void *, u_int, u_int8_t); 113 u_int8_t tga_ramdac_rd(void *, u_int); 114 void tga_bt463_wr(void *, u_int, u_int8_t); 115 u_int8_t tga_bt463_rd(void *, u_int); 116 void tga2_ramdac_wr(void *, u_int, u_int8_t); 117 u_int8_t tga2_ramdac_rd(void *, u_int); 118 119 /* Interrupt handler */ 120 int tga_intr(void *); 121 122 /* The NULL entries will get filled in by rasops_init(). 123 * XXX and the non-NULL ones will be overwritten; reset after calling it. 124 */ 125 struct wsdisplay_emulops tga_emulops = { 126 NULL, 127 NULL, 128 tga_putchar, 129 tga_copycols, 130 tga_erasecols, 131 tga_copyrows, 132 tga_eraserows, 133 NULL, 134 NULL 135 }; 136 137 struct wsscreen_descr tga_stdscreen = { 138 "std", 139 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 140 &tga_emulops, 141 0, 0, 142 WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 143 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE 144 }; 145 146 const struct wsscreen_descr *_tga_scrlist[] = { 147 &tga_stdscreen, 148 /* XXX other formats, graphics screen? */ 149 }; 150 151 struct wsscreen_list tga_screenlist = { 152 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 153 }; 154 155 struct wsdisplay_accessops tga_accessops = { 156 tga_ioctl, 157 tga_mmap, 158 tga_alloc_screen, 159 tga_free_screen, 160 tga_show_screen, 161 NULL, /* load_font */ 162 NULL, /* scrollback */ 163 NULL, /* getchar */ 164 tga_burner, 165 }; 166 167 void tga_blank(struct tga_devconfig *); 168 void tga_unblank(struct tga_devconfig *); 169 170 #ifdef TGA_DEBUG 171 #define DPRINTF(...) printf (__VA_ARGS__) 172 #define DPRINTFN(n, ...) if (tgadebug > (n)) printf (__VA_ARGS__) 173 int tgadebug = 0; 174 #else 175 #define DPRINTF(...) 176 #define DPRINTFN(n,...) 177 #endif 178 179 const struct pci_matchid tga_devices[] = { 180 { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21030 }, 181 { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PBXGB }, 182 }; 183 184 int 185 tgamatch(parent, match, aux) 186 struct device *parent; 187 struct cfdata *match; 188 void *aux; 189 { 190 if (pci_matchbyid((struct pci_attach_args *)aux, tga_devices, 191 sizeof(tga_devices) / sizeof(tga_devices[0]))) 192 return (10); /* need to return more than vga_pci here! */ 193 194 return (0); 195 } 196 197 void 198 tga_getdevconfig(memt, pc, tag, dc) 199 bus_space_tag_t memt; 200 pci_chipset_tag_t pc; 201 pcitag_t tag; 202 struct tga_devconfig *dc; 203 { 204 const struct tga_conf *tgac; 205 struct rasops_info *rip; 206 int cookie; 207 bus_size_t pcisize; 208 int i; 209 210 dc->dc_memt = memt; 211 212 dc->dc_pcitag = tag; 213 214 DPRINTF("tga_getdevconfig: Getting map info\n"); 215 /* XXX magic number */ 216 if (pci_mapreg_info(pc, tag, 0x10, 217 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 218 &dc->dc_pcipaddr, &pcisize, NULL)) 219 return; 220 221 DPRINTF("tga_getdevconfig: preparing to map\n"); 222 if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 223 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 224 return; 225 #ifdef __OpenBSD__ 226 dc->dc_vaddr = dc->dc_memh; 227 #else 228 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 229 #endif 230 DPRINTF("tga_getdevconfig: mapped\n"); 231 232 #ifdef __alpha__ 233 dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */ 234 #endif 235 DPRINTF("tga_getdevconfig: allocating subregion\n"); 236 bus_space_subregion(dc->dc_memt, dc->dc_memh, 237 TGA_MEM_CREGS, TGA_CREGS_SIZE, 238 &dc->dc_regs); 239 240 DPRINTF("tga_getdevconfig: going to identify\n"); 241 dc->dc_tga_type = tga_identify(dc); 242 243 DPRINTF("tga_getdevconfig: preparing to get config\n"); 244 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 245 if (tgac == NULL) 246 return; 247 248 #if 0 249 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 250 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 251 panic("tga_getdevconfig: memory size mismatch?"); 252 #endif 253 254 DPRINTF("tga_getdevconfig: get revno\n"); 255 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 256 case 0x01: 257 case 0x02: 258 case 0x03: 259 case 0x04: 260 dc->dc_tga2 = 0; 261 break; 262 case 0x20: 263 case 0x21: 264 case 0x22: 265 dc->dc_tga2 = 1; 266 break; 267 default: 268 panic("tga_getdevconfig: TGA Revision not recognized"); 269 } 270 271 if (dc->dc_tga2) { 272 tga2_init(dc); 273 } 274 275 i = TGARREG(dc, TGA_REG_VHCR) & 0x1ff; 276 DPRINTF("tga_getdevconfig: TGA_REG_VHCR & 0x1ff = %d\n", i); 277 switch (i) { /* XXX */ 278 case 0: 279 dc->dc_wid = 8192; 280 break; 281 282 case 1: 283 dc->dc_wid = 8196; 284 break; 285 286 default: 287 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 288 break; 289 } 290 291 DPRINTF("tga_getdevconfig: dc->dc_wid = %d\n", dc->dc_wid); 292 /* 293 * XXX XXX Turning off "odd" shouldn't be necessary, 294 * XXX XXX but I can't make X work with the weird size. 295 */ 296 DPRINTF("tga_getdevconfig: beginning magic incantation\n"); 297 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 298 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 299 TGAWREG(dc, TGA_REG_VHCR, 300 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 301 dc->dc_wid -= 4; 302 } 303 304 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 305 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 306 DPRINTF("tga_getdevconfig: rowbytes = %d, tgac_phys_depth = %d\n" 307 " dc_wid = %d, dc_ht = %d\n", 308 dc->dc_rowbytes, dc->dc_tgaconf->tgac_phys_depth, 309 dc->dc_wid, dc->dc_ht); 310 311 /* XXX this seems to be what DEC does */ 312 DPRINTF("tga_getdevconfig: more magic\n"); 313 TGAWREG(dc, TGA_REG_CCBR, 0); 314 TGAWREG(dc, TGA_REG_VVBR, 1); 315 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 316 1 * tgac->tgac_vvbr_units; 317 dc->dc_blanked = 1; 318 tga_unblank(dc); 319 320 DPRINTF("tga_getdevconfig: dc_videobase = 0x%016llx\n" 321 " dc_vaddr = 0x%016llx\n" 322 " tgac_dbuf[0] = %d\n" 323 " tgac_vvbr_units = %d\n", 324 dc->dc_videobase, dc->dc_vaddr, tgac->tgac_dbuf[0], 325 tgac->tgac_vvbr_units); 326 327 /* 328 * Set all bits in the pixel mask, to enable writes to all pixels. 329 * It seems that the console firmware clears some of them 330 * under some circumstances, which causes cute vertical stripes. 331 */ 332 DPRINTF("tga_getdevconfig: set pixel mask\n"); 333 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 334 335 /* clear the screen */ 336 DPRINTF("tga_getdevconfig: clear screen\n"); 337 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 338 *(u_int32_t *)(dc->dc_videobase + i) = 0; 339 340 DPRINTF("tga_getdevconfig: raster ops\n"); 341 /* Initialize rasops descriptor */ 342 rip = &dc->dc_rinfo; 343 rip->ri_flg = RI_CENTER; 344 rip->ri_depth = tgac->tgac_phys_depth; 345 rip->ri_bits = (void *)dc->dc_videobase; 346 rip->ri_width = dc->dc_wid; 347 rip->ri_height = dc->dc_ht; 348 rip->ri_stride = dc->dc_rowbytes; 349 rip->ri_hw = dc; 350 351 if (tgac->tgac_phys_depth == 32) { 352 rip->ri_rnum = 8; 353 rip->ri_gnum = 8; 354 rip->ri_bnum = 8; 355 rip->ri_rpos = 16; 356 rip->ri_gpos = 8; 357 rip->ri_bpos = 0; 358 } 359 360 DPRINTF("tga_getdevconfig: wsfont_init\n"); 361 wsfont_init(); 362 if (rip->ri_width > 80*12) 363 /* High res screen, choose a big font */ 364 cookie = wsfont_find(NULL, 12, 0, 0); 365 else 366 /* lower res, choose a 8 pixel wide font */ 367 cookie = wsfont_find(NULL, 8, 0, 0); 368 if (cookie <= 0) 369 cookie = wsfont_find(NULL, 0, 0, 0); 370 if (cookie <= 0) { 371 printf("tga: no appropriate fonts.\n"); 372 return; 373 } 374 375 /* the accelerated tga_putchar() needs LSbit left */ 376 if (wsfont_lock(cookie, &rip->ri_font, 377 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) { 378 printf("tga: couldn't lock font\n"); 379 return; 380 } 381 rip->ri_wsfcookie = cookie; 382 /* fill screen size */ 383 rasops_init(rip, rip->ri_height / rip->ri_font->fontheight, 384 rip->ri_width / rip->ri_font->fontwidth); 385 386 /* add our accelerated functions */ 387 /* XXX shouldn't have to do this; rasops should leave non-NULL 388 * XXX entries alone. 389 */ 390 rip->ri_ops.copyrows = tga_copyrows; 391 rip->ri_ops.eraserows = tga_eraserows; 392 rip->ri_ops.erasecols = tga_erasecols; 393 rip->ri_ops.copycols = tga_copycols; 394 rip->ri_ops.putchar = tga_putchar; 395 396 tga_stdscreen.nrows = rip->ri_rows; 397 tga_stdscreen.ncols = rip->ri_cols; 398 tga_stdscreen.textops = &rip->ri_ops; 399 tga_stdscreen.capabilities = rip->ri_caps; 400 401 dc->dc_intrenabled = 0; 402 } 403 404 void 405 tgaattach(parent, self, aux) 406 struct device *parent, *self; 407 void *aux; 408 { 409 struct pci_attach_args *pa = aux; 410 struct tga_softc *sc = (struct tga_softc *)self; 411 struct wsemuldisplaydev_attach_args aa; 412 pci_intr_handle_t intrh; 413 const char *intrstr; 414 u_int8_t rev; 415 int console; 416 417 #if defined(__alpha__) 418 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 419 #else 420 console = 0; 421 #endif 422 if (console) { 423 sc->sc_dc = &tga_console_dc; 424 sc->nscreens = 1; 425 } else { 426 sc->sc_dc = malloc(sizeof(struct tga_devconfig), M_DEVBUF, 427 M_NOWAIT | M_ZERO); 428 if (sc->sc_dc == NULL) 429 return; 430 tga_getdevconfig(pa->pa_memt, pa->pa_pc, pa->pa_tag, 431 sc->sc_dc); 432 } 433 if (sc->sc_dc->dc_vaddr == 0) { 434 printf(": can't map mem space\n"); 435 return; 436 } 437 438 /* XXX say what's going on. */ 439 intrstr = NULL; 440 if (pci_intr_map(pa, &intrh)) { 441 printf(": can't map interrupt"); 442 return; 443 } 444 intrstr = pci_intr_string(pa->pa_pc, intrh); 445 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 446 sc->sc_dc, sc->sc_dev.dv_xname); 447 if (sc->sc_intr == NULL) { 448 printf(": can't establish interrupt"); 449 if (intrstr != NULL) 450 printf("at %s", intrstr); 451 printf("\n"); 452 return; 453 } 454 455 rev = PCI_REVISION(pa->pa_class); 456 switch (rev) { 457 case 0x1: 458 case 0x2: 459 case 0x3: 460 printf(": DC21030 step %c", 'A' + rev - 1); 461 break; 462 case 0x20: 463 printf(": TGA2 abstract software model"); 464 break; 465 case 0x21: 466 case 0x22: 467 printf(": TGA2 pass %d", rev - 0x20); 468 break; 469 470 default: 471 printf("unknown stepping (0x%x)", rev); 472 break; 473 } 474 printf(", "); 475 476 /* 477 * Get RAMDAC function vectors and call the RAMDAC functions 478 * to allocate its private storage and pass that back to us. 479 */ 480 481 DPRINTF("tgaattach: Get RAMDAC functions\n"); 482 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 483 if (!sc->sc_dc->dc_tga2) { 484 DPRINTF("tgaattach: !sc->sc_dc->dc_tga2\n"); 485 DPRINTF("tgaattach: sc->sc_dc->dc_tgaconf->ramdac_funcs %s " 486 "bt485_funcs\n", 487 (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 488 ? "==" : "!="); 489 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 490 sc->sc_dc->dc_ramdac_cookie = 491 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 492 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 493 else 494 sc->sc_dc->dc_ramdac_cookie = 495 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 496 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 497 } else { 498 DPRINTF("tgaattach: sc->sc_dc->dc_tga2\n"); 499 sc->sc_dc->dc_ramdac_cookie = 500 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 501 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 502 503 /* XXX this is a bit of a hack, setting the dotclock here */ 504 if (sc->sc_dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 505 (*sc->sc_dc->dc_ramdac_funcs->ramdac_set_dotclock) 506 (sc->sc_dc->dc_ramdac_cookie, 507 tga_getdotclock(sc->sc_dc)); 508 } 509 DPRINTF("tgaattach: sc->sc_dc->dc_ramdac_cookie = 0x%016llx\n", 510 sc->sc_dc->dc_ramdac_cookie); 511 /* 512 * Initialize the RAMDAC. Initialization includes disabling 513 * cursor, setting a sane colormap, etc. 514 */ 515 DPRINTF("tgaattach: Initializing RAMDAC.\n"); 516 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 517 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 518 519 if (sc->sc_dc->dc_tgaconf == NULL) { 520 printf("unknown board configuration\n"); 521 return; 522 } 523 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 524 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 525 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 526 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 527 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 528 529 if (intrstr != NULL) 530 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 531 intrstr); 532 533 aa.console = console; 534 aa.scrdata = &tga_screenlist; 535 aa.accessops = &tga_accessops; 536 aa.accesscookie = sc; 537 aa.defaultscreens = 0; 538 539 config_found(self, &aa, wsemuldisplaydevprint); 540 541 #ifdef __NetBSD__ 542 config_interrupts(self, tga_config_interrupts); 543 #else 544 tga_config_interrupts(self); 545 #endif 546 } 547 548 void 549 tga_config_interrupts (d) 550 struct device *d; 551 { 552 struct tga_softc *sc = (struct tga_softc *)d; 553 sc->sc_dc->dc_intrenabled = 1; 554 } 555 556 557 int 558 tga_ioctl(v, cmd, data, flag, p) 559 void *v; 560 u_long cmd; 561 caddr_t data; 562 int flag; 563 struct proc *p; 564 { 565 struct tga_softc *sc = v; 566 struct tga_devconfig *dc = sc->sc_dc; 567 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 568 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 569 570 switch (cmd) { 571 case WSDISPLAYIO_GTYPE: 572 *(u_int *)data = WSDISPLAY_TYPE_TGA; 573 break; 574 575 case WSDISPLAYIO_SMODE: 576 sc->sc_mode = *(u_int *)data; 577 switch (sc->sc_mode) { 578 case WSDISPLAYIO_MODE_DUMBFB: 579 /* in dump fb mode start the framebuffer at 0 */ 580 TGAWREG(dc, TGA_REG_VVBR, 0); 581 break; 582 default: 583 /* XXX it this useful, except for not breaking Xtga? */ 584 TGAWREG(dc, TGA_REG_VVBR, 1); 585 break; 586 } 587 break; 588 589 case WSDISPLAYIO_GINFO: 590 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 591 wsd_fbip->height = sc->sc_dc->dc_ht; 592 wsd_fbip->width = sc->sc_dc->dc_wid; 593 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 594 wsd_fbip->cmsize = 1024; /* XXX ??? */ 595 #undef wsd_fbip 596 break; 597 598 case WSDISPLAYIO_LINEBYTES: 599 *(u_int *)data = sc->sc_dc->dc_rowbytes; 600 break; 601 602 case WSDISPLAYIO_GETCMAP: 603 return (*dcrf->ramdac_get_cmap)(dcrc, 604 (struct wsdisplay_cmap *)data); 605 case WSDISPLAYIO_PUTCMAP: 606 return (*dcrf->ramdac_set_cmap)(dcrc, 607 (struct wsdisplay_cmap *)data); 608 609 case WSDISPLAYIO_SVIDEO: 610 case WSDISPLAYIO_GVIDEO: 611 break; 612 613 case WSDISPLAYIO_GCURPOS: 614 return (*dcrf->ramdac_get_curpos)(dcrc, 615 (struct wsdisplay_curpos *)data); 616 617 case WSDISPLAYIO_SCURPOS: 618 return (*dcrf->ramdac_set_curpos)(dcrc, 619 (struct wsdisplay_curpos *)data); 620 621 case WSDISPLAYIO_GCURMAX: 622 return (*dcrf->ramdac_get_curmax)(dcrc, 623 (struct wsdisplay_curpos *)data); 624 625 case WSDISPLAYIO_GCURSOR: 626 return (*dcrf->ramdac_get_cursor)(dcrc, 627 (struct wsdisplay_cursor *)data); 628 629 case WSDISPLAYIO_SCURSOR: 630 return (*dcrf->ramdac_set_cursor)(dcrc, 631 (struct wsdisplay_cursor *)data); 632 633 default: 634 return (-1); 635 } 636 637 return (0); 638 } 639 640 int 641 tga_sched_update(v, f) 642 void *v; 643 void (*f)(void *); 644 { 645 struct tga_devconfig *dc = v; 646 647 if (dc->dc_intrenabled) { 648 /* Arrange for f to be called at the next end-of-frame interrupt */ 649 dc->dc_ramdac_intr = f; 650 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 651 } else { 652 /* Spin until the end-of-frame, then call f */ 653 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 654 TGAREGWB(dc, TGA_REG_SISR, 1); 655 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 656 ; 657 f(dc->dc_ramdac_cookie); 658 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 659 TGAREGWB(dc, TGA_REG_SISR, 1); 660 } 661 662 return 0; 663 } 664 665 int 666 tga_intr(v) 667 void *v; 668 { 669 struct tga_devconfig *dc = v; 670 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 671 672 u_int32_t reg; 673 674 reg = TGARREG(dc, TGA_REG_SISR); 675 if (( reg & 0x00010001) != 0x00010001) { 676 /* Odd. We never set any of the other interrupt enables. */ 677 if ((reg & 0x1f) != 0) { 678 /* Clear the mysterious pending interrupts. */ 679 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 680 TGAREGWB(dc, TGA_REG_SISR, 1); 681 /* This was our interrupt, even if we're puzzled as to why 682 * we got it. Don't make the interrupt handler think it 683 * was a stray. 684 */ 685 return -1; 686 } else { 687 return 0; 688 } 689 } 690 /* if we have something to do, do it */ 691 if (dc->dc_ramdac_intr) { 692 dc->dc_ramdac_intr(dcrc); 693 dc->dc_ramdac_intr = NULL; 694 } 695 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 696 TGAREGWB(dc, TGA_REG_SISR, 1); 697 return (1); 698 } 699 700 paddr_t 701 tga_mmap(v, offset, prot) 702 void *v; 703 off_t offset; 704 int prot; 705 { 706 struct tga_softc *sc = v; 707 struct tga_devconfig *dc = sc->sc_dc; 708 709 if (offset >= dc->dc_tgaconf->tgac_cspace_size || offset < 0) 710 return -1; 711 712 if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { 713 /* 714 * The framebuffer starts at the upper half of tga mem 715 */ 716 offset += dc->dc_tgaconf->tgac_cspace_size / 2; 717 } 718 #if defined(__alpha__) || defined(__mips__) 719 return (sc->sc_dc->dc_paddr + offset); 720 #else 721 return (-1); 722 #endif 723 } 724 725 int 726 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 727 void *v; 728 const struct wsscreen_descr *type; 729 void **cookiep; 730 int *curxp, *curyp; 731 long *attrp; 732 { 733 struct tga_softc *sc = v; 734 long defattr; 735 736 if (sc->nscreens > 0) 737 return (ENOMEM); 738 739 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 740 *curxp = 0; 741 *curyp = 0; 742 sc->sc_dc->dc_rinfo.ri_ops.alloc_attr(&sc->sc_dc->dc_rinfo, 743 0, 0, 0, &defattr); 744 *attrp = defattr; 745 sc->nscreens++; 746 return (0); 747 } 748 749 void 750 tga_free_screen(v, cookie) 751 void *v; 752 void *cookie; 753 { 754 struct tga_softc *sc = v; 755 756 if (sc->sc_dc == &tga_console_dc) 757 panic("tga_free_screen: console"); 758 759 sc->nscreens--; 760 } 761 762 int 763 tga_show_screen(v, cookie, waitok, cb, cbarg) 764 void *v; 765 void *cookie; 766 int waitok; 767 void (*cb)(void *, int, int); 768 void *cbarg; 769 { 770 771 return (0); 772 } 773 774 int 775 tga_cnattach(iot, memt, pc, bus, device, function) 776 bus_space_tag_t iot, memt; 777 pci_chipset_tag_t pc; 778 int bus, device, function; 779 { 780 struct tga_devconfig *dcp = &tga_console_dc; 781 long defattr; 782 783 tga_getdevconfig(memt, pc, 784 pci_make_tag(pc, bus, device, function), dcp); 785 786 /* sanity checks */ 787 if (dcp->dc_vaddr == 0) 788 panic("tga_console(%d, %d): can't map mem space", 789 device, function); 790 if (dcp->dc_tgaconf == NULL) 791 panic("tga_console(%d, %d): unknown board configuration", 792 device, function); 793 794 /* 795 * Initialize the RAMDAC but DO NOT allocate any private storage. 796 * Initialization includes disabling cursor, setting a sane 797 * colormap, etc. It will be reinitialized in tgaattach(). 798 */ 799 if (dcp->dc_tga2) { 800 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 801 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 802 tga2_ramdac_rd); 803 else 804 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 805 tga2_ramdac_rd, tga_getdotclock(dcp)); 806 } else { 807 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 808 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 809 tga_ramdac_rd); 810 else { 811 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 812 tga_bt463_rd); 813 } 814 } 815 dcp->dc_rinfo.ri_ops.alloc_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 816 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 817 818 return(0); 819 } 820 821 /* 822 * Functions to blank and unblank the display. 823 */ 824 void 825 tga_burner(v, on, flags) 826 void *v; 827 u_int on, flags; 828 { 829 struct tga_softc *sc = v; 830 831 if (on) { 832 tga_unblank(sc->sc_dc); 833 } else { 834 tga_blank(sc->sc_dc); 835 } 836 } 837 838 void 839 tga_blank(dc) 840 struct tga_devconfig *dc; 841 { 842 843 if (!dc->dc_blanked) { 844 dc->dc_blanked = 1; 845 /* XXX */ 846 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 847 } 848 } 849 850 void 851 tga_unblank(dc) 852 struct tga_devconfig *dc; 853 { 854 855 if (dc->dc_blanked) { 856 dc->dc_blanked = 0; 857 /* XXX */ 858 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 859 } 860 } 861 862 /* 863 * Functions to manipulate the built-in cursor handing hardware. 864 */ 865 int 866 tga_builtin_set_cursor(dc, cursorp) 867 struct tga_devconfig *dc; 868 struct wsdisplay_cursor *cursorp; 869 { 870 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 871 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 872 u_int count, v; 873 int error; 874 875 v = cursorp->which; 876 if (v & WSDISPLAY_CURSOR_DOCMAP) { 877 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 878 if (error) 879 return (error); 880 } 881 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 882 if ((u_int)cursorp->size.x != 64 || 883 (u_int)cursorp->size.y > 64) 884 return (EINVAL); 885 } 886 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 887 return EINVAL; 888 889 /* parameters are OK; do it */ 890 if (v & WSDISPLAY_CURSOR_DOCUR) { 891 if (cursorp->enable) 892 /* XXX */ 893 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 894 else 895 /* XXX */ 896 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 897 } 898 if (v & WSDISPLAY_CURSOR_DOPOS) { 899 TGAWREG(dc, TGA_REG_CXYR, 900 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 901 } 902 if (v & WSDISPLAY_CURSOR_DOCMAP) { 903 /* can't fail. */ 904 dcrf->ramdac_set_curcmap(dcrc, cursorp); 905 } 906 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 907 /* The cursor is 2 bits deep, and there is no mask */ 908 count = (cursorp->size.y * 64 * 2) / NBBY; 909 TGAWREG(dc, TGA_REG_CCBR, 910 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 911 if ((error = copyin(cursorp->image,(char *)(dc->dc_vaddr + 912 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), count)) != 0) 913 return (error); 914 } 915 return (0); 916 } 917 918 int 919 tga_builtin_get_cursor(dc, cursorp) 920 struct tga_devconfig *dc; 921 struct wsdisplay_cursor *cursorp; 922 { 923 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 924 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 925 int error; 926 u_int count; 927 928 cursorp->which = WSDISPLAY_CURSOR_DOALL & 929 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 930 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 931 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 932 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 933 cursorp->size.x = 64; 934 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 935 936 if (cursorp->image != NULL) { 937 count = (cursorp->size.y * 64 * 2) / NBBY; 938 error = copyout((char *)(dc->dc_vaddr + 939 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 940 cursorp->image, count); 941 if (error) 942 return (error); 943 /* No mask */ 944 } 945 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 946 return (error); 947 } 948 949 int 950 tga_builtin_set_curpos(dc, curposp) 951 struct tga_devconfig *dc; 952 struct wsdisplay_curpos *curposp; 953 { 954 955 TGAWREG(dc, TGA_REG_CXYR, 956 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 957 return (0); 958 } 959 960 int 961 tga_builtin_get_curpos(dc, curposp) 962 struct tga_devconfig *dc; 963 struct wsdisplay_curpos *curposp; 964 { 965 966 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 967 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 968 return (0); 969 } 970 971 int 972 tga_builtin_get_curmax(dc, curposp) 973 struct tga_devconfig *dc; 974 struct wsdisplay_curpos *curposp; 975 { 976 977 curposp->x = curposp->y = 64; 978 return (0); 979 } 980 981 /* 982 * Copy columns (characters) in a row (line). 983 */ 984 int 985 tga_copycols(id, row, srccol, dstcol, ncols) 986 void *id; 987 int row, srccol, dstcol, ncols; 988 { 989 struct rasops_info *ri = id; 990 int y, srcx, dstx, nx; 991 992 y = ri->ri_font->fontheight * row; 993 srcx = ri->ri_font->fontwidth * srccol; 994 dstx = ri->ri_font->fontwidth * dstcol; 995 nx = ri->ri_font->fontwidth * ncols; 996 997 tga_rop(ri, dstx, y, nx, ri->ri_font->fontheight, ri, srcx, y); 998 999 return 0; 1000 } 1001 1002 /* 1003 * Copy rows (lines). 1004 */ 1005 int 1006 tga_copyrows(id, srcrow, dstrow, nrows) 1007 void *id; 1008 int srcrow, dstrow, nrows; 1009 { 1010 struct rasops_info *ri = id; 1011 int srcy, dsty, ny; 1012 1013 srcy = ri->ri_font->fontheight * srcrow; 1014 dsty = ri->ri_font->fontheight * dstrow; 1015 ny = ri->ri_font->fontheight * nrows; 1016 1017 tga_rop(ri, 0, dsty, ri->ri_emuwidth, ny, ri, 0, srcy); 1018 1019 return 0; 1020 } 1021 1022 /* 1023 * Generic TGA raster op. 1024 * This covers all possible raster ops, and 1025 * clips the sizes and all of that. 1026 */ 1027 int 1028 tga_rop(dst, dx, dy, w, h, src, sx, sy) 1029 struct rasops_info *dst; 1030 int dx, dy, w, h; 1031 struct rasops_info *src; 1032 int sx, sy; 1033 { 1034 if (dst == NULL || src == NULL) 1035 return -1; 1036 1037 /* Clip against src */ 1038 if (sx < 0) { 1039 w += sx; 1040 sx = 0; 1041 } 1042 if (sy < 0) { 1043 h += sy; 1044 sy = 0; 1045 } 1046 if (sx + w > src->ri_emuwidth) 1047 w = src->ri_emuwidth - sx; 1048 if (sy + h > src->ri_emuheight) 1049 h = src->ri_emuheight - sy; 1050 1051 /* Clip against dst. We modify src regardless of using it, 1052 * since it really doesn't matter. 1053 */ 1054 if (dx < 0) { 1055 w += dx; 1056 sx -= dx; 1057 dx = 0; 1058 } 1059 if (dy < 0) { 1060 h += dy; 1061 sy -= dy; 1062 dy = 0; 1063 } 1064 if (dx + w > dst->ri_emuwidth) 1065 w = dst->ri_emuwidth - dx; 1066 if (dy + h > dst->ri_emuheight) 1067 h = dst->ri_emuheight - dy; 1068 if (w <= 0 || h <= 0) 1069 return 0; /* Vacuously true; */ 1070 1071 return tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy); 1072 } 1073 1074 1075 1076 /* 1077 * Video to Video raster ops. 1078 * This function deals with all raster ops that have a src and dst 1079 * that are on the card. 1080 */ 1081 int 1082 tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy) 1083 struct rasops_info *dst; 1084 int dx, dy, w, h; 1085 struct rasops_info *src; 1086 int sx, sy; 1087 { 1088 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1089 int srcb, dstb, tga_srcb, tga_dstb; 1090 int x, y, wb; 1091 int xstart, xend, xdir; 1092 int ystart, yend, ydir, yinc; 1093 int xleft, lastx, lastleft; 1094 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1095 1096 /* 1097 * I don't yet want to deal with unaligned guys, really. And we don't 1098 * deal with copies from one card to another. 1099 */ 1100 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1101 /* XXX Punt! */ 1102 /* XXX should never happen, since it's only being used to 1103 * XXX copy 8-pixel-wide characters. 1104 */ 1105 return -1; 1106 } 1107 1108 wb = w * (dst->ri_depth / 8); 1109 if (sy >= dy) { 1110 ystart = 0; 1111 yend = h; 1112 ydir = 1; 1113 } else { 1114 ystart = h; 1115 yend = 0; 1116 ydir = -1; 1117 } 1118 if (sx >= dx) { /* moving to the left */ 1119 xstart = 0; 1120 xend = w * (dst->ri_depth / 8) - 4; 1121 xdir = 1; 1122 } else { /* moving to the right */ 1123 xstart = wb - ( wb >= 4*64 ? 4*64 : wb >= 64 ? 64 : 4 ); 1124 xend = 0; 1125 xdir = -1; 1126 } 1127 #define XINC4 4 1128 #define XINC64 64 1129 #define XINC256 (64*4) 1130 yinc = ydir * dst->ri_stride; 1131 ystart *= dst->ri_stride; 1132 yend *= dst->ri_stride; 1133 1134 srcb = sy * src->ri_stride + sx * (src->ri_depth/8); 1135 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); 1136 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1137 (sx + src->ri_xorigin) * (src->ri_depth/8); 1138 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1139 (dx + dst->ri_xorigin) * (dst->ri_depth/8); 1140 1141 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1142 TGAWALREG(dc, TGA_REG_GOPR, 3, 0x0003); /* SRC */ 1143 1144 /* 1145 * we have 3 sizes of pixels to move in X direction: 1146 * 4 * 64 (unrolled TGA ops) 1147 * 64 (single TGA op) 1148 * 4 (CPU, using long word) 1149 */ 1150 1151 if (xdir == 1) { /* move to the left */ 1152 1153 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1154 1155 /* 4*64 byte chunks */ 1156 for (xleft = wb, x = xstart; 1157 x <= xend && xleft >= 4*64; 1158 x += XINC256, xleft -= XINC256) { 1159 1160 /* XXX XXX Eight writes to different addresses should fill 1161 * XXX XXX up the write buffers on 21064 and 21164 chips, 1162 * XXX XXX but later CPUs might have larger write buffers which 1163 * XXX XXX require further unrolling of this loop, or the 1164 * XXX XXX insertion of memory barriers. 1165 */ 1166 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1167 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1168 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64); 1169 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64); 1170 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64); 1171 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64); 1172 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64); 1173 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64); 1174 } 1175 1176 /* 64 byte chunks */ 1177 for ( ; x <= xend && xleft >= 64; 1178 x += XINC64, xleft -= XINC64) { 1179 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1180 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1181 } 1182 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1183 1184 } 1185 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1186 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1187 1188 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1189 /* 4 byte granularity */ 1190 for (x = lastx, xleft = lastleft; 1191 x <= xend && xleft >= 4; 1192 x += XINC4, xleft -= XINC4) { 1193 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1194 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1195 } 1196 } 1197 } 1198 else { /* above move to the left, below move to the right */ 1199 1200 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1201 1202 /* 4*64 byte chunks */ 1203 for (xleft = wb, x = xstart; 1204 x >= xend && xleft >= 4*64; 1205 x -= XINC256, xleft -= XINC256) { 1206 1207 /* XXX XXX Eight writes to different addresses should fill 1208 * XXX XXX up the write buffers on 21064 and 21164 chips, 1209 * XXX XXX but later CPUs might have larger write buffers which 1210 * XXX XXX require further unrolling of this loop, or the 1211 * XXX XXX insertion of memory barriers. 1212 */ 1213 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64); 1214 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64); 1215 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64); 1216 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64); 1217 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64); 1218 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64); 1219 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64); 1220 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64); 1221 } 1222 1223 if (xleft) x += XINC256 - XINC64; 1224 1225 /* 64 byte chunks */ 1226 for ( ; x >= xend && xleft >= 64; 1227 x -= XINC64, xleft -= XINC64) { 1228 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64); 1229 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64); 1230 } 1231 if (xleft) x += XINC64 - XINC4; 1232 lastx = x; lastleft = xleft; /* remember for CPU loop */ 1233 } 1234 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1235 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1236 1237 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1238 /* 4 byte granularity */ 1239 for (x = lastx, xleft = lastleft; 1240 x >= xend && xleft >= 4; 1241 x -= XINC4, xleft -= XINC4) { 1242 *(uint32_t *)(dst->ri_bits + dstb + y + x) = 1243 *(uint32_t *)(dst->ri_bits + srcb + y + x); 1244 } 1245 } 1246 } 1247 return 0; 1248 } 1249 1250 1251 int 1252 tga_putchar(c, row, col, uc, attr) 1253 void *c; 1254 int row, col; 1255 u_int uc; 1256 long attr; 1257 { 1258 struct rasops_info *ri = c; 1259 struct tga_devconfig *dc = ri->ri_hw; 1260 int fs, height, width; 1261 int fg, bg, ul; 1262 u_char *fr; 1263 int32_t *rp; 1264 1265 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1266 1267 height = ri->ri_font->fontheight; 1268 width = ri->ri_font->fontwidth; 1269 1270 uc -= ri->ri_font->firstchar; 1271 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1272 fs = ri->ri_font->stride; 1273 1274 /* Set foreground and background color. XXX memoize this somehow? 1275 * The rasops code has already expanded the color entry to 32 bits 1276 * for us, even for 8-bit displays, so we don't have to do anything. 1277 */ 1278 ri->ri_ops.unpack_attr(c, attr, &fg, &bg, &ul); 1279 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[fg]); 1280 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[bg]); 1281 1282 /* Set raster operation to "copy"... */ 1283 if (ri->ri_depth == 8) 1284 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1285 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1286 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1287 1288 /* Set which pixels we're drawing (of a possible 32). */ 1289 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1290 1291 /* Set drawing mode to opaque stipple. */ 1292 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1293 1294 /* Insert write barrier before actually sending data */ 1295 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1296 TGAREGWB(dc, TGA_REG_GMOR, 1); 1297 1298 while (height--) { 1299 /* The actual stipple write */ 1300 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1301 1302 fr += fs; 1303 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1304 } 1305 1306 /* Do underline */ 1307 if (ul) { 1308 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1309 *rp = 0xffffffff; 1310 } 1311 1312 /* Set grapics mode back to normal. */ 1313 TGAWREG(dc, TGA_REG_GMOR, 0); 1314 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1315 1316 return 0; 1317 } 1318 1319 int 1320 tga_eraserows(c, row, num, attr) 1321 void *c; 1322 int row, num; 1323 long attr; 1324 { 1325 struct rasops_info *ri = c; 1326 struct tga_devconfig *dc = ri->ri_hw; 1327 int32_t color, lines, pixels; 1328 int fg, bg; 1329 int32_t *rp; 1330 1331 ri->ri_ops.unpack_attr(c, attr, &fg, &bg, NULL); 1332 color = ri->ri_devcmap[bg]; 1333 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1334 lines = num * ri->ri_font->fontheight; 1335 pixels = ri->ri_emuwidth - 1; 1336 1337 /* Set fill color in block-color registers */ 1338 TGAWREG(dc, TGA_REG_GBCR0, color); 1339 TGAWREG(dc, TGA_REG_GBCR1, color); 1340 if (ri->ri_depth != 8) { 1341 TGAWREG(dc, TGA_REG_GBCR2, color); 1342 TGAWREG(dc, TGA_REG_GBCR3, color); 1343 TGAWREG(dc, TGA_REG_GBCR4, color); 1344 TGAWREG(dc, TGA_REG_GBCR5, color); 1345 TGAWREG(dc, TGA_REG_GBCR6, color); 1346 TGAWREG(dc, TGA_REG_GBCR7, color); 1347 } 1348 1349 /* Set raster operation to "copy"... */ 1350 if (ri->ri_depth == 8) 1351 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1352 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1353 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1354 1355 /* Set which pixels we're drawing (of a possible 32). */ 1356 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1357 1358 /* Set drawing mode to block fill. */ 1359 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1360 1361 /* Insert write barrier before actually sending data */ 1362 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1363 TGAREGWB(dc, TGA_REG_GMOR, 1); 1364 1365 while (lines--) { 1366 *rp = pixels; 1367 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1368 } 1369 1370 /* Set grapics mode back to normal. */ 1371 TGAWREG(dc, TGA_REG_GMOR, 0); 1372 1373 return 0; 1374 } 1375 1376 int 1377 tga_erasecols (c, row, col, num, attr) 1378 void *c; 1379 int row, col, num; 1380 long attr; 1381 { 1382 struct rasops_info *ri = c; 1383 struct tga_devconfig *dc = ri->ri_hw; 1384 int32_t color, lines, pixels; 1385 int fg, bg; 1386 int32_t *rp; 1387 1388 ri->ri_ops.unpack_attr(c, attr, &fg, &bg, NULL); 1389 color = ri->ri_devcmap[bg]; 1390 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1391 lines = ri->ri_font->fontheight; 1392 pixels = (num * ri->ri_font->fontwidth) - 1; 1393 1394 /* Set fill color in block-color registers */ 1395 TGAWREG(dc, TGA_REG_GBCR0, color); 1396 TGAWREG(dc, TGA_REG_GBCR1, color); 1397 if (ri->ri_depth != 8) { 1398 TGAWREG(dc, TGA_REG_GBCR2, color); 1399 TGAWREG(dc, TGA_REG_GBCR3, color); 1400 TGAWREG(dc, TGA_REG_GBCR4, color); 1401 TGAWREG(dc, TGA_REG_GBCR5, color); 1402 TGAWREG(dc, TGA_REG_GBCR6, color); 1403 TGAWREG(dc, TGA_REG_GBCR7, color); 1404 } 1405 1406 /* Set raster operation to "copy"... */ 1407 if (ri->ri_depth == 8) 1408 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1409 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1410 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1411 1412 /* Set which pixels we're drawing (of a possible 32). */ 1413 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1414 1415 /* Set drawing mode to block fill. */ 1416 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1417 1418 /* Insert write barrier before actually sending data */ 1419 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1420 TGAREGWB(dc, TGA_REG_GMOR, 1); 1421 1422 while (lines--) { 1423 *rp = pixels; 1424 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1425 } 1426 1427 /* Set grapics mode back to normal. */ 1428 TGAWREG(dc, TGA_REG_GMOR, 0); 1429 1430 return 0; 1431 } 1432 1433 1434 void 1435 tga_ramdac_wr(v, btreg, val) 1436 void *v; 1437 u_int btreg; 1438 u_int8_t val; 1439 { 1440 struct tga_devconfig *dc = v; 1441 1442 if (btreg > BT485_REG_MAX) 1443 panic("tga_ramdac_wr: reg %d out of range", btreg); 1444 1445 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1446 TGAREGWB(dc, TGA_REG_EPDR, 1); 1447 } 1448 1449 void 1450 tga2_ramdac_wr(v, btreg, val) 1451 void *v; 1452 u_int btreg; 1453 u_int8_t val; 1454 { 1455 struct tga_devconfig *dc = v; 1456 bus_space_handle_t ramdac; 1457 1458 if (btreg > BT485_REG_MAX) 1459 panic("tga_ramdac_wr: reg %d out of range", btreg); 1460 1461 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1462 (0xe << 12) + (btreg << 8), 4, &ramdac); 1463 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1464 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1465 } 1466 1467 u_int8_t 1468 tga_bt463_rd(v, btreg) 1469 void *v; 1470 u_int btreg; 1471 { 1472 struct tga_devconfig *dc = v; 1473 tga_reg_t rdval; 1474 1475 /* 1476 * Strobe CE# (high->low->high) since status and data are latched on 1477 * the falling and rising edges (repsectively) of this active-low signal. 1478 */ 1479 1480 TGAREGWB(dc, TGA_REG_EPSR, 1); 1481 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1482 TGAREGWB(dc, TGA_REG_EPSR, 1); 1483 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1484 1485 TGAREGRB(dc, TGA_REG_EPSR, 1); 1486 1487 rdval = TGARREG(dc, TGA_REG_EPDR); 1488 TGAREGWB(dc, TGA_REG_EPSR, 1); 1489 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1490 1491 return (rdval >> 16) & 0xff; 1492 } 1493 1494 void 1495 tga_bt463_wr(v, btreg, val) 1496 void *v; 1497 u_int btreg; 1498 u_int8_t val; 1499 { 1500 struct tga_devconfig *dc = v; 1501 1502 /* 1503 * In spite of the 21030 documentation, to set the MPU bus bits for 1504 * a write, you set them in the upper bits of EPDR, not EPSR. 1505 */ 1506 1507 /* 1508 * Strobe CE# (high->low->high) since status and data are latched on 1509 * the falling and rising edges of this active-low signal. 1510 */ 1511 1512 TGAREGWB(dc, TGA_REG_EPDR, 1); 1513 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1514 TGAREGWB(dc, TGA_REG_EPDR, 1); 1515 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1516 TGAREGWB(dc, TGA_REG_EPDR, 1); 1517 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1518 1519 } 1520 1521 u_int8_t 1522 tga_ramdac_rd(v, btreg) 1523 void *v; 1524 u_int btreg; 1525 { 1526 struct tga_devconfig *dc = v; 1527 tga_reg_t rdval; 1528 1529 if (btreg > BT485_REG_MAX) 1530 panic("tga_ramdac_rd: reg %d out of range", btreg); 1531 1532 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1533 TGAREGWB(dc, TGA_REG_EPSR, 1); 1534 1535 rdval = TGARREG(dc, TGA_REG_EPDR); 1536 return (rdval >> 16) & 0xff; /* XXX */ 1537 } 1538 1539 u_int8_t 1540 tga2_ramdac_rd(v, btreg) 1541 void *v; 1542 u_int btreg; 1543 { 1544 struct tga_devconfig *dc = v; 1545 bus_space_handle_t ramdac; 1546 u_int8_t retval; 1547 1548 if (btreg > BT485_REG_MAX) 1549 panic("tga_ramdac_rd: reg %d out of range", btreg); 1550 1551 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1552 (0xe << 12) + (btreg << 8), 4, &ramdac); 1553 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1554 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1555 return retval; 1556 } 1557 1558 #include <dev/ic/decmonitors.c> 1559 void tga2_ics9110_wr( 1560 struct tga_devconfig *dc, 1561 int dotclock 1562 ); 1563 1564 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1565 1566 void 1567 tga2_init(dc) 1568 struct tga_devconfig *dc; 1569 { 1570 struct monitor *m = tga_getmonitor(dc); 1571 1572 1573 /* Deal with the dot clocks. 1574 */ 1575 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1576 /* Set this up as a reference clock for the 1577 * ibm561's PLL. 1578 */ 1579 tga2_ics9110_wr(dc, 14300000); 1580 /* XXX Can't set up the dotclock properly, until such time 1581 * as the RAMDAC is configured. 1582 */ 1583 } else { 1584 /* otherwise the ics9110 is our clock. */ 1585 tga2_ics9110_wr(dc, m->dotclock); 1586 } 1587 #if 0 1588 TGAWREG(dc, TGA_REG_VHCR, 1589 ((m->hbp / 4) << 21) | 1590 ((m->hsync / 4) << 14) | 1591 (((m->hfp - 4) / 4) << 9) | 1592 ((m->cols + 4) / 4)); 1593 #else 1594 TGAWREG(dc, TGA_REG_VHCR, 1595 ((m->hbp / 4) << 21) | 1596 ((m->hsync / 4) << 14) | 1597 (((m->hfp) / 4) << 9) | 1598 ((m->cols) / 4)); 1599 #endif 1600 TGAWREG(dc, TGA_REG_VVCR, 1601 (m->vbp << 22) | 1602 (m->vsync << 16) | 1603 (m->vfp << 11) | 1604 (m->rows)); 1605 TGAWREG(dc, TGA_REG_VVBR, 1); 1606 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1607 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1608 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1609 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1610 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1611 } 1612 1613 void 1614 tga2_ics9110_wr(dc, dotclock) 1615 struct tga_devconfig *dc; 1616 int dotclock; 1617 { 1618 bus_space_handle_t clock; 1619 u_int32_t valU; 1620 int N, M, R, V, X; 1621 int i; 1622 1623 switch (dotclock) { 1624 case 130808000: 1625 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1626 case 119840000: 1627 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1628 case 108180000: 1629 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1630 case 103994000: 1631 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1632 case 175000000: 1633 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1634 case 75000000: 1635 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1636 case 74000000: 1637 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1638 case 69000000: 1639 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1640 case 65000000: 1641 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1642 case 50000000: 1643 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1644 case 40000000: 1645 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1646 case 31500000: 1647 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1648 case 25175000: 1649 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1650 case 135000000: 1651 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1652 case 110000000: 1653 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1654 case 202500000: 1655 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1656 case 14300000: /* this one is just a ref clock */ 1657 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1658 default: 1659 panic("unrecognized clock rate %d", dotclock); 1660 } 1661 1662 /* XXX -- hard coded, bad */ 1663 valU = N | ( M << 7 ) | (V << 14); 1664 valU |= (X << 15) | (R << 17); 1665 valU |= 0x17 << 19; 1666 1667 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1668 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1669 1670 for (i = 24; i > 0; i--) { 1671 u_int32_t writeval; 1672 1673 writeval = valU & 0x1; 1674 if (i == 1) 1675 writeval |= 0x2; 1676 valU >>= 1; 1677 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1678 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1679 } 1680 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1681 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1682 &clock); /* XXX */ 1683 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1684 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1685 } 1686 1687 struct monitor * 1688 tga_getmonitor(dc) 1689 struct tga_devconfig *dc; 1690 { 1691 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1692 } 1693 1694 unsigned 1695 tga_getdotclock(dc) 1696 struct tga_devconfig *dc; 1697 { 1698 return tga_getmonitor(dc)->dotclock; 1699 } 1700