1 /* $OpenBSD: vmwpvs.c,v 1.27 2022/04/16 19:19:59 naddy Exp $ */ 2 3 /* 4 * Copyright (c) 2013 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/param.h> 20 #include <sys/systm.h> 21 #include <sys/device.h> 22 #include <sys/ioctl.h> 23 #include <sys/malloc.h> 24 #include <sys/kernel.h> 25 #include <sys/rwlock.h> 26 #include <sys/dkio.h> 27 #include <sys/task.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcireg.h> 32 #include <dev/pci/pcivar.h> 33 #include <dev/pci/pcidevs.h> 34 35 #include <scsi/scsi_all.h> 36 #include <scsi/scsi_message.h> 37 #include <scsi/scsiconf.h> 38 39 /* pushbuttons */ 40 #define VMWPVS_OPENINGS 64 /* according to the linux driver */ 41 #define VMWPVS_RING_PAGES 2 42 #define VMWPVS_MAXSGL (MAXPHYS / PAGE_SIZE) 43 #define VMWPVS_SENSELEN roundup(sizeof(struct scsi_sense_data), 16) 44 45 /* "chip" definitions */ 46 47 #define VMWPVS_R_COMMAND 0x0000 48 #define VMWPVS_R_COMMAND_DATA 0x0004 49 #define VMWPVS_R_COMMAND_STATUS 0x0008 50 #define VMWPVS_R_LAST_STS_0 0x0100 51 #define VMWPVS_R_LAST_STS_1 0x0104 52 #define VMWPVS_R_LAST_STS_2 0x0108 53 #define VMWPVS_R_LAST_STS_3 0x010c 54 #define VMWPVS_R_INTR_STATUS 0x100c 55 #define VMWPVS_R_INTR_MASK 0x2010 56 #define VMWPVS_R_KICK_NON_RW_IO 0x3014 57 #define VMWPVS_R_DEBUG 0x3018 58 #define VMWPVS_R_KICK_RW_IO 0x4018 59 60 #define VMWPVS_INTR_CMPL_0 (1 << 0) 61 #define VMWPVS_INTR_CMPL_1 (1 << 1) 62 #define VMWPVS_INTR_CMPL_MASK (VMWPVS_INTR_CMPL_0 | VMWPVS_INTR_CMPL_1) 63 #define VMWPVS_INTR_MSG_0 (1 << 2) 64 #define VMWPVS_INTR_MSG_1 (1 << 3) 65 #define VMWPVS_INTR_MSG_MASK (VMWPVS_INTR_MSG_0 | VMWPVS_INTR_MSG_1) 66 #define VMWPVS_INTR_ALL_MASK (VMWPVS_INTR_CMPL_MASK | VMWPVS_INTR_MSG_MASK) 67 68 #define VMWPVS_PAGE_SHIFT 12 69 #define VMWPVS_PAGE_SIZE (1 << VMWPVS_PAGE_SHIFT) 70 71 #define VMWPVS_NPG_COMMAND 1 72 #define VMWPVS_NPG_INTR_STATUS 1 73 #define VMWPVS_NPG_MISC 2 74 #define VMWPVS_NPG_KICK_IO 2 75 #define VMWPVS_NPG_MSI_X 2 76 77 #define VMWPVS_PG_COMMAND 0 78 #define VMWPVS_PG_INTR_STATUS (VMWPVS_PG_COMMAND + \ 79 VMWPVS_NPG_COMMAND * VMWPVS_PAGE_SIZE) 80 #define VMWPVS_PG_MISC (VMWPVS_PG_INTR_STATUS + \ 81 VMWPVS_NPG_INTR_STATUS * VMWPVS_PAGE_SIZE) 82 #define VMWPVS_PG_KICK_IO (VMWPVS_PG_MISC + \ 83 VMWPVS_NPG_MISC * VMWPVS_PAGE_SIZE) 84 #define VMWPVS_PG_MSI_X (VMWPVS_PG_KICK_IO + \ 85 VMWPVS_NPG_KICK_IO * VMWPVS_PAGE_SIZE) 86 #define VMMPVS_PG_LEN (VMWPVS_PG_MSI_X + \ 87 VMWPVS_NPG_MSI_X * VMWPVS_PAGE_SIZE) 88 89 struct vmwpvw_ring_state { 90 u_int32_t req_prod; 91 u_int32_t req_cons; 92 u_int32_t req_entries; /* log 2 */ 93 94 u_int32_t cmp_prod; 95 u_int32_t cmp_cons; 96 u_int32_t cmp_entries; /* log 2 */ 97 98 u_int32_t __reserved[26]; 99 100 u_int32_t msg_prod; 101 u_int32_t msg_cons; 102 u_int32_t msg_entries; /* log 2 */ 103 } __packed; 104 105 struct vmwpvs_ring_req { 106 u_int64_t context; 107 108 u_int64_t data_addr; 109 u_int64_t data_len; 110 111 u_int64_t sense_addr; 112 u_int32_t sense_len; 113 114 u_int32_t flags; 115 #define VMWPVS_REQ_SGL (1 << 0) 116 #define VMWPVS_REQ_OOBCDB (1 << 1) 117 #define VMWPVS_REQ_DIR_NONE (1 << 2) 118 #define VMWPVS_REQ_DIR_IN (1 << 3) 119 #define VMWPVS_REQ_DIR_OUT (1 << 4) 120 121 u_int8_t cdb[16]; 122 u_int8_t cdblen; 123 u_int8_t lun[8]; 124 u_int8_t tag; 125 u_int8_t bus; 126 u_int8_t target; 127 u_int8_t vcpu_hint; 128 129 u_int8_t __reserved[59]; 130 } __packed; 131 #define VMWPVS_REQ_COUNT ((VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE) / \ 132 sizeof(struct vmwpvs_ring_req)) 133 134 struct vmwpvs_ring_cmp { 135 u_int64_t context; 136 u_int64_t data_len; 137 u_int32_t sense_len; 138 u_int16_t host_status; 139 u_int16_t scsi_status; 140 u_int32_t __reserved[2]; 141 } __packed; 142 #define VMWPVS_CMP_COUNT ((VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE) / \ 143 sizeof(struct vmwpvs_ring_cmp)) 144 145 struct vmwpvs_sge { 146 u_int64_t addr; 147 u_int32_t len; 148 u_int32_t flags; 149 } __packed; 150 151 struct vmwpvs_ring_msg { 152 u_int32_t type; 153 u_int32_t __args[31]; 154 } __packed; 155 #define VMWPVS_MSG_COUNT ((VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE) / \ 156 sizeof(struct vmwpvs_ring_msg)) 157 158 #define VMWPVS_MSG_T_ADDED 0 159 #define VMWPVS_MSG_T_REMOVED 1 160 161 struct vmwpvs_ring_msg_dev { 162 u_int32_t type; 163 u_int32_t bus; 164 u_int32_t target; 165 u_int8_t lun[8]; 166 167 u_int32_t __pad[27]; 168 } __packed; 169 170 struct vmwpvs_cfg_cmd { 171 u_int64_t cmp_addr; 172 u_int32_t pg_addr; 173 u_int32_t pg_addr_type; 174 u_int32_t pg_num; 175 u_int32_t __reserved; 176 } __packed; 177 178 #define VMWPVS_MAX_RING_PAGES 32 179 struct vmwpvs_setup_rings_cmd { 180 u_int32_t req_pages; 181 u_int32_t cmp_pages; 182 u_int64_t state_ppn; 183 u_int64_t req_page_ppn[VMWPVS_MAX_RING_PAGES]; 184 u_int64_t cmp_page_ppn[VMWPVS_MAX_RING_PAGES]; 185 } __packed; 186 187 #define VMWPVS_MAX_MSG_RING_PAGES 16 188 struct vmwpvs_setup_rings_msg { 189 u_int32_t msg_pages; 190 u_int32_t __reserved; 191 u_int64_t msg_page_ppn[VMWPVS_MAX_MSG_RING_PAGES]; 192 } __packed; 193 194 #define VMWPVS_CMD_FIRST 0 195 #define VMWPVS_CMD_ADAPTER_RESET 1 196 #define VMWPVS_CMD_ISSUE_SCSI 2 197 #define VMWPVS_CMD_SETUP_RINGS 3 198 #define VMWPVS_CMD_RESET_BUS 4 199 #define VMWPVS_CMD_RESET_DEVICE 5 200 #define VMWPVS_CMD_ABORT_CMD 6 201 #define VMWPVS_CMD_CONFIG 7 202 #define VMWPVS_CMD_SETUP_MSG_RING 8 203 #define VMWPVS_CMD_DEVICE_UNPLUG 9 204 #define VMWPVS_CMD_LAST 10 205 206 #define VMWPVS_CFGPG_CONTROLLER 0x1958 207 #define VMWPVS_CFGPG_PHY 0x1959 208 #define VMWPVS_CFGPG_DEVICE 0x195a 209 210 #define VMWPVS_CFGPGADDR_CONTROLLER 0x2120 211 #define VMWPVS_CFGPGADDR_TARGET 0x2121 212 #define VMWPVS_CFGPGADDR_PHY 0x2122 213 214 struct vmwpvs_cfg_pg_header { 215 u_int32_t pg_num; 216 u_int16_t num_dwords; 217 u_int16_t host_status; 218 u_int16_t scsi_status; 219 u_int16_t __reserved[3]; 220 } __packed; 221 222 #define VMWPVS_HOST_STATUS_SUCCESS 0x00 223 #define VMWPVS_HOST_STATUS_LINKED_CMD_COMPLETED 0x0a 224 #define VMWPVS_HOST_STATUS_LINKED_CMD_COMPLETED_WITH_FLAG 0x0b 225 #define VMWPVS_HOST_STATUS_UNDERRUN 0x0c 226 #define VMWPVS_HOST_STATUS_SELTIMEOUT 0x11 227 #define VMWPVS_HOST_STATUS_DATARUN 0x12 228 #define VMWPVS_HOST_STATUS_BUSFREE 0x13 229 #define VMWPVS_HOST_STATUS_INVPHASE 0x14 230 #define VMWPVS_HOST_STATUS_LUNMISMATCH 0x17 231 #define VMWPVS_HOST_STATUS_INVPARAM 0x1a 232 #define VMWPVS_HOST_STATUS_SENSEFAILED 0x1b 233 #define VMWPVS_HOST_STATUS_TAGREJECT 0x1c 234 #define VMWPVS_HOST_STATUS_BADMSG 0x1d 235 #define VMWPVS_HOST_STATUS_HAHARDWARE 0x20 236 #define VMWPVS_HOST_STATUS_NORESPONSE 0x21 237 #define VMWPVS_HOST_STATUS_SENT_RST 0x22 238 #define VMWPVS_HOST_STATUS_RECV_RST 0x23 239 #define VMWPVS_HOST_STATUS_DISCONNECT 0x24 240 #define VMWPVS_HOST_STATUS_BUS_RESET 0x25 241 #define VMWPVS_HOST_STATUS_ABORT_QUEUE 0x26 242 #define VMWPVS_HOST_STATUS_HA_SOFTWARE 0x27 243 #define VMWPVS_HOST_STATUS_HA_TIMEOUT 0x30 244 #define VMWPVS_HOST_STATUS_SCSI_PARITY 0x34 245 246 #define VMWPVS_SCSI_STATUS_OK 0x00 247 #define VMWPVS_SCSI_STATUS_CHECK 0x02 248 249 struct vmwpvs_cfg_pg_controller { 250 struct vmwpvs_cfg_pg_header header; 251 252 u_int64_t wwnn; 253 u_int16_t manufacturer[64]; 254 u_int16_t serial_number[64]; 255 u_int16_t oprom_version[32]; 256 u_int16_t hardware_version[32]; 257 u_int16_t firmware_version[32]; 258 u_int32_t num_phys; 259 u_int8_t use_consec_phy_wwns; 260 u_int8_t __reserved[3]; 261 } __packed; 262 263 /* driver stuff */ 264 265 struct vmwpvs_dmamem { 266 bus_dmamap_t dm_map; 267 bus_dma_segment_t dm_seg; 268 size_t dm_size; 269 caddr_t dm_kva; 270 }; 271 #define VMWPVS_DMA_MAP(_dm) (_dm)->dm_map 272 #define VMWPVS_DMA_DVA(_dm) (_dm)->dm_map->dm_segs[0].ds_addr 273 #define VMWPVS_DMA_KVA(_dm) (void *)(_dm)->dm_kva 274 275 struct vmwpvs_sgl { 276 struct vmwpvs_sge list[VMWPVS_MAXSGL]; 277 } __packed; 278 279 struct vmwpvs_ccb { 280 SIMPLEQ_ENTRY(vmwpvs_ccb) 281 ccb_entry; 282 283 bus_dmamap_t ccb_dmamap; 284 struct scsi_xfer *ccb_xs; 285 u_int64_t ccb_ctx; 286 287 struct vmwpvs_sgl *ccb_sgl; 288 bus_addr_t ccb_sgl_offset; 289 290 void *ccb_sense; 291 bus_addr_t ccb_sense_offset; 292 }; 293 SIMPLEQ_HEAD(vmwpvs_ccb_list, vmwpvs_ccb); 294 295 struct vmwpvs_softc { 296 struct device sc_dev; 297 298 pci_chipset_tag_t sc_pc; 299 pcitag_t sc_tag; 300 301 bus_space_tag_t sc_iot; 302 bus_space_handle_t sc_ioh; 303 bus_size_t sc_ios; 304 bus_dma_tag_t sc_dmat; 305 306 struct vmwpvs_dmamem *sc_req_ring; 307 struct vmwpvs_dmamem *sc_cmp_ring; 308 struct vmwpvs_dmamem *sc_msg_ring; 309 struct vmwpvs_dmamem *sc_ring_state; 310 struct mutex sc_ring_mtx; 311 312 struct vmwpvs_dmamem *sc_sgls; 313 struct vmwpvs_dmamem *sc_sense; 314 struct vmwpvs_ccb *sc_ccbs; 315 struct vmwpvs_ccb_list sc_ccb_list; 316 struct mutex sc_ccb_mtx; 317 318 void *sc_ih; 319 320 struct task sc_msg_task; 321 322 u_int sc_bus_width; 323 324 struct scsi_iopool sc_iopool; 325 struct scsibus_softc *sc_scsibus; 326 }; 327 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 328 329 int vmwpvs_match(struct device *, void *, void *); 330 void vmwpvs_attach(struct device *, struct device *, void *); 331 332 int vmwpvs_intx(void *); 333 int vmwpvs_intr(void *); 334 335 #define vmwpvs_read(_s, _r) \ 336 bus_space_read_4((_s)->sc_iot, (_s)->sc_ioh, (_r)) 337 #define vmwpvs_write(_s, _r, _v) \ 338 bus_space_write_4((_s)->sc_iot, (_s)->sc_ioh, (_r), (_v)) 339 #define vmwpvs_barrier(_s, _r, _l, _d) \ 340 bus_space_barrier((_s)->sc_iot, (_s)->sc_ioh, (_r), (_l), (_d)) 341 342 const struct cfattach vmwpvs_ca = { 343 sizeof(struct vmwpvs_softc), 344 vmwpvs_match, 345 vmwpvs_attach, 346 NULL 347 }; 348 349 struct cfdriver vmwpvs_cd = { 350 NULL, 351 "vmwpvs", 352 DV_DULL 353 }; 354 355 void vmwpvs_scsi_cmd(struct scsi_xfer *); 356 357 const struct scsi_adapter vmwpvs_switch = { 358 vmwpvs_scsi_cmd, NULL, NULL, NULL, NULL 359 }; 360 361 #define dwordsof(s) (sizeof(s) / sizeof(u_int32_t)) 362 363 void vmwpvs_ccb_put(void *, void *); 364 void * vmwpvs_ccb_get(void *); 365 366 struct vmwpvs_dmamem * 367 vmwpvs_dmamem_alloc(struct vmwpvs_softc *, size_t); 368 struct vmwpvs_dmamem * 369 vmwpvs_dmamem_zalloc(struct vmwpvs_softc *, size_t); 370 void vmwpvs_dmamem_free(struct vmwpvs_softc *, 371 struct vmwpvs_dmamem *); 372 373 void vmwpvs_cmd(struct vmwpvs_softc *, u_int32_t, void *, size_t); 374 int vmwpvs_get_config(struct vmwpvs_softc *); 375 void vmwpvs_setup_rings(struct vmwpvs_softc *); 376 void vmwpvs_setup_msg_ring(struct vmwpvs_softc *); 377 void vmwpvs_msg_task(void *); 378 379 struct vmwpvs_ccb * 380 vmwpvs_scsi_cmd_poll(struct vmwpvs_softc *); 381 struct vmwpvs_ccb * 382 vmwpvs_scsi_cmd_done(struct vmwpvs_softc *, 383 struct vmwpvs_ring_cmp *); 384 385 int 386 vmwpvs_match(struct device *parent, void *match, void *aux) 387 { 388 struct pci_attach_args *pa = aux; 389 390 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VMWARE && 391 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VMWARE_PVSCSI) 392 return (1); 393 394 return (0); 395 } 396 397 void 398 vmwpvs_attach(struct device *parent, struct device *self, void *aux) 399 { 400 struct vmwpvs_softc *sc = (struct vmwpvs_softc *)self; 401 struct pci_attach_args *pa = aux; 402 struct scsibus_attach_args saa; 403 pcireg_t memtype; 404 u_int i, r, use_msg; 405 int (*isr)(void *) = vmwpvs_intx; 406 u_int32_t intmask; 407 pci_intr_handle_t ih; 408 409 struct vmwpvs_ccb *ccb; 410 struct vmwpvs_sgl *sgls; 411 u_int8_t *sense; 412 413 sc->sc_pc = pa->pa_pc; 414 sc->sc_tag = pa->pa_tag; 415 sc->sc_dmat = pa->pa_dmat; 416 417 sc->sc_bus_width = 16; 418 mtx_init(&sc->sc_ring_mtx, IPL_BIO); 419 mtx_init(&sc->sc_ccb_mtx, IPL_BIO); 420 task_set(&sc->sc_msg_task, vmwpvs_msg_task, sc); 421 SIMPLEQ_INIT(&sc->sc_ccb_list); 422 423 for (r = PCI_MAPREG_START; r < PCI_MAPREG_END; r += sizeof(memtype)) { 424 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, r); 425 if ((memtype & PCI_MAPREG_TYPE_MASK) == PCI_MAPREG_TYPE_MEM) 426 break; 427 } 428 if (r >= PCI_MAPREG_END) { 429 printf(": unable to locate registers\n"); 430 return; 431 } 432 433 if (pci_mapreg_map(pa, r, memtype, 0, &sc->sc_iot, &sc->sc_ioh, 434 NULL, &sc->sc_ios, VMMPVS_PG_LEN) != 0) { 435 printf(": unable to map registers\n"); 436 return; 437 } 438 439 /* hook up the interrupt */ 440 vmwpvs_write(sc, VMWPVS_R_INTR_MASK, 0); 441 442 if (pci_intr_map_msi(pa, &ih) == 0) 443 isr = vmwpvs_intr; 444 else if (pci_intr_map(pa, &ih) != 0) { 445 printf(": unable to map interrupt\n"); 446 goto unmap; 447 } 448 printf(": %s\n", pci_intr_string(sc->sc_pc, ih)); 449 450 /* do we have msg support? */ 451 vmwpvs_write(sc, VMWPVS_R_COMMAND, VMWPVS_CMD_SETUP_MSG_RING); 452 use_msg = (vmwpvs_read(sc, VMWPVS_R_COMMAND_STATUS) != 0xffffffff); 453 454 if (vmwpvs_get_config(sc) != 0) { 455 printf("%s: get configuration failed\n", DEVNAME(sc)); 456 goto unmap; 457 } 458 459 sc->sc_ring_state = vmwpvs_dmamem_zalloc(sc, VMWPVS_PAGE_SIZE); 460 if (sc->sc_ring_state == NULL) { 461 printf("%s: unable to allocate ring state\n", DEVNAME(sc)); 462 goto unmap; 463 } 464 465 sc->sc_req_ring = vmwpvs_dmamem_zalloc(sc, 466 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE); 467 if (sc->sc_req_ring == NULL) { 468 printf("%s: unable to allocate req ring\n", DEVNAME(sc)); 469 goto free_ring_state; 470 } 471 472 sc->sc_cmp_ring = vmwpvs_dmamem_zalloc(sc, 473 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE); 474 if (sc->sc_cmp_ring == NULL) { 475 printf("%s: unable to allocate cmp ring\n", DEVNAME(sc)); 476 goto free_req_ring; 477 } 478 479 if (use_msg) { 480 sc->sc_msg_ring = vmwpvs_dmamem_zalloc(sc, 481 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE); 482 if (sc->sc_msg_ring == NULL) { 483 printf("%s: unable to allocate msg ring\n", 484 DEVNAME(sc)); 485 goto free_cmp_ring; 486 } 487 } 488 489 r = (VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE) / 490 sizeof(struct vmwpvs_ring_req); 491 492 sc->sc_sgls = vmwpvs_dmamem_alloc(sc, r * sizeof(struct vmwpvs_sgl)); 493 if (sc->sc_sgls == NULL) { 494 printf("%s: unable to allocate sgls\n", DEVNAME(sc)); 495 goto free_msg_ring; 496 } 497 498 sc->sc_sense = vmwpvs_dmamem_alloc(sc, r * VMWPVS_SENSELEN); 499 if (sc->sc_sense == NULL) { 500 printf("%s: unable to allocate sense data\n", DEVNAME(sc)); 501 goto free_sgl; 502 } 503 504 sc->sc_ccbs = mallocarray(r, sizeof(struct vmwpvs_ccb), 505 M_DEVBUF, M_WAITOK); 506 /* cant fail */ 507 508 sgls = VMWPVS_DMA_KVA(sc->sc_sgls); 509 sense = VMWPVS_DMA_KVA(sc->sc_sense); 510 for (i = 0; i < r; i++) { 511 ccb = &sc->sc_ccbs[i]; 512 513 if (bus_dmamap_create(sc->sc_dmat, MAXPHYS, 514 VMWPVS_MAXSGL, MAXPHYS, 0, 515 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 516 &ccb->ccb_dmamap) != 0) { 517 printf("%s: unable to create ccb map\n", DEVNAME(sc)); 518 goto free_ccbs; 519 } 520 521 ccb->ccb_ctx = 0xdeadbeef00000000ULL | (u_int64_t)i; 522 523 ccb->ccb_sgl_offset = i * sizeof(*sgls); 524 ccb->ccb_sgl = &sgls[i]; 525 526 ccb->ccb_sense_offset = i * VMWPVS_SENSELEN; 527 ccb->ccb_sense = sense + ccb->ccb_sense_offset; 528 529 vmwpvs_ccb_put(sc, ccb); 530 } 531 532 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_BIO, 533 isr, sc, DEVNAME(sc)); 534 if (sc->sc_ih == NULL) 535 goto free_msg_ring; 536 537 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_cmp_ring), 0, 538 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD); 539 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_req_ring), 0, 540 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREWRITE); 541 if (use_msg) { 542 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_msg_ring), 0, 543 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD); 544 } 545 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 546 VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 547 548 intmask = VMWPVS_INTR_CMPL_MASK; 549 550 vmwpvs_setup_rings(sc); 551 if (use_msg) { 552 vmwpvs_setup_msg_ring(sc); 553 intmask |= VMWPVS_INTR_MSG_MASK; 554 } 555 556 vmwpvs_write(sc, VMWPVS_R_INTR_MASK, intmask); 557 558 scsi_iopool_init(&sc->sc_iopool, sc, vmwpvs_ccb_get, vmwpvs_ccb_put); 559 560 saa.saa_adapter = &vmwpvs_switch; 561 saa.saa_adapter_softc = sc; 562 saa.saa_adapter_target = SDEV_NO_ADAPTER_TARGET; 563 saa.saa_adapter_buswidth = sc->sc_bus_width; 564 saa.saa_luns = 8; 565 saa.saa_openings = VMWPVS_OPENINGS; 566 saa.saa_pool = &sc->sc_iopool; 567 saa.saa_quirks = saa.saa_flags = 0; 568 saa.saa_wwpn = saa.saa_wwnn = 0; 569 570 sc->sc_scsibus = (struct scsibus_softc *)config_found(&sc->sc_dev, &saa, 571 scsiprint); 572 573 return; 574 free_ccbs: 575 while ((ccb = vmwpvs_ccb_get(sc)) != NULL) 576 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 577 free(sc->sc_ccbs, M_DEVBUF, r * sizeof(struct vmwpvs_ccb)); 578 /* free_sense: */ 579 vmwpvs_dmamem_free(sc, sc->sc_sense); 580 free_sgl: 581 vmwpvs_dmamem_free(sc, sc->sc_sgls); 582 free_msg_ring: 583 if (use_msg) 584 vmwpvs_dmamem_free(sc, sc->sc_msg_ring); 585 free_cmp_ring: 586 vmwpvs_dmamem_free(sc, sc->sc_cmp_ring); 587 free_req_ring: 588 vmwpvs_dmamem_free(sc, sc->sc_req_ring); 589 free_ring_state: 590 vmwpvs_dmamem_free(sc, sc->sc_ring_state); 591 unmap: 592 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 593 sc->sc_ios = 0; 594 } 595 596 void 597 vmwpvs_setup_rings(struct vmwpvs_softc *sc) 598 { 599 struct vmwpvs_setup_rings_cmd cmd; 600 u_int64_t ppn; 601 u_int i; 602 603 memset(&cmd, 0, sizeof(cmd)); 604 cmd.req_pages = VMWPVS_RING_PAGES; 605 cmd.cmp_pages = VMWPVS_RING_PAGES; 606 cmd.state_ppn = VMWPVS_DMA_DVA(sc->sc_ring_state) >> VMWPVS_PAGE_SHIFT; 607 608 ppn = VMWPVS_DMA_DVA(sc->sc_req_ring) >> VMWPVS_PAGE_SHIFT; 609 for (i = 0; i < VMWPVS_RING_PAGES; i++) 610 cmd.req_page_ppn[i] = ppn + i; 611 612 ppn = VMWPVS_DMA_DVA(sc->sc_cmp_ring) >> VMWPVS_PAGE_SHIFT; 613 for (i = 0; i < VMWPVS_RING_PAGES; i++) 614 cmd.cmp_page_ppn[i] = ppn + i; 615 616 vmwpvs_cmd(sc, VMWPVS_CMD_SETUP_RINGS, &cmd, sizeof(cmd)); 617 } 618 619 void 620 vmwpvs_setup_msg_ring(struct vmwpvs_softc *sc) 621 { 622 struct vmwpvs_setup_rings_msg cmd; 623 u_int64_t ppn; 624 u_int i; 625 626 memset(&cmd, 0, sizeof(cmd)); 627 cmd.msg_pages = VMWPVS_RING_PAGES; 628 629 ppn = VMWPVS_DMA_DVA(sc->sc_msg_ring) >> VMWPVS_PAGE_SHIFT; 630 for (i = 0; i < VMWPVS_RING_PAGES; i++) 631 cmd.msg_page_ppn[i] = ppn + i; 632 633 vmwpvs_cmd(sc, VMWPVS_CMD_SETUP_MSG_RING, &cmd, sizeof(cmd)); 634 } 635 636 int 637 vmwpvs_get_config(struct vmwpvs_softc *sc) 638 { 639 struct vmwpvs_cfg_cmd cmd; 640 struct vmwpvs_dmamem *dm; 641 struct vmwpvs_cfg_pg_controller *pg; 642 struct vmwpvs_cfg_pg_header *hdr; 643 int rv = 0; 644 645 dm = vmwpvs_dmamem_alloc(sc, VMWPVS_PAGE_SIZE); 646 if (dm == NULL) 647 return (ENOMEM); 648 649 memset(&cmd, 0, sizeof(cmd)); 650 cmd.cmp_addr = VMWPVS_DMA_DVA(dm); 651 cmd.pg_addr_type = VMWPVS_CFGPGADDR_CONTROLLER; 652 cmd.pg_num = VMWPVS_CFGPG_CONTROLLER; 653 654 pg = VMWPVS_DMA_KVA(dm); 655 memset(pg, 0, VMWPVS_PAGE_SIZE); 656 hdr = &pg->header; 657 hdr->host_status = VMWPVS_HOST_STATUS_INVPARAM; 658 hdr->scsi_status = VMWPVS_SCSI_STATUS_CHECK; 659 660 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(dm), 0, VMWPVS_PAGE_SIZE, 661 BUS_DMASYNC_PREREAD); 662 vmwpvs_cmd(sc, VMWPVS_CMD_CONFIG, &cmd, sizeof(cmd)); 663 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(dm), 0, VMWPVS_PAGE_SIZE, 664 BUS_DMASYNC_POSTREAD); 665 666 if (hdr->host_status != VMWPVS_HOST_STATUS_SUCCESS || 667 hdr->scsi_status != VMWPVS_SCSI_STATUS_OK) { 668 rv = EIO; 669 goto done; 670 } 671 672 sc->sc_bus_width = pg->num_phys; 673 674 done: 675 vmwpvs_dmamem_free(sc, dm); 676 677 return (rv); 678 679 } 680 681 void 682 vmwpvs_cmd(struct vmwpvs_softc *sc, u_int32_t cmd, void *buf, size_t len) 683 { 684 u_int32_t *p = buf; 685 u_int i; 686 687 len /= sizeof(*p); 688 689 vmwpvs_write(sc, VMWPVS_R_COMMAND, cmd); 690 for (i = 0; i < len; i++) 691 vmwpvs_write(sc, VMWPVS_R_COMMAND_DATA, p[i]); 692 } 693 694 int 695 vmwpvs_intx(void *xsc) 696 { 697 struct vmwpvs_softc *sc = xsc; 698 u_int32_t status; 699 700 status = vmwpvs_read(sc, VMWPVS_R_INTR_STATUS); 701 if ((status & VMWPVS_INTR_ALL_MASK) == 0) 702 return (0); 703 704 vmwpvs_write(sc, VMWPVS_R_INTR_STATUS, status); 705 706 return (vmwpvs_intr(sc)); 707 } 708 709 int 710 vmwpvs_intr(void *xsc) 711 { 712 struct vmwpvs_softc *sc = xsc; 713 volatile struct vmwpvw_ring_state *s = 714 VMWPVS_DMA_KVA(sc->sc_ring_state); 715 struct vmwpvs_ring_cmp *ring = VMWPVS_DMA_KVA(sc->sc_cmp_ring); 716 struct vmwpvs_ccb_list list = SIMPLEQ_HEAD_INITIALIZER(list); 717 struct vmwpvs_ccb *ccb; 718 u_int32_t cons, prod; 719 int msg; 720 721 mtx_enter(&sc->sc_ring_mtx); 722 723 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 724 VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 725 cons = s->cmp_cons; 726 prod = s->cmp_prod; 727 s->cmp_cons = prod; 728 729 msg = (sc->sc_msg_ring != NULL && s->msg_cons != s->msg_prod); 730 731 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 732 VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 733 734 if (cons != prod) { 735 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_cmp_ring), 736 0, VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD); 737 738 do { 739 ccb = vmwpvs_scsi_cmd_done(sc, 740 &ring[cons++ % VMWPVS_CMP_COUNT]); 741 SIMPLEQ_INSERT_TAIL(&list, ccb, ccb_entry); 742 } while (cons != prod); 743 744 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_cmp_ring), 745 0, VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD); 746 } 747 748 mtx_leave(&sc->sc_ring_mtx); 749 750 while ((ccb = SIMPLEQ_FIRST(&list)) != NULL) { 751 SIMPLEQ_REMOVE_HEAD(&list, ccb_entry); 752 scsi_done(ccb->ccb_xs); 753 } 754 755 if (msg) 756 task_add(systq, &sc->sc_msg_task); 757 758 return (1); 759 } 760 761 void 762 vmwpvs_msg_task(void *xsc) 763 { 764 struct vmwpvs_softc *sc = xsc; 765 volatile struct vmwpvw_ring_state *s = 766 VMWPVS_DMA_KVA(sc->sc_ring_state); 767 struct vmwpvs_ring_msg *ring = VMWPVS_DMA_KVA(sc->sc_msg_ring); 768 struct vmwpvs_ring_msg *msg; 769 struct vmwpvs_ring_msg_dev *dvmsg; 770 u_int32_t cons, prod; 771 772 mtx_enter(&sc->sc_ring_mtx); 773 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 774 VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 775 cons = s->msg_cons; 776 prod = s->msg_prod; 777 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 778 VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 779 mtx_leave(&sc->sc_ring_mtx); 780 781 /* 782 * we dont have to lock around the msg ring cos the system taskq has 783 * only one thread. 784 */ 785 786 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_msg_ring), 0, 787 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD); 788 while (cons != prod) { 789 msg = &ring[cons++ % VMWPVS_MSG_COUNT]; 790 791 switch (letoh32(msg->type)) { 792 case VMWPVS_MSG_T_ADDED: 793 dvmsg = (struct vmwpvs_ring_msg_dev *)msg; 794 if (letoh32(dvmsg->bus) != 0) { 795 printf("%s: ignoring request to add device" 796 " on bus %d\n", DEVNAME(sc), 797 letoh32(msg->type)); 798 break; 799 } 800 801 if (scsi_probe_lun(sc->sc_scsibus, 802 letoh32(dvmsg->target), dvmsg->lun[1]) != 0) { 803 printf("%s: error probing target %d lun %d\n", 804 DEVNAME(sc), letoh32(dvmsg->target), 805 dvmsg->lun[1]); 806 }; 807 break; 808 809 case VMWPVS_MSG_T_REMOVED: 810 dvmsg = (struct vmwpvs_ring_msg_dev *)msg; 811 if (letoh32(dvmsg->bus) != 0) { 812 printf("%s: ignoring request to remove device" 813 " on bus %d\n", DEVNAME(sc), 814 letoh32(msg->type)); 815 break; 816 } 817 818 if (scsi_detach_lun(sc->sc_scsibus, 819 letoh32(dvmsg->target), dvmsg->lun[1], 820 DETACH_FORCE) != 0) { 821 printf("%s: error detaching target %d lun %d\n", 822 DEVNAME(sc), letoh32(dvmsg->target), 823 dvmsg->lun[1]); 824 }; 825 break; 826 827 default: 828 printf("%s: unknown msg type %u\n", DEVNAME(sc), 829 letoh32(msg->type)); 830 break; 831 } 832 } 833 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_msg_ring), 0, 834 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD); 835 836 mtx_enter(&sc->sc_ring_mtx); 837 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 838 VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 839 s->msg_cons = prod; 840 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 841 VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 842 mtx_leave(&sc->sc_ring_mtx); 843 } 844 845 void 846 vmwpvs_scsi_cmd(struct scsi_xfer *xs) 847 { 848 struct scsi_link *link = xs->sc_link; 849 struct vmwpvs_softc *sc = link->bus->sb_adapter_softc; 850 struct vmwpvs_ccb *ccb = xs->io; 851 bus_dmamap_t dmap = ccb->ccb_dmamap; 852 volatile struct vmwpvw_ring_state *s = 853 VMWPVS_DMA_KVA(sc->sc_ring_state); 854 struct vmwpvs_ring_req *ring = VMWPVS_DMA_KVA(sc->sc_req_ring), *r; 855 u_int32_t prod; 856 struct vmwpvs_ccb_list list; 857 int error; 858 u_int i; 859 860 ccb->ccb_xs = xs; 861 862 if (xs->datalen > 0) { 863 error = bus_dmamap_load(sc->sc_dmat, dmap, 864 xs->data, xs->datalen, NULL, (xs->flags & SCSI_NOSLEEP) ? 865 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 866 if (error) { 867 xs->error = XS_DRIVER_STUFFUP; 868 scsi_done(xs); 869 return; 870 } 871 872 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 873 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : 874 BUS_DMASYNC_PREWRITE); 875 } 876 877 mtx_enter(&sc->sc_ring_mtx); 878 879 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 880 VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 881 882 prod = s->req_prod; 883 r = &ring[prod % VMWPVS_REQ_COUNT]; 884 885 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_req_ring), 886 prod * sizeof(*r), sizeof(*r), BUS_DMASYNC_POSTWRITE); 887 888 memset(r, 0, sizeof(*r)); 889 r->context = ccb->ccb_ctx; 890 891 if (xs->datalen > 0) { 892 r->data_len = xs->datalen; 893 if (dmap->dm_nsegs == 1) { 894 r->data_addr = dmap->dm_segs[0].ds_addr; 895 } else { 896 struct vmwpvs_sge *sgl = ccb->ccb_sgl->list, *sge; 897 898 r->data_addr = VMWPVS_DMA_DVA(sc->sc_sgls) + 899 ccb->ccb_sgl_offset; 900 r->flags = VMWPVS_REQ_SGL; 901 902 for (i = 0; i < dmap->dm_nsegs; i++) { 903 sge = &sgl[i]; 904 sge->addr = dmap->dm_segs[i].ds_addr; 905 sge->len = dmap->dm_segs[i].ds_len; 906 sge->flags = 0; 907 } 908 909 bus_dmamap_sync(sc->sc_dmat, 910 VMWPVS_DMA_MAP(sc->sc_sgls), ccb->ccb_sgl_offset, 911 sizeof(*sge) * dmap->dm_nsegs, 912 BUS_DMASYNC_PREWRITE); 913 } 914 } 915 r->sense_addr = VMWPVS_DMA_DVA(sc->sc_sense) + ccb->ccb_sense_offset; 916 r->sense_len = sizeof(xs->sense); 917 918 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_req_ring), 0, 919 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_POSTWRITE); 920 921 switch (xs->flags & (SCSI_DATA_IN | SCSI_DATA_OUT)) { 922 case SCSI_DATA_IN: 923 r->flags |= VMWPVS_REQ_DIR_IN; 924 break; 925 case SCSI_DATA_OUT: 926 r->flags |= VMWPVS_REQ_DIR_OUT; 927 break; 928 default: 929 r->flags |= VMWPVS_REQ_DIR_NONE; 930 break; 931 } 932 933 memcpy(r->cdb, &xs->cmd, xs->cmdlen); 934 r->cdblen = xs->cmdlen; 935 r->lun[1] = link->lun; /* ugly :( */ 936 r->tag = MSG_SIMPLE_Q_TAG; 937 r->bus = 0; 938 r->target = link->target; 939 r->vcpu_hint = 0; 940 941 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_req_ring), 0, 942 VMWPVS_RING_PAGES * VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREWRITE); 943 944 s->req_prod = prod + 1; 945 946 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_ring_state), 0, 947 VMWPVS_PAGE_SIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 948 949 vmwpvs_write(sc, xs->bp == NULL ? 950 VMWPVS_R_KICK_NON_RW_IO : VMWPVS_R_KICK_RW_IO, 0); 951 952 if (!ISSET(xs->flags, SCSI_POLL)) { 953 mtx_leave(&sc->sc_ring_mtx); 954 return; 955 } 956 957 SIMPLEQ_INIT(&list); 958 do { 959 ccb = vmwpvs_scsi_cmd_poll(sc); 960 SIMPLEQ_INSERT_TAIL(&list, ccb, ccb_entry); 961 } while (xs->io != ccb); 962 963 mtx_leave(&sc->sc_ring_mtx); 964 965 while ((ccb = SIMPLEQ_FIRST(&list)) != NULL) { 966 SIMPLEQ_REMOVE_HEAD(&list, ccb_entry); 967 scsi_done(ccb->ccb_xs); 968 } 969 } 970 971 struct vmwpvs_ccb * 972 vmwpvs_scsi_cmd_poll(struct vmwpvs_softc *sc) 973 { 974 volatile struct vmwpvw_ring_state *s = 975 VMWPVS_DMA_KVA(sc->sc_ring_state); 976 struct vmwpvs_ring_cmp *ring = VMWPVS_DMA_KVA(sc->sc_cmp_ring); 977 struct vmwpvs_ccb *ccb; 978 u_int32_t prod, cons; 979 980 for (;;) { 981 bus_dmamap_sync(sc->sc_dmat, 982 VMWPVS_DMA_MAP(sc->sc_ring_state), 0, VMWPVS_PAGE_SIZE, 983 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 984 985 cons = s->cmp_cons; 986 prod = s->cmp_prod; 987 988 if (cons != prod) 989 s->cmp_cons = cons + 1; 990 991 bus_dmamap_sync(sc->sc_dmat, 992 VMWPVS_DMA_MAP(sc->sc_ring_state), 0, VMWPVS_PAGE_SIZE, 993 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 994 995 if (cons != prod) 996 break; 997 else 998 delay(1000); 999 } 1000 1001 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_cmp_ring), 1002 0, VMWPVS_PAGE_SIZE * VMWPVS_RING_PAGES, 1003 BUS_DMASYNC_POSTREAD); 1004 ccb = vmwpvs_scsi_cmd_done(sc, &ring[cons % VMWPVS_CMP_COUNT]); 1005 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_cmp_ring), 1006 0, VMWPVS_PAGE_SIZE * VMWPVS_RING_PAGES, 1007 BUS_DMASYNC_PREREAD); 1008 1009 return (ccb); 1010 } 1011 1012 struct vmwpvs_ccb * 1013 vmwpvs_scsi_cmd_done(struct vmwpvs_softc *sc, struct vmwpvs_ring_cmp *c) 1014 { 1015 u_int64_t ctx = c->context; 1016 struct vmwpvs_ccb *ccb = &sc->sc_ccbs[ctx & 0xffffffff]; 1017 bus_dmamap_t dmap = ccb->ccb_dmamap; 1018 struct scsi_xfer *xs = ccb->ccb_xs; 1019 1020 bus_dmamap_sync(sc->sc_dmat, VMWPVS_DMA_MAP(sc->sc_sense), 1021 ccb->ccb_sense_offset, sizeof(xs->sense), BUS_DMASYNC_POSTREAD); 1022 1023 if (xs->datalen > 0) { 1024 if (dmap->dm_nsegs > 1) { 1025 bus_dmamap_sync(sc->sc_dmat, 1026 VMWPVS_DMA_MAP(sc->sc_sgls), ccb->ccb_sgl_offset, 1027 sizeof(struct vmwpvs_sge) * dmap->dm_nsegs, 1028 BUS_DMASYNC_POSTWRITE); 1029 } 1030 1031 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 1032 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1033 BUS_DMASYNC_POSTWRITE); 1034 1035 bus_dmamap_unload(sc->sc_dmat, dmap); 1036 } 1037 1038 xs->status = c->scsi_status; 1039 switch (c->host_status) { 1040 case VMWPVS_HOST_STATUS_SUCCESS: 1041 case VMWPVS_HOST_STATUS_LINKED_CMD_COMPLETED: 1042 case VMWPVS_HOST_STATUS_LINKED_CMD_COMPLETED_WITH_FLAG: 1043 if (c->scsi_status == VMWPVS_SCSI_STATUS_CHECK) { 1044 memcpy(&xs->sense, ccb->ccb_sense, sizeof(xs->sense)); 1045 xs->error = XS_SENSE; 1046 } else 1047 xs->error = XS_NOERROR; 1048 xs->resid = 0; 1049 break; 1050 1051 case VMWPVS_HOST_STATUS_UNDERRUN: 1052 case VMWPVS_HOST_STATUS_DATARUN: 1053 xs->resid = xs->datalen - c->data_len; 1054 xs->error = XS_NOERROR; 1055 break; 1056 1057 case VMWPVS_HOST_STATUS_SELTIMEOUT: 1058 xs->error = XS_SELTIMEOUT; 1059 break; 1060 1061 default: 1062 printf("%s: %s:%d h:0x%x s:0x%x\n", DEVNAME(sc), 1063 __FUNCTION__, __LINE__, c->host_status, c->scsi_status); 1064 xs->error = XS_DRIVER_STUFFUP; 1065 break; 1066 } 1067 1068 return (ccb); 1069 } 1070 1071 void * 1072 vmwpvs_ccb_get(void *xsc) 1073 { 1074 struct vmwpvs_softc *sc = xsc; 1075 struct vmwpvs_ccb *ccb; 1076 1077 mtx_enter(&sc->sc_ccb_mtx); 1078 ccb = SIMPLEQ_FIRST(&sc->sc_ccb_list); 1079 if (ccb != NULL) 1080 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_list, ccb_entry); 1081 mtx_leave(&sc->sc_ccb_mtx); 1082 1083 return (ccb); 1084 } 1085 1086 void 1087 vmwpvs_ccb_put(void *xsc, void *io) 1088 { 1089 struct vmwpvs_softc *sc = xsc; 1090 struct vmwpvs_ccb *ccb = io; 1091 1092 mtx_enter(&sc->sc_ccb_mtx); 1093 SIMPLEQ_INSERT_HEAD(&sc->sc_ccb_list, ccb, ccb_entry); 1094 mtx_leave(&sc->sc_ccb_mtx); 1095 } 1096 1097 struct vmwpvs_dmamem * 1098 vmwpvs_dmamem_alloc(struct vmwpvs_softc *sc, size_t size) 1099 { 1100 struct vmwpvs_dmamem *dm; 1101 int nsegs; 1102 1103 dm = malloc(sizeof(*dm), M_DEVBUF, M_NOWAIT | M_ZERO); 1104 if (dm == NULL) 1105 return (NULL); 1106 1107 dm->dm_size = size; 1108 1109 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1110 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &dm->dm_map) != 0) 1111 goto dmfree; 1112 1113 if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &dm->dm_seg, 1114 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0) 1115 goto destroy; 1116 1117 if (bus_dmamem_map(sc->sc_dmat, &dm->dm_seg, nsegs, size, 1118 &dm->dm_kva, BUS_DMA_NOWAIT) != 0) 1119 goto free; 1120 1121 if (bus_dmamap_load(sc->sc_dmat, dm->dm_map, dm->dm_kva, size, 1122 NULL, BUS_DMA_NOWAIT) != 0) 1123 goto unmap; 1124 1125 return (dm); 1126 1127 unmap: 1128 bus_dmamem_unmap(sc->sc_dmat, dm->dm_kva, size); 1129 free: 1130 bus_dmamem_free(sc->sc_dmat, &dm->dm_seg, 1); 1131 destroy: 1132 bus_dmamap_destroy(sc->sc_dmat, dm->dm_map); 1133 dmfree: 1134 free(dm, M_DEVBUF, sizeof *dm); 1135 1136 return (NULL); 1137 } 1138 1139 struct vmwpvs_dmamem * 1140 vmwpvs_dmamem_zalloc(struct vmwpvs_softc *sc, size_t size) 1141 { 1142 struct vmwpvs_dmamem *dm; 1143 1144 dm = vmwpvs_dmamem_alloc(sc, size); 1145 if (dm == NULL) 1146 return (NULL); 1147 1148 memset(VMWPVS_DMA_KVA(dm), 0, size); 1149 1150 return (dm); 1151 } 1152 1153 void 1154 vmwpvs_dmamem_free(struct vmwpvs_softc *sc, struct vmwpvs_dmamem *dm) 1155 { 1156 bus_dmamap_unload(sc->sc_dmat, dm->dm_map); 1157 bus_dmamem_unmap(sc->sc_dmat, dm->dm_kva, dm->dm_size); 1158 bus_dmamem_free(sc->sc_dmat, &dm->dm_seg, 1); 1159 bus_dmamap_destroy(sc->sc_dmat, dm->dm_map); 1160 free(dm, M_DEVBUF, sizeof *dm); 1161 } 1162