1 /* $OpenBSD: be.c,v 1.14 2003/06/27 01:50:52 jason Exp $ */ 2 /* $NetBSD: be.c,v 1.26 2001/03/20 15:39:20 pk Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 55 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 57 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 58 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 62 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 #include "bpfilter.h" 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/timeout.h> 70 #include <sys/kernel.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 79 #include <net/if.h> 80 #include <net/if_dl.h> 81 #include <net/if_types.h> 82 #include <net/netisr.h> 83 #include <net/if_media.h> 84 85 #ifdef INET 86 #include <netinet/in.h> 87 #include <netinet/in_systm.h> 88 #include <netinet/in_var.h> 89 #include <netinet/ip.h> 90 #include <netinet/if_ether.h> 91 #endif 92 93 #ifdef NS 94 #include <netns/ns.h> 95 #include <netns/ns_if.h> 96 #endif 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <machine/bus.h> 104 #include <machine/intr.h> 105 #include <machine/autoconf.h> 106 107 #include <dev/sbus/sbusvar.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/sbus/qecreg.h> 113 #include <dev/sbus/qecvar.h> 114 #include <dev/sbus/bereg.h> 115 116 struct be_softc { 117 struct device sc_dev; 118 struct sbusdev sc_sd; /* sbus device */ 119 bus_space_tag_t sc_bustag; /* bus & dma tags */ 120 bus_dma_tag_t sc_dmatag; 121 bus_dmamap_t sc_dmamap; 122 struct arpcom sc_arpcom; 123 /*struct ifmedia sc_ifmedia; -* interface media */ 124 struct mii_data sc_mii; /* MII media control */ 125 #define sc_media sc_mii.mii_media/* shorthand */ 126 int sc_phys[2]; /* MII instance -> phy */ 127 128 struct timeout sc_tick_ch; 129 130 /* 131 * Some `mii_softc' items we need to emulate MII operation 132 * for our internal transceiver. 133 */ 134 int sc_mii_inst; /* instance of internal phy */ 135 int sc_mii_active; /* currently active medium */ 136 int sc_mii_ticks; /* tick counter */ 137 int sc_mii_flags; /* phy status flags */ 138 #define MIIF_HAVELINK 0x04000000 139 int sc_intphy_curspeed; /* Established link speed */ 140 141 struct qec_softc *sc_qec; /* QEC parent */ 142 143 bus_space_handle_t sc_qr; /* QEC registers */ 144 bus_space_handle_t sc_br; /* BE registers */ 145 bus_space_handle_t sc_cr; /* channel registers */ 146 bus_space_handle_t sc_tr; /* transceiver registers */ 147 148 u_int sc_rev; 149 150 int sc_channel; /* channel number */ 151 int sc_burst; 152 153 struct qec_ring sc_rb; /* Packet Ring Buffer */ 154 }; 155 156 int bematch(struct device *, void *, void *); 157 void beattach(struct device *, struct device *, void *); 158 159 void beinit(struct be_softc *); 160 void bestart(struct ifnet *); 161 void bestop(struct be_softc *); 162 void bewatchdog(struct ifnet *); 163 int beioctl(struct ifnet *, u_long, caddr_t); 164 void bereset(struct be_softc *); 165 166 int beintr(void *); 167 int berint(struct be_softc *); 168 int betint(struct be_softc *); 169 int beqint(struct be_softc *, u_int32_t); 170 int beeint(struct be_softc *, u_int32_t); 171 172 static void be_read(struct be_softc *, int, int); 173 static int be_put(struct be_softc *, int, struct mbuf *); 174 static struct mbuf *be_get(struct be_softc *, int, int); 175 176 void be_pal_gate(struct be_softc *, int); 177 178 /* ifmedia callbacks */ 179 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 180 int be_ifmedia_upd(struct ifnet *); 181 182 void be_mcreset(struct be_softc *); 183 184 /* MII methods & callbacks */ 185 static int be_mii_readreg(struct device *, int, int); 186 static void be_mii_writereg(struct device *, int, int, int); 187 static void be_mii_statchg(struct device *); 188 189 /* MII helpers */ 190 static void be_mii_sync(struct be_softc *); 191 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 192 static int be_mii_reset(struct be_softc *, int); 193 static int be_tcvr_read_bit(struct be_softc *, int); 194 static void be_tcvr_write_bit(struct be_softc *, int, int); 195 196 void be_tick(void *); 197 void be_intphy_auto(struct be_softc *); 198 void be_intphy_status(struct be_softc *); 199 int be_intphy_service(struct be_softc *, struct mii_data *, int); 200 201 202 struct cfattach be_ca = { 203 sizeof(struct be_softc), bematch, beattach 204 }; 205 206 struct cfdriver be_cd = { 207 NULL, "be", DV_IFNET 208 }; 209 210 int 211 bematch(struct device *parent, void *vcf, void *aux) 212 { 213 struct cfdata *cf = vcf; 214 struct sbus_attach_args *sa = aux; 215 216 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 217 } 218 219 void 220 beattach(struct device *parent, struct device *self, void *aux) 221 { 222 struct sbus_attach_args *sa = aux; 223 struct qec_softc *qec = (struct qec_softc *)parent; 224 struct be_softc *sc = (struct be_softc *)self; 225 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 226 struct mii_data *mii = &sc->sc_mii; 227 struct mii_softc *child; 228 int node = sa->sa_node; 229 bus_dma_tag_t dmatag = sa->sa_dmatag; 230 bus_dma_segment_t seg; 231 bus_size_t size; 232 int instance; 233 int rseg, error; 234 u_int32_t v; 235 extern void myetheraddr(u_char *); 236 237 /* Pass on the bus tags */ 238 sc->sc_bustag = sa->sa_bustag; 239 sc->sc_dmatag = sa->sa_dmatag; 240 241 if (sa->sa_nreg < 3) { 242 printf("%s: only %d register sets\n", 243 self->dv_xname, sa->sa_nreg); 244 return; 245 } 246 247 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 248 (bus_addr_t)sa->sa_reg[0].sbr_offset, 249 (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) { 250 printf("beattach: cannot map registers\n"); 251 return; 252 } 253 254 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, 255 (bus_addr_t)sa->sa_reg[1].sbr_offset, 256 (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_br) != 0) { 257 printf("beattach: cannot map registers\n"); 258 return; 259 } 260 261 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[2].sbr_slot, 262 (bus_addr_t)sa->sa_reg[2].sbr_offset, 263 (bus_size_t)sa->sa_reg[2].sbr_size, 0, 0, &sc->sc_tr) != 0) { 264 printf("beattach: cannot map registers\n"); 265 return; 266 } 267 268 sc->sc_qec = qec; 269 sc->sc_qr = qec->sc_regs; 270 271 sc->sc_rev = getpropint(node, "board-version", -1); 272 printf(" rev %x", sc->sc_rev); 273 274 bestop(sc); 275 276 sc->sc_channel = getpropint(node, "channel#", -1); 277 if (sc->sc_channel == -1) 278 sc->sc_channel = 0; 279 280 sc->sc_burst = getpropint(node, "burst-sizes", -1); 281 if (sc->sc_burst == -1) 282 sc->sc_burst = qec->sc_burst; 283 284 /* Clamp at parent's burst sizes */ 285 sc->sc_burst &= qec->sc_burst; 286 287 /* Establish interrupt handler */ 288 if (sa->sa_nintr == 0 || bus_intr_establish(sa->sa_bustag, sa->sa_pri, 289 IPL_NET, 0, beintr, sc, self->dv_xname) == NULL) { 290 printf(": no interrupt established\n"); 291 return; 292 } 293 294 myetheraddr(sc->sc_arpcom.ac_enaddr); 295 printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 296 297 /* 298 * Allocate descriptor ring and buffers. 299 */ 300 301 /* for now, allocate as many bufs as there are ring descriptors */ 302 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 303 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 304 305 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 306 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 307 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 308 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 309 310 /* Get a DMA handle */ 311 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 312 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 313 printf("%s: DMA map create error %d\n", self->dv_xname, error); 314 return; 315 } 316 317 /* Allocate DMA buffer */ 318 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 319 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 320 printf("%s: DMA buffer alloc error %d\n", 321 self->dv_xname, error); 322 return; 323 } 324 325 /* Map DMA memory in CPU addressable space */ 326 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 327 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 328 printf("%s: DMA buffer map error %d\n", 329 self->dv_xname, error); 330 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 331 return; 332 } 333 334 /* Load the buffer */ 335 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 336 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 337 printf("%s: DMA buffer map load error %d\n", 338 self->dv_xname, error); 339 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 340 bus_dmamem_free(dmatag, &seg, rseg); 341 return; 342 } 343 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 344 345 /* 346 * Initialize our media structures and MII info. 347 */ 348 mii->mii_ifp = ifp; 349 mii->mii_readreg = be_mii_readreg; 350 mii->mii_writereg = be_mii_writereg; 351 mii->mii_statchg = be_mii_statchg; 352 353 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 354 355 timeout_set(&sc->sc_tick_ch, be_tick, sc); 356 357 /* 358 * Initialize transceiver and determine which PHY connection to use. 359 */ 360 be_mii_sync(sc); 361 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 362 363 instance = 0; 364 365 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 366 367 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 368 MII_OFFSET_ANY, 0); 369 370 child = LIST_FIRST(&mii->mii_phys); 371 if (child == NULL) { 372 /* No PHY attached */ 373 ifmedia_add(&sc->sc_media, 374 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 375 0, NULL); 376 ifmedia_set(&sc->sc_media, 377 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 378 } else { 379 /* 380 * Note: we support just one PHY on the external 381 * MII connector. 382 */ 383 #ifdef DIAGNOSTIC 384 if (LIST_NEXT(child, mii_list) != NULL) { 385 printf("%s: spurious MII device %s attached\n", 386 sc->sc_dev.dv_xname, 387 child->mii_dev.dv_xname); 388 } 389 #endif 390 if (child->mii_phy != BE_PHY_EXTERNAL || 391 child->mii_inst > 0) { 392 printf("%s: cannot accommodate MII device %s" 393 " at phy %d, instance %d\n", 394 sc->sc_dev.dv_xname, 395 child->mii_dev.dv_xname, 396 child->mii_phy, child->mii_inst); 397 } else { 398 sc->sc_phys[instance] = child->mii_phy; 399 } 400 401 /* 402 * XXX - we can really do the following ONLY if the 403 * phy indeed has the auto negotiation capability!! 404 */ 405 ifmedia_set(&sc->sc_media, 406 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 407 408 /* Mark our current media setting */ 409 be_pal_gate(sc, BE_PHY_EXTERNAL); 410 instance++; 411 } 412 413 } 414 415 if ((v & MGMT_PAL_INT_MDIO) != 0) { 416 /* 417 * The be internal phy looks vaguely like MII hardware, 418 * but not enough to be able to use the MII device 419 * layer. Hence, we have to take care of media selection 420 * ourselves. 421 */ 422 423 sc->sc_mii_inst = instance; 424 sc->sc_phys[instance] = BE_PHY_INTERNAL; 425 426 /* Use `ifm_data' to store BMCR bits */ 427 ifmedia_add(&sc->sc_media, 428 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 0, NULL); 429 ifmedia_add(&sc->sc_media, 430 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 431 BMCR_S100, NULL); 432 ifmedia_add(&sc->sc_media, 433 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 0, NULL); 434 435 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 436 self->dv_xname); 437 438 be_mii_reset(sc, BE_PHY_INTERNAL); 439 /* Only set default medium here if there's no external PHY */ 440 if (instance == 0) { 441 be_pal_gate(sc, BE_PHY_INTERNAL); 442 ifmedia_set(&sc->sc_media, 443 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 444 } else 445 be_mii_writereg((void *)sc, 446 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 447 } 448 449 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 450 ifp->if_softc = sc; 451 ifp->if_start = bestart; 452 ifp->if_ioctl = beioctl; 453 ifp->if_watchdog = bewatchdog; 454 ifp->if_flags = 455 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 456 IFQ_SET_READY(&ifp->if_snd); 457 458 /* Attach the interface. */ 459 if_attach(ifp); 460 ether_ifattach(ifp); 461 } 462 463 464 /* 465 * Routine to copy from mbuf chain to transmit buffer in 466 * network buffer memory. 467 */ 468 static __inline__ int 469 be_put(struct be_softc *sc, int idx, struct mbuf *m) 470 { 471 struct mbuf *n; 472 int len, tlen = 0, boff = 0; 473 caddr_t bp; 474 475 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 476 477 for (; m; m = n) { 478 len = m->m_len; 479 if (len == 0) { 480 MFREE(m, n); 481 continue; 482 } 483 bcopy(mtod(m, caddr_t), bp+boff, len); 484 boff += len; 485 tlen += len; 486 MFREE(m, n); 487 } 488 return (tlen); 489 } 490 491 /* 492 * Pull data off an interface. 493 * Len is the length of data, with local net header stripped. 494 * We copy the data into mbufs. When full cluster sized units are present, 495 * we copy into clusters. 496 */ 497 static __inline__ struct mbuf * 498 be_get(struct be_softc *sc, int idx, int totlen) 499 { 500 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 501 struct mbuf *m; 502 struct mbuf *top, **mp; 503 int len, pad, boff = 0; 504 caddr_t bp; 505 506 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 507 508 MGETHDR(m, M_DONTWAIT, MT_DATA); 509 if (m == NULL) 510 return (NULL); 511 m->m_pkthdr.rcvif = ifp; 512 m->m_pkthdr.len = totlen; 513 514 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 515 m->m_data += pad; 516 len = MHLEN - pad; 517 top = NULL; 518 mp = ⊤ 519 520 while (totlen > 0) { 521 if (top) { 522 MGET(m, M_DONTWAIT, MT_DATA); 523 if (m == NULL) { 524 m_freem(top); 525 return (NULL); 526 } 527 len = MLEN; 528 } 529 if (top && totlen >= MINCLSIZE) { 530 MCLGET(m, M_DONTWAIT); 531 if (m->m_flags & M_EXT) 532 len = MCLBYTES; 533 } 534 m->m_len = len = min(totlen, len); 535 bcopy(bp + boff, mtod(m, caddr_t), len); 536 boff += len; 537 totlen -= len; 538 *mp = m; 539 mp = &m->m_next; 540 } 541 542 return (top); 543 } 544 545 /* 546 * Pass a packet to the higher levels. 547 */ 548 static __inline__ void 549 be_read(struct be_softc *sc, int idx, int len) 550 { 551 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 552 struct mbuf *m; 553 554 if (len <= sizeof(struct ether_header) || 555 len > ETHERMTU + sizeof(struct ether_header)) { 556 557 printf("%s: invalid packet size %d; dropping\n", 558 ifp->if_xname, len); 559 560 ifp->if_ierrors++; 561 return; 562 } 563 564 /* 565 * Pull packet off interface. 566 */ 567 m = be_get(sc, idx, len); 568 if (m == NULL) { 569 ifp->if_ierrors++; 570 return; 571 } 572 ifp->if_ipackets++; 573 574 #if NBPFILTER > 0 575 /* 576 * Check if there's a BPF listener on this interface. 577 * If so, hand off the raw packet to BPF. 578 */ 579 if (ifp->if_bpf) 580 bpf_mtap(ifp->if_bpf, m); 581 #endif 582 /* Pass the packet up. */ 583 ether_input_mbuf(ifp, m); 584 } 585 586 /* 587 * Start output on interface. 588 * We make two assumptions here: 589 * 1) that the current priority is set to splnet _before_ this code 590 * is called *and* is returned to the appropriate priority after 591 * return 592 * 2) that the IFF_OACTIVE flag is checked before this code is called 593 * (i.e. that the output part of the interface is idle) 594 */ 595 void 596 bestart(struct ifnet *ifp) 597 { 598 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 599 struct qec_xd *txd = sc->sc_rb.rb_txd; 600 struct mbuf *m; 601 unsigned int bix, len; 602 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 603 604 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 605 return; 606 607 bix = sc->sc_rb.rb_tdhead; 608 609 for (;;) { 610 IFQ_DEQUEUE(&ifp->if_snd, m); 611 if (m == 0) 612 break; 613 614 #if NBPFILTER > 0 615 /* 616 * If BPF is listening on this interface, let it see the 617 * packet before we commit it to the wire. 618 */ 619 if (ifp->if_bpf) 620 bpf_mtap(ifp->if_bpf, m); 621 #endif 622 623 /* 624 * Copy the mbuf chain into the transmit buffer. 625 */ 626 len = be_put(sc, bix, m); 627 628 /* 629 * Initialize transmit registers and start transmission 630 */ 631 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 632 (len & QEC_XD_LENGTH); 633 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 634 BE_CR_CTRL_TWAKEUP); 635 636 if (++bix == QEC_XD_RING_MAXSIZE) 637 bix = 0; 638 639 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 640 ifp->if_flags |= IFF_OACTIVE; 641 break; 642 } 643 } 644 645 sc->sc_rb.rb_tdhead = bix; 646 } 647 648 void 649 bestop(struct be_softc *sc) 650 { 651 int n; 652 bus_space_tag_t t = sc->sc_bustag; 653 bus_space_handle_t br = sc->sc_br; 654 655 timeout_del(&sc->sc_tick_ch); 656 657 /* Down the MII. */ 658 mii_down(&sc->sc_mii); 659 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 660 661 /* Stop the transmitter */ 662 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 663 for (n = 32; n > 0; n--) { 664 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 665 break; 666 DELAY(20); 667 } 668 669 /* Stop the receiver */ 670 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 671 for (n = 32; n > 0; n--) { 672 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 673 break; 674 DELAY(20); 675 } 676 } 677 678 /* 679 * Reset interface. 680 */ 681 void 682 bereset(struct be_softc *sc) 683 { 684 int s; 685 686 s = splnet(); 687 bestop(sc); 688 if ((sc->sc_arpcom.ac_if.if_flags & IFF_UP) != 0) 689 beinit(sc); 690 splx(s); 691 } 692 693 void 694 bewatchdog(struct ifnet *ifp) 695 { 696 struct be_softc *sc = ifp->if_softc; 697 698 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 699 ++sc->sc_arpcom.ac_if.if_oerrors; 700 bereset(sc); 701 } 702 703 int 704 beintr(void *v) 705 { 706 struct be_softc *sc = (struct be_softc *)v; 707 bus_space_tag_t t = sc->sc_bustag; 708 u_int32_t whyq, whyb, whyc; 709 int r = 0; 710 711 /* Read QEC status, channel status and BE status */ 712 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 713 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 714 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 715 716 if (whyq & QEC_STAT_BM) 717 r |= beeint(sc, whyb); 718 719 if (whyq & QEC_STAT_ER) 720 r |= beqint(sc, whyc); 721 722 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 723 r |= betint(sc); 724 725 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 726 r |= berint(sc); 727 728 return (r); 729 } 730 731 /* 732 * QEC Interrupt. 733 */ 734 int 735 beqint(struct be_softc *sc, u_int32_t why) 736 { 737 int r = 0, rst = 0; 738 739 if (why & BE_CR_STAT_TXIRQ) 740 r |= 1; 741 if (why & BE_CR_STAT_RXIRQ) 742 r |= 1; 743 744 if (why & BE_CR_STAT_BERROR) { 745 r |= 1; 746 rst = 1; 747 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 748 } 749 750 if (why & BE_CR_STAT_TXDERR) { 751 r |= 1; 752 rst = 1; 753 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 754 } 755 756 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 757 r |= 1; 758 rst = 1; 759 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 760 if (why & BE_CR_STAT_TXLERR) 761 printf("Late "); 762 if (why & BE_CR_STAT_TXPERR) 763 printf("Parity "); 764 if (why & BE_CR_STAT_TXSERR) 765 printf("Generic "); 766 printf(")\n"); 767 } 768 769 if (why & BE_CR_STAT_RXDROP) { 770 r |= 1; 771 rst = 1; 772 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 773 } 774 775 if (why & BE_CR_STAT_RXSMALL) { 776 r |= 1; 777 rst = 1; 778 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 779 } 780 781 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 782 r |= 1; 783 rst = 1; 784 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 785 if (why & BE_CR_STAT_RXLERR) 786 printf("Late "); 787 if (why & BE_CR_STAT_RXPERR) 788 printf("Parity "); 789 if (why & BE_CR_STAT_RXSERR) 790 printf("Generic "); 791 printf(")\n"); 792 } 793 794 if (!r) { 795 rst = 1; 796 printf("%s: unexpected error interrupt %08x\n", 797 sc->sc_dev.dv_xname, why); 798 } 799 800 if (rst) { 801 printf("%s: resetting\n", sc->sc_dev.dv_xname); 802 bereset(sc); 803 } 804 805 return (r); 806 } 807 808 /* 809 * Error interrupt. 810 */ 811 int 812 beeint(struct be_softc *sc, u_int32_t why) 813 { 814 int r = 0, rst = 0; 815 816 if (why & BE_BR_STAT_RFIFOVF) { 817 r |= 1; 818 rst = 1; 819 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 820 } 821 if (why & BE_BR_STAT_TFIFO_UND) { 822 r |= 1; 823 rst = 1; 824 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 825 } 826 if (why & BE_BR_STAT_MAXPKTERR) { 827 r |= 1; 828 rst = 1; 829 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 830 } 831 832 if (!r) { 833 rst = 1; 834 printf("%s: unexpected error interrupt %08x\n", 835 sc->sc_dev.dv_xname, why); 836 } 837 838 if (rst) { 839 printf("%s: resetting\n", sc->sc_dev.dv_xname); 840 bereset(sc); 841 } 842 843 return (r); 844 } 845 846 /* 847 * Transmit interrupt. 848 */ 849 int 850 betint(struct be_softc *sc) 851 { 852 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 853 bus_space_tag_t t = sc->sc_bustag; 854 bus_space_handle_t br = sc->sc_br; 855 unsigned int bix, txflags; 856 857 /* 858 * Unload collision counters 859 */ 860 ifp->if_collisions += 861 bus_space_read_4(t, br, BE_BRI_NCCNT) + 862 bus_space_read_4(t, br, BE_BRI_FCCNT) + 863 bus_space_read_4(t, br, BE_BRI_EXCNT) + 864 bus_space_read_4(t, br, BE_BRI_LTCNT); 865 866 /* 867 * the clear the hardware counters 868 */ 869 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 870 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 871 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 872 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 873 874 bix = sc->sc_rb.rb_tdtail; 875 876 for (;;) { 877 if (sc->sc_rb.rb_td_nbusy <= 0) 878 break; 879 880 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 881 882 if (txflags & QEC_XD_OWN) 883 break; 884 885 ifp->if_flags &= ~IFF_OACTIVE; 886 ifp->if_opackets++; 887 888 if (++bix == QEC_XD_RING_MAXSIZE) 889 bix = 0; 890 891 --sc->sc_rb.rb_td_nbusy; 892 } 893 894 sc->sc_rb.rb_tdtail = bix; 895 896 bestart(ifp); 897 898 if (sc->sc_rb.rb_td_nbusy == 0) 899 ifp->if_timer = 0; 900 901 return (1); 902 } 903 904 /* 905 * Receive interrupt. 906 */ 907 int 908 berint(struct be_softc *sc) 909 { 910 struct qec_xd *xd = sc->sc_rb.rb_rxd; 911 unsigned int bix, len; 912 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 913 914 bix = sc->sc_rb.rb_rdtail; 915 916 /* 917 * Process all buffers with valid data. 918 */ 919 for (;;) { 920 len = xd[bix].xd_flags; 921 if (len & QEC_XD_OWN) 922 break; 923 924 len &= QEC_XD_LENGTH; 925 be_read(sc, bix, len); 926 927 /* ... */ 928 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 929 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 930 931 if (++bix == QEC_XD_RING_MAXSIZE) 932 bix = 0; 933 } 934 935 sc->sc_rb.rb_rdtail = bix; 936 937 return (1); 938 } 939 940 int 941 beioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 942 { 943 struct be_softc *sc = ifp->if_softc; 944 struct ifaddr *ifa = (struct ifaddr *)data; 945 struct ifreq *ifr = (struct ifreq *)data; 946 int s, error = 0; 947 948 s = splnet(); 949 950 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) { 951 splx(s); 952 return (error); 953 } 954 955 switch (cmd) { 956 case SIOCSIFADDR: 957 ifp->if_flags |= IFF_UP; 958 switch (ifa->ifa_addr->sa_family) { 959 #ifdef INET 960 case AF_INET: 961 beinit(sc); 962 arp_ifinit(&sc->sc_arpcom, ifa); 963 break; 964 #endif /* INET */ 965 #ifdef NS 966 case AF_NS: 967 { 968 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 969 970 if (ns_nullhost(*ina)) 971 ina->x_host = 972 *(union ns_host *)LLADDR(ifp->if_sadl); 973 else 974 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 975 sizeof(sc->sc_arpcom.ac_enaddr)); 976 /* Set new address. */ 977 beinit(sc); 978 break; 979 } 980 #endif /* NS */ 981 default: 982 beinit(sc); 983 break; 984 } 985 break; 986 987 case SIOCSIFFLAGS: 988 if ((ifp->if_flags & IFF_UP) == 0 && 989 (ifp->if_flags & IFF_RUNNING) != 0) { 990 /* 991 * If interface is marked down and it is running, then 992 * stop it. 993 */ 994 bestop(sc); 995 ifp->if_flags &= ~IFF_RUNNING; 996 } else if ((ifp->if_flags & IFF_UP) != 0 && 997 (ifp->if_flags & IFF_RUNNING) == 0) { 998 /* 999 * If interface is marked up and it is stopped, then 1000 * start it. 1001 */ 1002 beinit(sc); 1003 } else { 1004 /* 1005 * Reset the interface to pick up changes in any other 1006 * flags that affect hardware registers. 1007 */ 1008 bestop(sc); 1009 beinit(sc); 1010 } 1011 #ifdef BEDEBUG 1012 if (ifp->if_flags & IFF_DEBUG) 1013 sc->sc_debug = 1; 1014 else 1015 sc->sc_debug = 0; 1016 #endif 1017 break; 1018 1019 case SIOCADDMULTI: 1020 case SIOCDELMULTI: 1021 error = (cmd == SIOCADDMULTI) ? 1022 ether_addmulti(ifr, &sc->sc_arpcom): 1023 ether_delmulti(ifr, &sc->sc_arpcom); 1024 1025 if (error == ENETRESET) { 1026 /* 1027 * Multicast list has changed; set the hardware filter 1028 * accordingly. 1029 */ 1030 be_mcreset(sc); 1031 error = 0; 1032 } 1033 break; 1034 case SIOCGIFMEDIA: 1035 case SIOCSIFMEDIA: 1036 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1037 break; 1038 default: 1039 error = EINVAL; 1040 break; 1041 } 1042 splx(s); 1043 return (error); 1044 } 1045 1046 1047 void 1048 beinit(struct be_softc *sc) 1049 { 1050 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1051 bus_space_tag_t t = sc->sc_bustag; 1052 bus_space_handle_t br = sc->sc_br; 1053 bus_space_handle_t cr = sc->sc_cr; 1054 struct qec_softc *qec = sc->sc_qec; 1055 u_int32_t v; 1056 u_int32_t qecaddr; 1057 u_int8_t *ea; 1058 int s; 1059 1060 s = splnet(); 1061 1062 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1063 1064 bestop(sc); 1065 1066 ea = sc->sc_arpcom.ac_enaddr; 1067 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1068 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1069 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1070 1071 /* Clear hash table */ 1072 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1073 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1074 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1075 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1076 1077 /* Re-initialize RX configuration */ 1078 v = BE_BR_RXCFG_FIFO; 1079 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1080 1081 be_mcreset(sc); 1082 1083 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1084 1085 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1086 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1087 1088 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1089 1090 /* 1091 * Turn off counter expiration interrupts as well as 1092 * 'gotframe' and 'sentframe' 1093 */ 1094 bus_space_write_4(t, br, BE_BRI_IMASK, 1095 BE_BR_IMASK_GOTFRAME | 1096 BE_BR_IMASK_RCNTEXP | 1097 BE_BR_IMASK_ACNTEXP | 1098 BE_BR_IMASK_CCNTEXP | 1099 BE_BR_IMASK_LCNTEXP | 1100 BE_BR_IMASK_CVCNTEXP | 1101 BE_BR_IMASK_SENTFRAME | 1102 BE_BR_IMASK_NCNTEXP | 1103 BE_BR_IMASK_ECNTEXP | 1104 BE_BR_IMASK_LCCNTEXP | 1105 BE_BR_IMASK_FCNTEXP | 1106 BE_BR_IMASK_DTIMEXP); 1107 1108 /* Channel registers: */ 1109 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1110 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1111 1112 qecaddr = sc->sc_channel * qec->sc_msize; 1113 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1114 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1115 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1116 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1117 1118 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1119 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1120 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1121 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1122 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1123 1124 /* Enable transmitter */ 1125 bus_space_write_4(t, br, BE_BRI_TXCFG, 1126 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1127 1128 /* Enable receiver */ 1129 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1130 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1131 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1132 1133 ifp->if_flags |= IFF_RUNNING; 1134 ifp->if_flags &= ~IFF_OACTIVE; 1135 1136 be_ifmedia_upd(ifp); 1137 timeout_add(&sc->sc_tick_ch, hz); 1138 splx(s); 1139 } 1140 1141 void 1142 be_mcreset(struct be_softc *sc) 1143 { 1144 struct arpcom *ac = &sc->sc_arpcom; 1145 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1146 bus_space_tag_t t = sc->sc_bustag; 1147 bus_space_handle_t br = sc->sc_br; 1148 u_int32_t crc; 1149 u_int16_t hash[4]; 1150 u_int8_t octet; 1151 u_int32_t v; 1152 int i, j; 1153 struct ether_multi *enm; 1154 struct ether_multistep step; 1155 1156 if (ifp->if_flags & IFF_PROMISC) { 1157 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1158 v |= BE_BR_RXCFG_PMISC; 1159 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1160 return; 1161 } 1162 1163 if (ifp->if_flags & IFF_ALLMULTI) { 1164 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1165 goto chipit; 1166 } 1167 1168 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1169 1170 ETHER_FIRST_MULTI(step, ac, enm); 1171 while (enm != NULL) { 1172 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1173 /* 1174 * We must listen to a range of multicast 1175 * addresses. For now, just accept all 1176 * multicasts, rather than trying to set only 1177 * those filter bits needed to match the range. 1178 * (At this time, the only use of address 1179 * ranges is for IP multicast routing, for 1180 * which the range is big enough to require 1181 * all bits set.) 1182 */ 1183 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1184 ifp->if_flags |= IFF_ALLMULTI; 1185 goto chipit; 1186 } 1187 1188 crc = 0xffffffff; 1189 1190 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1191 octet = enm->enm_addrlo[i]; 1192 1193 for (j = 0; j < 8; j++) { 1194 if ((crc & 1) ^ (octet & 1)) { 1195 crc >>= 1; 1196 crc ^= MC_POLY_LE; 1197 } 1198 else 1199 crc >>= 1; 1200 octet >>= 1; 1201 } 1202 } 1203 1204 crc >>= 26; 1205 hash[crc >> 4] |= 1 << (crc & 0xf); 1206 ETHER_NEXT_MULTI(step, enm); 1207 } 1208 1209 ifp->if_flags &= ~IFF_ALLMULTI; 1210 1211 chipit: 1212 /* Enable the hash filter */ 1213 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1214 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1215 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1216 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1217 1218 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1219 v &= ~BE_BR_RXCFG_PMISC; 1220 v |= BE_BR_RXCFG_HENABLE; 1221 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1222 } 1223 1224 /* 1225 * Set the tcvr to an idle state 1226 */ 1227 void 1228 be_mii_sync(struct be_softc *sc) 1229 { 1230 bus_space_tag_t t = sc->sc_bustag; 1231 bus_space_handle_t tr = sc->sc_tr; 1232 int n = 32; 1233 1234 while (n--) { 1235 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1236 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1237 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1238 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1239 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1240 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1241 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1242 } 1243 } 1244 1245 void 1246 be_pal_gate(struct be_softc *sc, int phy) 1247 { 1248 bus_space_tag_t t = sc->sc_bustag; 1249 bus_space_handle_t tr = sc->sc_tr; 1250 u_int32_t v; 1251 1252 be_mii_sync(sc); 1253 1254 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1255 if (phy == BE_PHY_INTERNAL) 1256 v &= ~TCVR_PAL_SERIAL; 1257 1258 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1259 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1260 } 1261 1262 static int 1263 be_tcvr_read_bit(struct be_softc *sc, int phy) 1264 { 1265 bus_space_tag_t t = sc->sc_bustag; 1266 bus_space_handle_t tr = sc->sc_tr; 1267 int ret; 1268 1269 if (phy == BE_PHY_INTERNAL) { 1270 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1271 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1272 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1273 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1274 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1275 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1276 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1277 } else { 1278 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1279 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1280 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1281 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1282 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1283 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1284 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1285 } 1286 1287 return (ret); 1288 } 1289 1290 static void 1291 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1292 { 1293 bus_space_tag_t t = sc->sc_bustag; 1294 bus_space_handle_t tr = sc->sc_tr; 1295 u_int32_t v; 1296 1297 if (phy == BE_PHY_INTERNAL) { 1298 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1299 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1300 } else { 1301 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1302 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1303 } 1304 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1305 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1306 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1307 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1308 } 1309 1310 static void 1311 be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits) 1312 { 1313 int i; 1314 1315 for (i = 1 << (nbits - 1); i != 0; i >>= 1) 1316 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1317 } 1318 1319 static int 1320 be_mii_readreg(struct device *self, int phy, int reg) 1321 { 1322 struct be_softc *sc = (struct be_softc *)self; 1323 int val = 0, i; 1324 1325 /* 1326 * Read the PHY register by manually driving the MII control lines. 1327 */ 1328 be_mii_sync(sc); 1329 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1330 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1331 be_mii_sendbits(sc, phy, phy, 5); 1332 be_mii_sendbits(sc, phy, reg, 5); 1333 1334 (void) be_tcvr_read_bit(sc, phy); 1335 (void) be_tcvr_read_bit(sc, phy); 1336 1337 for (i = 15; i >= 0; i--) 1338 val |= (be_tcvr_read_bit(sc, phy) << i); 1339 1340 (void) be_tcvr_read_bit(sc, phy); 1341 (void) be_tcvr_read_bit(sc, phy); 1342 (void) be_tcvr_read_bit(sc, phy); 1343 1344 return (val); 1345 } 1346 1347 void 1348 be_mii_writereg(struct device *self, int phy, int reg, int val) 1349 { 1350 struct be_softc *sc = (struct be_softc *)self; 1351 int i; 1352 1353 /* 1354 * Write the PHY register by manually driving the MII control lines. 1355 */ 1356 be_mii_sync(sc); 1357 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1358 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1359 be_mii_sendbits(sc, phy, phy, 5); 1360 be_mii_sendbits(sc, phy, reg, 5); 1361 1362 be_tcvr_write_bit(sc, phy, 1); 1363 be_tcvr_write_bit(sc, phy, 0); 1364 1365 for (i = 15; i >= 0; i--) 1366 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1367 } 1368 1369 int 1370 be_mii_reset(struct be_softc *sc, int phy) 1371 { 1372 int n; 1373 1374 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1375 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1376 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1377 1378 for (n = 16; n >= 0; n--) { 1379 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1380 if ((bmcr & BMCR_RESET) == 0) 1381 break; 1382 DELAY(20); 1383 } 1384 if (n == 0) { 1385 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1386 return (EIO); 1387 } 1388 1389 return (0); 1390 } 1391 1392 void 1393 be_tick(void *arg) 1394 { 1395 struct be_softc *sc = arg; 1396 int s = splnet(); 1397 1398 mii_tick(&sc->sc_mii); 1399 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1400 1401 timeout_add(&sc->sc_tick_ch, hz); 1402 splx(s); 1403 } 1404 1405 void 1406 be_mii_statchg(struct device *self) 1407 { 1408 struct be_softc *sc = (struct be_softc *)self; 1409 bus_space_tag_t t = sc->sc_bustag; 1410 bus_space_handle_t br = sc->sc_br; 1411 u_int instance; 1412 u_int32_t v; 1413 1414 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1415 #ifdef DIAGNOSTIC 1416 if (instance > 1) 1417 panic("be_mii_statchg: instance %d out of range", instance); 1418 #endif 1419 1420 /* Update duplex mode in TX configuration */ 1421 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1422 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1423 v |= BE_BR_TXCFG_FULLDPLX; 1424 else 1425 v &= ~BE_BR_TXCFG_FULLDPLX; 1426 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1427 1428 /* Change to appropriate gate in transceiver PAL */ 1429 be_pal_gate(sc, sc->sc_phys[instance]); 1430 } 1431 1432 /* 1433 * Get current media settings. 1434 */ 1435 void 1436 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1437 { 1438 struct be_softc *sc = ifp->if_softc; 1439 1440 mii_pollstat(&sc->sc_mii); 1441 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1442 1443 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1444 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1445 return; 1446 } 1447 1448 /* 1449 * Set media options. 1450 */ 1451 int 1452 be_ifmedia_upd(struct ifnet *ifp) 1453 { 1454 struct be_softc *sc = ifp->if_softc; 1455 int error; 1456 1457 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1458 return (error); 1459 1460 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1461 } 1462 1463 /* 1464 * Service routine for our pseudo-MII internal transceiver. 1465 */ 1466 int 1467 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1468 { 1469 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1470 int bmcr, bmsr; 1471 int error; 1472 1473 switch (cmd) { 1474 case MII_POLLSTAT: 1475 /* 1476 * If we're not polling our PHY instance, just return. 1477 */ 1478 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1479 return (0); 1480 1481 break; 1482 1483 case MII_MEDIACHG: 1484 1485 /* 1486 * If the media indicates a different PHY instance, 1487 * isolate ourselves. 1488 */ 1489 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1490 bmcr = be_mii_readreg((void *)sc, 1491 BE_PHY_INTERNAL, MII_BMCR); 1492 be_mii_writereg((void *)sc, 1493 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1494 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1495 sc->sc_intphy_curspeed = 0; 1496 return (0); 1497 } 1498 1499 1500 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1501 return (error); 1502 1503 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1504 1505 /* 1506 * Select the new mode and take out of isolation 1507 */ 1508 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1509 bmcr |= BMCR_S100; 1510 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1511 bmcr &= ~BMCR_S100; 1512 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1513 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1514 bmcr &= ~BMCR_S100; 1515 bmcr |= sc->sc_intphy_curspeed; 1516 } else { 1517 /* Keep isolated until link is up */ 1518 bmcr |= BMCR_ISO; 1519 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1520 } 1521 } 1522 1523 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1524 bmcr |= BMCR_FDX; 1525 else 1526 bmcr &= ~BMCR_FDX; 1527 1528 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1529 break; 1530 1531 case MII_TICK: 1532 /* 1533 * If we're not currently selected, just return. 1534 */ 1535 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1536 return (0); 1537 1538 /* Only used for automatic media selection */ 1539 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1540 return (0); 1541 1542 /* Is the interface even up? */ 1543 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1544 return (0); 1545 1546 /* 1547 * Check link status; if we don't have a link, try another 1548 * speed. We can't detect duplex mode, so half-duplex is 1549 * what we have to settle for. 1550 */ 1551 1552 /* Read twice in case the register is latched */ 1553 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1554 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1555 1556 if ((bmsr & BMSR_LINK) != 0) { 1557 /* We have a carrier */ 1558 bmcr = be_mii_readreg((void *)sc, 1559 BE_PHY_INTERNAL, MII_BMCR); 1560 1561 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1562 bmcr = be_mii_readreg((void *)sc, 1563 BE_PHY_INTERNAL, MII_BMCR); 1564 1565 sc->sc_mii_flags |= MIIF_HAVELINK; 1566 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1567 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1568 1569 bmcr &= ~BMCR_ISO; 1570 be_mii_writereg((void *)sc, 1571 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1572 1573 printf("%s: link up at %s Mbps\n", 1574 sc->sc_dev.dv_xname, 1575 (bmcr & BMCR_S100) ? "100" : "10"); 1576 } 1577 return (0); 1578 } 1579 1580 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1581 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1582 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1583 sc->sc_intphy_curspeed = 0; 1584 printf("%s: link down\n", sc->sc_dev.dv_xname); 1585 } 1586 1587 /* Only retry autonegotiation every 5 seconds. */ 1588 if (++sc->sc_mii_ticks < 5) 1589 return(0); 1590 1591 sc->sc_mii_ticks = 0; 1592 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1593 /* Just flip the fast speed bit */ 1594 bmcr ^= BMCR_S100; 1595 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1596 1597 break; 1598 1599 case MII_DOWN: 1600 /* Isolate this phy */ 1601 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1602 be_mii_writereg((void *)sc, 1603 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1604 return (0); 1605 } 1606 1607 /* Update the media status. */ 1608 be_intphy_status(sc); 1609 1610 /* Callback if something changed. */ 1611 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1612 (*mii->mii_statchg)((struct device *)sc); 1613 sc->sc_mii_active = mii->mii_media_active; 1614 } 1615 return (0); 1616 } 1617 1618 /* 1619 * Determine status of internal transceiver 1620 */ 1621 void 1622 be_intphy_status(struct be_softc *sc) 1623 { 1624 struct mii_data *mii = &sc->sc_mii; 1625 int media_active, media_status; 1626 int bmcr, bmsr; 1627 1628 media_status = IFM_AVALID; 1629 media_active = 0; 1630 1631 /* 1632 * Internal transceiver; do the work here. 1633 */ 1634 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1635 1636 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1637 case (BMCR_S100 | BMCR_FDX): 1638 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1639 break; 1640 case BMCR_S100: 1641 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1642 break; 1643 case BMCR_FDX: 1644 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1645 break; 1646 case 0: 1647 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1648 break; 1649 } 1650 1651 /* Read twice in case the register is latched */ 1652 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1653 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1654 if (bmsr & BMSR_LINK) 1655 media_status |= IFM_ACTIVE; 1656 1657 mii->mii_media_status = media_status; 1658 mii->mii_media_active = media_active; 1659 } 1660