1 /* $OpenBSD: dwc2.c,v 1.68 2022/09/18 21:12:19 mglocker Exp $ */ 2 /* $NetBSD: dwc2.c,v 1.32 2014/09/02 23:26:20 macallan Exp $ */ 3 4 /*- 5 * Copyright (c) 2013 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Nick Hudson 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/kernel.h> 37 #include <sys/device.h> 38 #include <sys/proc.h> 39 #include <sys/queue.h> 40 #include <sys/endian.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/usb/usb.h> 45 #include <dev/usb/usbdi.h> 46 #include <dev/usb/usbdivar.h> 47 #include <dev/usb/usb_mem.h> 48 49 #include <dev/usb/dwc2/dwc2.h> 50 #include <dev/usb/dwc2/dwc2var.h> 51 52 #include <dev/usb/dwc2/dwc2_core.h> 53 #include <dev/usb/dwc2/dwc2_hcd.h> 54 55 #ifdef DWC2_COUNTERS 56 #define DWC2_EVCNT_ADD(a,b) ((void)((a).ev_count += (b))) 57 #else 58 #define DWC2_EVCNT_ADD(a,b) do { } while (/*CONSTCOND*/0) 59 #endif 60 #define DWC2_EVCNT_INCR(a) DWC2_EVCNT_ADD((a), 1) 61 62 #ifdef DWC2_DEBUG 63 #define DPRINTFN(n,fmt,...) do { \ 64 if (dwc2debug >= (n)) { \ 65 printf("%s: " fmt, \ 66 __FUNCTION__,## __VA_ARGS__); \ 67 } \ 68 } while (0) 69 #define DPRINTF(...) DPRINTFN(1, __VA_ARGS__) 70 int dwc2debug = 0; 71 #else 72 #define DPRINTF(...) do { } while (0) 73 #define DPRINTFN(...) do { } while (0) 74 #endif 75 76 STATIC usbd_status dwc2_open(struct usbd_pipe *); 77 STATIC int dwc2_setaddr(struct usbd_device *, int); 78 STATIC void dwc2_poll(struct usbd_bus *); 79 STATIC void dwc2_softintr(void *); 80 81 STATIC struct usbd_xfer *dwc2_allocx(struct usbd_bus *); 82 STATIC void dwc2_freex(struct usbd_bus *, struct usbd_xfer *); 83 84 STATIC usbd_status dwc2_root_ctrl_transfer(struct usbd_xfer *); 85 STATIC usbd_status dwc2_root_ctrl_start(struct usbd_xfer *); 86 STATIC void dwc2_root_ctrl_abort(struct usbd_xfer *); 87 STATIC void dwc2_root_ctrl_close(struct usbd_pipe *); 88 STATIC void dwc2_root_ctrl_done(struct usbd_xfer *); 89 90 STATIC usbd_status dwc2_root_intr_transfer(struct usbd_xfer *); 91 STATIC usbd_status dwc2_root_intr_start(struct usbd_xfer *); 92 STATIC void dwc2_root_intr_abort(struct usbd_xfer *); 93 STATIC void dwc2_root_intr_close(struct usbd_pipe *); 94 STATIC void dwc2_root_intr_done(struct usbd_xfer *); 95 96 STATIC usbd_status dwc2_device_ctrl_transfer(struct usbd_xfer *); 97 STATIC usbd_status dwc2_device_ctrl_start(struct usbd_xfer *); 98 STATIC void dwc2_device_ctrl_abort(struct usbd_xfer *); 99 STATIC void dwc2_device_ctrl_close(struct usbd_pipe *); 100 STATIC void dwc2_device_ctrl_done(struct usbd_xfer *); 101 102 STATIC usbd_status dwc2_device_bulk_transfer(struct usbd_xfer *); 103 STATIC usbd_status dwc2_device_bulk_start(struct usbd_xfer *); 104 STATIC void dwc2_device_bulk_abort(struct usbd_xfer *); 105 STATIC void dwc2_device_bulk_close(struct usbd_pipe *); 106 STATIC void dwc2_device_bulk_done(struct usbd_xfer *); 107 108 STATIC usbd_status dwc2_device_intr_transfer(struct usbd_xfer *); 109 STATIC usbd_status dwc2_device_intr_start(struct usbd_xfer *); 110 STATIC void dwc2_device_intr_abort(struct usbd_xfer *); 111 STATIC void dwc2_device_intr_close(struct usbd_pipe *); 112 STATIC void dwc2_device_intr_done(struct usbd_xfer *); 113 114 STATIC usbd_status dwc2_device_isoc_transfer(struct usbd_xfer *); 115 STATIC usbd_status dwc2_device_isoc_start(struct usbd_xfer *); 116 STATIC void dwc2_device_isoc_abort(struct usbd_xfer *); 117 STATIC void dwc2_device_isoc_close(struct usbd_pipe *); 118 STATIC void dwc2_device_isoc_done(struct usbd_xfer *); 119 120 STATIC usbd_status dwc2_device_start(struct usbd_xfer *); 121 122 STATIC void dwc2_close_pipe(struct usbd_pipe *); 123 STATIC void dwc2_abort_xfer(struct usbd_xfer *, usbd_status); 124 125 STATIC void dwc2_device_clear_toggle(struct usbd_pipe *); 126 STATIC void dwc2_noop(struct usbd_pipe *pipe); 127 128 STATIC int dwc2_interrupt(struct dwc2_softc *); 129 STATIC void dwc2_rhc(void *); 130 131 STATIC void dwc2_timeout(void *); 132 STATIC void dwc2_timeout_task(void *); 133 134 int dwc2_check_core_version(struct dwc2_hsotg *); 135 136 #define DWC2_INTR_ENDPT 1 137 138 STATIC const struct usbd_bus_methods dwc2_bus_methods = { 139 .open_pipe = dwc2_open, 140 .dev_setaddr = dwc2_setaddr, 141 .soft_intr = dwc2_softintr, 142 .do_poll = dwc2_poll, 143 .allocx = dwc2_allocx, 144 .freex = dwc2_freex, 145 }; 146 147 STATIC const struct usbd_pipe_methods dwc2_root_ctrl_methods = { 148 .transfer = dwc2_root_ctrl_transfer, 149 .start = dwc2_root_ctrl_start, 150 .abort = dwc2_root_ctrl_abort, 151 .close = dwc2_root_ctrl_close, 152 .cleartoggle = dwc2_noop, 153 .done = dwc2_root_ctrl_done, 154 }; 155 156 STATIC const struct usbd_pipe_methods dwc2_root_intr_methods = { 157 .transfer = dwc2_root_intr_transfer, 158 .start = dwc2_root_intr_start, 159 .abort = dwc2_root_intr_abort, 160 .close = dwc2_root_intr_close, 161 .cleartoggle = dwc2_noop, 162 .done = dwc2_root_intr_done, 163 }; 164 165 STATIC const struct usbd_pipe_methods dwc2_device_ctrl_methods = { 166 .transfer = dwc2_device_ctrl_transfer, 167 .start = dwc2_device_ctrl_start, 168 .abort = dwc2_device_ctrl_abort, 169 .close = dwc2_device_ctrl_close, 170 .cleartoggle = dwc2_noop, 171 .done = dwc2_device_ctrl_done, 172 }; 173 174 STATIC const struct usbd_pipe_methods dwc2_device_intr_methods = { 175 .transfer = dwc2_device_intr_transfer, 176 .start = dwc2_device_intr_start, 177 .abort = dwc2_device_intr_abort, 178 .close = dwc2_device_intr_close, 179 .cleartoggle = dwc2_device_clear_toggle, 180 .done = dwc2_device_intr_done, 181 }; 182 183 STATIC const struct usbd_pipe_methods dwc2_device_bulk_methods = { 184 .transfer = dwc2_device_bulk_transfer, 185 .start = dwc2_device_bulk_start, 186 .abort = dwc2_device_bulk_abort, 187 .close = dwc2_device_bulk_close, 188 .cleartoggle = dwc2_device_clear_toggle, 189 .done = dwc2_device_bulk_done, 190 }; 191 192 STATIC const struct usbd_pipe_methods dwc2_device_isoc_methods = { 193 .transfer = dwc2_device_isoc_transfer, 194 .start = dwc2_device_isoc_start, 195 .abort = dwc2_device_isoc_abort, 196 .close = dwc2_device_isoc_close, 197 .cleartoggle = dwc2_noop, 198 .done = dwc2_device_isoc_done, 199 }; 200 201 /* 202 * Work around the half configured control (default) pipe when setting 203 * the address of a device. 204 */ 205 STATIC int 206 dwc2_setaddr(struct usbd_device *dev, int addr) 207 { 208 if (usbd_set_address(dev, addr)) 209 return (1); 210 211 dev->address = addr; 212 213 /* 214 * Re-establish the default pipe with the new address and the 215 * new max packet size. 216 */ 217 dwc2_close_pipe(dev->default_pipe); 218 if (dwc2_open(dev->default_pipe)) 219 return (EINVAL); 220 221 return (0); 222 } 223 224 struct usbd_xfer * 225 dwc2_allocx(struct usbd_bus *bus) 226 { 227 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 228 struct dwc2_xfer *dxfer; 229 230 DPRINTFN(10, "\n"); 231 232 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolget); 233 dxfer = pool_get(&sc->sc_xferpool, PR_NOWAIT | PR_ZERO); 234 if (dxfer != NULL) { 235 #ifdef DIAGNOSTIC 236 dxfer->xfer.busy_free = XFER_ONQU; 237 #endif 238 } 239 return (struct usbd_xfer *)dxfer; 240 } 241 242 void 243 dwc2_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 244 { 245 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 246 247 DPRINTFN(10, "\n"); 248 249 #ifdef DIAGNOSTIC 250 if (xfer->busy_free != XFER_ONQU && 251 xfer->status != USBD_NOT_STARTED) { 252 DPRINTF("xfer=%p not busy, 0x%08x\n", xfer, xfer->busy_free); 253 } 254 xfer->busy_free = XFER_FREE; 255 #endif 256 DWC2_EVCNT_INCR(sc->sc_ev_xferpoolput); 257 pool_put(&sc->sc_xferpool, xfer); 258 } 259 260 STATIC void 261 dwc2_rhc(void *addr) 262 { 263 struct dwc2_softc *sc = addr; 264 struct usbd_xfer *xfer; 265 u_char *p; 266 267 DPRINTF("\n"); 268 mtx_enter(&sc->sc_lock); 269 xfer = sc->sc_intrxfer; 270 271 if (xfer == NULL) { 272 /* Just ignore the change. */ 273 mtx_leave(&sc->sc_lock); 274 return; 275 276 } 277 278 /* set port bit */ 279 p = KERNADDR(&xfer->dmabuf, 0); 280 281 p[0] = 0x02; /* we only have one port (1 << 1) */ 282 283 xfer->actlen = xfer->length; 284 xfer->status = USBD_NORMAL_COMPLETION; 285 286 usb_transfer_complete(xfer); 287 mtx_leave(&sc->sc_lock); 288 } 289 290 STATIC void 291 dwc2_softintr(void *v) 292 { 293 struct usbd_bus *bus = v; 294 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 295 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 296 struct dwc2_xfer *dxfer, *next; 297 TAILQ_HEAD(, dwc2_xfer) claimed = TAILQ_HEAD_INITIALIZER(claimed); 298 299 /* 300 * Grab all the xfers that have not been aborted or timed out. 301 * Do so under a single lock -- without dropping it to run 302 * usb_transfer_complete as we go -- so that dwc2_abortx won't 303 * remove next out from under us during iteration when we've 304 * dropped the lock. 305 */ 306 mtx_enter(&hsotg->lock); 307 TAILQ_FOREACH_SAFE(dxfer, &sc->sc_complete, xnext, next) { 308 KASSERT(dxfer->xfer.status == USBD_IN_PROGRESS); 309 KASSERT(dxfer->intr_status != USBD_CANCELLED); 310 KASSERT(dxfer->intr_status != USBD_TIMEOUT); 311 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 312 TAILQ_INSERT_TAIL(&claimed, dxfer, xnext); 313 } 314 mtx_leave(&hsotg->lock); 315 316 /* Now complete them. */ 317 while (!TAILQ_EMPTY(&claimed)) { 318 dxfer = TAILQ_FIRST(&claimed); 319 KASSERT(dxfer->xfer.status == USBD_IN_PROGRESS); 320 KASSERT(dxfer->intr_status != USBD_CANCELLED); 321 KASSERT(dxfer->intr_status != USBD_TIMEOUT); 322 TAILQ_REMOVE(&claimed, dxfer, xnext); 323 324 dxfer->xfer.status = dxfer->intr_status; 325 usb_transfer_complete(&dxfer->xfer); 326 } 327 } 328 329 STATIC void 330 dwc2_timeout(void *addr) 331 { 332 struct usbd_xfer *xfer = addr; 333 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 334 335 if (sc->sc_bus.dying) { 336 dwc2_timeout_task(addr); 337 return; 338 } 339 340 /* Execute the abort in a process context. */ 341 usb_init_task(&xfer->abort_task, dwc2_timeout_task, addr, 342 USB_TASK_TYPE_ABORT); 343 usb_add_task(xfer->device, &xfer->abort_task); 344 } 345 346 STATIC void 347 dwc2_timeout_task(void *addr) 348 { 349 struct usbd_xfer *xfer = addr; 350 int s; 351 352 s = splusb(); 353 dwc2_abort_xfer(xfer, USBD_TIMEOUT); 354 splx(s); 355 } 356 357 usbd_status 358 dwc2_open(struct usbd_pipe *pipe) 359 { 360 struct usbd_device *dev = pipe->device; 361 struct dwc2_softc *sc = DWC2_PIPE2SC(pipe); 362 struct dwc2_pipe *dpipe = DWC2_PIPE2DPIPE(pipe); 363 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 364 uint8_t addr = dev->address; 365 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 366 usbd_status err; 367 368 DPRINTF("pipe %p addr %d xfertype %d dir %s\n", pipe, addr, xfertype, 369 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? "in" : "out"); 370 371 if (sc->sc_bus.dying) { 372 return USBD_IOERROR; 373 } 374 375 if (addr == sc->sc_addr) { 376 switch (ed->bEndpointAddress) { 377 case USB_CONTROL_ENDPOINT: 378 pipe->methods = &dwc2_root_ctrl_methods; 379 break; 380 case UE_DIR_IN | DWC2_INTR_ENDPT: 381 pipe->methods = &dwc2_root_intr_methods; 382 break; 383 default: 384 DPRINTF("bad bEndpointAddress 0x%02x\n", 385 ed->bEndpointAddress); 386 return USBD_INVAL; 387 } 388 DPRINTF("root hub pipe open\n"); 389 return USBD_NORMAL_COMPLETION; 390 } 391 392 switch (xfertype) { 393 case UE_CONTROL: 394 pipe->methods = &dwc2_device_ctrl_methods; 395 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 396 0, USB_DMA_COHERENT, &dpipe->req_dma); 397 if (err) 398 return USBD_NOMEM; 399 break; 400 case UE_INTERRUPT: 401 pipe->methods = &dwc2_device_intr_methods; 402 break; 403 case UE_ISOCHRONOUS: 404 pipe->methods = &dwc2_device_isoc_methods; 405 break; 406 case UE_BULK: 407 pipe->methods = &dwc2_device_bulk_methods; 408 break; 409 default: 410 DPRINTF("bad xfer type %d\n", xfertype); 411 return USBD_INVAL; 412 } 413 414 /* QH */ 415 dpipe->priv = NULL; 416 417 return USBD_NORMAL_COMPLETION; 418 } 419 420 STATIC void 421 dwc2_poll(struct usbd_bus *bus) 422 { 423 struct dwc2_softc *sc = DWC2_BUS2SC(bus); 424 425 dwc2_interrupt(sc); 426 } 427 428 /* 429 * Close a reqular pipe. 430 * Assumes that there are no pending transactions. 431 */ 432 STATIC void 433 dwc2_close_pipe(struct usbd_pipe *pipe) 434 { 435 /* nothing */ 436 } 437 438 /* 439 * Abort a device request. 440 */ 441 STATIC void 442 dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 443 { 444 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 445 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 446 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 447 struct dwc2_xfer *d; 448 int err; 449 450 splsoftassert(IPL_SOFTUSB); 451 452 DPRINTF("xfer %p pipe %p status 0x%08x\n", xfer, xfer->pipe, 453 xfer->status); 454 455 /* XXX The stack should not call abort() in this case. */ 456 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 457 xfer->status = status; 458 timeout_del(&xfer->timeout_handle); 459 usb_rem_task(xfer->device, &xfer->abort_task); 460 usb_transfer_complete(xfer); 461 return; 462 } 463 464 KASSERT(xfer->status != USBD_CANCELLED); 465 /* Transfer is already done. */ 466 if (xfer->status != USBD_IN_PROGRESS) { 467 DPRINTF("%s: already done \n", __func__); 468 return; 469 } 470 471 /* Prevent any timeout to kick in. */ 472 timeout_del(&xfer->timeout_handle); 473 usb_rem_task(xfer->device, &xfer->abort_task); 474 475 /* Claim the transfer status as cancelled. */ 476 xfer->status = USBD_CANCELLED; 477 478 KASSERTMSG((xfer->status == USBD_CANCELLED || 479 xfer->status == USBD_TIMEOUT), 480 "bad abort status: %d", xfer->status); 481 482 mtx_enter(&hsotg->lock); 483 484 /* 485 * Check whether we aborted or timed out after the hardware 486 * completion interrupt determined that it's done but before 487 * the soft interrupt could actually complete it. If so, it's 488 * too late for the soft interrupt -- at this point we've 489 * already committed to abort it or time it out, so we need to 490 * take it off the softint's list of work in case the caller, 491 * say, frees the xfer before the softint runs. 492 * 493 * This logic is unusual among host controller drivers, and 494 * happens because dwc2 decides to complete xfers in the hard 495 * interrupt handler rather than in the soft interrupt handler, 496 * but usb_transfer_complete must be deferred to softint -- and 497 * we happened to swoop in between the hard interrupt and the 498 * soft interrupt. Other host controller drivers do almost all 499 * processing in the softint so there's no intermediate stage. 500 * 501 * Fortunately, this linear search to discern the intermediate 502 * stage is not likely to be a serious performance impact 503 * because it happens only on abort or timeout. 504 */ 505 TAILQ_FOREACH(d, &sc->sc_complete, xnext) { 506 if (d == dxfer) { 507 TAILQ_REMOVE(&sc->sc_complete, dxfer, xnext); 508 break; 509 } 510 } 511 512 /* 513 * HC Step 1: Handle the hardware. 514 */ 515 err = dwc2_hcd_urb_dequeue(hsotg, dxfer->urb); 516 if (err) { 517 DPRINTF("dwc2_hcd_urb_dequeue failed\n"); 518 } 519 520 mtx_leave(&hsotg->lock); 521 522 /* 523 * Final Step: Notify completion to waiting xfers. 524 */ 525 usb_transfer_complete(xfer); 526 } 527 528 STATIC void 529 dwc2_noop(struct usbd_pipe *pipe) 530 { 531 532 } 533 534 STATIC void 535 dwc2_device_clear_toggle(struct usbd_pipe *pipe) 536 { 537 DPRINTF("toggle %d -> 0", pipe->endpoint->savedtoggle); 538 } 539 540 /* 541 * Data structures and routines to emulate the root hub. 542 */ 543 544 STATIC const usb_device_descriptor_t dwc2_devd = { 545 .bLength = sizeof(usb_device_descriptor_t), 546 .bDescriptorType = UDESC_DEVICE, 547 .bcdUSB = {0x00, 0x02}, 548 .bDeviceClass = UDCLASS_HUB, 549 .bDeviceSubClass = UDSUBCLASS_HUB, 550 .bDeviceProtocol = UDPROTO_HSHUBSTT, 551 .bMaxPacketSize = 64, 552 .bcdDevice = {0x00, 0x01}, 553 .iManufacturer = 1, 554 .iProduct = 2, 555 .bNumConfigurations = 1, 556 }; 557 558 struct dwc2_config_desc { 559 usb_config_descriptor_t confd; 560 usb_interface_descriptor_t ifcd; 561 usb_endpoint_descriptor_t endpd; 562 } __packed; 563 564 STATIC const struct dwc2_config_desc dwc2_confd = { 565 .confd = { 566 .bLength = USB_CONFIG_DESCRIPTOR_SIZE, 567 .bDescriptorType = UDESC_CONFIG, 568 .wTotalLength[0] = sizeof(dwc2_confd), 569 .bNumInterfaces = 1, 570 .bConfigurationValue = 1, 571 .iConfiguration = 0, 572 .bmAttributes = UC_BUS_POWERED | UC_SELF_POWERED, 573 .bMaxPower = 0, 574 }, 575 .ifcd = { 576 .bLength = USB_INTERFACE_DESCRIPTOR_SIZE, 577 .bDescriptorType = UDESC_INTERFACE, 578 .bInterfaceNumber = 0, 579 .bAlternateSetting = 0, 580 .bNumEndpoints = 1, 581 .bInterfaceClass = UICLASS_HUB, 582 .bInterfaceSubClass = UISUBCLASS_HUB, 583 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 584 .iInterface = 0 585 }, 586 .endpd = { 587 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 588 .bDescriptorType = UDESC_ENDPOINT, 589 .bEndpointAddress = UE_DIR_IN | DWC2_INTR_ENDPT, 590 .bmAttributes = UE_INTERRUPT, 591 .wMaxPacketSize = {8, 0}, /* max packet */ 592 .bInterval = 255, 593 }, 594 }; 595 596 STATIC usbd_status 597 dwc2_root_ctrl_transfer(struct usbd_xfer *xfer) 598 { 599 usbd_status err; 600 601 err = usb_insert_transfer(xfer); 602 if (err) 603 return err; 604 605 return dwc2_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 606 } 607 608 STATIC usbd_status 609 dwc2_root_ctrl_start(struct usbd_xfer *xfer) 610 { 611 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 612 usb_device_request_t *req; 613 uint8_t *buf; 614 uint16_t len; 615 int value, index, l, s, totlen; 616 usbd_status err = USBD_IOERROR; 617 618 KASSERT(xfer->rqflags & URQ_REQUEST); 619 620 if (sc->sc_bus.dying) 621 return USBD_IOERROR; 622 623 req = &xfer->request; 624 625 DPRINTFN(4, "type=0x%02x request=%02x\n", 626 req->bmRequestType, req->bRequest); 627 628 len = UGETW(req->wLength); 629 value = UGETW(req->wValue); 630 index = UGETW(req->wIndex); 631 632 buf = len ? KERNADDR(&xfer->dmabuf, 0) : NULL; 633 634 totlen = 0; 635 636 #define C(x,y) ((x) | ((y) << 8)) 637 switch (C(req->bRequest, req->bmRequestType)) { 638 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 639 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 640 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 641 /* 642 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 643 * for the integrated root hub. 644 */ 645 break; 646 case C(UR_GET_CONFIG, UT_READ_DEVICE): 647 if (len > 0) { 648 *buf = sc->sc_conf; 649 totlen = 1; 650 } 651 break; 652 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 653 DPRINTFN(8, "wValue=0x%04x\n", value); 654 655 if (len == 0) 656 break; 657 switch (value) { 658 case C(0, UDESC_DEVICE): 659 l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 660 memcpy(buf, &dwc2_devd, l); 661 buf += l; 662 len -= l; 663 totlen += l; 664 665 break; 666 case C(0, UDESC_CONFIG): 667 l = min(len, sizeof(dwc2_confd)); 668 memcpy(buf, &dwc2_confd, l); 669 buf += l; 670 len -= l; 671 totlen += l; 672 673 break; 674 #define sd ((usb_string_descriptor_t *)buf) 675 case C(0, UDESC_STRING): 676 totlen = usbd_str(sd, len, "\001"); 677 break; 678 case C(1, UDESC_STRING): 679 totlen = usbd_str(sd, len, sc->sc_vendor); 680 break; 681 case C(2, UDESC_STRING): 682 totlen = usbd_str(sd, len, "DWC2 root hub"); 683 break; 684 #undef sd 685 default: 686 goto fail; 687 } 688 break; 689 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 690 if (len > 0) { 691 *buf = 0; 692 totlen = 1; 693 } 694 break; 695 case C(UR_GET_STATUS, UT_READ_DEVICE): 696 if (len > 1) { 697 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 698 totlen = 2; 699 } 700 break; 701 case C(UR_GET_STATUS, UT_READ_INTERFACE): 702 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 703 if (len > 1) { 704 USETW(((usb_status_t *)buf)->wStatus, 0); 705 totlen = 2; 706 } 707 break; 708 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 709 DPRINTF("UR_SET_ADDRESS, UT_WRITE_DEVICE: addr %d\n", 710 value); 711 if (value >= USB_MAX_DEVICES) 712 goto fail; 713 714 sc->sc_addr = value; 715 break; 716 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 717 if (value != 0 && value != 1) 718 goto fail; 719 720 sc->sc_conf = value; 721 break; 722 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 723 break; 724 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 725 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 726 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 727 err = USBD_IOERROR; 728 goto fail; 729 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 730 break; 731 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 732 break; 733 default: 734 /* Hub requests - XXXNH len check? */ 735 err = dwc2_hcd_hub_control(sc->sc_hsotg, 736 C(req->bRequest, req->bmRequestType), value, index, 737 buf, len); 738 if (err) { 739 err = USBD_IOERROR; 740 goto fail; 741 } 742 totlen = len; 743 } 744 xfer->actlen = totlen; 745 err = USBD_NORMAL_COMPLETION; 746 747 fail: 748 s = splusb(); 749 xfer->status = err; 750 usb_transfer_complete(xfer); 751 splx(s); 752 753 return err; 754 } 755 756 STATIC void 757 dwc2_root_ctrl_abort(struct usbd_xfer *xfer) 758 { 759 } 760 761 STATIC void 762 dwc2_root_ctrl_close(struct usbd_pipe *pipe) 763 { 764 } 765 766 STATIC void 767 dwc2_root_ctrl_done(struct usbd_xfer *xfer) 768 { 769 } 770 771 STATIC usbd_status 772 dwc2_root_intr_transfer(struct usbd_xfer *xfer) 773 { 774 usbd_status err; 775 776 err = usb_insert_transfer(xfer); 777 if (err) 778 return err; 779 780 return dwc2_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 781 } 782 783 STATIC usbd_status 784 dwc2_root_intr_start(struct usbd_xfer *xfer) 785 { 786 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 787 788 if (sc->sc_bus.dying) 789 return USBD_IOERROR; 790 791 sc->sc_intrxfer = xfer; 792 793 return USBD_IN_PROGRESS; 794 } 795 796 STATIC void 797 dwc2_root_intr_abort(struct usbd_xfer *xfer) 798 { 799 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 800 int s; 801 802 sc->sc_intrxfer = NULL; 803 804 xfer->status = USBD_CANCELLED; 805 s = splusb(); 806 usb_transfer_complete(xfer); 807 splx(s); 808 } 809 810 STATIC void 811 dwc2_root_intr_close(struct usbd_pipe *pipe) 812 { 813 } 814 815 STATIC void 816 dwc2_root_intr_done(struct usbd_xfer *xfer) 817 { 818 } 819 820 STATIC usbd_status 821 dwc2_device_ctrl_transfer(struct usbd_xfer *xfer) 822 { 823 usbd_status err; 824 825 err = usb_insert_transfer(xfer); 826 if (err) 827 return err; 828 829 return dwc2_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 830 } 831 832 STATIC usbd_status 833 dwc2_device_ctrl_start(struct usbd_xfer *xfer) 834 { 835 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 836 usbd_status err; 837 838 KASSERT(xfer->rqflags & URQ_REQUEST); 839 840 if (sc->sc_bus.dying) 841 return USBD_IOERROR; 842 843 err = dwc2_device_start(xfer); 844 if (err) 845 return err; 846 847 return USBD_IN_PROGRESS; 848 } 849 850 STATIC void 851 dwc2_device_ctrl_abort(struct usbd_xfer *xfer) 852 { 853 dwc2_abort_xfer(xfer, USBD_CANCELLED); 854 } 855 856 STATIC void 857 dwc2_device_ctrl_close(struct usbd_pipe *pipe) 858 { 859 struct dwc2_softc * const sc = DWC2_PIPE2SC(pipe); 860 struct dwc2_pipe * const dpipe = DWC2_PIPE2DPIPE(pipe); 861 862 dwc2_close_pipe(pipe); 863 usb_freemem(&sc->sc_bus, &dpipe->req_dma); 864 } 865 866 STATIC void 867 dwc2_device_ctrl_done(struct usbd_xfer *xfer) 868 { 869 KASSERT(xfer->rqflags & URQ_REQUEST); 870 } 871 872 STATIC usbd_status 873 dwc2_device_bulk_transfer(struct usbd_xfer *xfer) 874 { 875 usbd_status err; 876 877 err = usb_insert_transfer(xfer); 878 if (err) 879 return err; 880 881 return dwc2_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 882 } 883 884 STATIC usbd_status 885 dwc2_device_bulk_start(struct usbd_xfer *xfer) 886 { 887 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 888 usbd_status err; 889 890 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 891 892 if (sc->sc_bus.dying) 893 return (USBD_IOERROR); 894 895 err = dwc2_device_start(xfer); 896 if (err) 897 return err; 898 899 return USBD_IN_PROGRESS; 900 } 901 902 STATIC void 903 dwc2_device_bulk_abort(struct usbd_xfer *xfer) 904 { 905 dwc2_abort_xfer(xfer, USBD_CANCELLED); 906 } 907 908 STATIC void 909 dwc2_device_bulk_close(struct usbd_pipe *pipe) 910 { 911 dwc2_close_pipe(pipe); 912 } 913 914 STATIC void 915 dwc2_device_bulk_done(struct usbd_xfer *xfer) 916 { 917 } 918 919 STATIC usbd_status 920 dwc2_device_intr_transfer(struct usbd_xfer *xfer) 921 { 922 usbd_status err; 923 924 err = usb_insert_transfer(xfer); 925 if (err) 926 return err; 927 928 return dwc2_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 929 } 930 931 STATIC usbd_status 932 dwc2_device_intr_start(struct usbd_xfer *xfer) 933 { 934 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 935 usbd_status err; 936 937 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 938 939 if (sc->sc_bus.dying) 940 return (USBD_IOERROR); 941 942 err = dwc2_device_start(xfer); 943 if (err) 944 return err; 945 946 return USBD_IN_PROGRESS; 947 } 948 949 STATIC void 950 dwc2_device_intr_abort(struct usbd_xfer *xfer) 951 { 952 KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer); 953 954 dwc2_abort_xfer(xfer, USBD_CANCELLED); 955 } 956 957 STATIC void 958 dwc2_device_intr_close(struct usbd_pipe *pipe) 959 { 960 dwc2_close_pipe(pipe); 961 } 962 963 STATIC void 964 dwc2_device_intr_done(struct usbd_xfer *xfer) 965 { 966 if (xfer->pipe->repeat) 967 dwc2_device_start(xfer); 968 } 969 970 usbd_status 971 dwc2_device_isoc_transfer(struct usbd_xfer *xfer) 972 { 973 usbd_status err; 974 975 err = usb_insert_transfer(xfer); 976 if (err) 977 return err; 978 979 return dwc2_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 980 } 981 982 usbd_status 983 dwc2_device_isoc_start(struct usbd_xfer *xfer) 984 { 985 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 986 struct dwc2_softc *sc = DWC2_DPIPE2SC(dpipe); 987 usbd_status err; 988 989 /* Why would you do that anyway? */ 990 if (sc->sc_bus.use_polling) 991 return (USBD_INVAL); 992 993 err = dwc2_device_start(xfer); 994 if (err) 995 return err; 996 997 return USBD_IN_PROGRESS; 998 } 999 1000 void 1001 dwc2_device_isoc_abort(struct usbd_xfer *xfer) 1002 { 1003 dwc2_abort_xfer(xfer, USBD_CANCELLED); 1004 } 1005 1006 void 1007 dwc2_device_isoc_close(struct usbd_pipe *pipe) 1008 { 1009 dwc2_close_pipe(pipe); 1010 } 1011 1012 void 1013 dwc2_device_isoc_done(struct usbd_xfer *xfer) 1014 { 1015 } 1016 1017 usbd_status 1018 dwc2_device_start(struct usbd_xfer *xfer) 1019 { 1020 struct dwc2_xfer *dxfer = DWC2_XFER2DXFER(xfer); 1021 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 1022 struct dwc2_softc *sc = DWC2_XFER2SC(xfer); 1023 struct dwc2_hsotg *hsotg = sc->sc_hsotg; 1024 struct dwc2_hcd_urb *dwc2_urb; 1025 1026 struct usbd_device *dev = xfer->pipe->device; 1027 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 1028 uint8_t addr = dev->address; 1029 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1030 uint8_t epnum = UE_GET_ADDR(ed->bEndpointAddress); 1031 uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 1032 uint32_t mps = UGETW(ed->wMaxPacketSize); 1033 uint32_t len; 1034 1035 uint32_t flags = 0; 1036 uint32_t off = 0; 1037 int retval, err; 1038 int alloc_bandwidth = 0; 1039 1040 DPRINTFN(1, "xfer=%p pipe=%p\n", xfer, xfer->pipe); 1041 1042 if (xfertype == UE_ISOCHRONOUS || 1043 xfertype == UE_INTERRUPT) { 1044 mtx_enter(&hsotg->lock); 1045 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, xfer)) 1046 alloc_bandwidth = 1; 1047 mtx_leave(&hsotg->lock); 1048 } 1049 1050 /* 1051 * For Control pipe the direction is from the request, all other 1052 * transfers have been set correctly at pipe open time. 1053 */ 1054 if (xfertype == UE_CONTROL) { 1055 usb_device_request_t *req = &xfer->request; 1056 1057 DPRINTFN(3, "xfer=%p type=0x%02x request=0x%02x wValue=0x%04x " 1058 "wIndex=0x%04x len=%d addr=%d endpt=%d dir=%s speed=%d " 1059 "mps=%d\n", 1060 xfer, req->bmRequestType, req->bRequest, UGETW(req->wValue), 1061 UGETW(req->wIndex), UGETW(req->wLength), dev->address, 1062 epnum, dir == UT_READ ? "in" :"out", dev->speed, 1063 UE_GET_SIZE(mps)); 1064 1065 /* Copy request packet to our DMA buffer */ 1066 memcpy(KERNADDR(&dpipe->req_dma, 0), req, sizeof(*req)); 1067 usb_syncmem(&dpipe->req_dma, 0, sizeof(*req), 1068 BUS_DMASYNC_PREWRITE); 1069 len = UGETW(req->wLength); 1070 if ((req->bmRequestType & UT_READ) == UT_READ) { 1071 dir = UE_DIR_IN; 1072 } else { 1073 dir = UE_DIR_OUT; 1074 } 1075 1076 DPRINTFN(3, "req = %p dma = %llx len %d dir %s\n", 1077 KERNADDR(&dpipe->req_dma, 0), 1078 (long long)DMAADDR(&dpipe->req_dma, 0), 1079 len, dir == UE_DIR_IN ? "in" : "out"); 1080 } else if (xfertype == UE_ISOCHRONOUS) { 1081 DPRINTFN(3, "xfer=%p nframes=%d flags=%d addr=%d endpt=%d," 1082 " mps=%d dir %s\n", xfer, xfer->nframes, xfer->flags, addr, 1083 epnum, UE_GET_SIZE(mps), dir == UT_READ ? "in" :"out"); 1084 1085 #ifdef DIAGNOSTIC 1086 len = 0; 1087 for (size_t i = 0; i < xfer->nframes; i++) 1088 len += xfer->frlengths[i]; 1089 if (len != xfer->length) 1090 panic("len (%d) != xfer->length (%d)", len, 1091 xfer->length); 1092 #endif 1093 len = xfer->length; 1094 } else { 1095 DPRINTFN(3, "xfer=%p len=%d flags=%d addr=%d endpt=%d," 1096 " mps=%d dir %s\n", xfer, xfer->length, xfer->flags, addr, 1097 epnum, UE_GET_SIZE(mps), dir == UT_READ ? "in" :"out"); 1098 1099 len = xfer->length; 1100 } 1101 1102 dxfer->urb = dwc2_hcd_urb_alloc(sc->sc_hsotg, xfer->nframes, M_NOWAIT); 1103 dwc2_urb = dxfer->urb; 1104 if (!dwc2_urb) 1105 return USBD_NOMEM; 1106 1107 memset(dwc2_urb, 0, sizeof(*dwc2_urb) + 1108 sizeof(dwc2_urb->iso_descs[0]) * xfer->nframes); 1109 1110 dwc2_urb->priv = xfer; 1111 dwc2_urb->packet_count = xfer->nframes; 1112 1113 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, addr, epnum, xfertype, dir, 1114 UE_GET_SIZE(mps), UE_GET_TRANS(mps) + 1); 1115 1116 if (xfertype == UE_CONTROL) { 1117 dwc2_urb->setup_usbdma = &dpipe->req_dma; 1118 dwc2_urb->setup_packet = KERNADDR(&dpipe->req_dma, 0); 1119 dwc2_urb->setup_dma = DMAADDR(&dpipe->req_dma, 0); 1120 } else { 1121 /* XXXNH - % mps required? */ 1122 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && (len % 1123 UE_GET_SIZE(mps)) == 0) 1124 flags |= URB_SEND_ZERO_PACKET; 1125 } 1126 flags |= URB_GIVEBACK_ASAP; 1127 1128 /* 1129 * control transfers with no data phase don't touch usbdma, but 1130 * everything else does. 1131 */ 1132 if (!(xfertype == UE_CONTROL && len == 0)) { 1133 dwc2_urb->usbdma = &xfer->dmabuf; 1134 dwc2_urb->buf = KERNADDR(dwc2_urb->usbdma, 0); 1135 dwc2_urb->dma = DMAADDR(dwc2_urb->usbdma, 0); 1136 1137 usb_syncmem(&xfer->dmabuf, 0, len, 1138 dir == UE_DIR_IN ? 1139 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1140 } 1141 dwc2_urb->length = len; 1142 dwc2_urb->flags = flags; 1143 dwc2_urb->status = -EINPROGRESS; 1144 1145 if (xfertype == UE_INTERRUPT || 1146 xfertype == UE_ISOCHRONOUS) { 1147 uint16_t ival; 1148 1149 if (xfertype == UE_INTERRUPT && 1150 dpipe->pipe.interval != USBD_DEFAULT_INTERVAL) { 1151 ival = dpipe->pipe.interval; 1152 } else { 1153 ival = ed->bInterval; 1154 } 1155 1156 if (ival < 1) { 1157 retval = -ENODEV; 1158 goto fail; 1159 } 1160 if (dev->speed == USB_SPEED_HIGH || 1161 (dev->speed == USB_SPEED_FULL && xfertype == UE_ISOCHRONOUS)) { 1162 if (ival > 16) { 1163 /* 1164 * illegal with HS/FS, but there were 1165 * documentation bugs in the spec 1166 */ 1167 ival = 256; 1168 } else { 1169 ival = (1 << (ival - 1)); 1170 } 1171 } else { 1172 if (xfertype == UE_INTERRUPT && ival < 10) 1173 ival = 10; 1174 } 1175 dwc2_urb->interval = ival; 1176 } 1177 1178 xfer->actlen = 0; 1179 1180 KASSERTMSG(xfer->nframes == 0 || xfertype == UE_ISOCHRONOUS, 1181 "nframes %d xfertype %d\n", xfer->nframes, xfertype); 1182 1183 off = 0; 1184 for (size_t i = 0; i < xfer->nframes; ++i) { 1185 DPRINTFN(3, "xfer=%p frame=%zu offset=%d length=%d\n", xfer, i, 1186 off, xfer->frlengths[i]); 1187 1188 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, off, 1189 xfer->frlengths[i]); 1190 off += xfer->frlengths[i]; 1191 } 1192 1193 struct dwc2_qh *qh = dpipe->priv; 1194 struct dwc2_qtd *qtd; 1195 bool qh_allocated = false; 1196 1197 /* Create QH for the endpoint if it doesn't exist */ 1198 if (!qh) { 1199 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, M_ZERO | M_NOWAIT); 1200 if (!qh) { 1201 retval = -ENOMEM; 1202 goto fail; 1203 } 1204 dpipe->priv = qh; 1205 qh_allocated = true; 1206 } 1207 1208 qtd = pool_get(&sc->sc_qtdpool, PR_NOWAIT | PR_ZERO); 1209 if (!qtd) { 1210 retval = -ENOMEM; 1211 goto fail1; 1212 } 1213 1214 /* might need to check cpu_intr_p */ 1215 mtx_enter(&hsotg->lock); 1216 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 1217 if (retval) 1218 goto fail2; 1219 if (xfer->timeout && !sc->sc_bus.use_polling) { 1220 timeout_set(&xfer->timeout_handle, dwc2_timeout, xfer); 1221 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 1222 } 1223 xfer->status = USBD_IN_PROGRESS; 1224 1225 if (alloc_bandwidth) { 1226 dwc2_allocate_bus_bandwidth(hsotg, 1227 dwc2_hcd_get_ep_bandwidth(hsotg, dpipe), 1228 xfer); 1229 } 1230 mtx_leave(&hsotg->lock); 1231 1232 return USBD_IN_PROGRESS; 1233 1234 fail2: 1235 dwc2_urb->priv = NULL; 1236 mtx_leave(&hsotg->lock); 1237 pool_put(&sc->sc_qtdpool, qtd); 1238 1239 fail1: 1240 if (qh_allocated) { 1241 dpipe->priv = NULL; 1242 dwc2_hcd_qh_free(hsotg, qh); 1243 } 1244 fail: 1245 1246 switch (retval) { 1247 case -EINVAL: 1248 case -ENODEV: 1249 err = USBD_INVAL; 1250 break; 1251 case -ENOMEM: 1252 err = USBD_NOMEM; 1253 break; 1254 default: 1255 err = USBD_IOERROR; 1256 } 1257 1258 return err; 1259 1260 } 1261 1262 int dwc2_intr(void *p) 1263 { 1264 struct dwc2_softc *sc = p; 1265 struct dwc2_hsotg *hsotg; 1266 int ret = 0; 1267 1268 if (sc == NULL) 1269 return 0; 1270 1271 hsotg = sc->sc_hsotg; 1272 // mtx_enter(&hsotg->lock); 1273 1274 if (sc->sc_bus.dying) 1275 goto done; 1276 1277 if (sc->sc_bus.use_polling) { 1278 uint32_t intrs; 1279 1280 intrs = dwc2_read_core_intr(hsotg); 1281 dwc2_writel(hsotg, intrs, GINTSTS); 1282 } else { 1283 ret = dwc2_interrupt(sc); 1284 } 1285 1286 done: 1287 // mtx_leave(&hsotg->lock); 1288 1289 return ret; 1290 } 1291 1292 int 1293 dwc2_interrupt(struct dwc2_softc *sc) 1294 { 1295 int ret = 0; 1296 1297 if (sc->sc_hcdenabled) 1298 ret |= dwc2_handle_hcd_intr(sc->sc_hsotg); 1299 1300 ret |= dwc2_handle_common_intr(sc->sc_hsotg); 1301 1302 return ret; 1303 } 1304 1305 int 1306 dwc2_detach(struct dwc2_softc *sc, int flags) 1307 { 1308 int rv = 0; 1309 1310 if (sc->sc_child != NULL) 1311 rv = config_detach(sc->sc_child, flags); 1312 1313 return rv; 1314 } 1315 1316 int 1317 dwc2_init(struct dwc2_softc *sc) 1318 { 1319 int retval, err = 0; 1320 struct dwc2_hsotg *hsotg; 1321 1322 sc->sc_bus.usbrev = USBREV_2_0; 1323 sc->sc_bus.methods = &dwc2_bus_methods; 1324 sc->sc_bus.pipe_size = sizeof(struct dwc2_pipe); 1325 sc->sc_hcdenabled = false; 1326 1327 mtx_init(&sc->sc_lock, IPL_SOFTUSB); 1328 1329 TAILQ_INIT(&sc->sc_complete); 1330 1331 sc->sc_rhc_si = softintr_establish(IPL_SOFTUSB, dwc2_rhc, sc); 1332 1333 pool_init(&sc->sc_xferpool, sizeof(struct dwc2_xfer), 0, IPL_VM, 0, 1334 "dwc2xfer", NULL); 1335 pool_init(&sc->sc_qhpool, sizeof(struct dwc2_qh), 0, IPL_VM, 0, 1336 "dwc2qh", NULL); 1337 pool_init(&sc->sc_qtdpool, sizeof(struct dwc2_qtd), 0, IPL_VM, 0, 1338 "dwc2qtd", NULL); 1339 1340 sc->sc_hsotg = malloc(sizeof(struct dwc2_hsotg), M_USBHC, 1341 M_ZERO | M_WAITOK); 1342 sc->sc_hsotg->hsotg_sc = sc; 1343 sc->sc_hsotg->dev = &sc->sc_bus.bdev; 1344 sc->sc_hcdenabled = true; 1345 hsotg = sc->sc_hsotg; 1346 1347 hsotg->dr_mode = USB_DR_MODE_HOST; 1348 1349 /* 1350 * Before performing any core related operations 1351 * check core version. 1352 */ 1353 retval = dwc2_check_core_version(hsotg); 1354 if (retval) 1355 goto fail2; 1356 1357 /* 1358 * Reset before dwc2_get_hwparams() then it could get power-on real 1359 * reset value form registers. 1360 */ 1361 retval = dwc2_core_reset(hsotg, false); 1362 if (retval) 1363 goto fail2; 1364 1365 /* Detect config values from hardware */ 1366 retval = dwc2_get_hwparams(hsotg); 1367 if (retval) 1368 goto fail2; 1369 1370 /* 1371 * For OTG cores, set the force mode bits to reflect the value 1372 * of dr_mode. Force mode bits should not be touched at any 1373 * other time after this. 1374 */ 1375 dwc2_force_dr_mode(hsotg); 1376 1377 retval = dwc2_init_params(hsotg); 1378 if (retval) 1379 goto fail2; 1380 #if 0 1381 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 1382 retval = dwc2_gadget_init(hsotg); 1383 if (retval) 1384 goto fail2; 1385 hsotg->gadget_enabled = 1; 1386 } 1387 #endif 1388 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 1389 retval = dwc2_hcd_init(hsotg); 1390 if (retval) { 1391 if (hsotg->gadget_enabled) 1392 dwc2_hsotg_remove(hsotg); 1393 goto fail2; 1394 } 1395 hsotg->hcd_enabled = 1; 1396 } 1397 1398 hsotg->hibernated = 0; 1399 1400 return 0; 1401 1402 fail2: 1403 err = -retval; 1404 free(sc->sc_hsotg, M_USBHC, sizeof(struct dwc2_hsotg)); 1405 softintr_disestablish(sc->sc_rhc_si); 1406 1407 return err; 1408 } 1409 1410 void 1411 dw_timeout(void *arg) 1412 { 1413 struct delayed_work *dw = arg; 1414 1415 task_set(&dw->work, dw->dw_fn, dw->dw_arg); 1416 task_add(dw->dw_wq, &dw->work); 1417 } 1418 1419 /*** platform.c ***************************************************************/ 1420 1421 int dwc2_check_core_version(struct dwc2_hsotg *hsotg) 1422 { 1423 struct dwc2_hw_params *hw = &hsotg->hw_params; 1424 1425 /* 1426 * Attempt to ensure this device is really a DWC_otg Controller. 1427 * Read and verify the GSNPSID register contents. The value should be 1428 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx 1429 */ 1430 1431 hw->snpsid = dwc2_readl(hsotg, GSNPSID); 1432 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID && 1433 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID && 1434 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) { 1435 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 1436 hw->snpsid); 1437 return -ENODEV; 1438 } 1439 1440 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 1441 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 1442 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 1443 return 0; 1444 } 1445