1 /* $OpenBSD: dwc2_hcd.h,v 1.15 2021/07/27 13:36:59 mglocker Exp $ */ 2 /* $NetBSD: dwc2_hcd.h,v 1.9 2014/09/03 10:00:08 skrll Exp $ */ 3 4 /* 5 * hcd.h - DesignWare HS OTG Controller host-mode declarations 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 #ifndef __DWC2_HCD_H__ 40 #define __DWC2_HCD_H__ 41 42 /* 43 * This file contains the structures, constants, and interfaces for the 44 * Host Contoller Driver (HCD) 45 * 46 * The Host Controller Driver (HCD) is responsible for translating requests 47 * from the USB Driver into the appropriate actions on the DWC_otg controller. 48 * It isolates the USBD from the specifics of the controller by providing an 49 * API to the USBD. 50 */ 51 52 struct dwc2_qh; 53 54 /** 55 * struct dwc2_host_chan - Software host channel descriptor 56 * 57 * @hc_num: Host channel number, used for register address lookup 58 * @dev_addr: Address of the device 59 * @ep_num: Endpoint of the device 60 * @ep_is_in: Endpoint direction 61 * @speed: Device speed. One of the following values: 62 * - USB_SPEED_LOW 63 * - USB_SPEED_FULL 64 * - USB_SPEED_HIGH 65 * @ep_type: Endpoint type. One of the following values: 66 * - USB_ENDPOINT_XFER_CONTROL: 0 67 * - USB_ENDPOINT_XFER_ISOC: 1 68 * - USB_ENDPOINT_XFER_BULK: 2 69 * - USB_ENDPOINT_XFER_INTR: 3 70 * @max_packet: Max packet size in bytes 71 * @data_pid_start: PID for initial transaction. 72 * 0: DATA0 73 * 1: DATA2 74 * 2: DATA1 75 * 3: MDATA (non-Control EP), 76 * SETUP (Control EP) 77 * @multi_count: Number of additional periodic transactions per 78 * (micro)frame 79 * @xfer_buf: Pointer to current transfer buffer position 80 * @xfer_dma: DMA address of xfer_buf 81 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not 82 * DWORD aligned 83 * @xfer_len: Total number of bytes to transfer 84 * @xfer_count: Number of bytes transferred so far 85 * @start_pkt_count: Packet count at start of transfer 86 * @xfer_started: True if the transfer has been started 87 * @ping: True if a PING request should be issued on this channel 88 * @error_state: True if the error count for this transaction is non-zero 89 * @halt_on_queue: True if this channel should be halted the next time a 90 * request is queued for the channel. This is necessary in 91 * slave mode if no request queue space is available when 92 * an attempt is made to halt the channel. 93 * @halt_pending: True if the host channel has been halted, but the core 94 * is not finished flushing queued requests 95 * @do_split: Enable split for the channel 96 * @complete_split: Enable complete split 97 * @hub_addr: Address of high speed hub for the split 98 * @hub_port: Port of the low/full speed device for the split 99 * @xact_pos: Split transaction position. One of the following values: 100 * - DWC2_HCSPLT_XACTPOS_MID 101 * - DWC2_HCSPLT_XACTPOS_BEGIN 102 * - DWC2_HCSPLT_XACTPOS_END 103 * - DWC2_HCSPLT_XACTPOS_ALL 104 * @requests: Number of requests issued for this channel since it was 105 * assigned to the current transfer (not counting PINGs) 106 * @schinfo: Scheduling micro-frame bitmap 107 * @ntd: Number of transfer descriptors for the transfer 108 * @halt_status: Reason for halting the host channel 109 * @hcint Contents of the HCINT register when the interrupt came 110 * @qh: QH for the transfer being processed by this channel 111 * @hc_list_entry: For linking to list of host channels 112 * @desc_list_addr: Current QH's descriptor list DMA address 113 * @desc_list_sz: Current QH's descriptor list size 114 * @split_order_list_entry: List entry for keeping track of the order of splits 115 * 116 * This structure represents the state of a single host channel when acting in 117 * host mode. It contains the data items needed to transfer packets to an 118 * endpoint via a host channel. 119 */ 120 struct dwc2_host_chan { 121 u8 hc_num; 122 123 unsigned dev_addr:7; 124 unsigned ep_num:4; 125 unsigned ep_is_in:1; 126 unsigned speed:4; 127 unsigned ep_type:2; 128 unsigned max_packet:11; 129 unsigned data_pid_start:2; 130 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 131 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 132 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 133 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 134 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 135 136 unsigned multi_count:2; 137 138 struct usb_dma *xfer_usbdma; 139 u8 *xfer_buf; 140 dma_addr_t xfer_dma; 141 dma_addr_t align_buf; 142 u32 xfer_len; 143 u32 xfer_count; 144 u16 start_pkt_count; 145 u8 xfer_started; 146 u8 do_ping; 147 u8 error_state; 148 u8 halt_on_queue; 149 u8 halt_pending; 150 u8 do_split; 151 u8 complete_split; 152 u8 hub_addr; 153 u8 hub_port; 154 u8 xact_pos; 155 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 156 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 157 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 158 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 159 160 u8 requests; 161 u8 schinfo; 162 u16 ntd; 163 enum dwc2_halt_status halt_status; 164 u32 hcint; 165 struct dwc2_qh *qh; 166 struct list_head hc_list_entry; 167 struct usb_dma desc_list_usbdma; 168 dma_addr_t desc_list_addr; 169 u32 desc_list_sz; 170 struct list_head split_order_list_entry; 171 }; 172 173 struct dwc2_hcd_pipe_info { 174 u8 dev_addr; 175 u8 ep_num; 176 u8 pipe_type; 177 u8 pipe_dir; 178 u16 mps; 179 }; 180 181 struct dwc2_hcd_iso_packet_desc { 182 u32 offset; 183 u32 length; 184 u32 actual_length; 185 u32 status; 186 }; 187 188 struct dwc2_qtd; 189 190 struct dwc2_hcd_urb { 191 void *priv; /* the xfer handle */ 192 struct dwc2_qtd *qtd; 193 struct usb_dma *usbdma; 194 u8 *buf; 195 dma_addr_t dma; 196 struct usb_dma *setup_usbdma; 197 void *setup_packet; 198 dma_addr_t setup_dma; 199 u32 length; 200 u32 actual_length; 201 u32 status; 202 u32 error_count; 203 u32 packet_count; 204 u32 flags; 205 u16 interval; 206 struct dwc2_hcd_pipe_info pipe_info; 207 struct dwc2_hcd_iso_packet_desc iso_descs[0]; 208 }; 209 210 /* Phases for control transfers */ 211 enum dwc2_control_phase { 212 DWC2_CONTROL_SETUP, 213 DWC2_CONTROL_DATA, 214 DWC2_CONTROL_STATUS, 215 }; 216 217 /* Transaction types */ 218 enum dwc2_transaction_type { 219 DWC2_TRANSACTION_NONE, 220 DWC2_TRANSACTION_PERIODIC, 221 DWC2_TRANSACTION_NON_PERIODIC, 222 DWC2_TRANSACTION_ALL, 223 }; 224 225 /** 226 * struct dwc2_qh - Software queue head structure 227 * 228 * @hsotg: The HCD state structure for the DWC OTG controller 229 * @ep_type: Endpoint type. One of the following values: 230 * - USB_ENDPOINT_XFER_CONTROL 231 * - USB_ENDPOINT_XFER_BULK 232 * - USB_ENDPOINT_XFER_INT 233 * - USB_ENDPOINT_XFER_ISOC 234 * @ep_is_in: Endpoint direction 235 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 236 * @dev_speed: Device speed. One of the following values: 237 * - USB_SPEED_LOW 238 * - USB_SPEED_FULL 239 * - USB_SPEED_HIGH 240 * @data_toggle: Determines the PID of the next data packet for 241 * non-controltransfers. Ignored for control transfers. 242 * One of the following values: 243 * - DWC2_HC_PID_DATA0 244 * - DWC2_HC_PID_DATA1 245 * @ping_state: Ping state 246 * @do_split: Full/low speed endpoint on high-speed hub requires split 247 * @td_first: Index of first activated isochronous transfer descriptor 248 * @td_last: Index of last activated isochronous transfer descriptor 249 * @usecs: Bandwidth in microseconds per (micro)frame 250 * @interval: Interval between transfers in (micro)frames 251 * @sched_frame: (Micro)frame to initialize a periodic transfer. 252 * The transfer executes in the following (micro)frame. 253 * @nak_frame: Internal variable used by the NAK holdoff code 254 * @frame_usecs: Internal variable used by the microframe scheduler 255 * @start_split_frame: (Micro)frame at which last start split was initialized 256 * @ntd: Actual number of transfer descriptors in a list 257 * @dw_align_buf: Used instead of original buffer if its physical address 258 * is not dword-aligned 259 * @dw_align_buf_size: Size of dw_align_buf 260 * @dw_align_buf_dma: DMA address for dw_align_buf 261 * @qtd_list: List of QTDs for this QH 262 * @channel: Host channel currently processing transfers for this QH 263 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 264 * schedule 265 * @desc_list: List of transfer descriptors 266 * @desc_list_dma: Physical address of desc_list 267 * @desc_list_sz: Size of descriptors list 268 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 269 * descriptor and indicates original XferSize value for the 270 * descriptor 271 * @wait_timer: Timer used to wait before re-queuing. 272 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 273 * @want_wait: We should wait before re-queuing; only matters for non- 274 * periodic transfers and is ignored for periodic ones. 275 * @wait_timer_cancel: Set to true to cancel the wait_timer. 276 * 277 * A Queue Head (QH) holds the static characteristics of an endpoint and 278 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 279 * be entered in either the non-periodic or periodic schedule. 280 */ 281 struct dwc2_qh { 282 struct dwc2_hsotg *hsotg; 283 u8 ep_type; 284 u8 ep_is_in; 285 u16 maxp; 286 u8 dev_speed; 287 u8 data_toggle; 288 u8 ping_state; 289 u8 do_split; 290 u8 td_first; 291 u8 td_last; 292 u16 usecs; 293 u16 interval; 294 u16 sched_frame; 295 u16 nak_frame; 296 u16 frame_usecs[8]; 297 u16 start_split_frame; 298 u16 ntd; 299 struct usb_dma dw_align_buf_usbdma; 300 u8 *dw_align_buf; 301 int dw_align_buf_size; 302 dma_addr_t dw_align_buf_dma; 303 struct list_head qtd_list; 304 struct dwc2_host_chan *channel; 305 struct list_head qh_list_entry; 306 struct usb_dma desc_list_usbdma; 307 struct dwc2_hcd_dma_desc *desc_list; 308 dma_addr_t desc_list_dma; 309 u32 desc_list_sz; 310 u32 *n_bytes; 311 /* XXX struct timer_list wait_timer; */ 312 struct timeout wait_timer; 313 unsigned tt_buffer_dirty:1; 314 unsigned want_wait:1; 315 unsigned wait_timer_cancel:1; 316 }; 317 318 /** 319 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 320 * 321 * @control_phase: Current phase for control transfers (Setup, Data, or 322 * Status) 323 * @in_process: Indicates if this QTD is currently processed by HW 324 * @data_toggle: Determines the PID of the next data packet for the 325 * data phase of control transfers. Ignored for other 326 * transfer types. One of the following values: 327 * - DWC2_HC_PID_DATA0 328 * - DWC2_HC_PID_DATA1 329 * @complete_split: Keeps track of the current split type for FS/LS 330 * endpoints on a HS Hub 331 * @isoc_split_pos: Position of the ISOC split in full/low speed 332 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 333 * transfer. A frame descriptor describes the buffer 334 * position and length of the data to be transferred in the 335 * next scheduled (micro)frame of an isochronous transfer. 336 * It also holds status for that transaction. The frame 337 * index starts at 0. 338 * @isoc_split_offset: Position of the ISOC split in the buffer for the 339 * current frame 340 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 341 * @error_count: Holds the number of bus errors that have occurred for 342 * a transaction within this transfer 343 * @n_desc: Number of DMA descriptors for this QTD 344 * @isoc_frame_index_last: Last activated frame (packet) index, used in 345 * descriptor DMA mode only 346 * @num_naks: Number of NAKs received on this QTD. 347 * @urb: URB for this transfer 348 * @qh: Queue head for this QTD 349 * @qtd_list_entry: For linking to the QH's list of QTDs 350 * 351 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 352 * interrupt, or isochronous transfer. A single QTD is created for each URB 353 * (of one of these types) submitted to the HCD. The transfer associated with 354 * a QTD may require one or multiple transactions. 355 * 356 * A QTD is linked to a Queue Head, which is entered in either the 357 * non-periodic or periodic schedule for execution. When a QTD is chosen for 358 * execution, some or all of its transactions may be executed. After 359 * execution, the state of the QTD is updated. The QTD may be retired if all 360 * its transactions are complete or if an error occurred. Otherwise, it 361 * remains in the schedule so more transactions can be executed later. 362 */ 363 struct dwc2_qtd { 364 enum dwc2_control_phase control_phase; 365 u8 in_process; 366 u8 data_toggle; 367 u8 complete_split; 368 u8 isoc_split_pos; 369 u16 isoc_frame_index; 370 u16 isoc_split_offset; 371 u16 isoc_td_last; 372 u16 isoc_td_first; 373 u32 ssplit_out_xfer_count; 374 u8 error_count; 375 u8 n_desc; 376 u16 isoc_frame_index_last; 377 u16 num_naks; 378 struct dwc2_hcd_urb *urb; 379 struct dwc2_qh *qh; 380 struct list_head qtd_list_entry; 381 }; 382 383 #ifdef DEBUG 384 struct hc_xfer_info { 385 struct dwc2_hsotg *hsotg; 386 struct dwc2_host_chan *chan; 387 }; 388 #endif 389 390 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 391 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 392 { 393 return (struct usb_hcd *)hsotg->priv; 394 } 395 396 /* 397 * Inline used to disable one channel interrupt. Channel interrupts are 398 * disabled when the channel is halted or released by the interrupt handler. 399 * There is no need to handle further interrupts of that type until the 400 * channel is re-assigned. In fact, subsequent handling may cause crashes 401 * because the channel structures are cleaned up when the channel is released. 402 */ 403 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 404 { 405 u32 mask = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 406 407 mask &= ~intr; 408 DWC2_WRITE_4(hsotg, HCINTMSK(chnum), mask); 409 } 410 411 /* 412 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 413 * are read as 1, they won't clear when written back. 414 */ 415 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 416 { 417 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 418 419 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 420 return hprt0; 421 } 422 423 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 424 { 425 return pipe->ep_num; 426 } 427 428 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 429 { 430 return pipe->pipe_type; 431 } 432 433 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 434 { 435 return pipe->mps; 436 } 437 438 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 439 { 440 return pipe->dev_addr; 441 } 442 443 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 444 { 445 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 446 } 447 448 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 449 { 450 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 451 } 452 453 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 454 { 455 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 456 } 457 458 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 459 { 460 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 461 } 462 463 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 464 { 465 return pipe->pipe_dir == USB_DIR_IN; 466 } 467 468 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 469 { 470 return !dwc2_hcd_is_pipe_in(pipe); 471 } 472 473 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg); 474 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 475 476 /* Transaction Execution Functions */ 477 extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 478 struct dwc2_hsotg *hsotg); 479 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 480 enum dwc2_transaction_type tr_type); 481 482 /* Schedule Queue Functions */ 483 /* Implemented in hcd_queue.c */ 484 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg); 485 extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 486 struct dwc2_hcd_urb *urb, 487 gfp_t mem_flags); 488 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 489 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 490 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 491 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 492 int sched_csplit); 493 494 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 495 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 496 struct dwc2_qh *qh); 497 498 /* Removes and frees a QTD */ 499 extern void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 500 struct dwc2_qtd *qtd, 501 struct dwc2_qh *qh); 502 503 /* Descriptor DMA support functions */ 504 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 505 struct dwc2_qh *qh); 506 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 507 struct dwc2_host_chan *chan, int chnum, 508 enum dwc2_halt_status halt_status); 509 510 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 511 gfp_t mem_flags); 512 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 513 514 /* Check if QH is non-periodic */ 515 #define dwc2_qh_is_non_per(_qh_ptr_) \ 516 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 517 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 518 519 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 520 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 521 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 522 static inline bool dbg_perio(void) { return true; } 523 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 524 static inline bool dbg_hc(struct dwc2_host_chan *hc) 525 { 526 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 527 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 528 } 529 530 static inline bool dbg_qh(struct dwc2_qh *qh) 531 { 532 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 533 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 534 } 535 536 537 static inline bool dbg_perio(void) { return false; } 538 #endif 539 540 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 541 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 542 543 /* Packet size for any kind of endpoint descriptor */ 544 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 545 546 /* 547 * Returns true if frame1 index is greater than frame2 index. The comparison 548 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the 549 * frame number when the max index frame number is reached. 550 */ 551 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2) 552 { 553 u16 diff = fr_idx1 - fr_idx2; 554 u16 sign = diff & (FRLISTEN_64_SIZE >> 1); 555 556 return diff && !sign; 557 } 558 559 /* 560 * Returns true if frame1 is less than or equal to frame2. The comparison is 561 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 562 * frame number when the max frame number is reached. 563 */ 564 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 565 { 566 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 567 } 568 569 /* 570 * Returns true if frame1 is greater than frame2. The comparison is done 571 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 572 * number when the max frame number is reached. 573 */ 574 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 575 { 576 return (frame1 != frame2) && 577 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 578 } 579 580 /* 581 * Increments frame by the amount specified by inc. The addition is done 582 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 583 */ 584 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 585 { 586 return (frame + inc) & HFNUM_MAX_FRNUM; 587 } 588 589 static inline u16 dwc2_full_frame_num(u16 frame) 590 { 591 return (frame & HFNUM_MAX_FRNUM) >> 3; 592 } 593 594 static inline u16 dwc2_micro_frame_num(u16 frame) 595 { 596 return frame & 0x7; 597 } 598 599 /* 600 * Returns the Core Interrupt Status register contents, ANDed with the Core 601 * Interrupt Mask register contents 602 */ 603 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 604 { 605 return DWC2_READ_4(hsotg, GINTSTS) & DWC2_READ_4(hsotg, GINTMSK); 606 } 607 608 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 609 { 610 return dwc2_urb->status; 611 } 612 613 static inline u32 dwc2_hcd_urb_get_actual_length( 614 struct dwc2_hcd_urb *dwc2_urb) 615 { 616 return dwc2_urb->actual_length; 617 } 618 619 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 620 { 621 return dwc2_urb->error_count; 622 } 623 624 static inline void dwc2_hcd_urb_set_iso_desc_params( 625 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 626 u32 length) 627 { 628 dwc2_urb->iso_descs[desc_num].offset = offset; 629 dwc2_urb->iso_descs[desc_num].length = length; 630 } 631 632 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 633 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 634 { 635 return dwc2_urb->iso_descs[desc_num].status; 636 } 637 638 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 639 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 640 { 641 return dwc2_urb->iso_descs[desc_num].actual_length; 642 } 643 644 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 645 struct usbd_xfer *xfer) 646 { 647 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer); 648 struct dwc2_qh *qh = dpipe->priv; 649 650 if (qh && !list_empty(&qh->qh_list_entry)) 651 return 1; 652 653 return 0; 654 } 655 656 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 657 struct dwc2_pipe *dpipe) 658 { 659 struct dwc2_qh *qh = dpipe->priv; 660 661 if (!qh) { 662 WARN_ON(1); 663 return 0; 664 } 665 666 return qh->usecs; 667 } 668 669 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 670 struct dwc2_host_chan *chan, int chnum, 671 struct dwc2_qtd *qtd); 672 673 /* HCD Core API */ 674 675 /** 676 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 677 * 678 * @hsotg: The DWC2 HCD 679 * 680 * Returns IRQ_HANDLED if interrupt is handled 681 * Return IRQ_NONE if interrupt is not handled 682 */ 683 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 684 685 /** 686 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 687 * 688 * @hsotg: The DWC2 HCD 689 */ 690 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 691 692 /** 693 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 694 * and 0 otherwise 695 * 696 * @hsotg: The DWC2 HCD 697 */ 698 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 699 700 /** 701 * dwc2_hcd_dump_state() - Dumps hsotg state 702 * 703 * @hsotg: The DWC2 HCD 704 * 705 * NOTE: This function will be removed once the peripheral controller code 706 * is integrated and the driver is stable 707 */ 708 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 709 710 /** 711 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF 712 * 713 * @hsotg: The DWC2 HCD 714 * 715 * This can be used to determine average interrupt latency. Frame remaining is 716 * also shown for start transfer and two additional sample points. 717 * 718 * NOTE: This function will be removed once the peripheral controller code 719 * is integrated and the driver is stable 720 */ 721 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); 722 723 /* URB interface */ 724 725 /* Transfer flags */ 726 #define URB_GIVEBACK_ASAP 0x1 727 #define URB_SEND_ZERO_PACKET 0x2 728 729 /* Host driver callbacks */ 730 731 extern void dwc2_host_start(struct dwc2_hsotg *hsotg); 732 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg); 733 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 734 int *hub_addr, int *hub_port); 735 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 736 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 737 int status); 738 739 #ifdef DEBUG 740 /* 741 * Macro to sample the remaining PHY clocks left in the current frame. This 742 * may be used during debugging to determine the average time it takes to 743 * execute sections of code. There are two possible sample points, "a" and 744 * "b", so the _letter_ argument must be one of these values. 745 * 746 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For 747 * example, "cat /sys/devices/lm0/hcd_frrem". 748 */ 749 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ 750 do { \ 751 struct hfnum_data _hfnum_; \ 752 struct dwc2_qtd *_qtd_; \ 753 \ 754 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ 755 qtd_list_entry); \ 756 if (usb_pipeint(_qtd_->urb->pipe) && \ 757 (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ 758 _hfnum_.d32 = DWC2_READ_4((_hcd_), HFNUM); \ 759 switch (_hfnum_.b.frnum & 0x7) { \ 760 case 7: \ 761 (_hcd_)->hfnum_7_samples_##_letter_++; \ 762 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ 763 _hfnum_.b.frrem; \ 764 break; \ 765 case 0: \ 766 (_hcd_)->hfnum_0_samples_##_letter_++; \ 767 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ 768 _hfnum_.b.frrem; \ 769 break; \ 770 default: \ 771 (_hcd_)->hfnum_other_samples_##_letter_++; \ 772 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ 773 _hfnum_.b.frrem; \ 774 break; \ 775 } \ 776 } \ 777 } while (0) 778 #else 779 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) 780 #endif 781 782 783 void dwc2_wakeup_detected(void *); 784 785 int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *, struct dwc2_hcd_urb *); 786 void dwc2_hcd_reinit(struct dwc2_hsotg *); 787 int dwc2_hcd_hub_control(struct dwc2_hsotg *, u16, u16, u16, char *, u16); 788 struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *); 789 int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 790 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 791 struct dwc2_qtd *qtd); 792 void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *, struct dwc2_hcd_urb *, 793 u8 ,u8, u8, u8, u16); 794 795 struct dwc2_hcd_urb * dwc2_hcd_urb_alloc(struct dwc2_hsotg *, int, gfp_t); 796 void dwc2_hcd_urb_free(struct dwc2_hsotg *, struct dwc2_hcd_urb *, int); 797 798 int _dwc2_hcd_start(struct dwc2_hsotg *); 799 800 int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *); 801 802 #endif /* __DWC2_HCD_H__ */ 803