1*7ebc5b51Smpi /* $OpenBSD: if_axereg.h,v 1.26 2015/06/12 15:47:31 mpi Exp $ */ 248f0b646Sjsg 3f63446eaSderaadt /* 4f63446eaSderaadt * Copyright (c) 1997, 1998, 1999, 2000-2003 5f63446eaSderaadt * Bill Paul <wpaul@windriver.com>. All rights reserved. 6f63446eaSderaadt * 7f63446eaSderaadt * Redistribution and use in source and binary forms, with or without 8f63446eaSderaadt * modification, are permitted provided that the following conditions 9f63446eaSderaadt * are met: 10f63446eaSderaadt * 1. Redistributions of source code must retain the above copyright 11f63446eaSderaadt * notice, this list of conditions and the following disclaimer. 12f63446eaSderaadt * 2. Redistributions in binary form must reproduce the above copyright 13f63446eaSderaadt * notice, this list of conditions and the following disclaimer in the 14f63446eaSderaadt * documentation and/or other materials provided with the distribution. 15f63446eaSderaadt * 3. All advertising materials mentioning features or use of this software 16f63446eaSderaadt * must display the following acknowledgement: 17f63446eaSderaadt * This product includes software developed by Bill Paul. 18f63446eaSderaadt * 4. Neither the name of the author nor the names of any co-contributors 19f63446eaSderaadt * may be used to endorse or promote products derived from this software 20f63446eaSderaadt * without specific prior written permission. 21f63446eaSderaadt * 22f63446eaSderaadt * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23f63446eaSderaadt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24f63446eaSderaadt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25f63446eaSderaadt * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26f63446eaSderaadt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27f63446eaSderaadt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28f63446eaSderaadt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29f63446eaSderaadt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30f63446eaSderaadt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31f63446eaSderaadt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32f63446eaSderaadt * THE POSSIBILITY OF SUCH DAMAGE. 33f63446eaSderaadt * 34f63446eaSderaadt * $FreeBSD: src/sys/dev/usb/if_axereg.h,v 1.2 2003/06/15 21:45:43 wpaul Exp $ 35f63446eaSderaadt */ 36f63446eaSderaadt 37f63446eaSderaadt /* 38f63446eaSderaadt * Definitions for the ASIX Electronics AX88172 to ethernet controller. 39f63446eaSderaadt */ 40f63446eaSderaadt 41f63446eaSderaadt 42f63446eaSderaadt /* 43f63446eaSderaadt * Vendor specific commands 44f63446eaSderaadt * ASIX conveniently doesn't document the 'set NODEID' command in their 45f63446eaSderaadt * datasheet (thanks a lot guys). 46f63446eaSderaadt * To make handling these commands easier, I added some extra data 47f63446eaSderaadt * which is decided by the axe_cmd() routine. Commands are encoded 48f63446eaSderaadt * in 16 bites, with the format: LDCC. L and D are both nibbles in 49f63446eaSderaadt * the high byte. L represents the data length (0 to 15) and D 50f63446eaSderaadt * represents the direction (0 for vendor read, 1 for vendor write). 51f63446eaSderaadt * CC is the command byte, as specified in the manual. 52f63446eaSderaadt */ 53f63446eaSderaadt 54f63446eaSderaadt #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) 555054db1dSpascoe #define AXE_CMD_DIR(x) (((x) & 0x0F00) >> 8) 56f63446eaSderaadt #define AXE_CMD_CMD(x) ((x) & 0x00FF) 57f63446eaSderaadt 5858ed394fSjsg #define AXE_172_CMD_READ_RXTX_SRAM 0x2002 5958ed394fSjsg #define AXE_182_CMD_READ_RXTX_SRAM 0x8002 6058ed394fSjsg #define AXE_172_CMD_WRITE_RX_SRAM 0x0103 6158ed394fSjsg #define AXE_172_CMD_WRITE_TX_SRAM 0x0104 6258ed394fSjsg #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 63f63446eaSderaadt #define AXE_CMD_MII_OPMODE_SW 0x0106 64f63446eaSderaadt #define AXE_CMD_MII_READ_REG 0x2007 65f63446eaSderaadt #define AXE_CMD_MII_WRITE_REG 0x2108 66f63446eaSderaadt #define AXE_CMD_MII_READ_OPMODE 0x1009 67f63446eaSderaadt #define AXE_CMD_MII_OPMODE_HW 0x010A 68f63446eaSderaadt #define AXE_CMD_SROM_READ 0x200B 69f63446eaSderaadt #define AXE_CMD_SROM_WRITE 0x010C 70f63446eaSderaadt #define AXE_CMD_SROM_WR_ENABLE 0x010D 71f63446eaSderaadt #define AXE_CMD_SROM_WR_DISABLE 0x010E 72f63446eaSderaadt #define AXE_CMD_RXCTL_READ 0x200F 73f63446eaSderaadt #define AXE_CMD_RXCTL_WRITE 0x0110 74f63446eaSderaadt #define AXE_CMD_READ_IPG012 0x3011 7558ed394fSjsg #define AXE_172_CMD_WRITE_IPG0 0x0112 7658ed394fSjsg #define AXE_172_CMD_WRITE_IPG1 0x0113 7758ed394fSjsg #define AXE_172_CMD_WRITE_IPG2 0x0114 7858ed394fSjsg #define AXE_178_CMD_WRITE_IPG012 0x0112 79f63446eaSderaadt #define AXE_CMD_READ_MCAST 0x8015 80f63446eaSderaadt #define AXE_CMD_WRITE_MCAST 0x8116 8158ed394fSjsg #define AXE_172_CMD_READ_NODEID 0x6017 8258ed394fSjsg #define AXE_172_CMD_WRITE_NODEID 0x6118 8358ed394fSjsg #define AXE_178_CMD_READ_NODEID 0x6013 842c184f77Sjsg #define AXE_178_CMD_WRITE_NODEID 0x6114 85f63446eaSderaadt #define AXE_CMD_READ_PHYID 0x2019 8658ed394fSjsg #define AXE_172_CMD_READ_MEDIA 0x101A 8758ed394fSjsg #define AXE_178_CMD_READ_MEDIA 0x201A 88f63446eaSderaadt #define AXE_CMD_WRITE_MEDIA 0x011B 89f63446eaSderaadt #define AXE_CMD_READ_MONITOR_MODE 0x101C 90f63446eaSderaadt #define AXE_CMD_WRITE_MONITOR_MODE 0x011D 91f63446eaSderaadt #define AXE_CMD_READ_GPIO 0x101E 92f63446eaSderaadt #define AXE_CMD_WRITE_GPIO 0x011F 9358ed394fSjsg #define AXE_CMD_SW_RESET_REG 0x0120 9458ed394fSjsg #define AXE_CMD_SW_PHY_STATUS 0x0021 9558ed394fSjsg #define AXE_CMD_SW_PHY_SELECT 0x0122 96f63446eaSderaadt 97838fd592Sjsg #define AXE_SW_RESET_CLEAR 0x00 98838fd592Sjsg #define AXE_SW_RESET_RR 0x01 99838fd592Sjsg #define AXE_SW_RESET_RT 0x02 100838fd592Sjsg #define AXE_SW_RESET_PRTE 0x04 101838fd592Sjsg #define AXE_SW_RESET_PRL 0x08 102838fd592Sjsg #define AXE_SW_RESET_BZ 0x10 103838fd592Sjsg #define AXE_SW_RESET_IPRL 0x20 104838fd592Sjsg #define AXE_SW_RESET_IPPD 0x40 105838fd592Sjsg 10658ed394fSjsg /* AX88178 documentation says to always write this bit... */ 10758ed394fSjsg #define AXE_178_RESET_MAGIC 0x40 10858ed394fSjsg 10958ed394fSjsg #define AXE_178_MEDIA_GMII 0x0001 11058ed394fSjsg #define AXE_MEDIA_FULL_DUPLEX 0x0002 11158ed394fSjsg #define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 11258ed394fSjsg /* AX88178 documentation says to always write 1 to reserved bit... */ 11358ed394fSjsg #define AXE_178_MEDIA_MAGIC 0x0004 11458ed394fSjsg #define AXE_178_MEDIA_ENCK 0x0008 11558ed394fSjsg #define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 11658ed394fSjsg #define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 11758ed394fSjsg #define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 11858ed394fSjsg #define AXE_178_MEDIA_JUMBO_EN 0x0040 11958ed394fSjsg #define AXE_178_MEDIA_LTPF_ONLY 0x0080 12058ed394fSjsg #define AXE_178_MEDIA_RX_EN 0x0100 121ef8190e3Sjsg #define AXE_178_MEDIA_100TX 0x0200 12258ed394fSjsg #define AXE_178_MEDIA_SBP 0x0800 12358ed394fSjsg #define AXE_178_MEDIA_SUPERMAC 0x1000 124810313afSdlg 125f63446eaSderaadt #define AXE_RXCMD_PROMISC 0x0001 126f63446eaSderaadt #define AXE_RXCMD_ALLMULTI 0x0002 12758ed394fSjsg #define AXE_172_RXCMD_UNICAST 0x0004 12858ed394fSjsg #define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 129f63446eaSderaadt #define AXE_RXCMD_BROADCAST 0x0008 130f63446eaSderaadt #define AXE_RXCMD_MULTICAST 0x0010 131f63446eaSderaadt #define AXE_RXCMD_ENABLE 0x0080 132bca247aaSjsg #define AXE_178_RXCMD_MFB 0x0300 133f63446eaSderaadt 134b7d042c6Sjsg #define AXE_PHY_SEL_PRI 1 135b7d042c6Sjsg #define AXE_PHY_SEL_SEC 0 136b7d042c6Sjsg #define AXE_PHY_TYPE_MASK 0xE0 137b7d042c6Sjsg #define AXE_PHY_TYPE_SHIFT 5 138b7d042c6Sjsg #define AXE_PHY_TYPE(x) \ 139b7d042c6Sjsg (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) 140b7d042c6Sjsg 141b7d042c6Sjsg #define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ 142b7d042c6Sjsg #define PHY_TYPE_GIG 1 /* Gigabit PHY */ 143b7d042c6Sjsg #define PHY_TYPE_SPECIAL 4 /* Special case */ 144b7d042c6Sjsg #define PHY_TYPE_RSVD 5 /* Reserved */ 145b7d042c6Sjsg #define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ 146b7d042c6Sjsg 147b7d042c6Sjsg #define AXE_PHY_NO_MASK 0x1F 148b7d042c6Sjsg #define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) 149b7d042c6Sjsg 150b7d042c6Sjsg #define AXE_PHY_NO_AX772_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ 151f63446eaSderaadt 1528715b6e5Syuo #define AXE_GPIO0_EN 0x01 1538715b6e5Syuo #define AXE_GPIO0 0x02 1548715b6e5Syuo #define AXE_GPIO1_EN 0x04 1558715b6e5Syuo #define AXE_GPIO1 0x08 1568715b6e5Syuo #define AXE_GPIO2_EN 0x10 1578715b6e5Syuo #define AXE_GPIO2 0x20 1588715b6e5Syuo #define AXE_GPIO_RELOAD_EEPROM 0x80 1598715b6e5Syuo 1608715b6e5Syuo #define AXE_PHY_MODE_MARVELL 0x00 1618715b6e5Syuo #define AXE_PHY_MODE_CICADA 0x01 1628715b6e5Syuo #define AXE_PHY_MODE_AGERE 0x02 1638715b6e5Syuo #define AXE_PHY_MODE_CICADA_V2 0x05 1648715b6e5Syuo #define AXE_PHY_MODE_CICADA_V2_ASIX 0x09 1658715b6e5Syuo #define AXE_PHY_MODE_REALTEK_8211CL 0x0c 1668715b6e5Syuo #define AXE_PHY_MODE_REALTEK_8211BN 0x0d 1678715b6e5Syuo #define AXE_PHY_MODE_REALTEK_8251CL 0x0e 1688715b6e5Syuo #define AXE_PHY_MODE_ATTANSIC 0x40 1698715b6e5Syuo 1706267c470Sjsg #define AXE_772B_RXCMD_RH1M 0x0100 1716267c470Sjsg #define AXE_772B_RXCMD_RH2M 0x0200 1726267c470Sjsg #define AXE_772B_RXCMD_RH3M 0x0400 1736267c470Sjsg 1746267c470Sjsg #define AXE_RH1M_RXLEN_MASK 0x07ff 1756267c470Sjsg 176f63446eaSderaadt #define AXE_TIMEOUT 1000 177e500abf8Sjsg #define AXE_172_BUFSZ 1536 178e500abf8Sjsg #define AXE_178_MIN_BUFSZ 2048 179e500abf8Sjsg #define AXE_178_MAX_BUFSZ 16384 180f63446eaSderaadt 181f63446eaSderaadt #define AXE_RX_LIST_CNT 1 182f63446eaSderaadt #define AXE_TX_LIST_CNT 1 183f63446eaSderaadt 184f63446eaSderaadt #define AXE_CTL_READ 0x01 185f63446eaSderaadt #define AXE_CTL_WRITE 0x02 186f63446eaSderaadt 187b47c3035Scanacar /* EEPROM Map */ 188b47c3035Scanacar #define AXE_EEPROM_772B_NODEID 0x04 189b47c3035Scanacar 190f63446eaSderaadt /* 191f63446eaSderaadt * The interrupt endpoint is currently unused 192f63446eaSderaadt * by the ASIX part. 193f63446eaSderaadt */ 194f63446eaSderaadt #define AXE_ENDPT_RX 0x0 195f63446eaSderaadt #define AXE_ENDPT_TX 0x1 196f63446eaSderaadt #define AXE_ENDPT_INTR 0x2 197f63446eaSderaadt #define AXE_ENDPT_MAX 0x3 198f63446eaSderaadt 199f63446eaSderaadt struct axe_type { 200f63446eaSderaadt struct usb_devno axe_dev; 201f63446eaSderaadt u_int16_t axe_flags; 20258ed394fSjsg #define AX178 0x0001 /* AX88178 */ 2039b39d331Sjsg #define AX772 0x0002 /* AX88772 */ 2046267c470Sjsg #define AX772B 0x0004 /* AX88772B */ 205f63446eaSderaadt }; 206f63446eaSderaadt 207f63446eaSderaadt struct axe_softc; 208f63446eaSderaadt 209f63446eaSderaadt struct axe_chain { 210f63446eaSderaadt struct axe_softc *axe_sc; 211ab0b1be7Smglocker struct usbd_xfer *axe_xfer; 212f63446eaSderaadt char *axe_buf; 213f63446eaSderaadt struct mbuf *axe_mbuf; 214f63446eaSderaadt int axe_accum; 215f63446eaSderaadt int axe_idx; 216f63446eaSderaadt }; 217f63446eaSderaadt 218f63446eaSderaadt struct axe_cdata { 219f63446eaSderaadt struct axe_chain axe_tx_chain[AXE_TX_LIST_CNT]; 220f63446eaSderaadt struct axe_chain axe_rx_chain[AXE_RX_LIST_CNT]; 221f63446eaSderaadt int axe_tx_prod; 222f63446eaSderaadt int axe_tx_cons; 223f63446eaSderaadt int axe_tx_cnt; 224f63446eaSderaadt int axe_rx_prod; 225f63446eaSderaadt }; 226f63446eaSderaadt 22721ca1aebSjsg struct axe_sframe_hdr { 22821ca1aebSjsg u_int16_t len; 22921ca1aebSjsg u_int16_t ilen; 23021ca1aebSjsg } __packed; 23121ca1aebSjsg 232f63446eaSderaadt struct axe_softc { 2338c5d01eeSmk struct device axe_dev; 234f63446eaSderaadt #define GET_MII(sc) (&(sc)->axe_mii) 235f63446eaSderaadt struct arpcom arpcom; 236f63446eaSderaadt #define GET_IFP(sc) (&(sc)->arpcom.ac_if) 237f63446eaSderaadt struct mii_data axe_mii; 238ab0b1be7Smglocker struct usbd_device *axe_udev; 239ab0b1be7Smglocker struct usbd_interface *axe_iface; 240f63446eaSderaadt 241f63446eaSderaadt u_int16_t axe_vendor; 242f63446eaSderaadt u_int16_t axe_product; 243f63446eaSderaadt 24458ed394fSjsg u_int16_t axe_flags; 24558ed394fSjsg 246f63446eaSderaadt int axe_ed[AXE_ENDPT_MAX]; 247ab0b1be7Smglocker struct usbd_pipe *axe_ep[AXE_ENDPT_MAX]; 248f63446eaSderaadt int axe_unit; 249f63446eaSderaadt struct axe_cdata axe_cdata; 25034eef271Smbalmer struct timeout axe_stat_ch; 251f63446eaSderaadt 252f63446eaSderaadt int axe_refcnt; 253f63446eaSderaadt 254f63446eaSderaadt struct usb_task axe_tick_task; 255f63446eaSderaadt struct usb_task axe_stop_task; 256f63446eaSderaadt 2571af31be2Sjsg struct rwlock axe_mii_lock; 258f63446eaSderaadt 259f63446eaSderaadt int axe_link; 260f63446eaSderaadt unsigned char axe_ipgs[3]; 261f63446eaSderaadt unsigned char axe_phyaddrs[2]; 262b7d042c6Sjsg int axe_phyno; 263f63446eaSderaadt struct timeval axe_rx_notice; 264e500abf8Sjsg u_int axe_bufsz; 265f63446eaSderaadt }; 266