1 /* $OpenBSD: if_muereg.h,v 1.2 2018/08/15 07:13:51 kevlo Exp $ */ 2 3 /* 4 * Copyright (c) 2018 Kevin Lo <kevlo@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * USB vendor requests. 21 */ 22 #define MUE_UR_WRITEREG 0xa0 23 #define MUE_UR_READREG 0xa1 24 25 /* 26 * Offset of MAC address inside EEPROM. 27 */ 28 #define MUE_EE_IND_OFFSET 0x00 29 #define MUE_EE_MAC_OFFSET 0x01 30 #define MUE_EE_LTM_OFFSET 0x3f 31 32 #define MUE_INT_STATUS 0x00c 33 #define MUE_HW_CFG 0x010 34 #define MUE_PMT_CTL 0x014 35 #define MUE_DP_SEL 0x024 36 #define MUE_DP_CMD 0x028 37 #define MUE_DP_ADDR 0x02c 38 #define MUE_DP_DATA 0x030 39 #define MUE_BURST_CAP 0x034 40 #define MUE_BULK_IN_DELAY 0x03c 41 #define MUE_E2P_CMD 0x040 42 #define MUE_E2P_DATA 0x044 43 #define MUE_RFE_CTL 0x060 44 #define MUE_USB_CFG0 0x080 45 #define MUE_USB_CFG1 0x084 46 #define MUE_FCT_RX_CTL 0x090 47 #define MUE_FCT_TX_CTL 0x094 48 #define MUE_FCT_RX_FIFO_END 0x098 49 #define MUE_FCT_TX_FIFO_END 0x098 50 #define MUE_FCT_FLOW 0x0a0 51 #define MUE_7800_RFE_CTL 0x0b0 52 #define MUE_7800_FCT_RX_CTL 0x0c0 53 #define MUE_7800_FCT_TX_CTL 0x0c4 54 #define MUE_7800_FCT_FLOW 0x0d0 55 #define MUE_LTM_INDEX(idx) (0x0e0 + (idx) * 4) 56 #define MUE_MAC_CR 0x100 57 #define MUE_MAC_RX 0x104 58 #define MUE_MAC_TX 0x108 59 #define MUE_FLOW 0x10c 60 #define MUE_RX_ADDRH 0x118 61 #define MUE_RX_ADDRL 0x11c 62 #define MUE_MII_ACCESS 0x120 63 #define MUE_MII_DATA 0x124 64 #define MUE_ADDR_FILTX 0x300 65 #define MUE_7800_ADDR_FILTX 0x400 66 67 #define MUE_7800_BURST_CAP MUE_FCT_RX_CTL 68 #define MUE_7800_BULK_IN_DELAY MUE_FCT_TX_CTL 69 70 /* Hardware configuration register */ 71 #define MUE_HW_CFG_SRST 0x00000001 72 #define MUE_HW_CFG_LRST 0x00000002 73 #define MUE_HW_CFG_BCE 0x00000004 74 #define MUE_HW_CFG_MEF 0x00000010 75 #define MUE_HW_CFG_BIR 0x00000080 76 #define MUE_HW_CFG_LED0_EN 0x00100000 77 #define MUE_HW_CFG_LED1_EN 0x00200000 78 79 /* Power management control register */ 80 #define MUE_PMT_CTL_PHY_RST 0x00000010 81 #define MUE_PMT_CTL_READY 0x00000080 82 83 /* Data port select register */ 84 #define MUE_DP_SEL_RSEL_MASK 0x0000000f 85 #define MUE_DP_SEL_VHF 0x00000001 86 #define MUE_DP_SEL_DPRDY 0x80000000 87 #define MUE_DP_SEL_VHF_HASH_LEN 16 88 #define MUE_DP_SEL_VHF_VLAN_LEN 128 89 90 /* Data port command register */ 91 #define MUE_DP_CMD_WRITE 0x00000001 92 93 /* EEPROM command register */ 94 #define MUE_E2P_CMD_ADDR_MASK 0x000001ff 95 #define MUE_E2P_CMD_READ 0x00000000 96 #define MUE_E2P_CMD_TIMEOUT 0x00000400 97 #define MUE_E2P_CMD_BUSY 0x80000000 98 99 /* Receive filtering engine control register */ 100 #define MUE_RFE_CTL_PERFECT 0x00000002 101 #define MUE_RFE_CTL_MULTICAST_HASH 0x00000008 102 #define MUE_RFE_CTL_UNICAST 0x00000100 103 #define MUE_RFE_CTL_MULTICAST 0x00000200 104 #define MUE_RFE_CTL_BROADCAST 0x00000400 105 106 /* USB configuration register 0 */ 107 #define MUE_USB_CFG0_BCE 0x00000020 108 #define MUE_USB_CFG0_BIR 0x00000040 109 110 /* USB configuration register 1 */ 111 #define MUE_USB_CFG1_LTM_ENABLE 0x00000100 112 #define MUE_USB_CFG1_DEV_U1_INIT_EN 0x00000400 113 #define MUE_USB_CFG1_DEV_U2_INIT_EN 0x00001000 114 115 /* RX FIFO control register */ 116 #define MUE_FCT_RX_CTL_EN 0x80000000 117 118 /* TX FIFO control register */ 119 #define MUE_FCT_TX_CTL_EN 0x80000000 120 121 /* MAC control register */ 122 #define MUE_MAC_CR_RST 0x00000001 123 #define MUE_MAC_CR_FULL_DUPLEX 0x00000008 124 #define MUE_MAC_CR_AUTO_SPEED 0x00000800 125 #define MUE_MAC_CR_AUTO_DUPLEX 0x00001000 126 #define MUE_MAC_CR_GMII_EN 0x00080000 127 128 /* MAC receive register */ 129 #define MUE_MAC_RX_RXEN 0x00000001 130 #define MUE_MAC_RX_MAX_SIZE_MASK 0x3fff0000 131 #define MUE_MAC_RX_MAX_SIZE_SHIFT 16 132 #define MUE_MAC_RX_MAX_LEN(x) \ 133 (((x) << MUE_MAC_RX_MAX_SIZE_SHIFT) & MUE_MAC_RX_MAX_SIZE_MASK) 134 135 /* MAC transmit register */ 136 #define MUE_MAC_TX_TXEN 0x00000001 137 138 /* Flow control register */ 139 #define MUE_FLOW_PAUSE_TIME 0x0000ffff 140 #define MUE_FLOW_RX_FCEN 0x20000000 141 #define MUE_FLOW_TX_FCEN 0x40000000 142 143 /* MII access register */ 144 #define MUE_MII_ACCESS_READ 0x00000000 145 #define MUE_MII_ACCESS_BUSY 0x00000001 146 #define MUE_MII_ACCESS_WRITE 0x00000002 147 #define MUE_MII_ACCESS_REGADDR_MASK 0x000007c0 148 #define MUE_MII_ACCESS_REGADDR_SHIFT 6 149 #define MUE_MII_ACCESS_PHYADDR_MASK 0x0000f800 150 #define MUE_MII_ACCESS_PHYADDR_SHIFT 11 151 #define MUE_MII_ACCESS_REGADDR(x) \ 152 (((x) << MUE_MII_ACCESS_REGADDR_SHIFT) & MUE_MII_ACCESS_REGADDR_MASK) 153 #define MUE_MII_ACCESS_PHYADDR(x) \ 154 (((x) << MUE_MII_ACCESS_PHYADDR_SHIFT) & MUE_MII_ACCESS_PHYADDR_MASK) 155 156 /* MAC address perfect filter register */ 157 #define MUE_ADDR_FILTX_VALID 0x80000000 158 159 #define MUE_DEFAULT_BULKIN_DELAY 0x00002000 160 #define MUE_7800_DEFAULT_BULKIN_DELAY 0x00000800 161 162 #define MUE_BURST_MAX_BUFSZ 129 163 #define MUE_BURST_MIN_BUFSZ 37 164 #define MUE_7800_BURST_MAX_BUFSZ 24 165 #define MUE_7800_BURST_MIN_BUFSZ 12 166 167 #define MUE_7800_BUFSZ 12288 168 #define MUE_MAX_BUFSZ 18944 169 #define MUE_MIN_BUFSZ 8256 170 171 #define MUE_EEPROM_INDICATOR 0xa5 172 173 /* 174 * The interrupt endpoint is currently unused by the Moschip part. 175 */ 176 #define MUE_ENDPT_RX 0x0 177 #define MUE_ENDPT_TX 0x1 178 #define MUE_ENDPT_INTR 0x2 179 #define MUE_ENDPT_MAX 0x3 180 181 #define MUE_RX_LIST_CNT 1 182 #define MUE_TX_LIST_CNT 1 183 184 struct mue_softc; 185 186 struct mue_chain { 187 struct mue_softc *mue_sc; 188 struct usbd_xfer *mue_xfer; 189 char *mue_buf; 190 struct mbuf *mue_mbuf; 191 int mue_accum; 192 int mue_idx; 193 }; 194 195 struct mue_cdata { 196 struct mue_chain mue_tx_chain[MUE_TX_LIST_CNT]; 197 struct mue_chain mue_rx_chain[MUE_RX_LIST_CNT]; 198 int mue_tx_prod; 199 int mue_tx_cons; 200 int mue_tx_cnt; 201 int mue_rx_prod; 202 }; 203 204 struct mue_rxbuf_hdr { 205 uint32_t rx_cmd_a; 206 #define MUE_RX_CMD_A_RED 0x00400000 207 #define MUE_RX_CMD_A_LEN_MASK 0x00003fff 208 209 uint32_t rx_cmd_b; 210 uint16_t rx_cmd_c; 211 } __packed; 212 213 struct mue_txbuf_hdr { 214 uint32_t tx_cmd_a; 215 #define MUE_TX_CMD_A_FCS 0x00400000 216 #define MUE_TX_CMD_A_LEN_MASK 0x000fffff 217 218 uint32_t tx_cmd_b; 219 } __packed; 220 221 struct mue_softc { 222 struct device mue_dev; 223 224 struct arpcom arpcom; 225 struct mii_data mue_mii; 226 #define GET_MII(sc) (&(sc)->mue_mii) 227 #define GET_IFP(sc) (&(sc)->arpcom.ac_if) 228 229 int mue_ed[MUE_ENDPT_MAX]; 230 struct usbd_pipe *mue_ep[MUE_ENDPT_MAX]; 231 struct mue_cdata mue_cdata; 232 struct timeout mue_stat_ch; 233 234 struct usbd_device *mue_udev; 235 struct usbd_interface *mue_iface; 236 237 struct usb_task mue_tick_task; 238 struct usb_task mue_stop_task; 239 240 struct rwlock mue_mii_lock; 241 242 struct timeval mue_rx_notice; 243 244 uint16_t mue_product; 245 uint16_t mue_flags; 246 247 int mue_refcnt; 248 249 int mue_phyno; 250 int mue_bufsz; 251 int mue_link; 252 int mue_eeprom_present; 253 }; 254