1 /* $OpenBSD: if_urereg.h,v 1.8 2019/12/07 08:45:28 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #define URE_CONFIG_IDX 0 /* config number 1 */ 31 #define URE_IFACE_IDX 0 32 33 #define URE_CTL_READ 0x01 34 #define URE_CTL_WRITE 0x02 35 36 #define URE_TIMEOUT 1000 37 #define URE_PHY_TIMEOUT 2000 38 39 #define URE_BYTE_EN_DWORD 0xff 40 #define URE_BYTE_EN_WORD 0x33 41 #define URE_BYTE_EN_BYTE 0x11 42 #define URE_BYTE_EN_SIX_BYTES 0x3f 43 44 #define URE_FRAMELEN(mtu) \ 45 (mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN) 46 #define URE_JUMBO_FRAMELEN (9 * 1024) 47 #define URE_JUMBO_MTU \ 48 (URE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - \ 49 ETHER_VLAN_ENCAP_LEN) 50 51 #define URE_PLA_IDR 0xc000 52 #define URE_PLA_RCR 0xc010 53 #define URE_PLA_RMS 0xc016 54 #define URE_PLA_RXFIFO_CTRL0 0xc0a0 55 #define URE_PLA_RXFIFO_CTRL1 0xc0a4 56 #define URE_PLA_RXFIFO_CTRL2 0xc0a8 57 #define URE_PLA_DMY_REG0 0xc0b0 58 #define URE_PLA_FMC 0xc0b4 59 #define URE_PLA_CFG_WOL 0xc0b6 60 #define URE_PLA_TEREDO_CFG 0xc0bc 61 #define URE_PLA_MAR 0xcd00 62 #define URE_PLA_BACKUP 0xd000 63 #define URE_PLA_BDC_CR 0xd1a0 64 #define URE_PLA_TEREDO_TIMER 0xd2cc 65 #define URE_PLA_REALWOW_TIMER 0xd2e8 66 #define URE_PLA_SUSPEND_FLAG 0xd38a 67 #define URE_PLA_INDICATE_FALG 0xd38c 68 #define URE_PLA_EXTRA_STATUS 0xd398 69 #define URE_PLA_LEDSEL 0xdd90 70 #define URE_PLA_LED_FEATURE 0xdd92 71 #define URE_PLA_PHYAR 0xde00 72 #define URE_PLA_BOOT_CTRL 0xe004 73 #define URE_PLA_GPHY_INTR_IMR 0xe022 74 #define URE_PLA_EEE_CR 0xe040 75 #define URE_PLA_EEEP_CR 0xe080 76 #define URE_PLA_MAC_PWR_CTRL 0xe0c0 77 #define URE_PLA_MAC_PWR_CTRL2 0xe0ca 78 #define URE_PLA_MAC_PWR_CTRL3 0xe0cc 79 #define URE_PLA_MAC_PWR_CTRL4 0xe0ce 80 #define URE_PLA_WDT6_CTRL 0xe428 81 #define URE_PLA_TCR0 0xe610 82 #define URE_PLA_TCR1 0xe612 83 #define URE_PLA_MTPS 0xe615 84 #define URE_PLA_TXFIFO_CTRL 0xe618 85 #define URE_PLA_RSTTALLY 0xe800 86 #define URE_PLA_CR 0xe813 87 #define URE_PLA_CRWECR 0xe81c 88 #define URE_PLA_CONFIG34 0xe820 89 #define URE_PLA_CONFIG5 0xe822 90 #define URE_PLA_PHY_PWR 0xe84c 91 #define URE_PLA_OOB_CTRL 0xe84f 92 #define URE_PLA_CPCR 0xe854 93 #define URE_PLA_MISC_0 0xe858 94 #define URE_PLA_MISC_1 0xe85a 95 #define URE_PLA_OCP_GPHY_BASE 0xe86c 96 #define URE_PLA_TELLYCNT 0xe890 97 #define URE_PLA_SFF_STS_7 0xe8de 98 #define URE_PLA_PHYSTATUS 0xe908 99 100 #define URE_USB_USB2PHY 0xb41e 101 #define URE_USB_SSPHYLINK2 0xb428 102 #define URE_USB_U2P3_CTRL 0xb460 103 #define URE_USB_CSR_DUMMY1 0xb464 104 #define URE_USB_CSR_DUMMY2 0xb466 105 #define URE_USB_DEV_STAT 0xb808 106 #define URE_USB_CONNECT_TIMER 0xcbf8 107 #define URE_USB_MSC_TIMER 0xcbfc 108 #define URE_USB_BURST_SIZE 0xcfc0 109 #define URE_USB_LPM_CONFIG 0xcfd8 110 #define URE_USB_USB_CTRL 0xd406 111 #define URE_USB_PHY_CTRL 0xd408 112 #define URE_USB_TX_AGG 0xd40a 113 #define URE_USB_RX_BUF_TH 0xd40c 114 #define URE_USB_LPM_CTRL 0xd41a 115 #define URE_USB_USB_TIMER 0xd428 116 #define URE_USB_RX_EARLY_AGG 0xd42c 117 #define URE_USB_RX_EARLY_SIZE 0xd42e 118 #define URE_USB_PM_CTRL_STATUS 0xd432 119 #define URE_USB_TX_DMA 0xd434 120 #define URE_USB_UPT_RXDMA_OWN 0xd437 121 #define URE_USB_TOLERANCE 0xd490 122 #define URE_USB_BMU_RESET 0xd4b0 123 #define URE_USB_U1U2_TIMER 0xd4da 124 #define URE_USB_UPS_CTRL 0xd800 125 #define URE_USB_POWER_CUT 0xd80a 126 #define URE_USB_MISC_0 0xd81a 127 #define URE_USB_POWER_CUT 0xd80a 128 #define URE_USB_AFE_CTRL2 0xd824 129 #define URE_USB_UPS_FLAGS 0xd848 130 #define URE_USB_WDT11_CTRL 0xe43c 131 132 /* OCP Registers. */ 133 #define URE_OCP_ALDPS_CONFIG 0x2010 134 #define URE_OCP_EEE_CONFIG1 0x2080 135 #define URE_OCP_EEE_CONFIG2 0x2092 136 #define URE_OCP_EEE_CONFIG3 0x2094 137 #define URE_OCP_BASE_MII 0xa400 138 #define URE_OCP_EEE_AR 0xa41a 139 #define URE_OCP_EEE_DATA 0xa41c 140 #define URE_OCP_PHY_STATUS 0xa420 141 #define URE_OCP_POWER_CFG 0xa430 142 #define URE_OCP_EEE_CFG 0xa432 143 #define URE_OCP_SRAM_ADDR 0xa436 144 #define URE_OCP_SRAM_DATA 0xa438 145 #define URE_OCP_DOWN_SPEED 0xa442 146 #define URE_OCP_EEE_ABLE 0xa5c4 147 #define URE_OCP_EEE_ADV 0xa5d0 148 #define URE_OCP_EEE_LPABLE 0xa5d2 149 #define URE_OCP_PHY_STATE 0xa708 150 #define URE_OCP_ADC_CFG 0xbc06 151 152 /* SRAM Register. */ 153 #define URE_SRAM_LPF_CFG 0x8012 154 #define URE_SRAM_10M_AMP1 0x8080 155 #define URE_SRAM_10M_AMP2 0x8082 156 #define URE_SRAM_IMPEDANCE 0x8084 157 158 /* URE_PLA_RCR */ 159 #define URE_RCR_AAP 0x00000001 160 #define URE_RCR_APM 0x00000002 161 #define URE_RCR_AM 0x00000004 162 #define URE_RCR_AB 0x00000008 163 #define URE_RCR_ACPT_ALL \ 164 (URE_RCR_AAP | URE_RCR_APM | URE_RCR_AM | URE_RCR_AB) 165 166 /* URE_PLA_RXFIFO_CTRL0 */ 167 #define URE_RXFIFO_THR1_NORMAL 0x00080002 168 #define URE_RXFIFO_THR1_OOB 0x01800003 169 170 /* URE_PLA_RXFIFO_CTRL1 */ 171 #define URE_RXFIFO_THR2_FULL 0x00000060 172 #define URE_RXFIFO_THR2_HIGH 0x00000038 173 #define URE_RXFIFO_THR2_OOB 0x0000004a 174 #define URE_RXFIFO_THR2_NORMAL 0x00a0 175 176 /* URE_PLA_RXFIFO_CTRL2 */ 177 #define URE_RXFIFO_THR3_FULL 0x00000078 178 #define URE_RXFIFO_THR3_HIGH 0x00000048 179 #define URE_RXFIFO_THR3_OOB 0x0000005a 180 #define URE_RXFIFO_THR3_NORMAL 0x0110 181 182 /* URE_PLA_TXFIFO_CTRL */ 183 #define URE_TXFIFO_THR_NORMAL 0x00400008 184 #define URE_TXFIFO_THR_NORMAL2 0x01000008 185 186 /* URE_PLA_DMY_REG0 */ 187 #define URE_ECM_ALDPS 0x0002 188 189 /* URE_PLA_FMC */ 190 #define URE_FMC_FCR_MCU_EN 0x0001 191 192 /* URE_PLA_EEEP_CR */ 193 #define URE_EEEP_CR_EEEP_TX 0x0002 194 195 /* URE_PLA_WDT6_CTRL */ 196 #define URE_WDT6_SET_MODE 0x0010 197 198 /* URE_PLA_TCR0 */ 199 #define URE_TCR0_AUTO_FIFO 0x0080 200 #define URE_TCR0_TX_EMPTY 0x0800 201 202 /* URE_PLA_TCR1 */ 203 #define URE_VERSION_MASK 0x7cf0 204 205 /* URE_PLA_MTPS */ 206 #define MTPS_DEFAULT 96 207 #define MTPS_JUMBO 192 208 209 /* URE_PLA_RSTTALLY */ 210 #define URE_TALLY_RESET 0x0001 211 212 /* URE_PLA_CR */ 213 #define URE_CR_RST 0x10 214 #define URE_CR_RE 0x08 215 #define URE_CR_TE 0x04 216 217 /* URE_PLA_CRWECR */ 218 #define URE_CRWECR_NORAML 0x00 219 #define URE_CRWECR_CONFIG 0xc0 220 221 /* URE_PLA_OOB_CTRL */ 222 #define URE_DIS_MCU_CLROOB 0x01 223 #define URE_LINK_LIST_READY 0x02 224 #define URE_RXFIFO_EMPTY 0x10 225 #define URE_TXFIFO_EMPTY 0x20 226 #define URE_NOW_IS_OOB 0x80 227 #define URE_FIFO_EMPTY (URE_TXFIFO_EMPTY | URE_RXFIFO_EMPTY) 228 229 /* URE_PLA_MISC_1 */ 230 #define URE_RXDY_GATED_EN 0x0008 231 232 /* URE_PLA_SFF_STS_7 */ 233 #define URE_MCU_BORW_EN 0x4000 234 #define URE_RE_INIT_LL 0x8000 235 236 /* URE_PLA_CPCR */ 237 #define URE_CPCR_RX_VLAN 0x0040 238 239 /* URE_PLA_TEREDO_CFG */ 240 #define URE_TEREDO_SEL 0x8000 241 #define URE_TEREDO_WAKE_MASK 0x7f00 242 #define URE_TEREDO_RS_EVENT_MASK 0x00fe 243 #define URE_OOB_TEREDO_EN 0x0001 244 245 /* URE_PLA_BDC_CR */ 246 #define URE_ALDPS_PROXY_MODE 0x0001 247 248 /* URE_PLA_CONFIG34 */ 249 #define URE_LINK_OFF_WAKE_EN 0x0008 250 #define URE_LINK_ON_WAKE_EN 0x0010 251 252 /* URE_PLA_CONFIG5 */ 253 #define URE_LAN_WAKE_EN 0x0002 254 255 /* URE_PLA_LED_FEATURE */ 256 #define URE_LED_MODE_MASK 0x0700 257 258 /* URE_PLA_PHY_PWR */ 259 #define URE_TX_10M_IDLE_EN 0x0080 260 #define URE_PFM_PWM_SWITCH 0x0040 261 262 /* URE_PLA_MAC_PWR_CTRL */ 263 #define URE_D3_CLK_GATED_EN 0x00004000 264 #define URE_MCU_CLK_RATIO 0x07010f07 265 #define URE_MCU_CLK_RATIO_MASK 0x0f0f0f0f 266 #define URE_ALDPS_SPDWN_RATIO 0x0f87 267 268 /* URE_PLA_MAC_PWR_CTRL2 */ 269 #define URE_MAC_CLK_SPDWN_EN 0x8000 270 #define URE_EEE_SPDWN_RATIO 0x8007 271 272 /* URE_PLA_MAC_PWR_CTRL3 */ 273 #define URE_L1_SPDWN_EN 0x0001 274 #define URE_U1U2_SPDWN_EN 0x0002 275 #define URE_SUSPEND_SPDWN_EN 0x0004 276 #define URE_PKT_AVAIL_SPDWN_EN 0x0100 277 278 /* URE_PLA_MAC_PWR_CTRL4 */ 279 #define URE_EEE_SPDWN_EN 0x0001 280 #define URE_TP1000_SPDWN_EN 0x0008 281 #define URE_TP500_SPDWN_EN 0x0010 282 #define URE_TP100_SPDWN_EN 0x0020 283 #define URE_TX10MIDLE_EN 0x0100 284 #define URE_RXDV_SPDWN_EN 0x0800 285 #define URE_PWRSAVE_SPDWN_EN 0x1000 286 287 /* URE_PLA_GPHY_INTR_IMR */ 288 #define URE_GPHY_STS_MSK 0x0001 289 #define URE_SPEED_DOWN_MSK 0x0002 290 #define URE_SPDWN_RXDV_MSK 0x0004 291 #define URE_SPDWN_LINKCHG_MSK 0x0008 292 293 /* URE_PLA_PHYAR */ 294 #define URE_PHYAR_PHYDATA 0x0000ffff 295 #define URE_PHYAR_BUSY 0x80000000 296 297 /* URE_PLA_EEE_CR */ 298 #define URE_EEE_RX_EN 0x0001 299 #define URE_EEE_TX_EN 0x0002 300 301 /* URE_PLA_BOOT_CTRL */ 302 #define URE_AUTOLOAD_DONE 0x0002 303 304 /* URE_PLA_SUSPEND_FLAG */ 305 #define URE_LINK_CHG_EVENT 0x01 306 307 /* URE_PLA_INDICATE_FALG */ 308 #define URE_UPCOMING_RUNTIME_D3 0x01 309 310 /* URE_PLA_EXTRA_STATUS */ 311 #define URE_LINK_CHANGE_FLAG 0x0100 312 313 /* URE_PLA_PHYSTATUS */ 314 #define URE_PHYSTATUS_FDX 0x0001 315 #define URE_PHYSTATUS_LINK 0x0002 316 #define URE_PHYSTATUS_10MBPS 0x0004 317 #define URE_PHYSTATUS_100MBPS 0x0008 318 #define URE_PHYSTATUS_1000MBPS 0x0010 319 #define URE_PHYSTATUS_2500MBPS 0x0400 320 321 /* URE_USB_USB2PHY */ 322 #define URE_USB2PHY_SUSPEND 0x0001 323 #define URE_USB2PHY_L1 0x0002 324 325 /* URE_USB_SSPHYLINK2 */ 326 #define URE_PWD_DN_SCALE_MASK 0x3ffe 327 #define URE_PWD_DN_SCALE(x) ((x) << 1) 328 329 /* URE_USB_CSR_DUMMY1 */ 330 #define URE_DYNAMIC_BURST 0x0001 331 332 /* URE_USB_CSR_DUMMY2 */ 333 #define URE_EP4_FULL_FC 0x0001 334 335 /* URE_USB_DEV_STAT */ 336 #define URE_STAT_SPEED_HIGH 0x0000 337 #define URE_STAT_SPEED_FULL 0x0001 338 #define URE_STAT_SPEED_MASK 0x0006 339 340 /* URE_USB_LPM_CONFIG */ 341 #define LPM_U1U2_EN 0x0001 342 343 /* URE_USB_TX_AGG */ 344 #define URE_TX_AGG_MAX_THRESHOLD 0x03 345 346 /* URE_USB_RX_BUF_TH */ 347 #define URE_RX_THR_SUPER 0x0c350180 348 #define URE_RX_THR_HIGH 0x7a120180 349 #define URE_RX_THR_SLOW 0xffff0180 350 #define URE_RX_THR_B 0x00010001 351 352 /* URE_USB_TX_DMA */ 353 #define URE_TEST_MODE_DISABLE 0x00000001 354 #define URE_TX_SIZE_ADJUST1 0x00000100 355 356 /* URE_USB_UPT_RXDMA_OWN */ 357 #define URE_OWN_UPDATE 0x01 358 #define URE_OWN_CLEAR 0x02 359 360 /* URE_USB_BMU_RESET */ 361 #define BMU_RESET_EP_IN 0x01 362 #define BMU_RESET_EP_OUT 0x02 363 364 /* URE_USB_UPS_CTRL */ 365 #define URE_POWER_CUT 0x0100 366 367 /* URE_USB_PM_CTRL_STATUS */ 368 #define URE_RESUME_INDICATE 0x0001 369 370 /* URE_USB_USB_CTRL */ 371 #define URE_RX_AGG_DISABLE 0x0010 372 #define URE_RX_ZERO_EN 0x0080 373 374 /* URE_USB_U2P3_CTRL */ 375 #define URE_U2P3_ENABLE 0x0001 376 377 /* URE_USB_POWER_CUT */ 378 #define URE_PWR_EN 0x0001 379 #define URE_PHASE2_EN 0x0008 380 #define URE_UPS_EN 0x0010 381 #define URE_USP_PREWAKE 0x0020 382 383 /* URE_USB_MISC_0 */ 384 #define URE_PCUT_STATUS 0x0001 385 386 /* URE_USB_RX_EARLY_AGG */ 387 #define URE_COALESCE_SUPER 85000U 388 #define URE_COALESCE_HIGH 250000U 389 #define URE_COALESCE_SLOW 524280U 390 391 /* URE_USB_WDT11_CTRL */ 392 #define URE_TIMER11_EN 0x0001 393 394 /* URE_USB_LPM_CTRL */ 395 #define URE_FIFO_EMPTY_1FB 0x30 396 #define URE_LPM_TIMER_MASK 0x0c 397 #define URE_LPM_TIMER_500MS 0x04 398 #define URE_LPM_TIMER_500US 0x0c 399 #define URE_ROK_EXIT_LPM 0x02 400 401 /* URE_USB_AFE_CTRL2 */ 402 #define URE_SEN_VAL_MASK 0xf800 403 #define URE_SEN_VAL_NORMAL 0xa000 404 #define URE_SEL_RXIDLE 0x0100 405 406 /* URE_USB_UPS_FLAGS */ 407 #define URE_UPS_FLAGS_EN_ALDPS 0x00000008 408 #define URE_UPS_FLAGS_MASK 0xffffffff 409 410 /* URE_OCP_ALDPS_CONFIG */ 411 #define URE_ENPWRSAVE 0x8000 412 #define URE_ENPDNPS 0x0200 413 #define URE_LINKENA 0x0100 414 #define URE_DIS_SDSAVE 0x0010 415 416 /* URE_OCP_PHY_STATUS */ 417 #define URE_PHY_STAT_MASK 0x0007 418 #define URE_PHY_STAT_EXT_INIT 2 419 #define URE_PHY_STAT_LAN_ON 3 420 #define URE_PHY_STAT_PWRDN 5 421 422 /* URE_OCP_POWER_CFG */ 423 #define URE_EEE_CLKDIV_EN 0x8000 424 #define URE_EN_ALDPS 0x0004 425 #define URE_EN_10M_PLLOFF 0x0001 426 427 /* URE_OCP_EEE_CFG */ 428 #define URE_CTAP_SHORT_EN 0x0040 429 #define URE_EEE10_EN 0x0010 430 431 /* URE_OCP_DOWN_SPEED */ 432 #define URE_EN_10M_BGOFF 0x0080 433 434 /* URE_OCP_PHY_STATE */ 435 #define URE_TXDIS_STATE 0x01 436 #define URE_ABD_STATE 0x02 437 438 /* URE_OCP_ADC_CFG */ 439 #define URE_EN_EMI_L 0x0040 440 #define URE_ADC_EN 0x0080 441 #define URE_CKADSEL_L 0x0100 442 443 #define URE_ADV_2500TFDX 0x0080 444 445 #define URE_MCU_TYPE_PLA 0x0100 446 #define URE_MCU_TYPE_USB 0x0000 447 448 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 449 450 struct ure_intrpkt { 451 uint8_t ure_tsr; 452 uint8_t ure_rsr; 453 uint8_t ure_gep_msr; 454 uint8_t ure_waksr; 455 uint8_t ure_txok_cnt; 456 uint8_t ure_rxlost_cnt; 457 uint8_t ure_crcerr_cnt; 458 uint8_t ure_col_cnt; 459 } __packed; 460 461 struct ure_rxpkt { 462 uint32_t ure_pktlen; 463 #define URE_RXPKT_LEN_MASK 0x7fff 464 uint32_t ure_vlan; 465 #define URE_RXPKT_UDP (1 << 23) 466 #define URE_RXPKT_TCP (1 << 22) 467 #define URE_RXPKT_IPV6 (1 << 20) 468 #define URE_RXPKT_IPV4 (1 << 19) 469 #define URE_RXPKT_VLAN_TAG (1 << 16) 470 #define URE_RXPKT_VLAN_DATA 0xffff 471 uint32_t ure_csum; 472 #define URE_RXPKT_IPSUMBAD (1 << 23) 473 #define URE_RXPKT_UDPSUMBAD (1 << 22) 474 #define URE_RXPKT_TCPSUMBAD (1 << 21) 475 uint32_t ure_rsvd2; 476 uint32_t ure_rsvd3; 477 uint32_t ure_rsvd4; 478 } __packed; 479 480 struct ure_txpkt { 481 uint32_t ure_pktlen; 482 #define URE_TXPKT_TX_FS (1 << 31) 483 #define URE_TXPKT_TX_LS (1 << 30) 484 #define URE_TXPKT_LEN_MASK 0xffff 485 uint32_t ure_vlan; 486 #define URE_TXPKT_UDP (1 << 31) 487 #define URE_TXPKT_TCP (1 << 30) 488 #define URE_TXPKT_IPV4 (1 << 29) 489 #define URE_TXPKT_IPV6 (1 << 28) 490 #define URE_TXPKT_VLAN_TAG (1 << 16) 491 } __packed; 492 493 #define URE_ENDPT_RX 0 494 #define URE_ENDPT_TX 1 495 #define URE_ENDPT_MAX 2 496 497 #define URE_TX_LIST_CNT 8 498 #define URE_RX_LIST_CNT 1 499 #define URE_RX_BUF_ALIGN sizeof(uint64_t) 500 501 #define URE_TXBUFSZ 16384 502 #define URE_8152_RXBUFSZ 16384 503 #define URE_8153_RXBUFSZ 32768 504 505 struct ure_chain { 506 struct ure_softc *uc_sc; 507 struct usbd_xfer *uc_xfer; 508 char *uc_buf; 509 struct mbuf *uc_mbuf; 510 int uc_accum; 511 int uc_idx; 512 }; 513 514 struct ure_cdata { 515 struct ure_chain tx_chain[URE_TX_LIST_CNT]; 516 struct ure_chain rx_chain[URE_RX_LIST_CNT]; 517 int tx_prod; 518 int tx_cnt; 519 }; 520 521 struct ure_softc { 522 struct device ure_dev; 523 struct usbd_device *ure_udev; 524 525 /* usb */ 526 struct usbd_interface *ure_iface; 527 struct usb_task ure_tick_task; 528 struct usb_task ure_stop_task; 529 int ure_ed[URE_ENDPT_MAX]; 530 struct usbd_pipe *ure_ep[URE_ENDPT_MAX]; 531 532 /* ethernet */ 533 struct arpcom ure_ac; 534 struct mii_data ure_mii; 535 struct ifmedia ure_ifmedia; 536 struct rwlock ure_mii_lock; 537 int ure_refcnt; 538 539 struct ure_cdata ure_cdata; 540 struct timeout ure_stat_ch; 541 542 struct timeval ure_rx_notice; 543 int ure_rxbufsz; 544 int ure_tx_list_cnt; 545 546 int ure_phyno; 547 548 u_int ure_flags; 549 #define URE_FLAG_LINK 0x0001 550 #define URE_FLAG_8152 0x1000 /* RTL8152 */ 551 #define URE_FLAG_8153B 0x2000 /* RTL8153B */ 552 #define URE_FLAG_8156 0x4000 /* RTL8156 */ 553 554 u_int ure_chip; 555 #define URE_CHIP_VER_4C00 0x01 556 #define URE_CHIP_VER_4C10 0x02 557 #define URE_CHIP_VER_5C00 0x04 558 #define URE_CHIP_VER_5C10 0x08 559 #define URE_CHIP_VER_5C20 0x10 560 #define URE_CHIP_VER_5C30 0x20 561 }; 562