1 /* $OpenBSD: ohci.c,v 1.92 2009/10/13 19:33:17 pirofti Exp $ */ 2 /* $NetBSD: ohci.c,v 1.139 2003/02/22 05:24:16 tsutsui Exp $ */ 3 /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */ 4 5 /* 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Lennart Augustsson (lennart@augustsson.net) at 11 * Carlstedt Research & Technology. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Open Host Controller driver. 37 * 38 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 39 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/selinfo.h> 48 #include <sys/proc.h> 49 #include <sys/queue.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 #include <dev/usb/usb_quirks.h> 59 60 #include <dev/usb/ohcireg.h> 61 #include <dev/usb/ohcivar.h> 62 63 struct cfdriver ohci_cd = { 64 NULL, "ohci", DV_DULL 65 }; 66 67 #ifdef OHCI_DEBUG 68 #define DPRINTF(x) do { if (ohcidebug) printf x; } while (0) 69 #define DPRINTFN(n,x) do { if (ohcidebug>(n)) printf x; } while (0) 70 int ohcidebug = 0; 71 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n,x) 75 #endif 76 77 #define mstohz(ms) ((ms) * hz / 1000) 78 79 /* 80 * The OHCI controller is little endian, so on big endian machines 81 * the data stored in memory needs to be swapped. 82 */ 83 84 struct ohci_pipe; 85 86 ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 87 void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 88 89 ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 90 void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 91 92 ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 93 void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 94 95 #if 0 96 void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 97 ohci_soft_td_t *); 98 #endif 99 usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 100 ohci_softc_t *, u_int, int, usbd_xfer_handle, 101 ohci_soft_td_t *, ohci_soft_td_t **); 102 103 void ohci_shutdown(void *v); 104 usbd_status ohci_open(usbd_pipe_handle); 105 void ohci_poll(struct usbd_bus *); 106 void ohci_softintr(void *); 107 void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 108 void ohci_add_done(ohci_softc_t *, ohci_physaddr_t); 109 void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 110 111 usbd_status ohci_device_request(usbd_xfer_handle xfer); 112 void ohci_add_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 113 void ohci_rem_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 114 void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 115 void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 116 ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 117 void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 118 void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 119 ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 120 121 usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 122 void ohci_device_isoc_enter(usbd_xfer_handle); 123 124 usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 125 void ohci_freem(struct usbd_bus *, usb_dma_t *); 126 127 usbd_xfer_handle ohci_allocx(struct usbd_bus *); 128 void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 129 130 usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 131 usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 132 void ohci_root_ctrl_abort(usbd_xfer_handle); 133 void ohci_root_ctrl_close(usbd_pipe_handle); 134 void ohci_root_ctrl_done(usbd_xfer_handle); 135 136 usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 137 usbd_status ohci_root_intr_start(usbd_xfer_handle); 138 void ohci_root_intr_abort(usbd_xfer_handle); 139 void ohci_root_intr_close(usbd_pipe_handle); 140 void ohci_root_intr_done(usbd_xfer_handle); 141 142 usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 143 usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 144 void ohci_device_ctrl_abort(usbd_xfer_handle); 145 void ohci_device_ctrl_close(usbd_pipe_handle); 146 void ohci_device_ctrl_done(usbd_xfer_handle); 147 148 usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 149 usbd_status ohci_device_bulk_start(usbd_xfer_handle); 150 void ohci_device_bulk_abort(usbd_xfer_handle); 151 void ohci_device_bulk_close(usbd_pipe_handle); 152 void ohci_device_bulk_done(usbd_xfer_handle); 153 154 usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 155 usbd_status ohci_device_intr_start(usbd_xfer_handle); 156 void ohci_device_intr_abort(usbd_xfer_handle); 157 void ohci_device_intr_close(usbd_pipe_handle); 158 void ohci_device_intr_done(usbd_xfer_handle); 159 160 usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 161 usbd_status ohci_device_isoc_start(usbd_xfer_handle); 162 void ohci_device_isoc_abort(usbd_xfer_handle); 163 void ohci_device_isoc_close(usbd_pipe_handle); 164 void ohci_device_isoc_done(usbd_xfer_handle); 165 166 usbd_status ohci_device_setintr(ohci_softc_t *sc, 167 struct ohci_pipe *pipe, int ival); 168 169 int ohci_str(usb_string_descriptor_t *, int, const char *); 170 171 void ohci_timeout(void *); 172 void ohci_timeout_task(void *); 173 void ohci_rhsc_able(ohci_softc_t *, int); 174 void ohci_rhsc_enable(void *); 175 176 void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 177 void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 178 179 void ohci_device_clear_toggle(usbd_pipe_handle pipe); 180 void ohci_noop(usbd_pipe_handle pipe); 181 182 #ifdef OHCI_DEBUG 183 void ohci_dumpregs(ohci_softc_t *); 184 void ohci_dump_tds(ohci_soft_td_t *); 185 void ohci_dump_td(ohci_soft_td_t *); 186 void ohci_dump_ed(ohci_soft_ed_t *); 187 void ohci_dump_itd(ohci_soft_itd_t *); 188 void ohci_dump_itds(ohci_soft_itd_t *); 189 #endif 190 191 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 192 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 193 #define OWRITE1(sc, r, x) \ 194 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 195 #define OWRITE2(sc, r, x) \ 196 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 197 #define OWRITE4(sc, r, x) \ 198 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 199 #define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->iot, (sc)->ioh, (r))) 200 #define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->iot, (sc)->ioh, (r))) 201 #define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->iot, (sc)->ioh, (r))) 202 203 /* Reverse the bits in a value 0 .. 31 */ 204 u_int8_t revbits[OHCI_NO_INTRS] = 205 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 206 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 207 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 208 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 209 210 struct ohci_pipe { 211 struct usbd_pipe pipe; 212 ohci_soft_ed_t *sed; 213 union { 214 ohci_soft_td_t *td; 215 ohci_soft_itd_t *itd; 216 } tail; 217 /* Info needed for different pipe kinds. */ 218 union { 219 /* Control pipe */ 220 struct { 221 usb_dma_t reqdma; 222 u_int length; 223 ohci_soft_td_t *setup, *data, *stat; 224 } ctl; 225 /* Interrupt pipe */ 226 struct { 227 int nslots; 228 int pos; 229 } intr; 230 /* Bulk pipe */ 231 struct { 232 u_int length; 233 int isread; 234 } bulk; 235 /* Iso pipe */ 236 struct iso { 237 int next, inuse; 238 } iso; 239 } u; 240 }; 241 242 #define OHCI_INTR_ENDPT 1 243 244 struct usbd_bus_methods ohci_bus_methods = { 245 ohci_open, 246 ohci_softintr, 247 ohci_poll, 248 ohci_allocm, 249 ohci_freem, 250 ohci_allocx, 251 ohci_freex, 252 }; 253 254 struct usbd_pipe_methods ohci_root_ctrl_methods = { 255 ohci_root_ctrl_transfer, 256 ohci_root_ctrl_start, 257 ohci_root_ctrl_abort, 258 ohci_root_ctrl_close, 259 ohci_noop, 260 ohci_root_ctrl_done, 261 }; 262 263 struct usbd_pipe_methods ohci_root_intr_methods = { 264 ohci_root_intr_transfer, 265 ohci_root_intr_start, 266 ohci_root_intr_abort, 267 ohci_root_intr_close, 268 ohci_noop, 269 ohci_root_intr_done, 270 }; 271 272 struct usbd_pipe_methods ohci_device_ctrl_methods = { 273 ohci_device_ctrl_transfer, 274 ohci_device_ctrl_start, 275 ohci_device_ctrl_abort, 276 ohci_device_ctrl_close, 277 ohci_noop, 278 ohci_device_ctrl_done, 279 }; 280 281 struct usbd_pipe_methods ohci_device_intr_methods = { 282 ohci_device_intr_transfer, 283 ohci_device_intr_start, 284 ohci_device_intr_abort, 285 ohci_device_intr_close, 286 ohci_device_clear_toggle, 287 ohci_device_intr_done, 288 }; 289 290 struct usbd_pipe_methods ohci_device_bulk_methods = { 291 ohci_device_bulk_transfer, 292 ohci_device_bulk_start, 293 ohci_device_bulk_abort, 294 ohci_device_bulk_close, 295 ohci_device_clear_toggle, 296 ohci_device_bulk_done, 297 }; 298 299 struct usbd_pipe_methods ohci_device_isoc_methods = { 300 ohci_device_isoc_transfer, 301 ohci_device_isoc_start, 302 ohci_device_isoc_abort, 303 ohci_device_isoc_close, 304 ohci_noop, 305 ohci_device_isoc_done, 306 }; 307 308 int 309 ohci_activate(struct device *self, int act) 310 { 311 struct ohci_softc *sc = (struct ohci_softc *)self; 312 int rv = 0; 313 314 switch (act) { 315 case DVACT_ACTIVATE: 316 break; 317 318 case DVACT_DEACTIVATE: 319 if (sc->sc_child != NULL) 320 rv = config_deactivate(sc->sc_child); 321 sc->sc_dying = 1; 322 break; 323 } 324 return (rv); 325 } 326 327 int 328 ohci_detach(struct ohci_softc *sc, int flags) 329 { 330 int rv = 0; 331 332 if (sc->sc_child != NULL) 333 rv = config_detach(sc->sc_child, flags); 334 335 if (rv != 0) 336 return (rv); 337 338 timeout_del(&sc->sc_tmo_rhsc); 339 340 if (sc->sc_shutdownhook != NULL) 341 shutdownhook_disestablish(sc->sc_shutdownhook); 342 343 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 344 345 /* free data structures XXX */ 346 347 return (rv); 348 } 349 350 ohci_soft_ed_t * 351 ohci_alloc_sed(ohci_softc_t *sc) 352 { 353 ohci_soft_ed_t *sed; 354 usbd_status err; 355 int i, offs; 356 usb_dma_t dma; 357 358 if (sc->sc_freeeds == NULL) { 359 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 360 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 361 OHCI_ED_ALIGN, &dma); 362 if (err) 363 return (0); 364 for(i = 0; i < OHCI_SED_CHUNK; i++) { 365 offs = i * OHCI_SED_SIZE; 366 sed = KERNADDR(&dma, offs); 367 sed->physaddr = DMAADDR(&dma, offs); 368 sed->next = sc->sc_freeeds; 369 sc->sc_freeeds = sed; 370 } 371 } 372 sed = sc->sc_freeeds; 373 sc->sc_freeeds = sed->next; 374 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 375 sed->next = 0; 376 return (sed); 377 } 378 379 void 380 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 381 { 382 sed->next = sc->sc_freeeds; 383 sc->sc_freeeds = sed; 384 } 385 386 ohci_soft_td_t * 387 ohci_alloc_std(ohci_softc_t *sc) 388 { 389 ohci_soft_td_t *std; 390 usbd_status err; 391 int i, offs; 392 usb_dma_t dma; 393 int s; 394 395 if (sc->sc_freetds == NULL) { 396 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 397 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 398 OHCI_TD_ALIGN, &dma); 399 if (err) 400 return (NULL); 401 s = splusb(); 402 for(i = 0; i < OHCI_STD_CHUNK; i++) { 403 offs = i * OHCI_STD_SIZE; 404 std = KERNADDR(&dma, offs); 405 std->physaddr = DMAADDR(&dma, offs); 406 std->nexttd = sc->sc_freetds; 407 sc->sc_freetds = std; 408 } 409 splx(s); 410 } 411 412 s = splusb(); 413 std = sc->sc_freetds; 414 sc->sc_freetds = std->nexttd; 415 memset(&std->td, 0, sizeof(ohci_td_t)); 416 std->nexttd = NULL; 417 std->xfer = NULL; 418 ohci_hash_add_td(sc, std); 419 splx(s); 420 421 return (std); 422 } 423 424 void 425 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 426 { 427 int s; 428 429 s = splusb(); 430 ohci_hash_rem_td(sc, std); 431 std->nexttd = sc->sc_freetds; 432 sc->sc_freetds = std; 433 splx(s); 434 } 435 436 usbd_status 437 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 438 u_int alen, int rd, usbd_xfer_handle xfer, 439 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 440 { 441 ohci_soft_td_t *next, *cur; 442 ohci_physaddr_t dataphys, dataphysend; 443 u_int32_t tdflags; 444 u_int len, curlen; 445 usb_dma_t *dma = &xfer->dmabuf; 446 u_int16_t flags = xfer->flags; 447 448 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%u\n", alen)); 449 450 len = alen; 451 cur = sp; 452 dataphys = DMAADDR(dma, 0); 453 dataphysend = OHCI_PAGE(dataphys + len - 1); 454 tdflags = htole32( 455 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 456 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 457 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 458 459 for (;;) { 460 next = ohci_alloc_std(sc); 461 if (next == NULL) 462 goto nomem; 463 464 /* The OHCI hardware can handle at most one page crossing. */ 465 if (OHCI_PAGE(dataphys) == dataphysend || 466 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 467 /* we can handle it in this TD */ 468 curlen = len; 469 } else { 470 /* must use multiple TDs, fill as much as possible. */ 471 curlen = 2 * OHCI_PAGE_SIZE - 472 (dataphys & (OHCI_PAGE_SIZE-1)); 473 /* the length must be a multiple of the max size */ 474 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 475 #ifdef DIAGNOSTIC 476 if (curlen == 0) 477 panic("ohci_alloc_std: curlen == 0"); 478 #endif 479 } 480 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 481 "dataphysend=0x%08x len=%u curlen=%u\n", 482 dataphys, dataphysend, 483 len, curlen)); 484 len -= curlen; 485 486 cur->td.td_flags = tdflags; 487 cur->td.td_cbp = htole32(dataphys); 488 cur->nexttd = next; 489 cur->td.td_nexttd = htole32(next->physaddr); 490 cur->td.td_be = htole32(dataphys + curlen - 1); 491 cur->len = curlen; 492 cur->flags = OHCI_ADD_LEN; 493 cur->xfer = xfer; 494 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 495 dataphys, dataphys + curlen - 1)); 496 if (len == 0) 497 break; 498 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 499 dataphys += curlen; 500 cur = next; 501 } 502 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 503 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 504 /* Force a 0 length transfer at the end. */ 505 506 cur = next; 507 next = ohci_alloc_std(sc); 508 if (next == NULL) 509 goto nomem; 510 511 cur->td.td_flags = tdflags; 512 cur->td.td_cbp = 0; /* indicate 0 length packet */ 513 cur->nexttd = next; 514 cur->td.td_nexttd = htole32(next->physaddr); 515 cur->td.td_be = ~0; 516 cur->len = 0; 517 cur->flags = 0; 518 cur->xfer = xfer; 519 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 520 } 521 *ep = cur; 522 523 return (USBD_NORMAL_COMPLETION); 524 525 nomem: 526 /* XXX free chain */ 527 return (USBD_NOMEM); 528 } 529 530 #if 0 531 void 532 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 533 ohci_soft_td_t *stdend) 534 { 535 ohci_soft_td_t *p; 536 537 for (; std != stdend; std = p) { 538 p = std->nexttd; 539 ohci_free_std(sc, std); 540 } 541 } 542 #endif 543 544 ohci_soft_itd_t * 545 ohci_alloc_sitd(ohci_softc_t *sc) 546 { 547 ohci_soft_itd_t *sitd; 548 usbd_status err; 549 int i, s, offs; 550 usb_dma_t dma; 551 552 if (sc->sc_freeitds == NULL) { 553 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 554 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 555 OHCI_ITD_ALIGN, &dma); 556 if (err) 557 return (NULL); 558 s = splusb(); 559 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 560 offs = i * OHCI_SITD_SIZE; 561 sitd = KERNADDR(&dma, offs); 562 sitd->physaddr = DMAADDR(&dma, offs); 563 sitd->nextitd = sc->sc_freeitds; 564 sc->sc_freeitds = sitd; 565 } 566 splx(s); 567 } 568 569 s = splusb(); 570 sitd = sc->sc_freeitds; 571 sc->sc_freeitds = sitd->nextitd; 572 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 573 sitd->nextitd = NULL; 574 sitd->xfer = NULL; 575 ohci_hash_add_itd(sc, sitd); 576 splx(s); 577 578 #ifdef DIAGNOSTIC 579 sitd->isdone = 0; 580 #endif 581 582 return (sitd); 583 } 584 585 void 586 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 587 { 588 int s; 589 590 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 591 592 #ifdef DIAGNOSTIC 593 if (!sitd->isdone) { 594 panic("ohci_free_sitd: sitd=%p not done", sitd); 595 return; 596 } 597 /* Warn double free */ 598 sitd->isdone = 0; 599 #endif 600 601 s = splusb(); 602 ohci_hash_rem_itd(sc, sitd); 603 sitd->nextitd = sc->sc_freeitds; 604 sc->sc_freeitds = sitd; 605 splx(s); 606 } 607 608 usbd_status 609 ohci_checkrev(ohci_softc_t *sc) 610 { 611 u_int32_t rev; 612 613 printf(","); 614 rev = OREAD4(sc, OHCI_REVISION); 615 printf(" version %d.%d%s\n", OHCI_REV_HI(rev), OHCI_REV_LO(rev), 616 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 617 618 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 619 printf("%s: unsupported OHCI revision\n", 620 sc->sc_bus.bdev.dv_xname); 621 sc->sc_bus.usbrev = USBREV_UNKNOWN; 622 return (USBD_INVAL); 623 } 624 sc->sc_bus.usbrev = USBREV_1_0; 625 626 return (USBD_NORMAL_COMPLETION); 627 } 628 629 usbd_status 630 ohci_handover(ohci_softc_t *sc) 631 { 632 u_int32_t s, ctl; 633 int i; 634 635 ctl = OREAD4(sc, OHCI_CONTROL); 636 if (ctl & OHCI_IR) { 637 /* SMM active, request change */ 638 DPRINTF(("ohci_handover: SMM active, request owner change\n")); 639 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 640 (OHCI_OC | OHCI_MIE)) 641 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 642 s = OREAD4(sc, OHCI_COMMAND_STATUS); 643 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 644 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 645 usb_delay_ms(&sc->sc_bus, 1); 646 ctl = OREAD4(sc, OHCI_CONTROL); 647 } 648 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 649 if (ctl & OHCI_IR) { 650 printf("%s: SMM does not respond, will reset\n", 651 sc->sc_bus.bdev.dv_xname); 652 } 653 } 654 655 return (USBD_NORMAL_COMPLETION); 656 } 657 658 usbd_status 659 ohci_init(ohci_softc_t *sc) 660 { 661 ohci_soft_ed_t *sed, *psed; 662 usbd_status err; 663 int i; 664 u_int32_t ctl, rwc, ival, hcr, fm, per, desca, descb; 665 666 DPRINTF(("ohci_init: start\n")); 667 668 for (i = 0; i < OHCI_HASH_SIZE; i++) 669 LIST_INIT(&sc->sc_hash_tds[i]); 670 for (i = 0; i < OHCI_HASH_SIZE; i++) 671 LIST_INIT(&sc->sc_hash_itds[i]); 672 673 SIMPLEQ_INIT(&sc->sc_free_xfers); 674 675 /* XXX determine alignment by R/W */ 676 /* Allocate the HCCA area. */ 677 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 678 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 679 if (err) 680 return (err); 681 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 682 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 683 684 sc->sc_eintrs = OHCI_NORMAL_INTRS; 685 686 /* Allocate dummy ED that starts the control list. */ 687 sc->sc_ctrl_head = ohci_alloc_sed(sc); 688 if (sc->sc_ctrl_head == NULL) { 689 err = USBD_NOMEM; 690 goto bad1; 691 } 692 sc->sc_ctrl_head->ed.ed_flags |= htole32(OHCI_ED_SKIP); 693 694 /* Allocate dummy ED that starts the bulk list. */ 695 sc->sc_bulk_head = ohci_alloc_sed(sc); 696 if (sc->sc_bulk_head == NULL) { 697 err = USBD_NOMEM; 698 goto bad2; 699 } 700 sc->sc_bulk_head->ed.ed_flags |= htole32(OHCI_ED_SKIP); 701 702 /* Allocate dummy ED that starts the isochronous list. */ 703 sc->sc_isoc_head = ohci_alloc_sed(sc); 704 if (sc->sc_isoc_head == NULL) { 705 err = USBD_NOMEM; 706 goto bad3; 707 } 708 sc->sc_isoc_head->ed.ed_flags |= htole32(OHCI_ED_SKIP); 709 710 /* Allocate all the dummy EDs that make up the interrupt tree. */ 711 for (i = 0; i < OHCI_NO_EDS; i++) { 712 sed = ohci_alloc_sed(sc); 713 if (sed == NULL) { 714 while (--i >= 0) 715 ohci_free_sed(sc, sc->sc_eds[i]); 716 err = USBD_NOMEM; 717 goto bad4; 718 } 719 /* All ED fields are set to 0. */ 720 sc->sc_eds[i] = sed; 721 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); 722 if (i != 0) 723 psed = sc->sc_eds[(i-1) / 2]; 724 else 725 psed= sc->sc_isoc_head; 726 sed->next = psed; 727 sed->ed.ed_nexted = htole32(psed->physaddr); 728 } 729 /* 730 * Fill HCCA interrupt table. The bit reversal is to get 731 * the tree set up properly to spread the interrupts. 732 */ 733 for (i = 0; i < OHCI_NO_INTRS; i++) 734 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 735 htole32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 736 737 #ifdef OHCI_DEBUG 738 if (ohcidebug > 15) { 739 for (i = 0; i < OHCI_NO_EDS; i++) { 740 printf("ed#%d ", i); 741 ohci_dump_ed(sc->sc_eds[i]); 742 } 743 printf("iso "); 744 ohci_dump_ed(sc->sc_isoc_head); 745 } 746 #endif 747 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 748 ctl = OREAD4(sc, OHCI_CONTROL); 749 rwc = ctl & OHCI_RWC; 750 fm = OREAD4(sc, OHCI_FM_INTERVAL); 751 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 752 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 753 754 /* Determine in what context we are running. */ 755 if (ctl & OHCI_IR) { 756 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 757 goto reset; 758 #if 0 759 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 760 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 761 /* BIOS started controller. */ 762 DPRINTF(("ohci_init: BIOS active\n")); 763 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 764 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 765 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 766 } 767 #endif 768 } else { 769 DPRINTF(("ohci_init: cold started\n")); 770 reset: 771 /* Controller was cold started. */ 772 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 773 } 774 775 /* 776 * This reset should not be necessary according to the OHCI spec, but 777 * without it some controllers do not start. 778 */ 779 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 780 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 781 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 782 783 /* We now own the host controller and the bus has been reset. */ 784 785 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 786 /* Nominal time for a reset is 10 us. */ 787 for (i = 0; i < 10; i++) { 788 delay(10); 789 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 790 if (!hcr) 791 break; 792 } 793 if (hcr) { 794 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 795 err = USBD_IOERROR; 796 goto bad5; 797 } 798 #ifdef OHCI_DEBUG 799 if (ohcidebug > 15) 800 ohci_dumpregs(sc); 801 #endif 802 803 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 804 805 /* Set up HC registers. */ 806 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 807 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 808 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 809 /* disable all interrupts and then switch on all desired interrupts */ 810 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 811 /* switch on desired functional features */ 812 ctl = OREAD4(sc, OHCI_CONTROL); 813 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 814 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 815 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 816 /* And finally start it! */ 817 OWRITE4(sc, OHCI_CONTROL, ctl); 818 819 /* 820 * The controller is now OPERATIONAL. Set a some final 821 * registers that should be set earlier, but that the 822 * controller ignores when in the SUSPEND state. 823 */ 824 ival = OHCI_GET_IVAL(fm); 825 fm = (OREAD4(sc, OHCI_FM_REMAINING) & OHCI_FIT) ^ OHCI_FIT; 826 fm |= OHCI_FSMPS(ival) | ival; 827 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 828 per = OHCI_PERIODIC(ival); /* 90% periodic */ 829 OWRITE4(sc, OHCI_PERIODIC_START, per); 830 831 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 832 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 833 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 834 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 835 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 836 OWRITE4(sc, OHCI_RH_DESCRIPTOR_B, descb); 837 usb_delay_ms(&sc->sc_bus, OHCI_GET_POTPGT(desca) * UHD_PWRON_FACTOR); 838 839 /* 840 * The AMD756 requires a delay before re-reading the register, 841 * otherwise it will occasionally report 0 ports. 842 */ 843 sc->sc_noport = 0; 844 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 845 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 846 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 847 } 848 849 #ifdef OHCI_DEBUG 850 if (ohcidebug > 5) 851 ohci_dumpregs(sc); 852 #endif 853 854 /* Set up the bus struct. */ 855 sc->sc_bus.methods = &ohci_bus_methods; 856 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 857 858 sc->sc_control = sc->sc_intre = 0; 859 sc->sc_shutdownhook = shutdownhook_establish(ohci_shutdown, sc); 860 861 timeout_set(&sc->sc_tmo_rhsc, ohci_rhsc_enable, sc); 862 863 /* Finally, turn on interrupts. */ 864 DPRINTFN(1,("ohci_init: enabling\n")); 865 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 866 867 return (USBD_NORMAL_COMPLETION); 868 869 bad5: 870 for (i = 0; i < OHCI_NO_EDS; i++) 871 ohci_free_sed(sc, sc->sc_eds[i]); 872 bad4: 873 ohci_free_sed(sc, sc->sc_isoc_head); 874 bad3: 875 ohci_free_sed(sc, sc->sc_bulk_head); 876 bad2: 877 ohci_free_sed(sc, sc->sc_ctrl_head); 878 bad1: 879 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 880 return (err); 881 } 882 883 usbd_status 884 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 885 { 886 struct ohci_softc *sc = (struct ohci_softc *)bus; 887 888 return (usb_allocmem(&sc->sc_bus, size, 0, dma)); 889 } 890 891 void 892 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 893 { 894 struct ohci_softc *sc = (struct ohci_softc *)bus; 895 896 usb_freemem(&sc->sc_bus, dma); 897 } 898 899 usbd_xfer_handle 900 ohci_allocx(struct usbd_bus *bus) 901 { 902 struct ohci_softc *sc = (struct ohci_softc *)bus; 903 usbd_xfer_handle xfer; 904 905 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 906 if (xfer != NULL) { 907 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 908 #ifdef DIAGNOSTIC 909 if (xfer->busy_free != XFER_FREE) { 910 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 911 xfer->busy_free); 912 } 913 #endif 914 } else { 915 xfer = malloc(sizeof(struct ohci_xfer), M_USB, M_NOWAIT); 916 } 917 if (xfer != NULL) { 918 memset(xfer, 0, sizeof (struct ohci_xfer)); 919 #ifdef DIAGNOSTIC 920 xfer->busy_free = XFER_BUSY; 921 #endif 922 } 923 return (xfer); 924 } 925 926 void 927 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 928 { 929 struct ohci_softc *sc = (struct ohci_softc *)bus; 930 931 #ifdef DIAGNOSTIC 932 if (xfer->busy_free != XFER_BUSY) { 933 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 934 xfer->busy_free); 935 return; 936 } 937 xfer->busy_free = XFER_FREE; 938 #endif 939 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 940 } 941 942 /* 943 * Shut down the controller when the system is going down. 944 */ 945 void 946 ohci_shutdown(void *v) 947 { 948 ohci_softc_t *sc = v; 949 950 DPRINTF(("ohci_shutdown: stopping the HC\n")); 951 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 952 } 953 954 /* 955 * Handle suspend/resume. 956 * 957 * We need to switch to polling mode here, because this routine is 958 * called from an interrupt context. This is all right since we 959 * are almost suspended anyway. 960 */ 961 void 962 ohci_power(int why, void *v) 963 { 964 ohci_softc_t *sc = v; 965 u_int32_t reg; 966 int s; 967 968 #ifdef OHCI_DEBUG 969 DPRINTF(("ohci_power: sc=%p, why=%d\n", sc, why)); 970 ohci_dumpregs(sc); 971 #endif 972 973 s = splhardusb(); 974 switch (why) { 975 case PWR_SUSPEND: 976 case PWR_STANDBY: 977 sc->sc_bus.use_polling++; 978 reg = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 979 if (sc->sc_control == 0) { 980 /* 981 * Preserve register values, in case that APM BIOS 982 * does not recover them. 983 */ 984 sc->sc_control = reg; 985 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 986 sc->sc_ival = OHCI_GET_IVAL(OREAD4(sc, 987 OHCI_FM_INTERVAL)); 988 } 989 reg |= OHCI_HCFS_SUSPEND; 990 OWRITE4(sc, OHCI_CONTROL, reg); 991 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 992 sc->sc_bus.use_polling--; 993 break; 994 case PWR_RESUME: 995 sc->sc_bus.use_polling++; 996 997 /* Some broken BIOSes do not recover these values */ 998 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 999 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 1000 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 1001 if (sc->sc_intre) 1002 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 1003 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 1004 if (sc->sc_control) 1005 reg = sc->sc_control; 1006 else 1007 reg = OREAD4(sc, OHCI_CONTROL); 1008 reg |= OHCI_HCFS_RESUME; 1009 OWRITE4(sc, OHCI_CONTROL, reg); 1010 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1011 reg = (reg & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1012 OWRITE4(sc, OHCI_CONTROL, reg); 1013 1014 reg = (OREAD4(sc, OHCI_FM_REMAINING) & OHCI_FIT) ^ OHCI_FIT; 1015 reg |= OHCI_FSMPS(sc->sc_ival) | sc->sc_ival; 1016 OWRITE4(sc, OHCI_FM_INTERVAL, reg); 1017 OWRITE4(sc, OHCI_PERIODIC_START, OHCI_PERIODIC(sc->sc_ival)); 1018 1019 /* Fiddle the No OverCurrent Protection to avoid a chip bug */ 1020 reg = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1021 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, reg | OHCI_NOCP); 1022 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1023 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1024 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, reg); 1025 1026 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1027 sc->sc_control = sc->sc_intre = sc->sc_ival = 0; 1028 sc->sc_bus.use_polling--; 1029 break; 1030 } 1031 splx(s); 1032 } 1033 1034 #ifdef OHCI_DEBUG 1035 void 1036 ohci_dumpregs(ohci_softc_t *sc) 1037 { 1038 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1039 OREAD4(sc, OHCI_REVISION), 1040 OREAD4(sc, OHCI_CONTROL), 1041 OREAD4(sc, OHCI_COMMAND_STATUS))); 1042 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1043 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1044 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1045 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1046 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1047 OREAD4(sc, OHCI_HCCA), 1048 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1049 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1050 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1051 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1052 OREAD4(sc, OHCI_BULK_HEAD_ED), 1053 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1054 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1055 OREAD4(sc, OHCI_DONE_HEAD), 1056 OREAD4(sc, OHCI_FM_INTERVAL), 1057 OREAD4(sc, OHCI_FM_REMAINING))); 1058 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1059 OREAD4(sc, OHCI_FM_NUMBER), 1060 OREAD4(sc, OHCI_PERIODIC_START), 1061 OREAD4(sc, OHCI_LS_THRESHOLD))); 1062 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1063 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1064 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1065 OREAD4(sc, OHCI_RH_STATUS))); 1066 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1067 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1068 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1069 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1070 letoh32(sc->sc_hcca->hcca_frame_number), 1071 letoh32(sc->sc_hcca->hcca_done_head))); 1072 } 1073 #endif 1074 1075 int ohci_intr1(ohci_softc_t *); 1076 1077 int 1078 ohci_intr(void *p) 1079 { 1080 ohci_softc_t *sc = p; 1081 1082 if (sc == NULL || sc->sc_dying) 1083 return (0); 1084 1085 /* If we get an interrupt while polling, then just ignore it. */ 1086 if (!cold && sc->sc_bus.use_polling) { 1087 #ifdef DIAGNOSTIC 1088 static struct timeval ohci_intr_tv; 1089 if ((OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) && 1090 usbd_ratecheck(&ohci_intr_tv)) 1091 DPRINTFN(16, 1092 ("ohci_intr: ignored interrupt while polling\n")); 1093 #endif 1094 return (0); 1095 } 1096 1097 return (ohci_intr1(sc)); 1098 } 1099 1100 int 1101 ohci_intr1(ohci_softc_t *sc) 1102 { 1103 u_int32_t intrs, eintrs; 1104 ohci_physaddr_t done; 1105 1106 DPRINTFN(14,("ohci_intr1: enter\n")); 1107 1108 /* In case the interrupt occurs before initialization has completed. */ 1109 if (sc == NULL || sc->sc_hcca == NULL) { 1110 #ifdef DIAGNOSTIC 1111 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1112 #endif 1113 return (0); 1114 } 1115 1116 intrs = 0; 1117 done = letoh32(sc->sc_hcca->hcca_done_head); 1118 if (done != 0) { 1119 if (done & ~OHCI_DONE_INTRS) 1120 intrs = OHCI_WDH; 1121 if (done & OHCI_DONE_INTRS) 1122 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1123 sc->sc_hcca->hcca_done_head = 0; 1124 } else { 1125 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1126 /* If we've flushed out a WDH then reread */ 1127 if (intrs & OHCI_WDH) { 1128 done = letoh32(sc->sc_hcca->hcca_done_head); 1129 sc->sc_hcca->hcca_done_head = 0; 1130 } 1131 } 1132 1133 if (intrs == 0xffffffff) { 1134 sc->sc_dying = 1; 1135 return (0); 1136 } 1137 1138 if (!intrs) 1139 return (0); 1140 1141 intrs &= ~OHCI_MIE; 1142 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 1143 eintrs = intrs & sc->sc_eintrs; 1144 if (!eintrs) 1145 return (0); 1146 1147 sc->sc_bus.intr_context++; 1148 sc->sc_bus.no_intrs++; 1149 DPRINTFN(7, ("ohci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 1150 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1151 (u_int)eintrs)); 1152 1153 if (eintrs & OHCI_SO) { 1154 sc->sc_overrun_cnt++; 1155 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1156 printf("%s: %u scheduling overruns\n", 1157 sc->sc_bus.bdev.dv_xname, sc->sc_overrun_cnt); 1158 sc->sc_overrun_cnt = 0; 1159 } 1160 /* XXX do what */ 1161 eintrs &= ~OHCI_SO; 1162 } 1163 if (eintrs & OHCI_WDH) { 1164 ohci_add_done(sc, done &~ OHCI_DONE_INTRS); 1165 usb_schedsoftintr(&sc->sc_bus); 1166 eintrs &= ~OHCI_WDH; 1167 } 1168 if (eintrs & OHCI_RD) { 1169 printf("%s: resume detect\n", sc->sc_bus.bdev.dv_xname); 1170 /* XXX process resume detect */ 1171 } 1172 if (eintrs & OHCI_UE) { 1173 printf("%s: unrecoverable error, controller halted\n", 1174 sc->sc_bus.bdev.dv_xname); 1175 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1176 /* XXX what else */ 1177 } 1178 if (eintrs & OHCI_RHSC) { 1179 ohci_rhsc(sc, sc->sc_intrxfer); 1180 /* 1181 * Disable RHSC interrupt for now, because it will be 1182 * on until the port has been reset. 1183 */ 1184 ohci_rhsc_able(sc, 0); 1185 DPRINTFN(2, ("%s: rhsc interrupt disabled\n", 1186 sc->sc_bus.bdev.dv_xname)); 1187 1188 /* Do not allow RHSC interrupts > 1 per second */ 1189 timeout_add_sec(&sc->sc_tmo_rhsc, 1); 1190 eintrs &= ~OHCI_RHSC; 1191 } 1192 1193 sc->sc_bus.intr_context--; 1194 1195 if (eintrs != 0) { 1196 /* Block unprocessed interrupts. XXX */ 1197 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1198 sc->sc_eintrs &= ~eintrs; 1199 printf("%s: blocking intrs 0x%x\n", 1200 sc->sc_bus.bdev.dv_xname, eintrs); 1201 } 1202 1203 return (1); 1204 } 1205 1206 void 1207 ohci_rhsc_able(ohci_softc_t *sc, int on) 1208 { 1209 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 1210 if (on) { 1211 sc->sc_eintrs |= OHCI_RHSC; 1212 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1213 } else { 1214 sc->sc_eintrs &= ~OHCI_RHSC; 1215 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1216 } 1217 } 1218 1219 void 1220 ohci_rhsc_enable(void *v_sc) 1221 { 1222 ohci_softc_t *sc = v_sc; 1223 int s; 1224 1225 s = splhardusb(); 1226 ohci_rhsc(sc, sc->sc_intrxfer); 1227 DPRINTFN(2, ("%s: rhsc interrupt enabled\n", 1228 sc->sc_bus.bdev.dv_xname)); 1229 1230 ohci_rhsc_able(sc, 1); 1231 splx(s); 1232 } 1233 1234 #ifdef OHCI_DEBUG 1235 char *ohci_cc_strs[] = { 1236 "NO_ERROR", 1237 "CRC", 1238 "BIT_STUFFING", 1239 "DATA_TOGGLE_MISMATCH", 1240 "STALL", 1241 "DEVICE_NOT_RESPONDING", 1242 "PID_CHECK_FAILURE", 1243 "UNEXPECTED_PID", 1244 "DATA_OVERRUN", 1245 "DATA_UNDERRUN", 1246 "BUFFER_OVERRUN", 1247 "BUFFER_UNDERRUN", 1248 "reserved", 1249 "reserved", 1250 "NOT_ACCESSED", 1251 "NOT_ACCESSED", 1252 }; 1253 #endif 1254 1255 void 1256 ohci_add_done(ohci_softc_t *sc, ohci_physaddr_t done) 1257 { 1258 ohci_soft_itd_t *sitd, *sidone, **ip; 1259 ohci_soft_td_t *std, *sdone, **p; 1260 1261 /* Reverse the done list. */ 1262 for (sdone = NULL, sidone = NULL; done != 0; ) { 1263 std = ohci_hash_find_td(sc, done); 1264 if (std != NULL) { 1265 std->dnext = sdone; 1266 done = letoh32(std->td.td_nexttd); 1267 sdone = std; 1268 DPRINTFN(10,("add TD %p\n", std)); 1269 continue; 1270 } 1271 sitd = ohci_hash_find_itd(sc, done); 1272 if (sitd != NULL) { 1273 sitd->dnext = sidone; 1274 done = letoh32(sitd->itd.itd_nextitd); 1275 sidone = sitd; 1276 DPRINTFN(5,("add ITD %p\n", sitd)); 1277 continue; 1278 } 1279 panic("ohci_add_done: addr 0x%08lx not found", (u_long)done); 1280 } 1281 1282 /* sdone & sidone now hold the done lists. */ 1283 /* Put them on the already processed lists. */ 1284 for (p = &sc->sc_sdone; *p != NULL; p = &(*p)->dnext) 1285 ; 1286 *p = sdone; 1287 for (ip = &sc->sc_sidone; *ip != NULL; ip = &(*ip)->dnext) 1288 ; 1289 *ip = sidone; 1290 } 1291 1292 void 1293 ohci_softintr(void *v) 1294 { 1295 ohci_softc_t *sc = v; 1296 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1297 ohci_soft_td_t *std, *sdone, *stdnext; 1298 usbd_xfer_handle xfer; 1299 struct ohci_pipe *opipe; 1300 int len, cc, s; 1301 int i, j, actlen, iframes, uedir; 1302 1303 DPRINTFN(10,("ohci_softintr: enter\n")); 1304 1305 sc->sc_bus.intr_context++; 1306 1307 s = splhardusb(); 1308 sdone = sc->sc_sdone; 1309 sc->sc_sdone = NULL; 1310 sidone = sc->sc_sidone; 1311 sc->sc_sidone = NULL; 1312 splx(s); 1313 1314 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1315 1316 #ifdef OHCI_DEBUG 1317 if (ohcidebug > 10) { 1318 DPRINTF(("ohci_process_done: TD done:\n")); 1319 ohci_dump_tds(sdone); 1320 } 1321 #endif 1322 1323 for (std = sdone; std; std = stdnext) { 1324 xfer = std->xfer; 1325 stdnext = std->dnext; 1326 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1327 std, xfer, xfer ? xfer->hcpriv : 0)); 1328 if (xfer == NULL) { 1329 /* 1330 * xfer == NULL: There seems to be no xfer associated 1331 * with this TD. It is tailp that happened to end up on 1332 * the done queue. 1333 * Shouldn't happen, but some chips are broken(?). 1334 */ 1335 continue; 1336 } 1337 if (xfer->status == USBD_CANCELLED || 1338 xfer->status == USBD_TIMEOUT) { 1339 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1340 xfer)); 1341 /* Handled by abort routine. */ 1342 continue; 1343 } 1344 timeout_del(&xfer->timeout_handle); 1345 1346 len = std->len; 1347 if (std->td.td_cbp != 0) 1348 len -= letoh32(std->td.td_be) - 1349 letoh32(std->td.td_cbp) + 1; 1350 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1351 std->flags)); 1352 if (std->flags & OHCI_ADD_LEN) 1353 xfer->actlen += len; 1354 1355 cc = OHCI_TD_GET_CC(letoh32(std->td.td_flags)); 1356 if (cc == OHCI_CC_NO_ERROR) { 1357 if (std->flags & OHCI_CALL_DONE) { 1358 xfer->status = USBD_NORMAL_COMPLETION; 1359 s = splusb(); 1360 usb_transfer_complete(xfer); 1361 splx(s); 1362 } 1363 ohci_free_std(sc, std); 1364 } else { 1365 /* 1366 * Endpoint is halted. First unlink all the TDs 1367 * belonging to the failed transfer, and then restart 1368 * the endpoint. 1369 */ 1370 ohci_soft_td_t *p, *n; 1371 opipe = (struct ohci_pipe *)xfer->pipe; 1372 1373 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1374 OHCI_TD_GET_CC(letoh32(std->td.td_flags)), 1375 ohci_cc_strs[OHCI_TD_GET_CC(letoh32(std->td.td_flags))])); 1376 1377 /* remove TDs */ 1378 for (p = std; p->xfer == xfer; p = n) { 1379 n = p->nexttd; 1380 ohci_free_std(sc, p); 1381 } 1382 1383 /* clear halt */ 1384 opipe->sed->ed.ed_headp = htole32(p->physaddr); 1385 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1386 1387 if (cc == OHCI_CC_STALL) 1388 xfer->status = USBD_STALLED; 1389 else 1390 xfer->status = USBD_IOERROR; 1391 s = splusb(); 1392 usb_transfer_complete(xfer); 1393 splx(s); 1394 } 1395 } 1396 1397 #ifdef OHCI_DEBUG 1398 if (ohcidebug > 10) { 1399 DPRINTF(("ohci_softintr: ITD done:\n")); 1400 ohci_dump_itds(sidone); 1401 } 1402 #endif 1403 1404 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1405 xfer = sitd->xfer; 1406 sitdnext = sitd->dnext; 1407 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1408 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1409 if (xfer == NULL) 1410 continue; 1411 if (xfer->status == USBD_CANCELLED || 1412 xfer->status == USBD_TIMEOUT) { 1413 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1414 xfer)); 1415 /* Handled by abort routine. */ 1416 continue; 1417 } 1418 #ifdef DIAGNOSTIC 1419 if (sitd->isdone) 1420 printf("ohci_softintr: sitd=%p is done\n", sitd); 1421 sitd->isdone = 1; 1422 #endif 1423 if (sitd->flags & OHCI_CALL_DONE) { 1424 ohci_soft_itd_t *next; 1425 1426 opipe = (struct ohci_pipe *)xfer->pipe; 1427 opipe->u.iso.inuse -= xfer->nframes; 1428 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1429 bEndpointAddress); 1430 xfer->status = USBD_NORMAL_COMPLETION; 1431 actlen = 0; 1432 for (i = 0, sitd = xfer->hcpriv;; 1433 sitd = next) { 1434 next = sitd->nextitd; 1435 if (OHCI_ITD_GET_CC(letoh32(sitd-> 1436 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1437 xfer->status = USBD_IOERROR; 1438 /* For input, update frlengths with actual */ 1439 /* XXX anything necessary for output? */ 1440 if (uedir == UE_DIR_IN && 1441 xfer->status == USBD_NORMAL_COMPLETION) { 1442 iframes = OHCI_ITD_GET_FC(letoh32( 1443 sitd->itd.itd_flags)); 1444 for (j = 0; j < iframes; i++, j++) { 1445 len = letoh16(sitd-> 1446 itd.itd_offset[j]); 1447 if ((OHCI_ITD_PSW_GET_CC(len) & 1448 OHCI_CC_NOT_ACCESSED_MASK) 1449 == OHCI_CC_NOT_ACCESSED) 1450 len = 0; 1451 else 1452 len = OHCI_ITD_PSW_LENGTH(len); 1453 xfer->frlengths[i] = len; 1454 actlen += len; 1455 } 1456 } 1457 if (sitd->flags & OHCI_CALL_DONE) 1458 break; 1459 ohci_free_sitd(sc, sitd); 1460 } 1461 ohci_free_sitd(sc, sitd); 1462 if (uedir == UE_DIR_IN && 1463 xfer->status == USBD_NORMAL_COMPLETION) 1464 xfer->actlen = actlen; 1465 xfer->hcpriv = NULL; 1466 1467 s = splusb(); 1468 usb_transfer_complete(xfer); 1469 splx(s); 1470 } 1471 } 1472 1473 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1474 if (sc->sc_softwake) { 1475 sc->sc_softwake = 0; 1476 wakeup(&sc->sc_softwake); 1477 } 1478 #endif /* __HAVE_GENERIC_SOFT_INTERRUPTS */ 1479 1480 sc->sc_bus.intr_context--; 1481 DPRINTFN(10,("ohci_softintr: done:\n")); 1482 } 1483 1484 void 1485 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1486 { 1487 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1488 1489 #ifdef DIAGNOSTIC 1490 if (!(xfer->rqflags & URQ_REQUEST)) { 1491 panic("ohci_device_ctrl_done: not a request"); 1492 } 1493 #endif 1494 } 1495 1496 void 1497 ohci_device_intr_done(usbd_xfer_handle xfer) 1498 { 1499 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1500 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1501 ohci_soft_ed_t *sed = opipe->sed; 1502 ohci_soft_td_t *data, *tail; 1503 1504 1505 DPRINTFN(10, ("ohci_device_intr_done: xfer=%p, actlen=%d\n", xfer, 1506 xfer->actlen)); 1507 1508 if (xfer->pipe->repeat) { 1509 data = opipe->tail.td; 1510 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1511 if (tail == NULL) { 1512 xfer->status = USBD_NOMEM; 1513 return; 1514 } 1515 tail->xfer = NULL; 1516 1517 data->td.td_flags = htole32( 1518 OHCI_TD_IN | OHCI_TD_NOCC | 1519 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1520 if (xfer->flags & USBD_SHORT_XFER_OK) 1521 data->td.td_flags |= htole32(OHCI_TD_R); 1522 data->td.td_cbp = htole32(DMAADDR(&xfer->dmabuf, 0)); 1523 data->nexttd = tail; 1524 data->td.td_nexttd = htole32(tail->physaddr); 1525 data->td.td_be = htole32(letoh32(data->td.td_cbp) + 1526 xfer->length - 1); 1527 data->len = xfer->length; 1528 data->xfer = xfer; 1529 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1530 xfer->hcpriv = data; 1531 xfer->actlen = 0; 1532 1533 sed->ed.ed_tailp = htole32(tail->physaddr); 1534 opipe->tail.td = tail; 1535 } 1536 } 1537 1538 void 1539 ohci_device_bulk_done(usbd_xfer_handle xfer) 1540 { 1541 DPRINTFN(10, ("ohci_device_bulk_done: xfer=%p, actlen=%d\n", xfer, 1542 xfer->actlen)); 1543 } 1544 1545 void 1546 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1547 { 1548 u_char *p; 1549 int i, m; 1550 int hstatus; 1551 1552 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1553 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1554 sc, xfer, hstatus)); 1555 1556 if (xfer == NULL) { 1557 /* Just ignore the change. */ 1558 return; 1559 } 1560 1561 p = KERNADDR(&xfer->dmabuf, 0); 1562 m = min(sc->sc_noport, xfer->length * 8 - 1); 1563 memset(p, 0, xfer->length); 1564 for (i = 1; i <= m; i++) { 1565 /* Pick out CHANGE bits from the status reg. */ 1566 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1567 p[i/8] |= 1 << (i%8); 1568 } 1569 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1570 xfer->actlen = xfer->length; 1571 xfer->status = USBD_NORMAL_COMPLETION; 1572 1573 usb_transfer_complete(xfer); 1574 } 1575 1576 void 1577 ohci_root_intr_done(usbd_xfer_handle xfer) 1578 { 1579 } 1580 1581 void 1582 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1583 { 1584 } 1585 1586 /* 1587 * Wait here until controller claims to have an interrupt. 1588 * Then call ohci_intr and return. Use timeout to avoid waiting 1589 * too long. 1590 */ 1591 void 1592 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1593 { 1594 int timo; 1595 u_int32_t intrs; 1596 1597 xfer->status = USBD_IN_PROGRESS; 1598 for (timo = xfer->timeout; timo >= 0; timo--) { 1599 usb_delay_ms(&sc->sc_bus, 1); 1600 if (sc->sc_dying) 1601 break; 1602 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1603 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1604 #ifdef OHCI_DEBUG 1605 if (ohcidebug > 15) 1606 ohci_dumpregs(sc); 1607 #endif 1608 if (intrs) { 1609 ohci_intr1(sc); 1610 if (xfer->status != USBD_IN_PROGRESS) 1611 return; 1612 } 1613 } 1614 1615 /* Timeout */ 1616 DPRINTF(("ohci_waitintr: timeout\n")); 1617 xfer->status = USBD_TIMEOUT; 1618 usb_transfer_complete(xfer); 1619 /* XXX should free TD */ 1620 } 1621 1622 void 1623 ohci_poll(struct usbd_bus *bus) 1624 { 1625 ohci_softc_t *sc = (ohci_softc_t *)bus; 1626 #ifdef OHCI_DEBUG 1627 static int last; 1628 int new; 1629 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1630 if (new != last) { 1631 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1632 last = new; 1633 } 1634 #endif 1635 1636 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 1637 ohci_intr1(sc); 1638 } 1639 1640 usbd_status 1641 ohci_device_request(usbd_xfer_handle xfer) 1642 { 1643 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1644 usb_device_request_t *req = &xfer->request; 1645 usbd_device_handle dev = opipe->pipe.device; 1646 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1647 int addr = dev->address; 1648 ohci_soft_td_t *setup, *stat, *next, *tail; 1649 ohci_soft_ed_t *sed; 1650 int isread; 1651 u_int len; 1652 usbd_status err; 1653 int s; 1654 1655 isread = req->bmRequestType & UT_READ; 1656 len = UGETW(req->wLength); 1657 1658 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1659 "wValue=0x%04x, wIndex=0x%04x len=%u, addr=%d, endpt=%d\n", 1660 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1661 UGETW(req->wIndex), len, addr, 1662 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1663 1664 setup = opipe->tail.td; 1665 stat = ohci_alloc_std(sc); 1666 if (stat == NULL) { 1667 err = USBD_NOMEM; 1668 goto bad1; 1669 } 1670 tail = ohci_alloc_std(sc); 1671 if (tail == NULL) { 1672 err = USBD_NOMEM; 1673 goto bad2; 1674 } 1675 tail->xfer = NULL; 1676 1677 sed = opipe->sed; 1678 opipe->u.ctl.length = len; 1679 1680 /* Update device address and length since they may have changed 1681 during the setup of the control pipe in usbd_new_device(). */ 1682 /* XXX This only needs to be done once, but it's too early in open. */ 1683 /* XXXX Should not touch ED here! */ 1684 sed->ed.ed_flags = htole32( 1685 (letoh32(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1686 OHCI_ED_SET_FA(addr) | 1687 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1688 1689 next = stat; 1690 1691 /* Set up data transaction */ 1692 if (len != 0) { 1693 ohci_soft_td_t *std = stat; 1694 1695 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1696 std, &stat); 1697 stat = stat->nexttd; /* point at free TD */ 1698 if (err) 1699 goto bad3; 1700 /* Start toggle at 1 and then use the carried toggle. */ 1701 std->td.td_flags &= htole32(~OHCI_TD_TOGGLE_MASK); 1702 std->td.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1703 } 1704 1705 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1706 1707 setup->td.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1708 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1709 setup->td.td_cbp = htole32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1710 setup->nexttd = next; 1711 setup->td.td_nexttd = htole32(next->physaddr); 1712 setup->td.td_be = htole32(letoh32(setup->td.td_cbp) + sizeof *req - 1); 1713 setup->len = 0; 1714 setup->xfer = xfer; 1715 setup->flags = 0; 1716 xfer->hcpriv = setup; 1717 1718 stat->td.td_flags = htole32( 1719 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1720 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1721 stat->td.td_cbp = 0; 1722 stat->nexttd = tail; 1723 stat->td.td_nexttd = htole32(tail->physaddr); 1724 stat->td.td_be = 0; 1725 stat->flags = OHCI_CALL_DONE; 1726 stat->len = 0; 1727 stat->xfer = xfer; 1728 1729 #ifdef OHCI_DEBUG 1730 if (ohcidebug > 5) { 1731 DPRINTF(("ohci_device_request:\n")); 1732 ohci_dump_ed(sed); 1733 ohci_dump_tds(setup); 1734 } 1735 #endif 1736 1737 /* Insert ED in schedule */ 1738 s = splusb(); 1739 sed->ed.ed_tailp = htole32(tail->physaddr); 1740 opipe->tail.td = tail; 1741 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1742 if (xfer->timeout && !sc->sc_bus.use_polling) { 1743 timeout_del(&xfer->timeout_handle); 1744 timeout_set(&xfer->timeout_handle, ohci_timeout, xfer); 1745 timeout_add(&xfer->timeout_handle, mstohz(xfer->timeout)); 1746 } 1747 splx(s); 1748 1749 #ifdef OHCI_DEBUG 1750 if (ohcidebug > 20) { 1751 delay(10000); 1752 DPRINTF(("ohci_device_request: status=%x\n", 1753 OREAD4(sc, OHCI_COMMAND_STATUS))); 1754 ohci_dumpregs(sc); 1755 printf("ctrl head:\n"); 1756 ohci_dump_ed(sc->sc_ctrl_head); 1757 printf("sed:\n"); 1758 ohci_dump_ed(sed); 1759 ohci_dump_tds(setup); 1760 } 1761 #endif 1762 1763 return (USBD_NORMAL_COMPLETION); 1764 1765 bad3: 1766 ohci_free_std(sc, tail); 1767 bad2: 1768 ohci_free_std(sc, stat); 1769 bad1: 1770 return (err); 1771 } 1772 1773 /* 1774 * Add an ED to the schedule. Called at splusb(). 1775 */ 1776 void 1777 ohci_add_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1778 { 1779 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1780 1781 SPLUSBCHECK; 1782 sed->next = head->next; 1783 sed->ed.ed_nexted = head->ed.ed_nexted; 1784 head->next = sed; 1785 head->ed.ed_nexted = htole32(sed->physaddr); 1786 } 1787 1788 /* 1789 * Remove an ED from the schedule. Called at splusb(). 1790 */ 1791 void 1792 ohci_rem_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1793 { 1794 ohci_soft_ed_t *p; 1795 1796 SPLUSBCHECK; 1797 1798 /* XXX */ 1799 for (p = head; p != NULL && p->next != sed; p = p->next) 1800 ; 1801 if (p == NULL) 1802 panic("ohci_rem_ed: ED not found"); 1803 p->next = sed->next; 1804 p->ed.ed_nexted = sed->ed.ed_nexted; 1805 } 1806 1807 /* 1808 * When a transfer is completed the TD is added to the done queue by 1809 * the host controller. This queue is the processed by software. 1810 * Unfortunately the queue contains the physical address of the TD 1811 * and we have no simple way to translate this back to a kernel address. 1812 * To make the translation possible (and fast) we use a hash table of 1813 * TDs currently in the schedule. The physical address is used as the 1814 * hash value. 1815 */ 1816 1817 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1818 /* Called at splusb() */ 1819 void 1820 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1821 { 1822 int h = HASH(std->physaddr); 1823 1824 SPLUSBCHECK; 1825 1826 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1827 } 1828 1829 /* Called at splusb() */ 1830 void 1831 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1832 { 1833 SPLUSBCHECK; 1834 1835 LIST_REMOVE(std, hnext); 1836 } 1837 1838 ohci_soft_td_t * 1839 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1840 { 1841 int h = HASH(a); 1842 ohci_soft_td_t *std; 1843 1844 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1845 std != NULL; 1846 std = LIST_NEXT(std, hnext)) 1847 if (std->physaddr == a) 1848 return (std); 1849 return (NULL); 1850 } 1851 1852 /* Called at splusb() */ 1853 void 1854 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1855 { 1856 int h = HASH(sitd->physaddr); 1857 1858 SPLUSBCHECK; 1859 1860 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1861 sitd, (u_long)sitd->physaddr)); 1862 1863 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1864 } 1865 1866 /* Called at splusb() */ 1867 void 1868 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1869 { 1870 SPLUSBCHECK; 1871 1872 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1873 sitd, (u_long)sitd->physaddr)); 1874 1875 LIST_REMOVE(sitd, hnext); 1876 } 1877 1878 ohci_soft_itd_t * 1879 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1880 { 1881 int h = HASH(a); 1882 ohci_soft_itd_t *sitd; 1883 1884 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1885 sitd != NULL; 1886 sitd = LIST_NEXT(sitd, hnext)) 1887 if (sitd->physaddr == a) 1888 return (sitd); 1889 return (NULL); 1890 } 1891 1892 void 1893 ohci_timeout(void *addr) 1894 { 1895 struct ohci_xfer *oxfer = addr; 1896 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1897 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1898 1899 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1900 1901 if (sc->sc_dying) { 1902 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1903 return; 1904 } 1905 1906 /* Execute the abort in a process context. */ 1907 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr); 1908 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task); 1909 } 1910 1911 void 1912 ohci_timeout_task(void *addr) 1913 { 1914 usbd_xfer_handle xfer = addr; 1915 int s; 1916 1917 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1918 1919 s = splusb(); 1920 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1921 splx(s); 1922 } 1923 1924 #ifdef OHCI_DEBUG 1925 void 1926 ohci_dump_tds(ohci_soft_td_t *std) 1927 { 1928 for (; std; std = std->nexttd) 1929 ohci_dump_td(std); 1930 } 1931 1932 void 1933 ohci_dump_td(ohci_soft_td_t *std) 1934 { 1935 char sbuf[128]; 1936 1937 bitmask_snprintf((u_int32_t)letoh32(std->td.td_flags), 1938 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1939 sbuf, sizeof(sbuf)); 1940 1941 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1942 "nexttd=0x%08lx be=0x%08lx\n", 1943 std, (u_long)std->physaddr, sbuf, 1944 OHCI_TD_GET_DI(letoh32(std->td.td_flags)), 1945 OHCI_TD_GET_EC(letoh32(std->td.td_flags)), 1946 OHCI_TD_GET_CC(letoh32(std->td.td_flags)), 1947 (u_long)letoh32(std->td.td_cbp), 1948 (u_long)letoh32(std->td.td_nexttd), 1949 (u_long)letoh32(std->td.td_be)); 1950 } 1951 1952 void 1953 ohci_dump_itd(ohci_soft_itd_t *sitd) 1954 { 1955 int i; 1956 1957 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 1958 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 1959 sitd, (u_long)sitd->physaddr, 1960 OHCI_ITD_GET_SF(letoh32(sitd->itd.itd_flags)), 1961 OHCI_ITD_GET_DI(letoh32(sitd->itd.itd_flags)), 1962 OHCI_ITD_GET_FC(letoh32(sitd->itd.itd_flags)), 1963 OHCI_ITD_GET_CC(letoh32(sitd->itd.itd_flags)), 1964 (u_long)letoh32(sitd->itd.itd_bp0), 1965 (u_long)letoh32(sitd->itd.itd_nextitd), 1966 (u_long)letoh32(sitd->itd.itd_be)); 1967 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 1968 printf("offs[%d]=0x%04x ", i, 1969 (u_int)letoh16(sitd->itd.itd_offset[i])); 1970 printf("\n"); 1971 } 1972 1973 void 1974 ohci_dump_itds(ohci_soft_itd_t *sitd) 1975 { 1976 for (; sitd; sitd = sitd->nextitd) 1977 ohci_dump_itd(sitd); 1978 } 1979 1980 void 1981 ohci_dump_ed(ohci_soft_ed_t *sed) 1982 { 1983 char sbuf[128], sbuf2[128]; 1984 1985 bitmask_snprintf((u_int32_t)letoh32(sed->ed.ed_flags), 1986 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 1987 sbuf, sizeof(sbuf)); 1988 bitmask_snprintf((u_int32_t)letoh32(sed->ed.ed_headp), 1989 "\20\1HALT\2CARRY", sbuf2, sizeof(sbuf2)); 1990 1991 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\n" 1992 "tailp=0x%08lx headflags=%s headp=0x%08lx nexted=0x%08lx\n", 1993 sed, (u_long)sed->physaddr, 1994 OHCI_ED_GET_FA(letoh32(sed->ed.ed_flags)), 1995 OHCI_ED_GET_EN(letoh32(sed->ed.ed_flags)), 1996 OHCI_ED_GET_MAXP(letoh32(sed->ed.ed_flags)), sbuf, 1997 (u_long)letoh32(sed->ed.ed_tailp), sbuf2, 1998 (u_long)letoh32(sed->ed.ed_headp), 1999 (u_long)letoh32(sed->ed.ed_nexted)); 2000 } 2001 #endif 2002 2003 usbd_status 2004 ohci_open(usbd_pipe_handle pipe) 2005 { 2006 usbd_device_handle dev = pipe->device; 2007 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2008 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2009 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2010 u_int8_t addr = dev->address; 2011 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2012 ohci_soft_ed_t *sed; 2013 ohci_soft_td_t *std; 2014 ohci_soft_itd_t *sitd; 2015 ohci_physaddr_t tdphys; 2016 u_int32_t fmt; 2017 usbd_status err; 2018 int s; 2019 int ival; 2020 2021 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2022 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2023 2024 if (sc->sc_dying) 2025 return (USBD_IOERROR); 2026 2027 std = NULL; 2028 sed = NULL; 2029 2030 if (addr == sc->sc_addr) { 2031 switch (ed->bEndpointAddress) { 2032 case USB_CONTROL_ENDPOINT: 2033 pipe->methods = &ohci_root_ctrl_methods; 2034 break; 2035 case UE_DIR_IN | OHCI_INTR_ENDPT: 2036 pipe->methods = &ohci_root_intr_methods; 2037 break; 2038 default: 2039 return (USBD_INVAL); 2040 } 2041 } else { 2042 sed = ohci_alloc_sed(sc); 2043 if (sed == NULL) 2044 goto bad0; 2045 opipe->sed = sed; 2046 if (xfertype == UE_ISOCHRONOUS) { 2047 sitd = ohci_alloc_sitd(sc); 2048 if (sitd == NULL) 2049 goto bad1; 2050 opipe->tail.itd = sitd; 2051 tdphys = sitd->physaddr; 2052 fmt = OHCI_ED_FORMAT_ISO; 2053 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2054 fmt |= OHCI_ED_DIR_IN; 2055 else 2056 fmt |= OHCI_ED_DIR_OUT; 2057 } else { 2058 std = ohci_alloc_std(sc); 2059 if (std == NULL) 2060 goto bad1; 2061 opipe->tail.td = std; 2062 tdphys = std->physaddr; 2063 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2064 } 2065 sed->ed.ed_flags = htole32( 2066 OHCI_ED_SET_FA(addr) | 2067 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2068 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2069 fmt | OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2070 sed->ed.ed_headp = htole32(tdphys | 2071 (pipe->endpoint->savedtoggle ? OHCI_TOGGLECARRY : 0)); 2072 sed->ed.ed_tailp = htole32(tdphys); 2073 2074 switch (xfertype) { 2075 case UE_CONTROL: 2076 pipe->methods = &ohci_device_ctrl_methods; 2077 err = usb_allocmem(&sc->sc_bus, 2078 sizeof(usb_device_request_t), 2079 0, &opipe->u.ctl.reqdma); 2080 if (err) 2081 goto bad; 2082 s = splusb(); 2083 ohci_add_ed(sed, sc->sc_ctrl_head); 2084 splx(s); 2085 break; 2086 case UE_INTERRUPT: 2087 pipe->methods = &ohci_device_intr_methods; 2088 ival = pipe->interval; 2089 if (ival == USBD_DEFAULT_INTERVAL) 2090 ival = ed->bInterval; 2091 return (ohci_device_setintr(sc, opipe, ival)); 2092 case UE_ISOCHRONOUS: 2093 pipe->methods = &ohci_device_isoc_methods; 2094 return (ohci_setup_isoc(pipe)); 2095 case UE_BULK: 2096 pipe->methods = &ohci_device_bulk_methods; 2097 s = splusb(); 2098 ohci_add_ed(sed, sc->sc_bulk_head); 2099 splx(s); 2100 break; 2101 } 2102 } 2103 return (USBD_NORMAL_COMPLETION); 2104 2105 bad: 2106 if (std != NULL) 2107 ohci_free_std(sc, std); 2108 bad1: 2109 if (sed != NULL) 2110 ohci_free_sed(sc, sed); 2111 bad0: 2112 return (USBD_NOMEM); 2113 2114 } 2115 2116 /* 2117 * Close a reqular pipe. 2118 * Assumes that there are no pending transactions. 2119 */ 2120 void 2121 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2122 { 2123 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2124 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2125 ohci_soft_ed_t *sed = opipe->sed; 2126 int s; 2127 2128 s = splusb(); 2129 #ifdef DIAGNOSTIC 2130 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); 2131 if ((letoh32(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2132 (letoh32(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2133 ohci_soft_td_t *std; 2134 std = ohci_hash_find_td(sc, letoh32(sed->ed.ed_headp)); 2135 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2136 "tl=0x%x pipe=%p, std=%p\n", sed, 2137 (int)letoh32(sed->ed.ed_headp), 2138 (int)letoh32(sed->ed.ed_tailp), 2139 pipe, std); 2140 #ifdef USB_DEBUG 2141 usbd_dump_pipe(&opipe->pipe); 2142 #endif 2143 #ifdef OHCI_DEBUG 2144 ohci_dump_ed(sed); 2145 if (std) 2146 ohci_dump_td(std); 2147 #endif 2148 usb_delay_ms(&sc->sc_bus, 2); 2149 if ((letoh32(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2150 (letoh32(sed->ed.ed_headp) & OHCI_HEADMASK)) 2151 printf("ohci_close_pipe: pipe still not empty\n"); 2152 } 2153 #endif 2154 ohci_rem_ed(sed, head); 2155 /* Make sure the host controller is not touching this ED */ 2156 usb_delay_ms(&sc->sc_bus, 1); 2157 splx(s); 2158 pipe->endpoint->savedtoggle = 2159 (letoh32(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2160 ohci_free_sed(sc, opipe->sed); 2161 } 2162 2163 /* 2164 * Abort a device request. 2165 * If this routine is called at splusb() it guarantees that the request 2166 * will be removed from the hardware scheduling and that the callback 2167 * for it will be called with USBD_CANCELLED status. 2168 * It's impossible to guarantee that the requested transfer will not 2169 * have happened since the hardware runs concurrently. 2170 * If the transaction has already happened we rely on the ordinary 2171 * interrupt processing to process it. 2172 */ 2173 void 2174 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2175 { 2176 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2177 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2178 ohci_soft_ed_t *sed = opipe->sed; 2179 ohci_soft_td_t *p, *n; 2180 ohci_physaddr_t headp; 2181 int s, hit; 2182 2183 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe, 2184 sed)); 2185 2186 if (sc->sc_dying) { 2187 /* If we're dying, just do the software part. */ 2188 s = splusb(); 2189 xfer->status = status; /* make software ignore it */ 2190 timeout_del(&xfer->timeout_handle); 2191 usb_transfer_complete(xfer); 2192 splx(s); 2193 return; 2194 } 2195 2196 if (xfer->device->bus->intr_context || !curproc) 2197 panic("ohci_abort_xfer: not in process context"); 2198 2199 /* 2200 * Step 1: Make interrupt routine and hardware ignore xfer. 2201 */ 2202 s = splusb(); 2203 xfer->status = status; /* make software ignore it */ 2204 timeout_del(&xfer->timeout_handle); 2205 splx(s); 2206 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2207 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); /* force hardware skip */ 2208 2209 /* 2210 * Step 2: Wait until we know hardware has finished any possible 2211 * use of the xfer. Also make sure the soft interrupt routine 2212 * has run. 2213 */ 2214 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2215 s = splusb(); 2216 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 2217 sc->sc_softwake = 1; 2218 #endif /* __HAVE_GENERIC_SOFT_INTERRUPTS */ 2219 usb_schedsoftintr(&sc->sc_bus); 2220 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 2221 tsleep(&sc->sc_softwake, PZERO, "ohciab", 0); 2222 #endif /* __HAVE_GENERIC_SOFT_INTERRUPTS */ 2223 splx(s); 2224 2225 /* 2226 * Step 3: Remove any vestiges of the xfer from the hardware. 2227 * The complication here is that the hardware may have executed 2228 * beyond the xfer we're trying to abort. So as we're scanning 2229 * the TDs of this xfer we check if the hardware points to 2230 * any of them. 2231 */ 2232 s = splusb(); /* XXX why? */ 2233 p = xfer->hcpriv; 2234 #ifdef DIAGNOSTIC 2235 if (p == NULL) { 2236 splx(s); 2237 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2238 return; 2239 } 2240 #endif 2241 #ifdef OHCI_DEBUG 2242 if (ohcidebug > 1) { 2243 DPRINTF(("ohci_abort_xfer: sed=\n")); 2244 ohci_dump_ed(sed); 2245 ohci_dump_tds(p); 2246 } 2247 #endif 2248 headp = letoh32(sed->ed.ed_headp) & OHCI_HEADMASK; 2249 hit = 0; 2250 for (; p->xfer == xfer; p = n) { 2251 hit |= headp == p->physaddr; 2252 n = p->nexttd; 2253 if (OHCI_TD_GET_CC(letoh32(p->td.td_flags)) == 2254 OHCI_CC_NOT_ACCESSED) 2255 ohci_free_std(sc, p); 2256 } 2257 /* Zap headp register if hardware pointed inside the xfer. */ 2258 if (hit) { 2259 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2260 (int)p->physaddr, (int)letoh32(sed->ed.ed_tailp))); 2261 sed->ed.ed_headp = htole32(p->physaddr); /* unlink TDs */ 2262 } else { 2263 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2264 } 2265 2266 /* 2267 * Step 4: Turn on hardware again. 2268 */ 2269 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); /* remove hardware skip */ 2270 2271 /* 2272 * Step 5: Execute callback. 2273 */ 2274 usb_transfer_complete(xfer); 2275 2276 splx(s); 2277 } 2278 2279 /* 2280 * Data structures and routines to emulate the root hub. 2281 */ 2282 usb_device_descriptor_t ohci_devd = { 2283 USB_DEVICE_DESCRIPTOR_SIZE, 2284 UDESC_DEVICE, /* type */ 2285 {0x00, 0x01}, /* USB version */ 2286 UDCLASS_HUB, /* class */ 2287 UDSUBCLASS_HUB, /* subclass */ 2288 UDPROTO_FSHUB, 2289 64, /* max packet */ 2290 {0},{0},{0x00,0x01}, /* device id */ 2291 1,2,0, /* string indices */ 2292 1 /* # of configurations */ 2293 }; 2294 2295 usb_config_descriptor_t ohci_confd = { 2296 USB_CONFIG_DESCRIPTOR_SIZE, 2297 UDESC_CONFIG, 2298 {USB_CONFIG_DESCRIPTOR_SIZE + 2299 USB_INTERFACE_DESCRIPTOR_SIZE + 2300 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2301 1, 2302 1, 2303 0, 2304 UC_SELF_POWERED, 2305 0 /* max power */ 2306 }; 2307 2308 usb_interface_descriptor_t ohci_ifcd = { 2309 USB_INTERFACE_DESCRIPTOR_SIZE, 2310 UDESC_INTERFACE, 2311 0, 2312 0, 2313 1, 2314 UICLASS_HUB, 2315 UISUBCLASS_HUB, 2316 UIPROTO_FSHUB, 2317 0 2318 }; 2319 2320 usb_endpoint_descriptor_t ohci_endpd = { 2321 USB_ENDPOINT_DESCRIPTOR_SIZE, 2322 UDESC_ENDPOINT, 2323 UE_DIR_IN | OHCI_INTR_ENDPT, 2324 UE_INTERRUPT, 2325 {8, 0}, /* max packet */ 2326 255 2327 }; 2328 2329 usb_hub_descriptor_t ohci_hubd = { 2330 USB_HUB_DESCRIPTOR_SIZE, 2331 UDESC_HUB, 2332 0, 2333 {0,0}, 2334 0, 2335 0, 2336 {0}, 2337 }; 2338 2339 int 2340 ohci_str(usb_string_descriptor_t *p, int l, const char *s) 2341 { 2342 int i; 2343 2344 if (l == 0) 2345 return (0); 2346 p->bLength = 2 * strlen(s) + 2; 2347 if (l == 1) 2348 return (1); 2349 p->bDescriptorType = UDESC_STRING; 2350 l -= 2; 2351 for (i = 0; s[i] && l > 1; i++, l -= 2) 2352 USETW2(p->bString[i], 0, s[i]); 2353 return (2*i+2); 2354 } 2355 2356 /* 2357 * Simulate a hardware hub by handling all the necessary requests. 2358 */ 2359 usbd_status 2360 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2361 { 2362 usbd_status err; 2363 2364 /* Insert last in queue. */ 2365 err = usb_insert_transfer(xfer); 2366 if (err) 2367 return (err); 2368 2369 /* Pipe isn't running, start first */ 2370 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2371 } 2372 2373 usbd_status 2374 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2375 { 2376 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 2377 usb_device_request_t *req; 2378 void *buf = NULL; 2379 int port, i; 2380 int s, len, value, index, l, totlen = 0; 2381 usb_port_status_t ps; 2382 usb_hub_descriptor_t hubd; 2383 usbd_status err; 2384 u_int32_t v; 2385 2386 if (sc->sc_dying) 2387 return (USBD_IOERROR); 2388 2389 #ifdef DIAGNOSTIC 2390 if (!(xfer->rqflags & URQ_REQUEST)) 2391 /* XXX panic */ 2392 return (USBD_INVAL); 2393 #endif 2394 req = &xfer->request; 2395 2396 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2397 req->bmRequestType, req->bRequest)); 2398 2399 len = UGETW(req->wLength); 2400 value = UGETW(req->wValue); 2401 index = UGETW(req->wIndex); 2402 2403 if (len != 0) 2404 buf = KERNADDR(&xfer->dmabuf, 0); 2405 2406 #define C(x,y) ((x) | ((y) << 8)) 2407 switch(C(req->bRequest, req->bmRequestType)) { 2408 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2409 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2410 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2411 /* 2412 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2413 * for the integrated root hub. 2414 */ 2415 break; 2416 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2417 if (len > 0) { 2418 *(u_int8_t *)buf = sc->sc_conf; 2419 totlen = 1; 2420 } 2421 break; 2422 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2423 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2424 switch(value >> 8) { 2425 case UDESC_DEVICE: 2426 if ((value & 0xff) != 0) { 2427 err = USBD_IOERROR; 2428 goto ret; 2429 } 2430 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2431 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2432 memcpy(buf, &ohci_devd, l); 2433 break; 2434 case UDESC_CONFIG: 2435 if ((value & 0xff) != 0) { 2436 err = USBD_IOERROR; 2437 goto ret; 2438 } 2439 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2440 memcpy(buf, &ohci_confd, l); 2441 buf = (char *)buf + l; 2442 len -= l; 2443 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2444 totlen += l; 2445 memcpy(buf, &ohci_ifcd, l); 2446 buf = (char *)buf + l; 2447 len -= l; 2448 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2449 totlen += l; 2450 memcpy(buf, &ohci_endpd, l); 2451 break; 2452 case UDESC_STRING: 2453 if (len == 0) 2454 break; 2455 *(u_int8_t *)buf = 0; 2456 totlen = 1; 2457 switch (value & 0xff) { 2458 case 0: /* Language table */ 2459 totlen = ohci_str(buf, len, "\001"); 2460 break; 2461 case 1: /* Vendor */ 2462 totlen = ohci_str(buf, len, sc->sc_vendor); 2463 break; 2464 case 2: /* Product */ 2465 totlen = ohci_str(buf, len, "OHCI root hub"); 2466 break; 2467 } 2468 break; 2469 default: 2470 err = USBD_IOERROR; 2471 goto ret; 2472 } 2473 break; 2474 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2475 if (len > 0) { 2476 *(u_int8_t *)buf = 0; 2477 totlen = 1; 2478 } 2479 break; 2480 case C(UR_GET_STATUS, UT_READ_DEVICE): 2481 if (len > 1) { 2482 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2483 totlen = 2; 2484 } 2485 break; 2486 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2487 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2488 if (len > 1) { 2489 USETW(((usb_status_t *)buf)->wStatus, 0); 2490 totlen = 2; 2491 } 2492 break; 2493 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2494 if (value >= USB_MAX_DEVICES) { 2495 err = USBD_IOERROR; 2496 goto ret; 2497 } 2498 sc->sc_addr = value; 2499 break; 2500 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2501 if (value != 0 && value != 1) { 2502 err = USBD_IOERROR; 2503 goto ret; 2504 } 2505 sc->sc_conf = value; 2506 break; 2507 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2508 break; 2509 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2510 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2511 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2512 err = USBD_IOERROR; 2513 goto ret; 2514 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2515 break; 2516 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2517 break; 2518 /* Hub requests */ 2519 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2520 break; 2521 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2522 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2523 "port=%d feature=%d\n", 2524 index, value)); 2525 if (index < 1 || index > sc->sc_noport) { 2526 err = USBD_IOERROR; 2527 goto ret; 2528 } 2529 port = OHCI_RH_PORT_STATUS(index); 2530 switch(value) { 2531 case UHF_PORT_ENABLE: 2532 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2533 break; 2534 case UHF_PORT_SUSPEND: 2535 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2536 break; 2537 case UHF_PORT_POWER: 2538 /* Yes, writing to the LOW_SPEED bit clears power. */ 2539 OWRITE4(sc, port, UPS_LOW_SPEED); 2540 break; 2541 case UHF_C_PORT_CONNECTION: 2542 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2543 break; 2544 case UHF_C_PORT_ENABLE: 2545 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2546 break; 2547 case UHF_C_PORT_SUSPEND: 2548 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2549 break; 2550 case UHF_C_PORT_OVER_CURRENT: 2551 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2552 break; 2553 case UHF_C_PORT_RESET: 2554 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2555 break; 2556 default: 2557 err = USBD_IOERROR; 2558 goto ret; 2559 } 2560 switch(value) { 2561 case UHF_C_PORT_CONNECTION: 2562 case UHF_C_PORT_ENABLE: 2563 case UHF_C_PORT_SUSPEND: 2564 case UHF_C_PORT_OVER_CURRENT: 2565 case UHF_C_PORT_RESET: 2566 /* Enable RHSC interrupt if condition is cleared. */ 2567 if ((OREAD4(sc, port) >> 16) == 0) 2568 ohci_rhsc_able(sc, 1); 2569 break; 2570 default: 2571 break; 2572 } 2573 break; 2574 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2575 if ((value & 0xff) != 0) { 2576 err = USBD_IOERROR; 2577 goto ret; 2578 } 2579 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2580 hubd = ohci_hubd; 2581 hubd.bNbrPorts = sc->sc_noport; 2582 USETW(hubd.wHubCharacteristics, 2583 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2584 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2585 /* XXX overcurrent */ 2586 ); 2587 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2588 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2589 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2590 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2591 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2592 l = min(len, hubd.bDescLength); 2593 totlen = l; 2594 memcpy(buf, &hubd, l); 2595 break; 2596 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2597 if (len != 4) { 2598 err = USBD_IOERROR; 2599 goto ret; 2600 } 2601 memset(buf, 0, len); /* ? XXX */ 2602 totlen = len; 2603 break; 2604 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2605 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2606 index)); 2607 if (index < 1 || index > sc->sc_noport) { 2608 err = USBD_IOERROR; 2609 goto ret; 2610 } 2611 if (len != 4) { 2612 err = USBD_IOERROR; 2613 goto ret; 2614 } 2615 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2616 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2617 v)); 2618 USETW(ps.wPortStatus, v); 2619 USETW(ps.wPortChange, v >> 16); 2620 l = min(len, sizeof ps); 2621 memcpy(buf, &ps, l); 2622 totlen = l; 2623 break; 2624 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2625 err = USBD_IOERROR; 2626 goto ret; 2627 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2628 break; 2629 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2630 if (index < 1 || index > sc->sc_noport) { 2631 err = USBD_IOERROR; 2632 goto ret; 2633 } 2634 port = OHCI_RH_PORT_STATUS(index); 2635 switch(value) { 2636 case UHF_PORT_ENABLE: 2637 OWRITE4(sc, port, UPS_PORT_ENABLED); 2638 break; 2639 case UHF_PORT_SUSPEND: 2640 OWRITE4(sc, port, UPS_SUSPEND); 2641 break; 2642 case UHF_PORT_RESET: 2643 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2644 index)); 2645 OWRITE4(sc, port, UPS_RESET); 2646 for (i = 0; i < 5; i++) { 2647 usb_delay_ms(&sc->sc_bus, 2648 USB_PORT_ROOT_RESET_DELAY); 2649 if (sc->sc_dying) { 2650 err = USBD_IOERROR; 2651 goto ret; 2652 } 2653 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2654 break; 2655 } 2656 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2657 index, OREAD4(sc, port))); 2658 break; 2659 case UHF_PORT_POWER: 2660 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2661 "%d\n", index)); 2662 OWRITE4(sc, port, UPS_PORT_POWER); 2663 break; 2664 case UHF_PORT_DISOWN_TO_1_1: 2665 /* accept, but do nothing */ 2666 break; 2667 default: 2668 err = USBD_IOERROR; 2669 goto ret; 2670 } 2671 break; 2672 default: 2673 err = USBD_IOERROR; 2674 goto ret; 2675 } 2676 xfer->actlen = totlen; 2677 err = USBD_NORMAL_COMPLETION; 2678 ret: 2679 xfer->status = err; 2680 s = splusb(); 2681 usb_transfer_complete(xfer); 2682 splx(s); 2683 return (USBD_IN_PROGRESS); 2684 } 2685 2686 /* Abort a root control request. */ 2687 void 2688 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2689 { 2690 /* Nothing to do, all transfers are synchronous. */ 2691 } 2692 2693 /* Close the root pipe. */ 2694 void 2695 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2696 { 2697 DPRINTF(("ohci_root_ctrl_close\n")); 2698 /* Nothing to do. */ 2699 } 2700 2701 usbd_status 2702 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2703 { 2704 usbd_status err; 2705 2706 /* Insert last in queue. */ 2707 err = usb_insert_transfer(xfer); 2708 if (err) 2709 return (err); 2710 2711 /* Pipe isn't running, start first */ 2712 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2713 } 2714 2715 usbd_status 2716 ohci_root_intr_start(usbd_xfer_handle xfer) 2717 { 2718 usbd_pipe_handle pipe = xfer->pipe; 2719 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2720 2721 if (sc->sc_dying) 2722 return (USBD_IOERROR); 2723 2724 sc->sc_intrxfer = xfer; 2725 2726 return (USBD_IN_PROGRESS); 2727 } 2728 2729 /* Abort a root interrupt request. */ 2730 void 2731 ohci_root_intr_abort(usbd_xfer_handle xfer) 2732 { 2733 int s; 2734 2735 if (xfer->pipe->intrxfer == xfer) { 2736 DPRINTF(("ohci_root_intr_abort: remove\n")); 2737 xfer->pipe->intrxfer = NULL; 2738 } 2739 xfer->status = USBD_CANCELLED; 2740 s = splusb(); 2741 usb_transfer_complete(xfer); 2742 splx(s); 2743 } 2744 2745 /* Close the root pipe. */ 2746 void 2747 ohci_root_intr_close(usbd_pipe_handle pipe) 2748 { 2749 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2750 2751 DPRINTF(("ohci_root_intr_close\n")); 2752 2753 sc->sc_intrxfer = NULL; 2754 } 2755 2756 /************************/ 2757 2758 usbd_status 2759 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2760 { 2761 usbd_status err; 2762 2763 /* Insert last in queue. */ 2764 err = usb_insert_transfer(xfer); 2765 if (err) 2766 return (err); 2767 2768 /* Pipe isn't running, start first */ 2769 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2770 } 2771 2772 usbd_status 2773 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2774 { 2775 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 2776 usbd_status err; 2777 2778 if (sc->sc_dying) 2779 return (USBD_IOERROR); 2780 2781 #ifdef DIAGNOSTIC 2782 if (!(xfer->rqflags & URQ_REQUEST)) { 2783 /* XXX panic */ 2784 printf("ohci_device_ctrl_transfer: not a request\n"); 2785 return (USBD_INVAL); 2786 } 2787 #endif 2788 2789 err = ohci_device_request(xfer); 2790 if (err) 2791 return (err); 2792 2793 if (sc->sc_bus.use_polling) 2794 ohci_waitintr(sc, xfer); 2795 2796 return (USBD_IN_PROGRESS); 2797 } 2798 2799 /* Abort a device control request. */ 2800 void 2801 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2802 { 2803 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2804 ohci_abort_xfer(xfer, USBD_CANCELLED); 2805 } 2806 2807 /* Close a device control pipe. */ 2808 void 2809 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2810 { 2811 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2812 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2813 2814 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2815 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2816 ohci_free_std(sc, opipe->tail.td); 2817 } 2818 2819 /************************/ 2820 2821 void 2822 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2823 { 2824 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2825 2826 opipe->sed->ed.ed_headp &= htole32(~OHCI_TOGGLECARRY); 2827 } 2828 2829 void 2830 ohci_noop(usbd_pipe_handle pipe) 2831 { 2832 } 2833 2834 usbd_status 2835 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2836 { 2837 usbd_status err; 2838 2839 /* Insert last in queue. */ 2840 err = usb_insert_transfer(xfer); 2841 if (err) 2842 return (err); 2843 2844 /* Pipe isn't running, start first */ 2845 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2846 } 2847 2848 usbd_status 2849 ohci_device_bulk_start(usbd_xfer_handle xfer) 2850 { 2851 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2852 usbd_device_handle dev = opipe->pipe.device; 2853 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2854 int addr = dev->address; 2855 ohci_soft_td_t *data, *tail, *tdp; 2856 ohci_soft_ed_t *sed; 2857 u_int len; 2858 int s, isread, endpt; 2859 usbd_status err; 2860 2861 if (sc->sc_dying) 2862 return (USBD_IOERROR); 2863 2864 #ifdef DIAGNOSTIC 2865 if (xfer->rqflags & URQ_REQUEST) { 2866 /* XXX panic */ 2867 printf("ohci_device_bulk_start: a request\n"); 2868 return (USBD_INVAL); 2869 } 2870 #endif 2871 2872 len = xfer->length; 2873 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2874 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2875 sed = opipe->sed; 2876 2877 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%u isread=%d " 2878 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 2879 endpt)); 2880 2881 opipe->u.bulk.isread = isread; 2882 opipe->u.bulk.length = len; 2883 2884 /* Update device address */ 2885 sed->ed.ed_flags = htole32( 2886 (letoh32(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2887 OHCI_ED_SET_FA(addr)); 2888 2889 /* Allocate a chain of new TDs (including a new tail). */ 2890 data = opipe->tail.td; 2891 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2892 data, &tail); 2893 /* We want interrupt at the end of the transfer. */ 2894 tail->td.td_flags &= htole32(~OHCI_TD_INTR_MASK); 2895 tail->td.td_flags |= htole32(OHCI_TD_SET_DI(1)); 2896 tail->flags |= OHCI_CALL_DONE; 2897 tail = tail->nexttd; /* point at sentinel */ 2898 if (err) 2899 return (err); 2900 2901 tail->xfer = NULL; 2902 xfer->hcpriv = data; 2903 2904 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 2905 "td_cbp=0x%08x td_be=0x%08x\n", 2906 (int)letoh32(sed->ed.ed_flags), 2907 (int)letoh32(data->td.td_flags), 2908 (int)letoh32(data->td.td_cbp), 2909 (int)letoh32(data->td.td_be))); 2910 2911 #ifdef OHCI_DEBUG 2912 if (ohcidebug > 5) { 2913 ohci_dump_ed(sed); 2914 ohci_dump_tds(data); 2915 } 2916 #endif 2917 2918 /* Insert ED in schedule */ 2919 s = splusb(); 2920 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2921 tdp->xfer = xfer; 2922 } 2923 sed->ed.ed_tailp = htole32(tail->physaddr); 2924 opipe->tail.td = tail; 2925 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); 2926 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2927 if (xfer->timeout && !sc->sc_bus.use_polling) { 2928 timeout_del(&xfer->timeout_handle); 2929 timeout_set(&xfer->timeout_handle, ohci_timeout, xfer); 2930 timeout_add(&xfer->timeout_handle, mstohz(xfer->timeout)); 2931 } 2932 2933 #if 0 2934 /* This goes wrong if we are too slow. */ 2935 if (ohcidebug > 10) { 2936 delay(10000); 2937 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 2938 OREAD4(sc, OHCI_COMMAND_STATUS))); 2939 ohci_dump_ed(sed); 2940 ohci_dump_tds(data); 2941 } 2942 #endif 2943 2944 splx(s); 2945 2946 if (sc->sc_bus.use_polling) 2947 ohci_waitintr(sc, xfer); 2948 2949 return (USBD_IN_PROGRESS); 2950 } 2951 2952 void 2953 ohci_device_bulk_abort(usbd_xfer_handle xfer) 2954 { 2955 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 2956 ohci_abort_xfer(xfer, USBD_CANCELLED); 2957 } 2958 2959 /* 2960 * Close a device bulk pipe. 2961 */ 2962 void 2963 ohci_device_bulk_close(usbd_pipe_handle pipe) 2964 { 2965 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2966 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2967 2968 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 2969 ohci_close_pipe(pipe, sc->sc_bulk_head); 2970 ohci_free_std(sc, opipe->tail.td); 2971 } 2972 2973 /************************/ 2974 2975 usbd_status 2976 ohci_device_intr_transfer(usbd_xfer_handle xfer) 2977 { 2978 usbd_status err; 2979 2980 /* Insert last in queue. */ 2981 err = usb_insert_transfer(xfer); 2982 if (err) 2983 return (err); 2984 2985 /* Pipe isn't running, start first */ 2986 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2987 } 2988 2989 usbd_status 2990 ohci_device_intr_start(usbd_xfer_handle xfer) 2991 { 2992 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2993 usbd_device_handle dev = opipe->pipe.device; 2994 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2995 ohci_soft_ed_t *sed = opipe->sed; 2996 ohci_soft_td_t *data, *tail; 2997 int s, len, isread, endpt; 2998 2999 if (sc->sc_dying) 3000 return (USBD_IOERROR); 3001 3002 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%u " 3003 "flags=%d priv=%p\n", 3004 xfer, xfer->length, xfer->flags, xfer->priv)); 3005 3006 #ifdef DIAGNOSTIC 3007 if (xfer->rqflags & URQ_REQUEST) 3008 panic("ohci_device_intr_transfer: a request"); 3009 #endif 3010 3011 len = xfer->length; 3012 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3013 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3014 3015 data = opipe->tail.td; 3016 tail = ohci_alloc_std(sc); 3017 if (tail == NULL) 3018 return (USBD_NOMEM); 3019 tail->xfer = NULL; 3020 3021 data->td.td_flags = htole32( 3022 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3023 OHCI_TD_NOCC | 3024 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3025 if (xfer->flags & USBD_SHORT_XFER_OK) 3026 data->td.td_flags |= htole32(OHCI_TD_R); 3027 data->td.td_cbp = htole32(DMAADDR(&xfer->dmabuf, 0)); 3028 data->nexttd = tail; 3029 data->td.td_nexttd = htole32(tail->physaddr); 3030 data->td.td_be = htole32(letoh32(data->td.td_cbp) + len - 1); 3031 data->len = len; 3032 data->xfer = xfer; 3033 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3034 xfer->hcpriv = data; 3035 3036 #ifdef OHCI_DEBUG 3037 if (ohcidebug > 5) { 3038 DPRINTF(("ohci_device_intr_transfer:\n")); 3039 ohci_dump_ed(sed); 3040 ohci_dump_tds(data); 3041 } 3042 #endif 3043 3044 /* Insert ED in schedule */ 3045 s = splusb(); 3046 sed->ed.ed_tailp = htole32(tail->physaddr); 3047 opipe->tail.td = tail; 3048 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); 3049 3050 #if 0 3051 /* 3052 * This goes horribly wrong, printing thousands of descriptors, 3053 * because false references are followed due to the fact that the 3054 * TD is gone. 3055 */ 3056 if (ohcidebug > 5) { 3057 usb_delay_ms(&sc->sc_bus, 5); 3058 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3059 OREAD4(sc, OHCI_COMMAND_STATUS))); 3060 ohci_dump_ed(sed); 3061 ohci_dump_tds(data); 3062 } 3063 #endif 3064 splx(s); 3065 3066 return (USBD_IN_PROGRESS); 3067 } 3068 3069 /* Abort a device control request. */ 3070 void 3071 ohci_device_intr_abort(usbd_xfer_handle xfer) 3072 { 3073 if (xfer->pipe->intrxfer == xfer) { 3074 DPRINTF(("ohci_device_intr_abort: remove\n")); 3075 xfer->pipe->intrxfer = NULL; 3076 } 3077 ohci_abort_xfer(xfer, USBD_CANCELLED); 3078 } 3079 3080 /* Close a device interrupt pipe. */ 3081 void 3082 ohci_device_intr_close(usbd_pipe_handle pipe) 3083 { 3084 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3085 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3086 int nslots = opipe->u.intr.nslots; 3087 int pos = opipe->u.intr.pos; 3088 int j; 3089 ohci_soft_ed_t *p, *sed = opipe->sed; 3090 int s; 3091 3092 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3093 pipe, nslots, pos)); 3094 s = splusb(); 3095 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); 3096 if ((letoh32(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3097 (letoh32(sed->ed.ed_headp) & OHCI_HEADMASK)) 3098 usb_delay_ms(&sc->sc_bus, 2); 3099 3100 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3101 ; 3102 #ifdef DIAGNOSTIC 3103 if (p == NULL) 3104 panic("ohci_device_intr_close: ED not found"); 3105 #endif 3106 p->next = sed->next; 3107 p->ed.ed_nexted = sed->ed.ed_nexted; 3108 splx(s); 3109 3110 for (j = 0; j < nslots; j++) 3111 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3112 3113 ohci_free_std(sc, opipe->tail.td); 3114 ohci_free_sed(sc, opipe->sed); 3115 } 3116 3117 usbd_status 3118 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3119 { 3120 int i, j, s, best; 3121 u_int npoll, slow, shigh, nslots; 3122 u_int bestbw, bw; 3123 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3124 3125 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3126 if (ival == 0) { 3127 printf("ohci_setintr: 0 interval\n"); 3128 return (USBD_INVAL); 3129 } 3130 3131 npoll = OHCI_NO_INTRS; 3132 while (npoll > ival) 3133 npoll /= 2; 3134 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3135 3136 /* 3137 * We now know which level in the tree the ED must go into. 3138 * Figure out which slot has most bandwidth left over. 3139 * Slots to examine: 3140 * npoll 3141 * 1 0 3142 * 2 1 2 3143 * 4 3 4 5 6 3144 * 8 7 8 9 10 11 12 13 14 3145 * N (N-1) .. (N-1+N-1) 3146 */ 3147 slow = npoll-1; 3148 shigh = slow + npoll; 3149 nslots = OHCI_NO_INTRS / npoll; 3150 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3151 bw = 0; 3152 for (j = 0; j < nslots; j++) 3153 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3154 if (bw < bestbw) { 3155 best = i; 3156 bestbw = bw; 3157 } 3158 } 3159 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3160 best, slow, shigh, bestbw)); 3161 3162 s = splusb(); 3163 hsed = sc->sc_eds[best]; 3164 sed->next = hsed->next; 3165 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3166 hsed->next = sed; 3167 hsed->ed.ed_nexted = htole32(sed->physaddr); 3168 splx(s); 3169 3170 for (j = 0; j < nslots; j++) 3171 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3172 opipe->u.intr.nslots = nslots; 3173 opipe->u.intr.pos = best; 3174 3175 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3176 return (USBD_NORMAL_COMPLETION); 3177 } 3178 3179 /***********************/ 3180 3181 usbd_status 3182 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3183 { 3184 usbd_status err; 3185 3186 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3187 3188 /* Put it on our queue, */ 3189 err = usb_insert_transfer(xfer); 3190 3191 /* bail out on error, */ 3192 if (err && err != USBD_IN_PROGRESS) 3193 return (err); 3194 3195 /* XXX should check inuse here */ 3196 3197 /* insert into schedule, */ 3198 ohci_device_isoc_enter(xfer); 3199 3200 /* and start if the pipe wasn't running */ 3201 if (!err) 3202 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3203 3204 return (err); 3205 } 3206 3207 void 3208 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3209 { 3210 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3211 usbd_device_handle dev = opipe->pipe.device; 3212 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 3213 ohci_soft_ed_t *sed = opipe->sed; 3214 struct iso *iso = &opipe->u.iso; 3215 ohci_soft_itd_t *sitd, *nsitd; 3216 ohci_physaddr_t buf, offs, noffs, bp0; 3217 int i, ncur, nframes; 3218 int s; 3219 3220 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3221 "nframes=%d\n", 3222 iso->inuse, iso->next, xfer, xfer->nframes)); 3223 3224 if (sc->sc_dying) 3225 return; 3226 3227 if (iso->next == -1) { 3228 /* Not in use yet, schedule it a few frames ahead. */ 3229 iso->next = letoh32(sc->sc_hcca->hcca_frame_number) + 5; 3230 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3231 iso->next)); 3232 } 3233 3234 sitd = opipe->tail.itd; 3235 buf = DMAADDR(&xfer->dmabuf, 0); 3236 bp0 = OHCI_PAGE(buf); 3237 offs = OHCI_PAGE_OFFSET(buf); 3238 nframes = xfer->nframes; 3239 xfer->hcpriv = sitd; 3240 for (i = ncur = 0; i < nframes; i++, ncur++) { 3241 noffs = offs + xfer->frlengths[i]; 3242 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3243 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3244 3245 /* Allocate next ITD */ 3246 nsitd = ohci_alloc_sitd(sc); 3247 if (nsitd == NULL) { 3248 /* XXX what now? */ 3249 printf("%s: isoc TD alloc failed\n", 3250 sc->sc_bus.bdev.dv_xname); 3251 return; 3252 } 3253 3254 /* Fill current ITD */ 3255 sitd->itd.itd_flags = htole32( 3256 OHCI_ITD_NOCC | 3257 OHCI_ITD_SET_SF(iso->next) | 3258 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3259 OHCI_ITD_SET_FC(ncur)); 3260 sitd->itd.itd_bp0 = htole32(bp0); 3261 sitd->nextitd = nsitd; 3262 sitd->itd.itd_nextitd = htole32(nsitd->physaddr); 3263 sitd->itd.itd_be = htole32(bp0 + offs - 1); 3264 sitd->xfer = xfer; 3265 sitd->flags = 0; 3266 3267 sitd = nsitd; 3268 iso->next = iso->next + ncur; 3269 bp0 = OHCI_PAGE(buf + offs); 3270 ncur = 0; 3271 } 3272 sitd->itd.itd_offset[ncur] = htole16(OHCI_ITD_MK_OFFS(offs)); 3273 offs = noffs; 3274 } 3275 nsitd = ohci_alloc_sitd(sc); 3276 if (nsitd == NULL) { 3277 /* XXX what now? */ 3278 printf("%s: isoc TD alloc failed\n", 3279 sc->sc_bus.bdev.dv_xname); 3280 return; 3281 } 3282 /* Fixup last used ITD */ 3283 sitd->itd.itd_flags = htole32( 3284 OHCI_ITD_NOCC | 3285 OHCI_ITD_SET_SF(iso->next) | 3286 OHCI_ITD_SET_DI(0) | 3287 OHCI_ITD_SET_FC(ncur)); 3288 sitd->itd.itd_bp0 = htole32(bp0); 3289 sitd->nextitd = nsitd; 3290 sitd->itd.itd_nextitd = htole32(nsitd->physaddr); 3291 sitd->itd.itd_be = htole32(bp0 + offs - 1); 3292 sitd->xfer = xfer; 3293 sitd->flags = OHCI_CALL_DONE; 3294 3295 iso->next = iso->next + ncur; 3296 iso->inuse += nframes; 3297 3298 xfer->actlen = offs; /* XXX pretend we did it all */ 3299 3300 xfer->status = USBD_IN_PROGRESS; 3301 3302 #ifdef OHCI_DEBUG 3303 if (ohcidebug > 5) { 3304 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3305 letoh32(sc->sc_hcca->hcca_frame_number))); 3306 ohci_dump_itds(xfer->hcpriv); 3307 ohci_dump_ed(sed); 3308 } 3309 #endif 3310 3311 s = splusb(); 3312 sed->ed.ed_tailp = htole32(nsitd->physaddr); 3313 opipe->tail.itd = nsitd; 3314 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); 3315 splx(s); 3316 3317 #ifdef OHCI_DEBUG 3318 if (ohcidebug > 5) { 3319 delay(150000); 3320 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3321 letoh32(sc->sc_hcca->hcca_frame_number))); 3322 ohci_dump_itds(xfer->hcpriv); 3323 ohci_dump_ed(sed); 3324 } 3325 #endif 3326 } 3327 3328 usbd_status 3329 ohci_device_isoc_start(usbd_xfer_handle xfer) 3330 { 3331 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3332 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3333 3334 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3335 3336 if (sc->sc_dying) 3337 return (USBD_IOERROR); 3338 3339 #ifdef DIAGNOSTIC 3340 if (xfer->status != USBD_IN_PROGRESS) 3341 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3342 #endif 3343 3344 /* XXX anything to do? */ 3345 3346 return (USBD_IN_PROGRESS); 3347 } 3348 3349 void 3350 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3351 { 3352 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3353 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3354 ohci_soft_ed_t *sed; 3355 ohci_soft_itd_t *sitd; 3356 int s; 3357 3358 s = splusb(); 3359 3360 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p\n", xfer)); 3361 3362 /* Transfer is already done. */ 3363 if (xfer->status != USBD_NOT_STARTED && 3364 xfer->status != USBD_IN_PROGRESS) { 3365 splx(s); 3366 printf("ohci_device_isoc_abort: early return\n"); 3367 return; 3368 } 3369 3370 /* Give xfer the requested abort code. */ 3371 xfer->status = USBD_CANCELLED; 3372 3373 sed = opipe->sed; 3374 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); /* force hardware skip */ 3375 3376 sitd = xfer->hcpriv; 3377 #ifdef DIAGNOSTIC 3378 if (sitd == NULL) { 3379 splx(s); 3380 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3381 return; 3382 } 3383 #endif 3384 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3385 #ifdef DIAGNOSTIC 3386 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3387 sitd->isdone = 1; 3388 #endif 3389 } 3390 3391 splx(s); 3392 3393 usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET); 3394 3395 s = splusb(); 3396 3397 /* Run callback. */ 3398 usb_transfer_complete(xfer); 3399 3400 sed->ed.ed_headp = htole32(sitd->physaddr); /* unlink TDs */ 3401 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); /* remove hardware skip */ 3402 3403 splx(s); 3404 } 3405 3406 void 3407 ohci_device_isoc_done(usbd_xfer_handle xfer) 3408 { 3409 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3410 } 3411 3412 usbd_status 3413 ohci_setup_isoc(usbd_pipe_handle pipe) 3414 { 3415 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3416 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3417 struct iso *iso = &opipe->u.iso; 3418 int s; 3419 3420 iso->next = -1; 3421 iso->inuse = 0; 3422 3423 s = splusb(); 3424 ohci_add_ed(opipe->sed, sc->sc_isoc_head); 3425 splx(s); 3426 3427 return (USBD_NORMAL_COMPLETION); 3428 } 3429 3430 void 3431 ohci_device_isoc_close(usbd_pipe_handle pipe) 3432 { 3433 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3434 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3435 3436 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3437 ohci_close_pipe(pipe, sc->sc_isoc_head); 3438 #ifdef DIAGNOSTIC 3439 opipe->tail.itd->isdone = 1; 3440 #endif 3441 ohci_free_sitd(sc, opipe->tail.itd); 3442 } 3443