1 /* $OpenBSD: udl.h,v 1.22 2017/03/26 15:31:15 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Marcus Glocker <mglocker@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Bulk command xfer structure. 21 */ 22 #define UDL_CMD_MAX_XFER_SIZE 1048576 23 #define UDL_CMD_MAX_DATA_SIZE 512 24 #define UDL_CMD_MAX_PIXEL_COUNT (UDL_CMD_MAX_DATA_SIZE / 2) 25 #define UDL_CMD_WRITE_HEAD_SIZE 6 26 #define UDL_CMD_COPY_HEAD_SIZE 9 27 #define UDL_CMD_WRITE_MAX_SIZE (UDL_CMD_WRITE_HEAD_SIZE + \ 28 UDL_CMD_MAX_DATA_SIZE + 2) 29 #define UDL_CMD_COPY_MAX_SIZE (UDL_CMD_COPY_HEAD_SIZE + 2) 30 31 struct udl_cmd_xfer { 32 struct udl_softc *sc; 33 struct usbd_xfer *xfer; 34 uint8_t busy; 35 uint8_t *buf; 36 }; 37 38 struct udl_cmd_buf { 39 #define UDL_CMD_XFER_SYNC 0 40 #define UDL_CMD_XFER_ASYNC 1 41 uint8_t xfer_type; 42 uint16_t compblock; 43 uint16_t compblock_save; 44 uint32_t off; 45 uint32_t off_save; 46 uint8_t *buf; 47 }; 48 49 /* 50 * Our per device structure. 51 */ 52 struct udl_softc { 53 struct device sc_dev; 54 struct usbd_device *sc_udev; 55 struct usbd_interface *sc_iface; 56 struct usbd_pipe *sc_tx_pipeh; 57 58 /* wsdisplay glue */ 59 struct device *sc_wsdisplay; 60 struct rasops_info sc_ri; 61 uint8_t sc_nscreens; 62 63 int sc_mode; 64 uint8_t sc_edid[128]; 65 struct edid_info sc_edid_info; 66 67 #define UDL_CMD_XFER_COUNT 8 68 int sc_cmd_xfer_cnt; 69 struct udl_cmd_xfer sc_cmd_xfer[UDL_CMD_XFER_COUNT]; 70 struct udl_cmd_buf sc_cmd_buf; 71 uint8_t *sc_huffman; 72 size_t sc_huffman_size; 73 uint16_t sc_width; 74 uint16_t sc_height; 75 uint8_t sc_depth; 76 uint8_t sc_cursor_on; 77 uint8_t *sc_fbmem; /* framebuffer for X11 */ 78 size_t sc_fbmemsize; 79 uint16_t sc_chip; 80 #define DLALL 0x0000 81 #define DL125 0x0000 /* max 1280x1024, 1440x900 */ 82 #define DL120 0x0001 /* max 1280x1024, 1440x1050 */ 83 #define DL160 0x0002 /* max 1600x1200, 1680x1050 */ 84 #define DL165 0x0003 /* max 1600x1200, 1920x1080 */ 85 #define DL195 0x0004 /* max 1920x1200, 2048x1152 */ 86 #define DLMAX 0x0004 87 #define DLUNK 0x00ff /* unknown */ 88 uint8_t sc_cur_mode; 89 u_int *sc_cbs; /* character backing store */ 90 91 /* 92 * We use function pointers to the framebuffer manipulation 93 * functions so we can easily differ between compressed and 94 * none-compressed mode. 95 */ 96 int (*udl_fb_off_write) 97 (struct udl_softc *, uint16_t, uint32_t, 98 uint16_t); 99 int (*udl_fb_line_write) 100 (struct udl_softc *, uint16_t, uint32_t, 101 uint32_t, uint32_t); 102 int (*udl_fb_block_write) 103 (struct udl_softc *, uint16_t, uint32_t, 104 uint32_t, uint32_t, uint32_t); 105 int (*udl_fb_buf_write) 106 (struct udl_softc *, uint8_t *, uint32_t, 107 uint32_t, uint16_t); 108 int (*udl_fb_off_copy) 109 (struct udl_softc *, uint32_t, uint32_t, 110 uint16_t); 111 int (*udl_fb_line_copy) 112 (struct udl_softc *, uint32_t, uint32_t, 113 uint32_t, uint32_t, uint32_t); 114 int (*udl_fb_block_copy) 115 (struct udl_softc *, uint32_t, uint32_t, 116 uint32_t, uint32_t, uint32_t, uint32_t); 117 }; 118 119 /* 120 * Chip commands. 121 */ 122 #define UDL_CTRL_CMD_READ_EDID 0x02 123 #define UDL_CTRL_CMD_WRITE_1 0x03 124 #define UDL_CTRL_CMD_READ_1 0x04 125 #define UDL_CTRL_CMD_POLL 0x06 126 #define UDL_CTRL_CMD_SET_KEY 0x12 127 128 #define UDL_BULK_SOC 0xaf /* start of command token */ 129 130 #define UDL_BULK_CMD_REG_WRITE_1 0x20 /* write 1 byte to register */ 131 #define UDL_BULK_CMD_EOC 0xa0 /* end of command stack */ 132 #define UDL_BULK_CMD_DECOMP 0xe0 /* send decompression table */ 133 134 #define UDL_BULK_CMD_FB_BASE 0x60 135 #define UDL_BULK_CMD_FB_WORD 0x08 136 #define UDL_BULK_CMD_FB_COMP 0x10 137 #define UDL_BULK_CMD_FB_WRITE (UDL_BULK_CMD_FB_BASE | 0x00) 138 #define UDL_BULK_CMD_FB_COPY (UDL_BULK_CMD_FB_BASE | 0x02) 139 140 /* 141 * Chip registers. 142 */ 143 #define UDL_REG_ADDR_START16 0x20 144 #define UDL_REG_ADDR_STRIDE16 0x23 145 #define UDL_REG_ADDR_START8 0x26 146 #define UDL_REG_ADDR_STRIDE8 0x29 147 148 #define UDL_REG_SCREEN 0x1f 149 #define UDL_REG_SCREEN_ON 0x00 150 #define UDL_REG_SCREEN_OFF 0x01 151 #define UDL_REG_SYNC 0xff 152 153 /* 154 * Register values for screen resolution initialization. 155 */ 156 uint8_t udl_reg_vals_640x480_60[] = { /* 25.17 Mhz 59.9 Hz VESA std */ 157 0x00, 0x99, 0x30, 0x26, 0x94, 0x60, 0xa9, 0xce, 0x60, 0x07, 0xb3, 0x0f, 158 0x79, 0xff, 0xff, 0x02, 0x80, 0x83, 0xbc, 0xff, 0xfc, 0xff, 0xff, 0x01, 159 0xe0, 0x01, 0x02, 0xab, 0x13 160 }; 161 uint8_t udl_reg_vals_640x480_67[] = { /* 30.25 MHz 66.6 Hz MAC std */ 162 0x00, 0x1d, 0x33, 0x07, 0xb3, 0x60, 0xa9, 0xce, 0x60, 0xb6, 0xa8, 0xff, 163 0xff, 0xbf, 0x70, 0x02, 0x80, 0x83, 0xbc, 0xff, 0xff, 0xff, 0xf9, 0x01, 164 0xe0, 0x01, 0x02, 0xa2, 0x17 165 }; 166 uint8_t udl_reg_vals_640x480_72[] = { /* 31.50 Mhz 72.8 Hz VESA std */ 167 0x00, 0x2b, 0xeb, 0x35, 0xd3, 0x0a, 0x95, 0xe6, 0x0e, 0x0f, 0xb5, 0x15, 168 0x2a, 0xff, 0xff, 0x02, 0x80, 0xcc, 0x1d, 0xff, 0xf9, 0xff, 0xff, 0x01, 169 0xe0, 0x01, 0x02, 0x9c, 0x18 170 }; 171 uint8_t udl_reg_vals_640x480_75[] = { /* 31.50 Mhz 75.7 Hz VESA std */ 172 0x00, 0xeb, 0xf7, 0xd3, 0x0f, 0x4f, 0x93, 0xfa, 0x47, 0xb5, 0x58, 0xff, 173 0xff, 0xbf, 0x70, 0x02, 0x80, 0xf4, 0x8f, 0xff, 0xff, 0xff, 0xf9, 0x01, 174 0xe0, 0x01, 0x02, 0x9c, 0x18 175 }; 176 uint8_t udl_reg_vals_800x480_61[] = { /* 33.00 MHz 61.9 Hz */ 177 0x00, 0x20, 0x3c, 0x7a, 0xc9, 0xf2, 0x6c, 0x48, 0xf9, 0x70, 0x53, 0xff, 178 0xff, 0x21, 0x27, 0x03, 0x20, 0x91, 0xf3, 0xff, 0xff, 0xff, 0xf9, 0x01, 179 0xe0, 0x01, 0x02, 0xc8, 0x19 180 }; 181 uint8_t udl_reg_vals_800x600_56[] = { /* 36.00 MHz 56.2 Hz VESA std */ 182 0x00, 0x65, 0x35, 0x48, 0xf4, 0xf2, 0x6c, 0x19, 0x18, 0xc9, 0x4b, 0xff, 183 0xff, 0x70, 0x35, 0x03, 0x20, 0x32, 0x31, 0xff, 0xff, 0xff, 0xfc, 0x02, 184 0x58, 0x01, 0x02, 0x20, 0x1c 185 }; 186 uint8_t udl_reg_vals_800x600_60[] = { /* 40.00 MHz 60.3 Hz VESA std */ 187 0x00, 0x20, 0x3c, 0x7a, 0xc9, 0x93, 0x60, 0xc8, 0xc7, 0x70, 0x53, 0xff, 188 0xff, 0x21, 0x27, 0x03, 0x20, 0x91, 0x8f, 0xff, 0xff, 0xff, 0xf2, 0x02, 189 0x58, 0x01, 0x02, 0x40, 0x1f 190 }; 191 uint8_t udl_reg_vals_800x600_72[] = { /* 50.00 MHz 72.1 Hz VESA std */ 192 0x00, 0xeb, 0xf7, 0xd1, 0x90, 0x4d, 0x82, 0x23, 0x1f, 0x39, 0xcf, 0xff, 193 0xff, 0x43, 0x21, 0x03, 0x20, 0x62, 0xc5, 0xff, 0xff, 0xff, 0xca, 0x02, 194 0x58, 0x01, 0x02, 0x10, 0x27 195 }; 196 uint8_t udl_reg_vals_800x600_74[] = { /* 50.00 MHz 74.4 Hz */ 197 0x00, 0xb3, 0x76, 0x39, 0xcf, 0x60, 0xa9, 0xc7, 0xf4, 0x70, 0x53, 0xff, 198 0xff, 0x35, 0x33, 0x03, 0x20, 0x8f, 0xe9, 0xff, 0xff, 0xff, 0xf9, 0x02, 199 0x58, 0x01, 0x02, 0x10, 0x27 200 }; 201 uint8_t udl_reg_vals_800x600_75[] = { /* 49.50 MHz 75.0 Hz VESA std */ 202 0x00, 0xb3, 0x76, 0x39, 0xcf, 0xf2, 0x6c, 0x19, 0x18, 0x70, 0x53, 0xff, 203 0xff, 0x35, 0x33, 0x03, 0x20, 0x32, 0x31, 0xff, 0xff, 0xff, 0xf9, 0x02, 204 0x58, 0x01, 0x02, 0xac, 0x26 205 }; 206 uint8_t udl_reg_vals_1024x768_60[] = { /* 65.00 MHz 60.0 Hz VESA std */ 207 0x00, 0x36, 0x18, 0xd5, 0x10, 0x60, 0xa9, 0x7b, 0x33, 0xa1, 0x2b, 0x27, 208 0x32, 0xff, 0xff, 0x04, 0x00, 0xd9, 0x9a, 0xff, 0xca, 0xff, 0xff, 0x03, 209 0x00, 0x04, 0x03, 0xc8, 0x32 210 }; 211 uint8_t udl_reg_vals_1024x768_70[] = { /* 75.00 MHz 70.0 Hz VESA std */ 212 0x00, 0xb4, 0xed, 0x4c, 0x5e, 0x60, 0xa9, 0x7b, 0x33, 0x10, 0x4d, 0xff, 213 0xff, 0x27, 0x32, 0x04, 0x00, 0xd9, 0x9a, 0xff, 0xff, 0xff, 0xca, 0x03, 214 0x00, 0x04, 0x02, 0x98, 0x3a 215 }; 216 uint8_t udl_reg_vals_1024x768_75[] = { /* 78.75 MHz 75.0 Hz VESA std */ 217 0x00, 0xec, 0xb4, 0xa0, 0x4c, 0x36, 0x0a, 0x07, 0xb3, 0x5e, 0xd5, 0xff, 218 0xff, 0x0f, 0x79, 0x04, 0x00, 0x0f, 0x66, 0xff, 0xff, 0xff, 0xf9, 0x03, 219 0x00, 0x04, 0x02, 0x86, 0x3d 220 }; 221 uint8_t udl_reg_vals_1280x800_60[] = { /* 83.46 MHz 59.9 MHz */ 222 0x00, 0xb2, 0x19, 0x34, 0xdf, 0x93, 0x60, 0x30, 0xfb, 0x9f, 0xca, 0xff, 223 0xff, 0x27, 0x32, 0x05, 0x00, 0x61, 0xf6, 0xff, 0xff, 0xff, 0xf9, 0x03, 224 0x20, 0x04, 0x02, 0x34, 0x41 225 }; 226 uint8_t udl_reg_vals_1280x960_60[] = { /* 108.00 MHz 60.0 Hz VESA std */ 227 0x00, 0xa6, 0x03, 0x5c, 0x7e, 0x0a, 0x95, 0x48, 0xf4, 0x61, 0xbd, 0xff, 228 0xff, 0x94, 0x43, 0x05, 0x00, 0x91, 0xe8, 0xff, 0xff, 0xff, 0xf9, 0x03, 229 0xc0, 0x04, 0x02, 0x60, 0x54 230 }; 231 uint8_t udl_reg_vals_1280x1024_60[] = { /* 108.00 MHz 60.0 Hz VESA std */ 232 0x00, 0x98, 0xf8, 0x0d, 0x57, 0x2a, 0x55, 0x4d, 0x54, 0xca, 0x0d, 0xff, 233 0xff, 0x94, 0x43, 0x05, 0x00, 0x9a, 0xa8, 0xff, 0xff, 0xff, 0xf9, 0x04, 234 0x00, 0x04, 0x02, 0x60, 0x54 235 }; 236 uint8_t udl_reg_vals_1280x1024_75[] = { /* 135.00 MHz 75.0 Hz VESA std */ 237 0x00, 0xce, 0x12, 0x3f, 0x9f, 0x2a, 0x55, 0x4d, 0x54, 0xca, 0x0d, 0xff, 238 0xff, 0x32, 0x60, 0x05, 0x00, 0x9a, 0xa8, 0xff, 0xff, 0xff, 0xf9, 0x04, 239 0x00, 0x04, 0x02, 0x78, 0x69 240 }; 241 uint8_t udl_reg_vals_1366x768_60[] = { /* 90 MHz 60.0 Hz */ 242 0x01, 0x19, 0x1e, 0x1f, 0xb0, 0x93, 0x60, 0x40, 0x7b, 0x36, 0xe8, 0x27, 243 0x32, 0xff, 0xff, 0x05, 0x56, 0x03, 0xd9, 0xff, 0xff, 0xfc, 0xa7, 0x03, 244 0x00, 0x04, 0x02, 0x9a, 0x42 245 }; 246 uint8_t udl_reg_vals_1440x900_60[] = { /* 106.47 MHz 59.9 Hz */ 247 0x00, 0x24, 0xce, 0xe7, 0x72, 0x36, 0x0a, 0x86, 0xca, 0x1c, 0x10, 0xff, 248 0xff, 0x60, 0x3a, 0x05, 0xa0, 0x0d, 0x94, 0xff, 0xff, 0xff, 0xf9, 0x03, 249 0x84, 0x04, 0x02, 0x2e, 0x53 250 }; 251 uint8_t udl_reg_vals_1440x900_59[] = { /* 106.50 MHz 59.8 Hz */ 252 0x00, 0x24, 0xce, 0xe7, 0x72, 0xd8, 0x2a, 0x1b, 0x28, 0x1c, 0x10, 0xff, 253 0xff, 0x60, 0x3a, 0x05, 0xa0, 0x36, 0x50, 0xff, 0xff, 0xff, 0xf9, 0x03, 254 0x84, 0x04, 0x02, 0x34, 0x53 255 }; 256 uint8_t udl_reg_vals_1440x900_75[] = { /* 136.49 MHz 75.0 Hz */ 257 0x00, 0x73, 0xa6, 0x14, 0xea, 0x0a, 0x95, 0xca, 0x10, 0x7f, 0x46, 0xff, 258 0xff, 0x60, 0x3a, 0x05, 0xa0, 0x94, 0x20, 0xff, 0xff, 0xff, 0xf9, 0x03, 259 0x84, 0x04, 0x02, 0xa2, 0x6a 260 }; 261 uint8_t udl_reg_vals_1680x1050_60[] = { /* 147.14 MHz 60.0 Hz */ 262 0x00, 0x53, 0x43, 0xa6, 0x71, 0xc1, 0x52, 0xd9, 0x29, 0x69, 0x9f, 0xff, 263 0xff, 0xd7, 0xee, 0x06, 0x90, 0xb2, 0x53, 0xff, 0xff, 0xff, 0xf9, 0x04, 264 0x1a, 0x04, 0x02, 0xf4, 0x72 265 }; 266 uint8_t udl_reg_vals_1600x1200_60[] = { /* 162.00 MHz 60.0 Hz VESA std */ 267 0x00, 0xcf, 0xa4, 0x3c, 0x4e, 0x55, 0x73, 0x71, 0x2b, 0x71, 0x52, 0xff, 268 0xff, 0xee, 0xca, 0x06, 0x40, 0xe2, 0x57, 0xff, 0xff, 0xff, 0xf9, 0x04, 269 0xb0, 0x04, 0x02, 0x90, 0x7e 270 }; 271 uint8_t udl_reg_vals_1920x1080_60[] = { /* 138.50 MHz 59.9 Hz */ 272 0x00, 0x73, 0xa6, 0x28, 0xb3, 0x54, 0xaa, 0x41, 0x5d, 0x0d, 0x9f, 0x32, 273 0x60, 0xff, 0xff, 0x07, 0x80, 0x0a, 0xea, 0xff, 0xf9, 0xff, 0xff, 0x04, 274 0x38, 0x04, 0x02, 0xe0, 0x7c 275 }; 276 277 struct udl_mode { 278 uint16_t hdisplay; 279 uint16_t vdisplay; 280 uint8_t hz; 281 uint16_t chip; 282 uint32_t clock; 283 #define UDL_MODE_SIZE 29 284 uint8_t *mode; 285 }; 286 287 static const struct udl_mode udl_modes[] = { 288 { 640, 480, 60, DLALL, 2520, udl_reg_vals_640x480_60 }, 289 { 640, 480, 67, DLALL, 3025, udl_reg_vals_640x480_67 }, 290 { 640, 480, 72, DLALL, 3150, udl_reg_vals_640x480_72 }, 291 { 640, 480, 75, DLALL, 3150, udl_reg_vals_640x480_75 }, 292 { 800, 480, 59, DLALL, 5000, udl_reg_vals_800x480_61 }, 293 { 800, 480, 61, DLALL, 3300, udl_reg_vals_800x480_61 }, 294 { 800, 600, 56, DLALL, 3600, udl_reg_vals_800x600_56 }, 295 { 800, 600, 60, DLALL, 4000, udl_reg_vals_800x600_60 }, 296 { 800, 600, 72, DLALL, 5000, udl_reg_vals_800x600_72 }, 297 { 800, 600, 74, DLALL, 5000, udl_reg_vals_800x600_74 }, 298 { 800, 600, 75, DLALL, 4950, udl_reg_vals_800x600_75 }, 299 { 1024, 768, 60, DLALL, 6500, udl_reg_vals_1024x768_60 }, 300 { 1024, 768, 70, DLALL, 7500, udl_reg_vals_1024x768_70 }, 301 { 1024, 768, 75, DLALL, 7850, udl_reg_vals_1024x768_75 }, 302 { 1280, 800, 60, DLALL, 8346, udl_reg_vals_1280x800_60 }, 303 { 1280, 960, 60, DLALL, 10800, udl_reg_vals_1280x960_60 }, 304 { 1280, 1024, 60, DLALL, 10800, udl_reg_vals_1280x1024_60 }, 305 { 1280, 1024, 75, DLALL, 13500, udl_reg_vals_1280x1024_75 }, 306 { 1366, 768, 60, DLALL, 9000, udl_reg_vals_1366x768_60 }, 307 { 1440, 900, 59, DL125, 10650, udl_reg_vals_1440x900_59 }, 308 { 1440, 900, 60, DL125, 10647, udl_reg_vals_1440x900_60 }, 309 { 1440, 900, 75, DL125, 13649, udl_reg_vals_1440x900_75 }, 310 { 1680, 1050, 60, DL160, 14714, udl_reg_vals_1680x1050_60 }, 311 { 1600, 1200, 60, DL160, 16200, udl_reg_vals_1600x1200_60 }, 312 { 1920, 1080, 60, DL165, 13850, udl_reg_vals_1920x1080_60 } 313 }; 314 #define MAX_DL_MODES nitems(udl_modes) 315 316 /* 317 * Encryption. 318 */ 319 uint8_t udl_null_key_1[] = { 320 0x57, 0xcd, 0xdc, 0xa7, 0x1c, 0x88, 0x5e, 0x15, 0x60, 0xfe, 0xc6, 0x97, 321 0x16, 0x3d, 0x47, 0xf2 322 }; 323 324 /* 325 * Compression. 326 */ 327 struct udl_huffman { 328 uint32_t bit_count; 329 uint32_t bit_pattern; 330 }; 331 #define UDL_HUFFMAN_RECORD_SIZE sizeof(struct udl_huffman) 332 #define UDL_HUFFMAN_RECORDS (65536 + 1) 333 #define UDL_HUFFMAN_BASE (((UDL_HUFFMAN_RECORDS - 1) / 2) * \ 334 UDL_HUFFMAN_RECORD_SIZE) 335 336 #define UDL_CB_TOTAL_SIZE 512 337 #define UDL_CB_TAIL_SIZE 4 338 #define UDL_CB_BODY_SIZE (UDL_CB_TOTAL_SIZE - UDL_CB_TAIL_SIZE) 339 #define UDL_CB_RESTART_SIZE (UDL_CB_BODY_SIZE - UDL_CB_TAIL_SIZE) 340 341 uint8_t udl_decomp_table[] = { 342 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 343 0x00, 0x00, 0x01, 0x60, 0x01, 0x00, 0x00, 0x00, 0x61, 344 0x00, 0x00, 0x00, 0x01, 0x23, 0x00, 0x00, 0x00, 0x01, 345 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 346 0x00, 0x00, 0x01, 0x60, 0x05, 0x00, 0x00, 0x00, 0x61, 347 0x00, 0x00, 0x00, 0x01, 0x67, 0x00, 0x01, 0x00, 0x01, 348 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x7f, 349 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x7f, 350 0x00, 0x00, 0x00, 0x01, 0x89, 0x00, 0x00, 0x00, 0x01, 351 0x00, 0x00, 0x00, 0x61, 0xab, 0x00, 0x00, 0x00, 0x61, 352 0x00, 0x00, 0x00, 0x01, 0xcd, 0x00, 0x00, 0x00, 0x01, 353 0x00, 0x00, 0x01, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x01, 354 0x00, 0x00, 0x01, 0x60, 0x0f, 0x00, 0x00, 0x00, 0x61, 355 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x7f, 356 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x7f, 357 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x7f, 358 0x00, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x02, 359 0x00, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x02, 360 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 361 0x00, 0x00, 0x01, 0x01, 0x22, 0x00, 0x00, 0x01, 0x02, 362 0x00, 0x00, 0x00, 0x02, 0x33, 0x00, 0x01, 0x00, 0x02, 363 0x00, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x02, 364 0x00, 0x00, 0x00, 0x02, 0x44, 0x00, 0x02, 0x00, 0x02, 365 0x00, 0x00, 0x00, 0x02, 0x44, 0x00, 0x02, 0x00, 0x02, 366 0x00, 0x00, 0x01, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 367 0x00, 0x00, 0x00, 0x02, 0x67, 0x00, 0x00, 0x00, 0x02, 368 0x00, 0x00, 0x01, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 369 0x00, 0x00, 0x00, 0x02, 0x67, 0x00, 0x00, 0x00, 0x02, 370 0x00, 0x00, 0x00, 0x02, 0x5b, 0x00, 0x00, 0x00, 0x01, 371 0x00, 0x00, 0x01, 0x01, 0xc8, 0x00, 0x00, 0x01, 0x02, 372 0x00, 0x00, 0x00, 0x02, 0x5b, 0x00, 0x00, 0x00, 0x01, 373 0x00, 0x00, 0x00, 0x02, 0x5b, 0x00, 0x00, 0x00, 0x01, 374 0x00, 0x00, 0x00, 0x02, 0x9a, 0x00, 0x00, 0x00, 0x02, 375 0x00, 0x00, 0x00, 0x02, 0x33, 0x00, 0x01, 0x00, 0x02, 376 0x00, 0x00, 0x01, 0x01, 0x2b, 0x00, 0x00, 0x01, 0x02, 377 0x00, 0x00, 0x00, 0x02, 0xcc, 0x00, 0x02, 0x00, 0x02, 378 0x00, 0x00, 0x00, 0x02, 0xdd, 0x00, 0x04, 0x00, 0x02, 379 0x00, 0x00, 0x00, 0x02, 0xef, 0x00, 0x00, 0x00, 0x02, 380 0x00, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x03, 381 0x00, 0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x03, 382 0x00, 0x00, 0x01, 0x01, 0xc4, 0x00, 0x00, 0x01, 0x03, 383 0x00, 0x29, 0x01, 0x00, 0x05, 0x00, 0x00, 0x00, 0x03, 384 0x00, 0xb7, 0x01, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03, 385 0x00, 0x00, 0x00, 0x03, 0x78, 0x00, 0x00, 0x00, 0x03, 386 0x00, 0x00, 0x00, 0x03, 0x99, 0x00, 0x04, 0x00, 0x03, 387 0x00, 0x00, 0x00, 0x03, 0xaa, 0x00, 0x08, 0x00, 0x03, 388 0x00, 0x00, 0x00, 0x03, 0xbc, 0x00, 0x00, 0x00, 0x03, 389 0x00, 0x00, 0x00, 0x03, 0xde, 0x00, 0x00, 0x00, 0x03, 390 0x00, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x00, 0x04, 391 0x00, 0x00, 0x00, 0x04, 0x12, 0x00, 0x00, 0x00, 0x04, 392 0x00, 0x00, 0x00, 0x04, 0x34, 0x00, 0x00, 0x00, 0x04, 393 0x00, 0x00, 0x00, 0x04, 0x56, 0x00, 0x00, 0x00, 0x04, 394 0x00, 0x00, 0x00, 0x04, 0x78, 0x00, 0x00, 0x00, 0x04, 395 0x00, 0x00, 0x00, 0x04, 0x9a, 0x00, 0x00, 0x00, 0x04, 396 0x00, 0xd7, 0x01, 0x00, 0x00, 0x00, 0x09, 0x01, 0x00, 397 0x00, 0x00, 0x01, 0x01, 0x22, 0x00, 0x00, 0x02, 0x01, 398 0x00, 0x00, 0x02, 0x04, 0xbb, 0x00, 0x00, 0x03, 0x04, 399 0x00, 0x00, 0x00, 0x04, 0xcc, 0x00, 0x08, 0x00, 0x04, 400 0x00, 0x00, 0x00, 0x04, 0xdd, 0x00, 0x10, 0x00, 0x04, 401 0x00, 0x20, 0x01, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x04, 402 0x00, 0x00, 0x00, 0x04, 0xf0, 0x00, 0x00, 0x00, 0x05, 403 0xff, 0xe0, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05, 404 0x00, 0x00, 0x00, 0x05, 0x23, 0x00, 0x00, 0x00, 0x05, 405 0x08, 0x00, 0x01, 0x00, 0x00, 0x08, 0x20, 0x01, 0x00, 406 0x00, 0x00, 0x00, 0x05, 0x45, 0x00, 0x00, 0x00, 0x05, 407 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x21, 0x01, 0x00, 408 0x00, 0x00, 0x00, 0x05, 0x67, 0x00, 0x00, 0x00, 0x05, 409 0xf8, 0x00, 0x01, 0x00, 0x00, 0xf7, 0xe0, 0x01, 0x00, 410 0x00, 0x00, 0x00, 0x05, 0x89, 0x00, 0x00, 0x00, 0x05, 411 0xff, 0xff, 0x01, 0x00, 0x00, 0xff, 0xdf, 0x01, 0x00, 412 0x00, 0x00, 0x00, 0x05, 0xab, 0x00, 0x00, 0x00, 0x05, 413 0x00, 0x00, 0x01, 0x01, 0xcc, 0x00, 0x00, 0x02, 0x01, 414 0x00, 0x00, 0x02, 0x05, 0xcc, 0x00, 0x00, 0x03, 0x05, 415 0x00, 0x12, 0x01, 0x00, 0x00, 0x00, 0x32, 0x01, 0x00, 416 0x00, 0xce, 0x01, 0x00, 0x00, 0x00, 0xae, 0x01, 0x00, 417 0x00, 0x00, 0x00, 0x05, 0xde, 0x00, 0x00, 0x00, 0x05, 418 0x00, 0x00, 0x00, 0x05, 0xff, 0x00, 0x10, 0x00, 0x05, 419 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x20, 0x00, 0x06, 420 0x08, 0x41, 0x01, 0x00, 0x00, 0x08, 0x21, 0x01, 0x00, 421 0x08, 0x61, 0x00, 0x06, 0x12, 0x00, 0x00, 0x00, 0x06, 422 0x00, 0x00, 0x00, 0x06, 0x34, 0x00, 0x00, 0x00, 0x06, 423 0xf7, 0xbf, 0x01, 0x00, 0x00, 0xf7, 0xdf, 0x01, 0x00, 424 0xf7, 0x9f, 0x00, 0x06, 0x56, 0x00, 0x00, 0x00, 0x06, 425 0x00, 0x00, 0x00, 0x06, 0x78, 0x00, 0x00, 0x00, 0x06, 426 0x10, 0x61, 0x00, 0x06, 0x9a, 0x00, 0x00, 0x00, 0x06, 427 0x00, 0x41, 0x00, 0x06, 0x9b, 0x00, 0x00, 0x00, 0x06, 428 0x08, 0x62, 0x00, 0x06, 0x9c, 0x00, 0x00, 0x00, 0x06, 429 0x08, 0x40, 0x00, 0x06, 0x9d, 0x00, 0x00, 0x00, 0x06, 430 0xef, 0x9f, 0x00, 0x06, 0xef, 0x00, 0x00, 0x00, 0x06, 431 0xff, 0xbf, 0x00, 0x06, 0xe0, 0x00, 0x00, 0x00, 0x07, 432 0xf7, 0x9e, 0x00, 0x06, 0xe1, 0x00, 0x00, 0x00, 0x07, 433 0xf7, 0xc0, 0x00, 0x06, 0xe2, 0x00, 0x00, 0x00, 0x07, 434 0x00, 0x00, 0x00, 0x07, 0x34, 0x00, 0x00, 0x00, 0x07, 435 0x00, 0x00, 0x01, 0x01, 0x22, 0x00, 0x00, 0x03, 0x01, 436 0x00, 0x00, 0x04, 0x07, 0x55, 0x00, 0x00, 0x06, 0x07, 437 0x00, 0x00, 0x00, 0x07, 0x66, 0x00, 0x20, 0x00, 0x07, 438 0x00, 0x00, 0x00, 0x07, 0x77, 0x00, 0x40, 0x00, 0x07, 439 0x00, 0x00, 0x00, 0x07, 0x88, 0x00, 0x20, 0x00, 0x07, 440 0x08, 0x01, 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0xcc, 0x00, 0x00, 0x03, 0x01, 458 0x00, 0x00, 0x04, 0x09, 0x00, 0x00, 0x00, 0x06, 0x09, 459 0x00, 0x00, 0x00, 0x09, 0x12, 0x00, 0x00, 0x00, 0x09, 460 0x00, 0x00, 0x00, 0x09, 0x33, 0x00, 0x40, 0x00, 0x09, 461 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 462 0x00, 0x00, 0x01, 0x00, 0x04, 0x08, 0x41, 0x00, 0x09, 463 0x00, 0x00, 0x00, 0x09, 0x55, 0x08, 0x01, 0x00, 0x09, 464 0x00, 0x00, 0x00, 0x09, 0x66, 0xf7, 0xff, 0x00, 0x09, 465 0x10, 0x42, 0x00, 0x06, 0x99, 0x10, 0x62, 0x00, 0x06, 466 0xf8, 0x1f, 0x00, 0x06, 0x99, 0x00, 0x40, 0x00, 0x06, 467 0x00, 0x00, 0x01, 0x00, 0x07, 0xf7, 0xbf, 0x00, 0x09, 468 0x00, 0x00, 0x00, 0x09, 0x88, 0xf7, 0xff, 0x00, 0x09, 469 0x00, 0x00, 0x00, 0x09, 0x99, 0x08, 0x01, 0x00, 0x09, 470 0xef, 0xbe, 0x00, 0x06, 0xee, 0xef, 0x9e, 0x00, 0x06, 471 0x07, 0xe1, 0x00, 0x06, 0xee, 0xff, 0xc0, 0x00, 0x06, 472 0x00, 0x00, 0x01, 0x00, 0x0a, 0x08, 0x41, 0x00, 0x09, 473 0xf8, 0x20, 0x00, 0x06, 0x99, 0x07, 0xff, 0x00, 0x06, 474 0x08, 0x1f, 0x00, 0x06, 0x9b, 0x00, 0x00, 0x00, 0x09, 475 0x00, 0x00, 0x00, 0x09, 0xcd, 0x00, 0x00, 0x00, 0x09, 476 0x00, 0x1f, 0x00, 0x06, 0x99, 0xf8, 0x01, 0x00, 0x06, 477 0xf8, 0x21, 0x00, 0x06, 0x9e, 0x00, 0x00, 0x00, 0x09, 478 0x00, 0x00, 0x00, 0x09, 0xf0, 0x00, 0x00, 0x00, 0x0a, 479 0x00, 0x00, 0x01, 0x00, 0x01, 0xf7, 0xbf, 0x00, 0x0a, 480 0x07, 0xe0, 0x00, 0x06, 0xee, 0xf8, 0x01, 0x00, 0x06, 481 0xf7, 0xe1, 0x00, 0x06, 0xe2, 0x00, 0x00, 0x00, 0x0a, 482 0x00, 0x00, 0x00, 0x0a, 0x34, 0x00, 0x00, 0x00, 0x0a, 483 0xff, 0xe1, 0x00, 0x06, 0xee, 0x07, 0xff, 0x00, 0x06, 484 0x07, 0xdf, 0x00, 0x06, 0xe5, 0x00, 0x00, 0x00, 0x0a, 485 0x00, 0x00, 0x00, 0x0a, 0x67, 0x00, 0x00, 0x00, 0x0a, 486 0x00, 0x00, 0x00, 0x0a, 0x89, 0x00, 0x00, 0x00, 0x0a, 487 0x00, 0x00, 0x01, 0x01, 0x22, 0x00, 0x00, 0x05, 0x01, 488 0x00, 0x00, 0x08, 0x0a, 0xaa, 0x00, 0x00, 0x0c, 0x0a, 489 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 490 0x00, 0x00, 0x00, 0x0a, 0xbb, 0x08, 0x41, 0x00, 0x0a, 491 0x00, 0x00, 0x00, 0x0a, 0xcd, 0x10, 0x02, 0x00, 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