1 /* $OpenBSD: uhcireg.h,v 1.16 2016/12/27 14:41:45 kettenis Exp $ */ 2 /* $NetBSD: uhcireg.h,v 1.16 2002/07/11 21:14:29 augustss Exp $ */ 3 /* $FreeBSD: src/sys/dev/usb/uhcireg.h,v 1.12 1999/11/17 22:33:42 n_hibma Exp $ */ 4 5 /* 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Lennart Augustsson (lennart@augustsson.net) at 11 * Carlstedt Research & Technology. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _DEV_PCI_UHCIREG_H_ 36 #define _DEV_PCI_UHCIREG_H_ 37 38 /*** PCI config registers ***/ 39 40 #define PCI_USBREV 0x60 /* USB protocol revision */ 41 #define PCI_USBREV_MASK 0xff 42 #define PCI_USBREV_PRE_1_0 0x00 43 #define PCI_USBREV_1_0 0x10 44 #define PCI_USBREV_1_1 0x11 45 46 #define PCI_LEGSUP 0xc0 /* Legacy Support register */ 47 #define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */ 48 49 #define PCI_CBIO 0x20 /* configuration base IO */ 50 51 #define PCI_INTERFACE_UHCI 0x00 52 53 /*** UHCI registers ***/ 54 55 #define UHCI_CMD 0x00 56 #define UHCI_CMD_RS 0x0001 57 #define UHCI_CMD_HCRESET 0x0002 58 #define UHCI_CMD_GRESET 0x0004 59 #define UHCI_CMD_EGSM 0x0008 60 #define UHCI_CMD_FGR 0x0010 61 #define UHCI_CMD_SWDBG 0x0020 62 #define UHCI_CMD_CF 0x0040 63 #define UHCI_CMD_MAXP 0x0080 64 65 #define UHCI_STS 0x02 66 #define UHCI_STS_USBINT 0x0001 67 #define UHCI_STS_USBEI 0x0002 68 #define UHCI_STS_RD 0x0004 69 #define UHCI_STS_HSE 0x0008 70 #define UHCI_STS_HCPE 0x0010 71 #define UHCI_STS_HCH 0x0020 72 #define UHCI_STS_ALLINTRS 0x003f 73 74 #define UHCI_INTR 0x04 75 #define UHCI_INTR_TOCRCIE 0x0001 76 #define UHCI_INTR_RIE 0x0002 77 #define UHCI_INTR_IOCE 0x0004 78 #define UHCI_INTR_SPIE 0x0008 79 80 #define UHCI_FRNUM 0x06 81 #define UHCI_FRNUM_MASK 0x03ff 82 83 84 #define UHCI_FLBASEADDR 0x08 85 86 #define UHCI_SOF 0x0c 87 #define UHCI_SOF_MASK 0x7f 88 89 #define UHCI_PORTSC1 0x010 90 #define UHCI_PORTSC2 0x012 91 #define UHCI_PORTSC_CCS 0x0001 92 #define UHCI_PORTSC_CSC 0x0002 93 #define UHCI_PORTSC_PE 0x0004 94 #define UHCI_PORTSC_POEDC 0x0008 95 #define UHCI_PORTSC_LS 0x0030 96 #define UHCI_PORTSC_LS_SHIFT 4 97 #define UHCI_PORTSC_RD 0x0040 98 #define UHCI_PORTSC_LSDA 0x0100 99 #define UHCI_PORTSC_PR 0x0200 100 #define UHCI_PORTSC_OCI 0x0400 101 #define UHCI_PORTSC_OCIC 0x0800 102 #define UHCI_PORTSC_SUSP 0x1000 103 104 #define URWMASK(x) \ 105 ((x) & (UHCI_PORTSC_SUSP | UHCI_PORTSC_PR | UHCI_PORTSC_RD | UHCI_PORTSC_PE)) 106 107 #define UHCI_FRAMELIST_COUNT 1024 108 #define UHCI_FRAMELIST_ALIGN 4096 109 110 #define UHCI_TD_ALIGN 16 111 #define UHCI_QH_ALIGN 16 112 113 typedef u_int32_t uhci_physaddr_t; 114 #define UHCI_PTR_T 0x00000001 115 #define UHCI_PTR_TD 0x00000000 116 #define UHCI_PTR_QH 0x00000002 117 #define UHCI_PTR_VF 0x00000004 118 119 /* 120 * Wait this long after a QH has been removed. This gives that HC a 121 * chance to stop looking at it before it's recycled. 122 */ 123 #define UHCI_QH_REMOVE_DELAY 5 124 125 /* 126 * The Queue Heads and Transfer Descriptors are accessed 127 * by both the CPU and the USB controller which run 128 * concurrently. This means that they have to be accessed 129 * with great care. As long as the data structures are 130 * not linked into the controller's frame list they cannot 131 * be accessed by it and anything goes. As soon as a 132 * TD is accessible by the controller it "owns" the td_status 133 * field; it will not be written by the CPU. Similarly 134 * the controller "owns" the qh_elink field. 135 */ 136 137 struct uhci_td { 138 uhci_physaddr_t td_link; 139 u_int32_t td_status; 140 #define UHCI_TD_GET_ACTLEN(s) (((s) + 1) & 0x3ff) 141 #define UHCI_TD_ZERO_ACTLEN(t) ((t) | 0x3ff) 142 #define UHCI_TD_BITSTUFF 0x00020000 143 #define UHCI_TD_CRCTO 0x00040000 144 #define UHCI_TD_NAK 0x00080000 145 #define UHCI_TD_BABBLE 0x00100000 146 #define UHCI_TD_DBUFFER 0x00200000 147 #define UHCI_TD_STALLED 0x00400000 148 #define UHCI_TD_ACTIVE 0x00800000 149 #define UHCI_TD_IOC 0x01000000 150 #define UHCI_TD_IOS 0x02000000 151 #define UHCI_TD_LS 0x04000000 152 #define UHCI_TD_GET_ERRCNT(s) (((s) >> 27) & 3) 153 #define UHCI_TD_SET_ERRCNT(n) ((n) << 27) 154 #define UHCI_TD_SPD 0x20000000 155 u_int32_t td_token; 156 #define UHCI_TD_PID_IN 0x00000069 157 #define UHCI_TD_PID_OUT 0x000000e1 158 #define UHCI_TD_PID_SETUP 0x0000002d 159 #define UHCI_TD_GET_PID(s) ((s) & 0xff) 160 #define UHCI_TD_SET_DEVADDR(a) ((a) << 8) 161 #define UHCI_TD_GET_DEVADDR(s) (((s) >> 8) & 0x7f) 162 #define UHCI_TD_SET_ENDPT(e) (((e)&0xf) << 15) 163 #define UHCI_TD_GET_ENDPT(s) (((s) >> 15) & 0xf) 164 #define UHCI_TD_SET_DT(t) ((t) << 19) 165 #define UHCI_TD_GET_DT(s) (((s) >> 19) & 1) 166 #define UHCI_TD_SET_MAXLEN(l) (((uint32_t)(l)-1) << 21) 167 #define UHCI_TD_GET_MAXLEN(s) ((((s) >> 21) + 1) & 0x7ff) 168 #define UHCI_TD_MAXLEN_MASK 0xffe00000 169 u_int32_t td_buffer; 170 }; 171 172 #define UHCI_TD_ERROR (UHCI_TD_BITSTUFF|UHCI_TD_CRCTO|UHCI_TD_BABBLE|UHCI_TD_DBUFFER|UHCI_TD_STALLED) 173 174 #define UHCI_TD_SETUP(len, endp, dev) (UHCI_TD_SET_MAXLEN(len) | \ 175 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_SETUP) 176 #define UHCI_TD_OUT(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \ 177 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | \ 178 UHCI_TD_PID_OUT | UHCI_TD_SET_DT(dt)) 179 #define UHCI_TD_IN(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \ 180 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_IN | \ 181 UHCI_TD_SET_DT(dt)) 182 183 struct uhci_qh { 184 uhci_physaddr_t qh_hlink; 185 uhci_physaddr_t qh_elink; 186 }; 187 188 #endif /* _DEV_PCI_UHCIREG_H_ */ 189