1 /* @(#)i386-opcode.h 6.2 (Berkeley) 03/16/91 2 3 Modified for Berkeley Unix by Donn Seeley, donn@okeeffe.berkeley.edu */ 4 5 /* i386-opcode.h -- Intel 80386 opcode table 6 Copyright (C) 1989, Free Software Foundation. 7 8 This file is part of GAS, the GNU Assembler. 9 10 GAS is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 1, or (at your option) 13 any later version. 14 15 GAS is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GAS; see the file COPYING. If not, write to 22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 23 24 template i386_optab[] = { 25 26 #define _ None 27 /* move instructions */ 28 { "mov", 2, 0xa0, _, DW|NoModrm, Disp32, Acc, 0 }, 29 { "mov", 2, 0x88, _, DW|Modrm, Reg, Reg|Mem, 0 }, 30 { "mov", 2, 0xb0, _, ShortFormW, Imm, Reg, 0 }, 31 { "mov", 2, 0xc6, _, W|Modrm, Imm, Reg|Mem, 0 }, 32 { "mov", 2, 0x8c, _, D|Modrm, SReg3|SReg2, Reg16|Mem16, 0 }, 33 /* move to/from control debug registers */ 34 { "mov", 2, 0x0f20, _, D|Modrm, Control, Reg32, 0}, 35 { "mov", 2, 0x0f21, _, D|Modrm, Debug, Reg32, 0}, 36 { "mov", 2, 0x0f24, _, D|Modrm, Test, Reg32, 0}, 37 38 /* move with sign extend */ 39 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid 40 conflict with the "movs" string move instruction. Thus, 41 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0}, 42 is not kosher; we must seperate the two instructions. */ 43 {"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg32, 0}, 44 {"movsbw", 2, 0x660fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16, 0}, 45 {"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0}, 46 47 /* move with zero extend */ 48 {"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0}, 49 {"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0}, 50 51 /* push instructions */ 52 {"push", 1, 0x50, _, ShortForm, WordReg,0,0 }, 53 {"push", 1, 0xff, 0x6, Modrm, WordReg|WordMem, 0, 0 }, 54 {"push", 1, 0x6a, _, NoModrm, Imm8S, 0, 0}, 55 {"push", 1, 0x68, _, NoModrm, Imm32, 0, 0}, 56 {"push", 1, 0x06, _, Seg2ShortForm, SReg2,0,0 }, 57 {"push", 1, 0x0fa0, _, Seg3ShortForm, SReg3,0,0 }, 58 /* push all */ 59 {"pusha", 0, 0x60, _, NoModrm, 0, 0, 0 }, 60 61 /* pop instructions */ 62 {"pop", 1, 0x58, _, ShortForm, WordReg,0,0 }, 63 {"pop", 1, 0x8f, 0x0, Modrm, WordReg|WordMem, 0, 0 }, 64 #define POP_SEG_SHORT 0x7 65 {"pop", 1, 0x07, _, Seg2ShortForm, SReg2,0,0 }, 66 {"pop", 1, 0x0fa1, _, Seg3ShortForm, SReg3,0,0 }, 67 /* pop all */ 68 {"popa", 0, 0x61, _, NoModrm, 0, 0, 0 }, 69 70 /* xchg exchange instructions 71 xchg commutes: we allow both operand orders */ 72 {"xchg", 2, 0x90, _, ShortForm, WordReg, Acc, 0 }, 73 {"xchg", 2, 0x90, _, ShortForm, Acc, WordReg, 0 }, 74 {"xchg", 2, 0x86, _, W|Modrm, Reg, Reg|Mem, 0 }, 75 {"xchg", 2, 0x86, _, W|Modrm, Reg|Mem, Reg, 0 }, 76 77 /* in/out from ports */ 78 {"in", 2, 0xe4, _, W|NoModrm, Imm8, Acc, 0 }, 79 {"in", 2, 0xec, _, W|NoModrm, InOutPortReg, Acc, 0 }, 80 {"out", 2, 0xe6, _, W|NoModrm, Acc, Imm8, 0 }, 81 {"out", 2, 0xee, _, W|NoModrm, Acc, InOutPortReg, 0 }, 82 83 /* load effective address */ 84 {"lea", 2, 0x8d, _, Modrm, WordMem, WordReg, 0 }, 85 86 /* load segment registers from memory */ 87 {"lds", 2, 0xc5, _, Modrm, Mem, Reg32, 0}, 88 {"les", 2, 0xc4, _, Modrm, Mem, Reg32, 0}, 89 {"lfs", 2, 0x0fb4, _, Modrm, Mem, Reg32, 0}, 90 {"lgs", 2, 0x0fb5, _, Modrm, Mem, Reg32, 0}, 91 {"lss", 2, 0x0fb2, _, Modrm, Mem, Reg32, 0}, 92 93 /* flags register instructions */ 94 {"clc", 0, 0xf8, _, NoModrm, 0, 0, 0}, 95 {"cld", 0, 0xfc, _, NoModrm, 0, 0, 0}, 96 {"cli", 0, 0xfa, _, NoModrm, 0, 0, 0}, 97 {"clts", 0, 0x0f06, _, NoModrm, 0, 0, 0}, 98 {"cmc", 0, 0xf5, _, NoModrm, 0, 0, 0}, 99 {"lahf", 0, 0x9f, _, NoModrm, 0, 0, 0}, 100 {"sahf", 0, 0x9e, _, NoModrm, 0, 0, 0}, 101 {"pushf", 0, 0x9c, _, NoModrm, 0, 0, 0}, 102 {"popf", 0, 0x9d, _, NoModrm, 0, 0, 0}, 103 {"stc", 0, 0xf9, _, NoModrm, 0, 0, 0}, 104 {"std", 0, 0xfd, _, NoModrm, 0, 0, 0}, 105 {"sti", 0, 0xfb, _, NoModrm, 0, 0, 0}, 106 107 {"add", 2, 0x0, _, DW|Modrm, Reg, Reg|Mem, 0}, 108 {"add", 2, 0x83, 0, Modrm, Imm8S, WordReg|WordMem, 0}, 109 {"add", 2, 0x4, _, W|NoModrm, Imm, Acc, 0}, 110 {"add", 2, 0x80, 0, W|Modrm, Imm, Reg|Mem, 0}, 111 112 {"inc", 1, 0x40, _, ShortForm, WordReg, 0, 0}, 113 {"inc", 1, 0xfe, 0, W|Modrm, Reg|Mem, 0, 0}, 114 115 {"sub", 2, 0x28, _, DW|Modrm, Reg, Reg|Mem, 0}, 116 {"sub", 2, 0x83, 5, Modrm, Imm8S, WordReg|WordMem, 0}, 117 {"sub", 2, 0x2c, _, W|NoModrm, Imm, Acc, 0}, 118 {"sub", 2, 0x80, 5, W|Modrm, Imm, Reg|Mem, 0}, 119 120 {"dec", 1, 0x48, _, ShortForm, WordReg, 0, 0}, 121 {"dec", 1, 0xfe, 1, W|Modrm, Reg|Mem, 0, 0}, 122 123 {"sbb", 2, 0x18, _, DW|Modrm, Reg, Reg|Mem, 0}, 124 {"sbb", 2, 0x83, 3, Modrm, Imm8S, WordReg|WordMem, 0}, 125 {"sbb", 2, 0x1c, _, W|NoModrm, Imm, Acc, 0}, 126 {"sbb", 2, 0x80, 3, W|Modrm, Imm, Reg|Mem, 0}, 127 128 {"cmp", 2, 0x38, _, DW|Modrm, Reg, Reg|Mem, 0}, 129 {"cmp", 2, 0x83, 7, Modrm, Imm8S, WordReg|WordMem, 0}, 130 {"cmp", 2, 0x3c, _, W|NoModrm, Imm, Acc, 0}, 131 {"cmp", 2, 0x80, 7, W|Modrm, Imm, Reg|Mem, 0}, 132 133 {"test", 2, 0x84, _, W|Modrm, Reg|Mem, Reg, 0}, 134 {"test", 2, 0x84, _, W|Modrm, Reg, Reg|Mem, 0}, 135 {"test", 2, 0xa8, _, W|NoModrm, Imm, Acc, 0}, 136 {"test", 2, 0xf6, 0, W|Modrm, Imm, Reg|Mem, 0}, 137 138 {"and", 2, 0x20, _, DW|Modrm, Reg, Reg|Mem, 0}, 139 {"and", 2, 0x83, 4, Modrm, Imm8S, WordReg|WordMem, 0}, 140 {"and", 2, 0x24, _, W|NoModrm, Imm, Acc, 0}, 141 {"and", 2, 0x80, 4, W|Modrm, Imm, Reg|Mem, 0}, 142 143 {"or", 2, 0x08, _, DW|Modrm, Reg, Reg|Mem, 0}, 144 {"or", 2, 0x83, 1, Modrm, Imm8S, WordReg|WordMem, 0}, 145 {"or", 2, 0x0c, _, W|NoModrm, Imm, Acc, 0}, 146 {"or", 2, 0x80, 1, W|Modrm, Imm, Reg|Mem, 0}, 147 148 {"xor", 2, 0x30, _, DW|Modrm, Reg, Reg|Mem, 0}, 149 {"xor", 2, 0x83, 6, Modrm, Imm8S, WordReg|WordMem, 0}, 150 {"xor", 2, 0x34, _, W|NoModrm, Imm, Acc, 0}, 151 {"xor", 2, 0x80, 6, W|Modrm, Imm, Reg|Mem, 0}, 152 153 {"adc", 2, 0x10, _, DW|Modrm, Reg, Reg|Mem, 0}, 154 {"adc", 2, 0x83, 2, Modrm, Imm8S, WordReg|WordMem, 0}, 155 {"adc", 2, 0x14, _, W|NoModrm, Imm, Acc, 0}, 156 {"adc", 2, 0x80, 2, W|Modrm, Imm, Reg|Mem, 0}, 157 158 {"neg", 1, 0xf6, 3, W|Modrm, Reg|Mem, 0, 0}, 159 {"not", 1, 0xf6, 2, W|Modrm, Reg|Mem, 0, 0}, 160 161 {"aaa", 0, 0x37, _, NoModrm, 0, 0, 0}, 162 {"aas", 0, 0x3f, _, NoModrm, 0, 0, 0}, 163 {"daa", 0, 0x27, _, NoModrm, 0, 0, 0}, 164 {"das", 0, 0x2f, _, NoModrm, 0, 0, 0}, 165 {"aad", 0, 0xd50a, _, NoModrm, 0, 0, 0}, 166 {"aam", 0, 0xd40a, _, NoModrm, 0, 0, 0}, 167 168 /* conversion insns */ 169 /* conversion: intel naming */ 170 {"cbw", 0, 0x6698, _, NoModrm, 0, 0, 0}, 171 {"cwd", 0, 0x6699, _, NoModrm, 0, 0, 0}, 172 {"cwde", 0, 0x98, _, NoModrm, 0, 0, 0}, 173 {"cdq", 0, 0x99, _, NoModrm, 0, 0, 0}, 174 /* att naming */ 175 {"cbtw", 0, 0x6698, _, NoModrm, 0, 0, 0}, 176 {"cwtl", 0, 0x98, _, NoModrm, 0, 0, 0}, 177 {"cwtd", 0, 0x6699, _, NoModrm, 0, 0, 0}, 178 {"cltd", 0, 0x99, _, NoModrm, 0, 0, 0}, 179 180 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are 181 expanding 64-bit multiplies, and *cannot* be selected to accomplish 182 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) 183 These multiplies can only be selected with single opearnd forms. */ 184 {"mul", 1, 0xf6, 4, W|Modrm, Reg|Mem, 0, 0}, 185 {"imul", 1, 0xf6, 5, W|Modrm, Reg|Mem, 0, 0}, 186 187 188 189 190 /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields. 191 These instructions are exceptions: 'imul $2, %eax, %ecx' would put 192 '%eax' in the reg field and '%ecx' in the regmem field if we did not 193 switch them. */ 194 {"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0}, 195 {"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, Imm8S, WordReg|Mem, WordReg}, 196 {"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, Imm16|Imm32, WordReg|Mem, WordReg}, 197 /* 198 imul with 2 operands mimicks imul with 3 by puting register both 199 in i.rm.reg & i.rm.regmem fields 200 */ 201 {"imul", 2, 0x6b, _, Modrm|imulKludge, Imm8S, WordReg, 0}, 202 {"imul", 2, 0x69, _, Modrm|imulKludge, Imm16|Imm32, WordReg, 0}, 203 {"div", 1, 0xf6, 6, W|Modrm, Reg|Mem, 0, 0}, 204 {"div", 2, 0xf6, 6, W|Modrm, Reg|Mem, Acc, 0}, 205 {"idiv", 1, 0xf6, 7, W|Modrm, Reg|Mem, 0, 0}, 206 {"idiv", 2, 0xf6, 7, W|Modrm, Reg|Mem, Acc, 0}, 207 208 {"rol", 2, 0xd0, 0, W|Modrm, Imm1, Reg|Mem, 0}, 209 {"rol", 2, 0xc0, 0, W|Modrm, Imm8, Reg|Mem, 0}, 210 {"rol", 2, 0xd2, 0, W|Modrm, ShiftCount, Reg|Mem, 0}, 211 {"rol", 1, 0xd0, 0, W|Modrm, Reg|Mem, 0, 0}, 212 213 {"ror", 2, 0xd0, 1, W|Modrm, Imm1, Reg|Mem, 0}, 214 {"ror", 2, 0xc0, 1, W|Modrm, Imm8, Reg|Mem, 0}, 215 {"ror", 2, 0xd2, 1, W|Modrm, ShiftCount, Reg|Mem, 0}, 216 {"ror", 1, 0xd0, 1, W|Modrm, Reg|Mem, 0, 0}, 217 218 {"rcl", 2, 0xd0, 2, W|Modrm, Imm1, Reg|Mem, 0}, 219 {"rcl", 2, 0xc0, 2, W|Modrm, Imm8, Reg|Mem, 0}, 220 {"rcl", 2, 0xd2, 2, W|Modrm, ShiftCount, Reg|Mem, 0}, 221 {"rcl", 1, 0xd0, 2, W|Modrm, Reg|Mem, 0, 0}, 222 223 {"rcr", 2, 0xd0, 3, W|Modrm, Imm1, Reg|Mem, 0}, 224 {"rcr", 2, 0xc0, 3, W|Modrm, Imm8, Reg|Mem, 0}, 225 {"rcr", 2, 0xd2, 3, W|Modrm, ShiftCount, Reg|Mem, 0}, 226 {"rcr", 1, 0xd0, 3, W|Modrm, Reg|Mem, 0, 0}, 227 228 {"sal", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0}, 229 {"sal", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0}, 230 {"sal", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0}, 231 {"sal", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0}, 232 {"shl", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0}, 233 {"shl", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0}, 234 {"shl", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0}, 235 {"shl", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0}, 236 237 {"shld", 3, 0x0fa4, _, Modrm, Imm8, WordReg, WordReg|Mem}, 238 {"shld", 3, 0x0fa5, _, Modrm, ShiftCount, WordReg, WordReg|Mem}, 239 240 {"shr", 2, 0xd0, 5, W|Modrm, Imm1, Reg|Mem, 0}, 241 {"shr", 2, 0xc0, 5, W|Modrm, Imm8, Reg|Mem, 0}, 242 {"shr", 2, 0xd2, 5, W|Modrm, ShiftCount, Reg|Mem, 0}, 243 {"shr", 1, 0xd0, 5, W|Modrm, Reg|Mem, 0, 0}, 244 245 {"shrd", 3, 0x0fac, _, Modrm, Imm8, WordReg, WordReg|Mem}, 246 {"shrd", 3, 0x0fad, _, Modrm, ShiftCount, WordReg, WordReg|Mem}, 247 248 {"sar", 2, 0xd0, 7, W|Modrm, Imm1, Reg|Mem, 0}, 249 {"sar", 2, 0xc0, 7, W|Modrm, Imm8, Reg|Mem, 0}, 250 {"sar", 2, 0xd2, 7, W|Modrm, ShiftCount, Reg|Mem, 0}, 251 {"sar", 1, 0xd0, 7, W|Modrm, Reg|Mem, 0, 0}, 252 253 /* control transfer instructions */ 254 #define CALL_PC_RELATIVE 0xe8 255 {"call", 1, 0xe8, _, JumpDword, Disp32, 0, 0}, 256 {"call", 1, 0xff, 2, Modrm, Reg|Mem|JumpAbsolute, 0, 0}, 257 #define CALL_FAR_IMMEDIATE 0x9a 258 {"lcall", 2, 0x9a, _, JumpInterSegment, Imm16, Imm32, 0}, 259 {"lcall", 1, 0xff, 3, Modrm, Mem, 0, 0}, 260 261 #define JUMP_PC_RELATIVE 0xeb 262 {"jmp", 1, 0xeb, _, Jump, Disp, 0, 0}, 263 {"jmp", 1, 0xff, 4, Modrm, Reg32|Mem|JumpAbsolute, 0, 0}, 264 #define JUMP_FAR_IMMEDIATE 0xea 265 {"ljmp", 2, 0xea, _, JumpInterSegment, Imm16, Imm32, 0}, 266 {"ljmp", 1, 0xff, 5, Modrm, Mem, 0, 0}, 267 268 {"ret", 0, 0xc3, _, NoModrm, 0, 0, 0}, 269 {"ret", 1, 0xc2, _, NoModrm, Imm16, 0, 0}, 270 {"lret", 0, 0xcb, _, NoModrm, 0, 0, 0}, 271 {"lret", 1, 0xca, _, NoModrm, Imm16, 0, 0}, 272 {"enter", 2, 0xc8, _, NoModrm, Imm16, Imm8, 0}, 273 {"leave", 0, 0xc9, _, NoModrm, 0, 0, 0}, 274 275 /* conditional jumps */ 276 {"jo", 1, 0x70, _, Jump, Disp, 0, 0}, 277 278 {"jno", 1, 0x71, _, Jump, Disp, 0, 0}, 279 280 {"jb", 1, 0x72, _, Jump, Disp, 0, 0}, 281 {"jc", 1, 0x72, _, Jump, Disp, 0, 0}, 282 {"jnae", 1, 0x72, _, Jump, Disp, 0, 0}, 283 284 {"jnb", 1, 0x73, _, Jump, Disp, 0, 0}, 285 {"jnc", 1, 0x73, _, Jump, Disp, 0, 0}, 286 {"jae", 1, 0x73, _, Jump, Disp, 0, 0}, 287 288 {"je", 1, 0x74, _, Jump, Disp, 0, 0}, 289 {"jz", 1, 0x74, _, Jump, Disp, 0, 0}, 290 291 {"jne", 1, 0x75, _, Jump, Disp, 0, 0}, 292 {"jnz", 1, 0x75, _, Jump, Disp, 0, 0}, 293 294 {"jbe", 1, 0x76, _, Jump, Disp, 0, 0}, 295 {"jna", 1, 0x76, _, Jump, Disp, 0, 0}, 296 297 {"jnbe", 1, 0x77, _, Jump, Disp, 0, 0}, 298 {"ja", 1, 0x77, _, Jump, Disp, 0, 0}, 299 300 {"js", 1, 0x78, _, Jump, Disp, 0, 0}, 301 302 {"jns", 1, 0x79, _, Jump, Disp, 0, 0}, 303 304 {"jp", 1, 0x7a, _, Jump, Disp, 0, 0}, 305 {"jpe", 1, 0x7a, _, Jump, Disp, 0, 0}, 306 307 {"jnp", 1, 0x7b, _, Jump, Disp, 0, 0}, 308 {"jpo", 1, 0x7b, _, Jump, Disp, 0, 0}, 309 310 {"jl", 1, 0x7c, _, Jump, Disp, 0, 0}, 311 {"jnge", 1, 0x7c, _, Jump, Disp, 0, 0}, 312 313 {"jnl", 1, 0x7d, _, Jump, Disp, 0, 0}, 314 {"jge", 1, 0x7d, _, Jump, Disp, 0, 0}, 315 316 {"jle", 1, 0x7e, _, Jump, Disp, 0, 0}, 317 {"jng", 1, 0x7e, _, Jump, Disp, 0, 0}, 318 319 {"jnle", 1, 0x7f, _, Jump, Disp, 0, 0}, 320 {"jg", 1, 0x7f, _, Jump, Disp, 0, 0}, 321 322 /* these turn into pseudo operations when disp is larger than 8 bits */ 323 #define IS_JUMP_ON_CX_ZERO(o) \ 324 (o == 0x67e3) 325 #define IS_JUMP_ON_ECX_ZERO(o) \ 326 (o == 0xe3) 327 328 {"jcxz", 1, 0x67e3, _, JumpByte, Disp, 0, 0}, 329 {"jecxz", 1, 0xe3, _, JumpByte, Disp, 0, 0}, 330 331 #define IS_LOOP_ECX_TIMES(o) \ 332 (o == 0xe2 || o == 0xe1 || o == 0xe0) 333 334 {"loop", 1, 0xe2, _, JumpByte, Disp, 0, 0}, 335 336 {"loopz", 1, 0xe1, _, JumpByte, Disp, 0, 0}, 337 {"loope", 1, 0xe1, _, JumpByte, Disp, 0, 0}, 338 339 {"loopnz", 1, 0xe0, _, JumpByte, Disp, 0, 0}, 340 {"loopne", 1, 0xe0, _, JumpByte, Disp, 0, 0}, 341 342 /* set byte on flag instructions */ 343 {"seto", 1, 0x0f90, 0, Modrm, Reg8|Mem, 0, 0}, 344 345 {"setno", 1, 0x0f91, 0, Modrm, Reg8|Mem, 0, 0}, 346 347 {"setb", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0}, 348 {"setnae", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0}, 349 350 {"setnb", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0}, 351 {"setae", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0}, 352 353 {"sete", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0}, 354 {"setz", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0}, 355 356 {"setne", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0}, 357 {"setnz", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0}, 358 359 {"setbe", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0}, 360 {"setna", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0}, 361 362 {"setnbe", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0}, 363 {"seta", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0}, 364 365 {"sets", 1, 0x0f98, 0, Modrm, Reg8|Mem, 0, 0}, 366 367 {"setns", 1, 0x0f99, 0, Modrm, Reg8|Mem, 0, 0}, 368 369 {"setp", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0}, 370 {"setpe", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0}, 371 372 {"setnp", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0}, 373 {"setpo", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0}, 374 375 {"setl", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0}, 376 {"setnge", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0}, 377 378 {"setnl", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0}, 379 {"setge", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0}, 380 381 {"setle", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0}, 382 {"setng", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0}, 383 384 {"setnle", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0}, 385 {"setg", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0}, 386 387 #define IS_STRING_INSTRUCTION(o) \ 388 ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \ 389 (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \ 390 (o) == 0xd7) 391 392 /* string manipulation */ 393 {"cmps", 0, 0xa6, _, W|NoModrm, 0, 0, 0}, 394 {"ins", 0, 0x6c, _, W|NoModrm, 0, 0, 0}, 395 {"outs", 0, 0x6e, _, W|NoModrm, 0, 0, 0}, 396 {"lods", 0, 0xac, _, W|NoModrm, 0, 0, 0}, 397 {"movs", 0, 0xa4, _, W|NoModrm, 0, 0, 0}, 398 {"scas", 0, 0xae, _, W|NoModrm, 0, 0, 0}, 399 {"stos", 0, 0xaa, _, W|NoModrm, 0, 0, 0}, 400 {"xlat", 0, 0xd7, _, NoModrm, 0, 0, 0}, 401 402 /* bit manipulation */ 403 {"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0}, 404 {"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0}, 405 {"bt", 2, 0x0fa3, _, Modrm, Reg, Reg|Mem, 0}, 406 {"bt", 2, 0x0fba, 4, Modrm, Imm8, Reg|Mem, 0}, 407 {"btc", 2, 0x0fbb, _, Modrm, Reg, Reg|Mem, 0}, 408 {"btc", 2, 0x0fba, 7, Modrm, Imm8, Reg|Mem, 0}, 409 {"btr", 2, 0x0fb3, _, Modrm, Reg, Reg|Mem, 0}, 410 {"btr", 2, 0x0fba, 6, Modrm, Imm8, Reg|Mem, 0}, 411 {"bts", 2, 0x0fab, _, Modrm, Reg, Reg|Mem, 0}, 412 {"bts", 2, 0x0fba, 5, Modrm, Imm8, Reg|Mem, 0}, 413 414 /* interrupts & op. sys insns */ 415 /* See i386.c for conversion of 'int $3' into the special int 3 insn. */ 416 #define INT_OPCODE 0xcd 417 #define INT3_OPCODE 0xcc 418 {"int", 1, 0xcd, _, NoModrm, Imm8, 0, 0}, 419 {"int3", 0, 0xcc, _, NoModrm, 0, 0, 0}, 420 {"into", 0, 0xce, _, NoModrm, 0, 0, 0}, 421 {"iret", 0, 0xcf, _, NoModrm, 0, 0, 0}, 422 423 {"boundl", 2, 0x62, _, Modrm, Reg32, Mem, 0}, 424 {"boundw", 2, 0x6662, _, Modrm, Reg16, Mem, 0}, 425 426 {"hlt", 0, 0xf4, _, NoModrm, 0, 0, 0}, 427 {"wait", 0, 0x9b, _, NoModrm, 0, 0, 0}, 428 /* nop is actually 'xchgl %eax, %eax' */ 429 {"nop", 0, 0x90, _, NoModrm, 0, 0, 0}, 430 431 /* protection control */ 432 {"arpl", 2, 0x63, _, Modrm, Reg16, Reg16|Mem, 0}, 433 {"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0}, 434 {"lgdt", 1, 0x0f01, 2, Modrm, Mem, 0, 0}, 435 {"lidt", 1, 0x0f01, 3, Modrm, Mem, 0, 0}, 436 {"lldt", 1, 0x0f00, 2, Modrm, WordReg|Mem, 0, 0}, 437 {"lmsw", 1, 0x0f01, 6, Modrm, WordReg|Mem, 0, 0}, 438 {"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0}, 439 {"ltr", 1, 0x0f00, 3, Modrm, WordReg|Mem, 0, 0}, 440 441 {"sgdt", 1, 0x0f01, 0, Modrm, Mem, 0, 0}, 442 {"sidt", 1, 0x0f01, 1, Modrm, Mem, 0, 0}, 443 {"sldt", 1, 0x0f00, 0, Modrm, WordReg|Mem, 0, 0}, 444 {"smsw", 1, 0x0f01, 4, Modrm, WordReg|Mem, 0, 0}, 445 {"str", 1, 0x0f00, 1, Modrm, Reg16|Mem, 0, 0}, 446 447 {"verr", 1, 0x0f00, 4, Modrm, WordReg|Mem, 0, 0}, 448 {"verw", 1, 0x0f00, 5, Modrm, WordReg|Mem, 0, 0}, 449 450 /* floating point instructions */ 451 452 /* load */ 453 {"fld", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */ 454 {"flds", 1, 0xd9, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem float */ 455 {"fildl", 1, 0xdb, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem word */ 456 {"fldl", 1, 0xdd, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem double */ 457 {"fldl", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */ 458 {"filds", 1, 0xdf, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem dword */ 459 {"fildq", 1, 0xdf, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem qword */ 460 {"fldt", 1, 0xdb, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem efloat */ 461 {"fbld", 1, 0xdf, 4, Modrm, Mem, 0, 0}, /* %st0 <-- mem bcd */ 462 463 /* store (no pop) */ 464 {"fst", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */ 465 {"fsts", 1, 0xd9, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem float */ 466 {"fistl", 1, 0xdb, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */ 467 {"fstl", 1, 0xdd, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem double */ 468 {"fstl", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */ 469 {"fists", 1, 0xdf, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem word */ 470 471 /* store (with pop) */ 472 {"fstp", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */ 473 {"fstps", 1, 0xd9, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem float */ 474 {"fistpl", 1, 0xdb, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem word */ 475 {"fstpl", 1, 0xdd, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem double */ 476 {"fstpl", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */ 477 {"fistps", 1, 0xdf, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */ 478 {"fistpq", 1, 0xdf, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem qword */ 479 {"fstpt", 1, 0xdb, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem efloat */ 480 {"fbstp", 1, 0xdf, 6, Modrm, Mem, 0, 0}, /* %st0 --> mem bcd */ 481 482 /* exchange %st<n> with %st0 */ 483 {"fxch", 1, 0xd9c8, _, ShortForm, FloatReg, 0, 0}, 484 485 /* comparison (without pop) */ 486 {"fcom", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0}, 487 {"fcoms", 1, 0xd8, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem float */ 488 {"ficoml", 1, 0xda, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem word */ 489 {"fcoml", 1, 0xdc, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem double */ 490 {"fcoml", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0}, 491 {"ficoms", 1, 0xde, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */ 492 493 /* comparison (with pop) */ 494 {"fcomp", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0}, 495 {"fcomps", 1, 0xd8, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem float */ 496 {"ficompl", 1, 0xda, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem word */ 497 {"fcompl", 1, 0xdc, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem double */ 498 {"fcompl", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0}, 499 {"ficomps", 1, 0xde, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */ 500 {"fcompp", 0, 0xded9, _, NoModrm, 0, 0, 0}, /* compare %st0, %st1 & pop twice */ 501 502 /* unordered comparison (with pop) */ 503 {"fucom", 1, 0xdde0, _, ShortForm, FloatReg, 0, 0}, 504 {"fucomp", 1, 0xdde8, _, ShortForm, FloatReg, 0, 0}, 505 {"fucompp", 0, 0xdae9, _, NoModrm, 0, 0, 0}, /* ucompare %st0, %st1 & pop twice */ 506 507 {"ftst", 0, 0xd9e4, _, NoModrm, 0, 0, 0}, /* test %st0 */ 508 {"fxam", 0, 0xd9e5, _, NoModrm, 0, 0, 0}, /* examine %st0 */ 509 510 /* load constants into %st0 */ 511 {"fld1", 0, 0xd9e8, _, NoModrm, 0, 0, 0}, /* %st0 <-- 1.0 */ 512 {"fldl2t", 0, 0xd9e9, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(10) */ 513 {"fldl2e", 0, 0xd9ea, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(e) */ 514 {"fldpi", 0, 0xd9eb, _, NoModrm, 0, 0, 0}, /* %st0 <-- pi */ 515 {"fldlg2", 0, 0xd9ec, _, NoModrm, 0, 0, 0}, /* %st0 <-- log10(2) */ 516 {"fldln2", 0, 0xd9ed, _, NoModrm, 0, 0, 0}, /* %st0 <-- ln(2) */ 517 {"fldz", 0, 0xd9ee, _, NoModrm, 0, 0, 0}, /* %st0 <-- 0.0 */ 518 519 /* arithmetic */ 520 521 /* add */ 522 {"fadd", 1, 0xd8c0, _, ShortForm, FloatReg, 0, 0}, 523 {"fadd", 2, 0xd8c0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0}, 524 {"fadd", 0, 0xdcc1, _, NoModrm, 0, 0, 0}, /* alias for fadd %st, %st(1) */ 525 {"faddp", 1, 0xdac0, _, ShortForm, FloatReg, 0, 0}, 526 {"faddp", 2, 0xdac0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0}, 527 {"faddp", 0, 0xdec1, _, NoModrm, 0, 0, 0}, /* alias for faddp %st, %st(1) */ 528 {"fadds", 1, 0xd8, 0, Modrm, Mem, 0, 0}, 529 {"fiaddl", 1, 0xda, 0, Modrm, Mem, 0, 0}, 530 {"faddl", 1, 0xdc, 0, Modrm, Mem, 0, 0}, 531 {"fiadds", 1, 0xde, 0, Modrm, Mem, 0, 0}, 532 533 /* sub */ 534 /* Note: intel has decided that certain of these operations are reversed 535 in assembler syntax. */ 536 {"fsub", 1, 0xd8e0, _, ShortForm, FloatReg, 0, 0}, 537 {"fsub", 2, 0xd8e0, _, ShortForm, FloatReg, FloatAcc, 0}, 538 #ifdef NON_BROKEN_OPCODES 539 {"fsub", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0}, 540 #else 541 {"fsub", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0}, 542 #endif 543 {"fsub", 0, 0xdce1, _, NoModrm, 0, 0, 0}, 544 {"fsubp", 1, 0xdae0, _, ShortForm, FloatReg, 0, 0}, 545 {"fsubp", 2, 0xdae0, _, ShortForm, FloatReg, FloatAcc, 0}, 546 #ifdef NON_BROKEN_OPCODES 547 {"fsubp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0}, 548 #else 549 {"fsubp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0}, 550 #endif 551 {"fsubp", 0, 0xdee1, _, NoModrm, 0, 0, 0}, 552 {"fsubs", 1, 0xd8, 4, Modrm, Mem, 0, 0}, 553 {"fisubl", 1, 0xda, 4, Modrm, Mem, 0, 0}, 554 {"fsubl", 1, 0xdc, 4, Modrm, Mem, 0, 0}, 555 {"fisubs", 1, 0xde, 4, Modrm, Mem, 0, 0}, 556 557 /* sub reverse */ 558 {"fsubr", 1, 0xd8e8, _, ShortForm, FloatReg, 0, 0}, 559 {"fsubr", 2, 0xd8e8, _, ShortForm, FloatReg, FloatAcc, 0}, 560 #ifdef NON_BROKEN_OPCODES 561 {"fsubr", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0}, 562 #else 563 {"fsubr", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0}, 564 #endif 565 {"fsubr", 0, 0xdce9, _, NoModrm, 0, 0, 0}, 566 {"fsubrp", 1, 0xdae8, _, ShortForm, FloatReg, 0, 0}, 567 {"fsubrp", 2, 0xdae8, _, ShortForm, FloatReg, FloatAcc, 0}, 568 #ifdef NON_BROKEN_OPCODES 569 {"fsubrp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0}, 570 #else 571 {"fsubrp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0}, 572 #endif 573 {"fsubrp", 0, 0xdee9, _, NoModrm, 0, 0, 0}, 574 {"fsubrs", 1, 0xd8, 5, Modrm, Mem, 0, 0}, 575 {"fisubrl", 1, 0xda, 5, Modrm, Mem, 0, 0}, 576 {"fsubrl", 1, 0xdc, 5, Modrm, Mem, 0, 0}, 577 {"fisubrs", 1, 0xde, 5, Modrm, Mem, 0, 0}, 578 579 /* mul */ 580 {"fmul", 1, 0xd8c8, _, ShortForm, FloatReg, 0, 0}, 581 {"fmul", 2, 0xd8c8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0}, 582 {"fmul", 0, 0xdcc9, _, NoModrm, 0, 0, 0}, 583 {"fmulp", 1, 0xdac8, _, ShortForm, FloatReg, 0, 0}, 584 {"fmulp", 2, 0xdac8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0}, 585 {"fmulp", 0, 0xdec9, _, NoModrm, 0, 0, 0}, 586 {"fmuls", 1, 0xd8, 1, Modrm, Mem, 0, 0}, 587 {"fimull", 1, 0xda, 1, Modrm, Mem, 0, 0}, 588 {"fmull", 1, 0xdc, 1, Modrm, Mem, 0, 0}, 589 {"fimuls", 1, 0xde, 1, Modrm, Mem, 0, 0}, 590 591 /* div */ 592 /* Note: intel has decided that certain of these operations are reversed 593 in assembler syntax. */ 594 {"fdiv", 1, 0xd8f0, _, ShortForm, FloatReg, 0, 0}, 595 {"fdiv", 2, 0xd8f0, _, ShortForm, FloatReg, FloatAcc, 0}, 596 #ifdef NON_BROKEN_OPCODES 597 {"fdiv", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0}, 598 #else 599 {"fdiv", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0}, 600 #endif 601 {"fdiv", 0, 0xdcf1, _, NoModrm, 0, 0, 0}, 602 {"fdivp", 1, 0xdaf0, _, ShortForm, FloatReg, 0, 0}, 603 {"fdivp", 2, 0xdaf0, _, ShortForm, FloatReg, FloatAcc, 0}, 604 #ifdef NON_BROKEN_OPCODES 605 {"fdivp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0}, 606 #else 607 {"fdivp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0}, 608 #endif 609 {"fdivp", 0, 0xdef1, _, NoModrm, 0, 0, 0}, 610 {"fdivs", 1, 0xd8, 6, Modrm, Mem, 0, 0}, 611 {"fidivl", 1, 0xda, 6, Modrm, Mem, 0, 0}, 612 {"fdivl", 1, 0xdc, 6, Modrm, Mem, 0, 0}, 613 {"fidivs", 1, 0xde, 6, Modrm, Mem, 0, 0}, 614 615 /* div reverse */ 616 {"fdivr", 1, 0xd8f8, _, ShortForm, FloatReg, 0, 0}, 617 {"fdivr", 2, 0xd8f8, _, ShortForm, FloatReg, FloatAcc, 0}, 618 #ifdef NON_BROKEN_OPCODES 619 {"fdivr", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0}, 620 #else 621 {"fdivr", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0}, 622 #endif 623 {"fdivr", 0, 0xdcf9, _, NoModrm, 0, 0, 0}, 624 {"fdivrp", 1, 0xdaf8, _, ShortForm, FloatReg, 0, 0}, 625 {"fdivrp", 2, 0xdaf8, _, ShortForm, FloatReg, FloatAcc, 0}, 626 #ifdef NON_BROKEN_OPCODES 627 {"fdivrp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0}, 628 #else 629 {"fdivrp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0}, 630 #endif 631 {"fdivrp", 0, 0xdef9, _, NoModrm, 0, 0, 0}, 632 {"fdivrs", 1, 0xd8, 7, Modrm, Mem, 0, 0}, 633 {"fidivrl", 1, 0xda, 7, Modrm, Mem, 0, 0}, 634 {"fdivrl", 1, 0xdc, 7, Modrm, Mem, 0, 0}, 635 {"fidivrs", 1, 0xde, 7, Modrm, Mem, 0, 0}, 636 637 {"f2xm1", 0, 0xd9f0, _, NoModrm, 0, 0, 0}, 638 {"fyl2x", 0, 0xd9f1, _, NoModrm, 0, 0, 0}, 639 {"fptan", 0, 0xd9f2, _, NoModrm, 0, 0, 0}, 640 {"fpatan", 0, 0xd9f3, _, NoModrm, 0, 0, 0}, 641 {"fxtract", 0, 0xd9f4, _, NoModrm, 0, 0, 0}, 642 {"fprem1", 0, 0xd9f5, _, NoModrm, 0, 0, 0}, 643 {"fdecstp", 0, 0xd9f6, _, NoModrm, 0, 0, 0}, 644 {"fincstp", 0, 0xd9f7, _, NoModrm, 0, 0, 0}, 645 {"fprem", 0, 0xd9f8, _, NoModrm, 0, 0, 0}, 646 {"fyl2xp1", 0, 0xd9f9, _, NoModrm, 0, 0, 0}, 647 {"fsqrt", 0, 0xd9fa, _, NoModrm, 0, 0, 0}, 648 {"fsincos", 0, 0xd9fb, _, NoModrm, 0, 0, 0}, 649 {"frndint", 0, 0xd9fc, _, NoModrm, 0, 0, 0}, 650 {"fscale", 0, 0xd9fd, _, NoModrm, 0, 0, 0}, 651 {"fsin", 0, 0xd9fe, _, NoModrm, 0, 0, 0}, 652 {"fcos", 0, 0xd9ff, _, NoModrm, 0, 0, 0}, 653 654 {"fchs", 0, 0xd9e0, _, NoModrm, 0, 0, 0}, 655 {"fabs", 0, 0xd9e1, _, NoModrm, 0, 0, 0}, 656 657 /* processor control */ 658 {"fninit", 0, 0xdbe3, _, NoModrm, 0, 0, 0}, 659 {"finit", 0, 0xdbe3, _, NoModrm, 0, 0, 0}, 660 {"fldcw", 1, 0xd9, 5, Modrm, Mem, 0, 0}, 661 {"fnstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0}, 662 {"fstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0}, 663 {"fnstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0}, 664 {"fnstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0}, 665 {"fnstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0}, 666 {"fstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0}, 667 {"fstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0}, 668 {"fstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0}, 669 {"fnclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0}, 670 {"fclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0}, 671 /* 672 We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor 673 instructions; i'm not sure how to add them or how they are different. 674 My 386/387 book offers no details about this. 675 */ 676 {"fnstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0}, 677 {"fstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0}, 678 {"fldenv", 1, 0xd9, 4, Modrm, Mem, 0, 0}, 679 {"fnsave", 1, 0xdd, 6, Modrm, Mem, 0, 0}, 680 {"fsave", 1, 0xdd, 6, Modrm, Mem, 0, 0}, 681 {"frstor", 1, 0xdd, 4, Modrm, Mem, 0, 0}, 682 683 {"ffree", 1, 0xddc0, _, ShortForm, FloatReg, 0, 0}, 684 {"fnop", 0, 0xd9d0, _, NoModrm, 0, 0, 0}, 685 {"fwait", 0, 0x9b, _, NoModrm, 0, 0, 0}, 686 687 /* 688 opcode prefixes; we allow them as seperate insns too 689 (see prefix table below) 690 */ 691 {"aword", 0, 0x67, _, NoModrm, 0, 0, 0}, 692 {"word", 0, 0x66, _, NoModrm, 0, 0, 0}, 693 {"lock", 0, 0xf0, _, NoModrm, 0, 0, 0}, 694 {"cs", 0, 0x2e, _, NoModrm, 0, 0, 0}, 695 {"ds", 0, 0x3e, _, NoModrm, 0, 0, 0}, 696 {"es", 0, 0x26, _, NoModrm, 0, 0, 0}, 697 {"fs", 0, 0x64, _, NoModrm, 0, 0, 0}, 698 {"gs", 0, 0x65, _, NoModrm, 0, 0, 0}, 699 {"ss", 0, 0x36, _, NoModrm, 0, 0, 0}, 700 {"rep", 0, 0xf3, _, NoModrm, 0, 0, 0}, 701 {"repe", 0, 0xf3, _, NoModrm, 0, 0, 0}, 702 { "repne", 0, 0xf2, _, NoModrm, 0, 0, 0}, 703 704 {"", 0, 0, 0, 0, 0, 0, 0} /* sentinal */ 705 }; 706 #undef _ 707 708 template *i386_optab_end 709 = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]); 710 711 /* 386 register table */ 712 713 reg_entry i386_regtab[] = { 714 /* 8 bit regs */ 715 {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2}, 716 {"bl", Reg8, 3}, 717 {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7}, 718 /* 16 bit regs */ 719 {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3}, 720 {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7}, 721 /* 32 bit regs */ 722 {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3}, 723 {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7}, 724 /* segment registers */ 725 {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2}, 726 {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5}, 727 /* control registers */ 728 {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3}, 729 /* debug registers */ 730 {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2}, 731 {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7}, 732 /* test registers */ 733 {"tr6", Test, 6}, {"tr7", Test, 7}, 734 /* float registers */ 735 {"st(0)", FloatReg|FloatAcc, 0}, 736 {"st", FloatReg|FloatAcc, 0}, 737 {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, 738 {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, 739 {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7} 740 }; 741 742 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ 743 744 reg_entry *i386_regtab_end 745 = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]); 746 747 /* segment stuff */ 748 seg_entry cs = { "cs", 0x2e }; 749 seg_entry ds = { "ds", 0x3e }; 750 seg_entry ss = { "ss", 0x36 }; 751 seg_entry es = { "es", 0x26 }; 752 seg_entry fs = { "fs", 0x64 }; 753 seg_entry gs = { "gs", 0x65 }; 754 seg_entry null = { "", 0x0 }; 755 756 /* 757 This table is used to store the default segment register implied by all 758 possible memory addressing modes. 759 It is indexed by the mode & modrm entries of the modrm byte as follows: 760 index = (mode<<3) | modrm; 761 */ 762 seg_entry *one_byte_segment_defaults[] = { 763 /* mode 0 */ 764 &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds, 765 /* mode 1 */ 766 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, 767 /* mode 2 */ 768 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, 769 /* mode 3 --- not a memory reference; never referenced */ 770 }; 771 772 seg_entry *two_byte_segment_defaults[] = { 773 /* mode 0 */ 774 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 775 /* mode 1 */ 776 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 777 /* mode 2 */ 778 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 779 /* mode 3 --- not a memory reference; never referenced */ 780 }; 781 782 prefix_entry i386_prefixtab[] = { 783 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing 784 * (How is this useful?) */ 785 #define WORD_PREFIX_OPCODE 0x66 786 { "data16", 0x66 }, /* operand size prefix */ 787 { "lock", 0xf0 }, /* bus lock prefix */ 788 { "wait", 0x9b }, /* wait for coprocessor */ 789 { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */ 790 { "es", 0x26 }, { "fs", 0x64 }, 791 { "gs", 0x65 }, { "ss", 0x36 }, 792 /* REPE & REPNE used to detect rep/repne with a non-string instruction */ 793 #define REPNE 0xf2 794 #define REPE 0xf3 795 { "rep", 0xf3 }, { "repe", 0xf3 }, /* repeat string instructions */ 796 { "repne", 0xf2 } 797 }; 798 799 prefix_entry *i386_prefixtab_end 800 = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]); 801 802