1;;- Machine description for GNU compiler 2;;- Motorola 68000 Version 3;; Copyright (C) 1987, 1988 Free Software Foundation, Inc. 4 5;; This file is part of GNU CC. 6 7;; GNU CC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 2, or (at your option) 10;; any later version. 11 12;; GNU CC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GNU CC; see the file COPYING. If not, write to 19;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20 21 22;;- instruction definitions 23 24;;- @@The original PO technology requires these to be ordered by speed, 25;;- @@ so that assigner will pick the fastest. 26 27;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 28 29;;- When naming insn's (operand 0 of define_insn) be careful about using 30;;- names from other targets machine descriptions. 31 32;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 33;;- updates for most instructions. 34 35;;- Operand classes for the register allocator: 36;;- 'a' one of the address registers can be used. 37;;- 'd' one of the data registers can be used. 38;;- 'f' one of the m68881 registers can be used 39;;- 'r' either a data or an address register can be used. 40;;- 'x' if one of the Sun FPA registers 41;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15). 42 43;;- Immediate Floating point operator constraints 44;;- 'G' a floating point constant that is *NOT* one of the standard 45;; 68881 constant values (to force calling output_move_const_double 46;; to get it from rom if it is a 68881 constant). 47;;- 'H' one of the standard FPA constant values 48;; 49;; See the functions standard_XXX_constant_p in output-m68k.c for more 50;; info. 51 52;;- Immediate integer operand constraints: 53;;- 'I' 1 .. 8 54;;- 'J' -32768 .. 32767 55;;- 'K' all integers EXCEPT -128 .. 127 56;;- 'L' -8 .. -1 57 58;;- Assembler specs: 59;;- "%." size separator ("." or "") move%.l d0,d1 60;;- "%#" immediate separator ("#" or "") move%.l %#0,d0 61;;- "%-" push operand "sp@-" move%.l d0,%- 62;;- "%+" pop operand "sp@+" move%.l d0,%+ 63;;- "%@" top of stack "sp@" move%.l d0,%@ 64;;- "%!" fpcr register 65;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1 66;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1 67 68;;- Information about 68040 port. 69 70;;- The 68040 executes all 68030 and 68881/2 instructions, but some must 71;;- be emulated in software by the OS. It is faster to avoid these 72;;- instructions and issue a library call rather than trapping into 73;;- the kernel. The affected instructions are fintrz and fscale. The 74;;- TARGET_68040 flag turns the use of the opcodes off. 75 76;;- The '040 also implements a set of new floating-point instructions 77;;- which specify the rounding precision in the opcode. This finally 78;;- permit the 68k series to be truly IEEE compliant, and solves all 79;;- issues of excess precision accumulating in the extended registers. 80;;- By default, GCC does not use these instructions, since such code will 81;;- not run on an '030. To use these instructions, use the -m68040-only 82;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY, 83;;- you can make these instructions the default. 84 85;;- These new instructions aren't directly in the md. They are brought 86;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather 87;;- than "". 88 89 90;;- FPA port explanation: 91 92;;- Usage of the Sun FPA and the 68881 together 93 94;;- The current port of gcc to the sun fpa disallows use of the m68881 95;;- instructions completely if code is targeted for the fpa. This is 96;;- for the following reasons: 97 98;;- 1) Expressing the preference hierarchy (ie. use the fpa if you 99;;- can, the 68881 otherwise, and data registers only if you are 100;;- forced to it) is a bitch with the current constraint scheme, 101;;- especially since it would have to work for any combination of 102;;- -mfpa, -m68881. 103 104;;- 2) There are no instructions to move between the two types of 105;;- registers; the stack must be used as an intermediary. 106 107;;- It could indeed be done; I think the best way would be to have 108;;- separate patterns for TARGET_FPA (which implies a 68881), 109;;- TARGET_68881, and no floating point co-processor. Use 110;;- define_expands for all of the named instruction patterns, and 111;;- include code in the FPA instruction to deal with the 68881 with 112;;- preferences specifically set to favor the fpa. Some of this has 113;;- already been done: 114;;- 115;;- 1) Separation of most of the patterns out into a TARGET_FPA 116;;- case and a TARGET_68881 case (the exceptions are the patterns 117;;- which would need one define_expand and three define_insn's under 118;;- it (with a lot of duplicate code between them) to replace the 119;;- current single define_insn. These are mov{[ds]f,[ds]i} and the 120;;- first two patterns in the md. 121;;- 122;;- Some would still have to be done: 123;;- 124;;- 1) Add code to the fpa patterns which correspond to 68881 125;;- patterns to deal with the 68881 case (including preferences!). 126;;- What you might actually do here is combine the fpa and 68881 code 127;;- back together into one pattern for those instructions where it's 128;;- absolutely necessary and save yourself some duplicate code. I'm 129;;- not completely sure as to whether you could get away with doing 130;;- this only for the mov* insns, or if you'd have to do it for all 131;;- named insns. 132;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle 133;;- moving between fpa regs and 68881 regs. 134 135;;- Since the fpa is more powerful than the 68881 and also has more 136;;- registers, and since I think the resultant md would be medium ugly 137;;- (lot's of duplicate code, ugly constraint strings), I elected not 138;;- to do this change. 139 140;;- Another reason why someone *might* want to do the change is to 141;;- control which register classes are accessed in a slightly cleaner 142;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in 143;;- the internals manual. 144 145;;- Yet another reason why someone might want to do this change is to 146;;- allow use of some of the 68881 insns which have no equivalent on 147;;- the fpa. The sqrt instruction comes fairly quickly to mind. 148 149;;- If this is ever done, don't forget to change sun3.h so that 150;;- it *will* define __HAVE_68881__ when the FPA is in use. 151 152;;- Condition code hack 153 154;;- When a floating point compare is done in the fpa, the resulting 155;;- condition codes are left in the fpastatus register. The values in 156;;- this register must be moved into the 68000 cc register before any 157;;- jump is executed. Once this has been done, regular jump 158;;- instructions are fine (ie. floating point jumps are not necessary. 159;;- They are only done if the cc is in the 68881). 160 161;;- The instructions that move the fpastatus register to the 68000 162;;- register clobber a data register (the move cannot be done direct). 163;;- These instructions might be bundled either with the compare 164;;- instruction, or the branch instruction. If we were using both the 165;;- fpa and the 68881 together, we would wish to only mark the 166;;- register clobbered if we were doing the compare in the fpa, but I 167;;- think that that decision (whether to clobber the register or not) 168;;- must be done before register allocation (makes sense) and hence we 169;;- can't know if the floating point compare will be done in the fpa 170;;- or the fp. So whenever we are asked for code that uses the fpa, 171;;- we will mark a data register as clobbered. This is reasonable, as 172;;- almost all floating point compare operations done with fpa code 173;;- enabled will be done in the fpa. It's even more reasonable since 174;;- we decided to make the 68881 and the fpa mutually exclusive. 175 176;;- We place to code to move the fpastatus register inside of a 177;;- define_expand so that we can do it conditionally based on whether 178;;- we are targeting an fpa or not. 179 180;;- This still leaves us with the question of where we wish to put the 181;;- code to move the fpastatus reg. If we put it in the compare 182;;- instruction, we can restrict the clobbering of the register to 183;;- floating point compares, but we can't take advantage of floating 184;;- point subtracts & etc. that alter the fpastatus register. If we 185;;- put it in the branch instruction, all branches compiled with fpa 186;;- code enabled will clobber a data register, but we will be able to 187;;- take advantage of fpa subtracts. This balance favors putting the 188;;- code in with the compare instruction. 189 190;;- Note that if some enterprising hacker should decide to switch 191;;- this, he'll need to modify the code in NOTICE_UPDATE_CC. 192 193;;- Usage of the top 16 fpa registers 194 195;;- The only locations which we may transfer fpa registers 16-31 from 196;;- or to are the fpa registers 0-15. (68000 registers and memory 197;;- locations are impossible). This causes problems in gcc, which 198;;- assumes that mov?? instructions require no additional registers 199;;- (see section 11.7) and since floating point moves *must* be 200;;- supported into general registers (see section 12.3 under 201;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere. 202 203;;- My solution was to reserve fpa0 for moves into or out of these top 204;;- 16 registers and to disparage the choice to reload into or out of 205;;- these registers as much as I could. That alternative is always 206;;- last in the list, so it will not be used unless all else fails. I 207;;- will note that according to my current information, sun's compiler 208;;- doesn't use these top 16 registers at all. 209 210;;- There is another possible way to do it. I *believe* that if you 211;;- make absolutely sure that the code will not be executed in the 212;;- reload pass, you can support the mov?? names with define_expands 213;;- which require new registers. This may be possible by the 214;;- appropriate juggling of constraints. I may come back to this later. 215 216;;- Usage of constant RAM 217 218;;- This has been handled correctly (I believe) but the way I've done 219;;- it could use a little explanation. The constant RAM can only be 220;;- accessed when the instruction is in "command register" mode. 221;;- "command register" mode means that no accessing of memory or the 222;;- 68000 registers is being done. This can be expressed easily in 223;;- constraints, so generally the mode of the instruction is 224;;- determined by a branch off of which_alternative. In outputting 225;;- instructions, a 'w' means to output an access to the constant ram 226;;- (if the arg is CONST_DOUBLE and is one of the available 227;;- constants), and 'x' means to output a register pair (if the arg is 228;;- a 68000 register) and a 'y' is the combination of the above two 229;;- processes. You use a 'y' in two operand DF instructions where you 230;;- *know* the other operand is an fpa register, you use an 'x' in DF 231;;- instructions where the arg might be a 68000 register and the 232;;- instruction is *not* in "command register" mode, and you use a 'w' 233;;- in two situations: 1) The instruction *is* in command register 234;;- mode (and hence won't be accessing 68000 registers), or 2) The 235;;- instruction is a two operand SF instruction where you know the 236;;- other operand is an fpa register. 237 238;;- Optimization issues 239 240;;- I actually think that I've included all of the fpa instructions 241;;- that should be included. Note that if someone is interested in 242;;- doing serious floating point work on the sun fpa, I would advise 243;;- the use of the "asm" instruction in gcc to allow you to use the 244;;- sin, cos, and exponential functions on the fpa board. 245 246;;- END FPA Explanation Section. 247 248 249;;- Some of these insn's are composites of several m68000 op codes. 250;;- The assembler (or final @@??) insures that the appropriate one is 251;;- selected. 252 253(define_insn "" 254 [(set (match_operand:DF 0 "push_operand" "=m") 255 (match_operand:DF 1 "general_operand" "ro<>fyE"))] 256 "" 257 "* 258{ 259 if (FP_REG_P (operands[1])) 260 return \"fmove%.d %f1,%0\"; 261 if (FPA_REG_P (operands[1])) 262 return \"fpmove%.d %1, %x0\"; 263 return output_move_double (operands); 264}") 265 266(define_insn "" 267 [(set (match_operand:DI 0 "push_operand" "=m") 268 (match_operand:DI 1 "general_operand" "ro<>Fy"))] 269 "" 270 "* 271{ 272 return output_move_double (operands); 273}") 274 275;; We don't want to allow a constant operand for test insns because 276;; (set (cc0) (const_int foo)) has no mode information. Such insns will 277;; be folded while optimizing anyway. 278(define_insn "tstsi" 279 [(set (cc0) 280 (match_operand:SI 0 "nonimmediate_operand" "rm"))] 281 "" 282 "* 283{ 284#ifdef ISI_OV 285 /* ISI's assembler fails to handle tstl a0. */ 286 if (! ADDRESS_REG_P (operands[0])) 287#else 288 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) 289#endif 290 return \"tst%.l %0\"; 291 /* If you think that the 68020 does not support tstl a0, 292 reread page B-167 of the 68020 manual more carefully. */ 293 /* On an address reg, cmpw may replace cmpl. */ 294#ifdef SGS_CMP_ORDER 295 return \"cmp%.w %0,%#0\"; 296#else 297 return \"cmp%.w %#0,%0\"; 298#endif 299}") 300 301;; This can't use an address register, because comparisons 302;; with address registers as second operand always test the whole word. 303(define_insn "tsthi" 304 [(set (cc0) 305 (match_operand:HI 0 "nonimmediate_operand" "dm"))] 306 "" 307 "tst%.w %0") 308 309(define_insn "tstqi" 310 [(set (cc0) 311 (match_operand:QI 0 "nonimmediate_operand" "dm"))] 312 "" 313 "tst%.b %0") 314 315(define_expand "tstsf" 316 [(set (cc0) 317 (match_operand:SF 0 "general_operand" ""))] 318 "TARGET_68881 || TARGET_FPA" 319 " 320{ 321 if (TARGET_FPA) 322 { 323 emit_insn (gen_tstsf_fpa (operands[0])); 324 DONE; 325 } 326}") 327 328(define_insn "tstsf_fpa" 329 [(set (cc0) 330 (match_operand:SF 0 "general_operand" "xmdF")) 331 (clobber (match_scratch:SI 1 "=d"))] 332 "TARGET_FPA" 333 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc") 334 335(define_insn "" 336 [(set (cc0) 337 (match_operand:SF 0 "general_operand" "fdm"))] 338 "TARGET_68881" 339 "* 340{ 341 cc_status.flags = CC_IN_68881; 342 if (FP_REG_P (operands[0])) 343 return \"ftst%.x %0\"; 344 return \"ftst%.s %0\"; 345}") 346 347(define_expand "tstdf" 348 [(set (cc0) 349 (match_operand:DF 0 "general_operand" ""))] 350 "TARGET_68881 || TARGET_FPA" 351 " 352{ 353 if (TARGET_FPA) 354 { 355 emit_insn (gen_tstsf_fpa (operands[0])); 356 DONE; 357 } 358}") 359 360(define_insn "tstdf_fpa" 361 [(set (cc0) 362 (match_operand:DF 0 "general_operand" "xrmF")) 363 (clobber (match_scratch:SI 1 "=d"))] 364 "TARGET_FPA" 365 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc") 366 367(define_insn "" 368 [(set (cc0) 369 (match_operand:DF 0 "general_operand" "fm"))] 370 "TARGET_68881" 371 "* 372{ 373 cc_status.flags = CC_IN_68881; 374 if (FP_REG_P (operands[0])) 375 return \"ftst%.x %0\"; 376 return \"ftst%.d %0\"; 377}") 378 379;; compare instructions. 380 381;; A composite of the cmp, cmpa, & cmpi m68000 op codes. 382(define_insn "cmpsi" 383 [(set (cc0) 384 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>") 385 (match_operand:SI 1 "general_operand" "mr,Ksr,>")))] 386 "" 387 "* 388{ 389 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 390 return \"cmpm%.l %1,%0\"; 391 if (REG_P (operands[1]) 392 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) 393 { cc_status.flags |= CC_REVERSED; 394#ifdef SGS_CMP_ORDER 395 return \"cmp%.l %d1,%d0\"; 396#else 397 return \"cmp%.l %d0,%d1\"; 398#endif 399 } 400#ifdef SGS_CMP_ORDER 401 return \"cmp%.l %d0,%d1\"; 402#else 403 return \"cmp%.l %d1,%d0\"; 404#endif 405}") 406 407(define_insn "cmphi" 408 [(set (cc0) 409 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m") 410 (match_operand:HI 1 "general_operand" "d,rnm,m,n")))] 411 "" 412 "* 413{ 414 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 415 return \"cmpm%.w %1,%0\"; 416 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1])) 417 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) 418 { cc_status.flags |= CC_REVERSED; 419#ifdef SGS_CMP_ORDER 420 return \"cmp%.w %d1,%d0\"; 421#else 422 return \"cmp%.w %d0,%d1\"; 423#endif 424 } 425#ifdef SGS_CMP_ORDER 426 return \"cmp%.w %d0,%d1\"; 427#else 428 return \"cmp%.w %d1,%d0\"; 429#endif 430}") 431 432(define_insn "cmpqi" 433 [(set (cc0) 434 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>") 435 (match_operand:QI 1 "general_operand" "dm,nd,>")))] 436 "" 437 "* 438{ 439 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 440 return \"cmpm%.b %1,%0\"; 441 if (REG_P (operands[1]) 442 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) 443 { cc_status.flags |= CC_REVERSED; 444#ifdef SGS_CMP_ORDER 445 return \"cmp%.b %d1,%d0\"; 446#else 447 return \"cmp%.b %d0,%d1\"; 448#endif 449 } 450#ifdef SGS_CMP_ORDER 451 return \"cmp%.b %d0,%d1\"; 452#else 453 return \"cmp%.b %d1,%d0\"; 454#endif 455}") 456 457(define_expand "cmpdf" 458 [(set (cc0) 459 (compare (match_operand:DF 0 "general_operand" "") 460 (match_operand:DF 1 "general_operand" "")))] 461 "TARGET_68881 || TARGET_FPA" 462 " 463{ 464 if (TARGET_FPA) 465 { 466 emit_insn (gen_cmpdf_fpa (operands[0], operands[1])); 467 DONE; 468 } 469}") 470 471(define_insn "cmpdf_fpa" 472 [(set (cc0) 473 (compare (match_operand:DF 0 "general_operand" "x,y") 474 (match_operand:DF 1 "general_operand" "xH,rmF"))) 475 (clobber (match_scratch:SI 2 "=d,d"))] 476 "TARGET_FPA" 477 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc") 478 479(define_insn "" 480 [(set (cc0) 481 (compare (match_operand:DF 0 "general_operand" "f,mG") 482 (match_operand:DF 1 "general_operand" "fmG,f")))] 483 "TARGET_68881" 484 "* 485{ 486 cc_status.flags = CC_IN_68881; 487#ifdef SGS_CMP_ORDER 488 if (REG_P (operands[0])) 489 { 490 if (REG_P (operands[1])) 491 return \"fcmp%.x %0,%1\"; 492 else 493 return \"fcmp%.d %0,%f1\"; 494 } 495 cc_status.flags |= CC_REVERSED; 496 return \"fcmp%.d %1,%f0\"; 497#else 498 if (REG_P (operands[0])) 499 { 500 if (REG_P (operands[1])) 501 return \"fcmp%.x %1,%0\"; 502 else 503 return \"fcmp%.d %f1,%0\"; 504 } 505 cc_status.flags |= CC_REVERSED; 506 return \"fcmp%.d %f0,%1\"; 507#endif 508}") 509 510(define_expand "cmpsf" 511 [(set (cc0) 512 (compare (match_operand:SF 0 "general_operand" "") 513 (match_operand:SF 1 "general_operand" "")))] 514 "TARGET_68881 || TARGET_FPA" 515 " 516{ 517 if (TARGET_FPA) 518 { 519 emit_insn (gen_cmpsf_fpa (operands[0], operands[1])); 520 DONE; 521 } 522}") 523 524(define_insn "cmpsf_fpa" 525 [(set (cc0) 526 (compare (match_operand:SF 0 "general_operand" "x,y") 527 (match_operand:SF 1 "general_operand" "xH,rmF"))) 528 (clobber (match_scratch:SI 2 "=d,d"))] 529 "TARGET_FPA" 530 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc") 531 532(define_insn "" 533 [(set (cc0) 534 (compare (match_operand:SF 0 "general_operand" "f,mdG") 535 (match_operand:SF 1 "general_operand" "fmdG,f")))] 536 "TARGET_68881" 537 "* 538{ 539 cc_status.flags = CC_IN_68881; 540#ifdef SGS_CMP_ORDER 541 if (FP_REG_P (operands[0])) 542 { 543 if (FP_REG_P (operands[1])) 544 return \"fcmp%.x %0,%1\"; 545 else 546 return \"fcmp%.s %0,%f1\"; 547 } 548 cc_status.flags |= CC_REVERSED; 549 return \"fcmp%.s %1,%f0\"; 550#else 551 if (FP_REG_P (operands[0])) 552 { 553 if (FP_REG_P (operands[1])) 554 return \"fcmp%.x %1,%0\"; 555 else 556 return \"fcmp%.s %f1,%0\"; 557 } 558 cc_status.flags |= CC_REVERSED; 559 return \"fcmp%.s %f0,%1\"; 560#endif 561}") 562 563;; Recognizers for btst instructions. 564 565(define_insn "" 566 [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do") 567 (const_int 1) 568 (minus:SI (const_int 7) 569 (match_operand:SI 1 "general_operand" "di"))))] 570 "" 571 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") 572 573(define_insn "" 574 [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d") 575 (const_int 1) 576 (minus:SI (const_int 31) 577 (match_operand:SI 1 "general_operand" "di"))))] 578 "" 579 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") 580 581;; The following two patterns are like the previous two 582;; except that they use the fact that bit-number operands 583;; are automatically masked to 3 or 5 bits. 584 585(define_insn "" 586 [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do") 587 (const_int 1) 588 (minus:SI (const_int 7) 589 (and:SI 590 (match_operand:SI 1 "general_operand" "d") 591 (const_int 7)))))] 592 "" 593 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") 594 595(define_insn "" 596 [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d") 597 (const_int 1) 598 (minus:SI (const_int 31) 599 (and:SI 600 (match_operand:SI 1 "general_operand" "d") 601 (const_int 31)))))] 602 "" 603 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") 604 605;; Nonoffsettable mem refs are ok in this one pattern 606;; since we don't try to adjust them. 607(define_insn "" 608 [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md") 609 (const_int 1) 610 (match_operand:SI 1 "general_operand" "i")))] 611 "GET_CODE (operands[1]) == CONST_INT 612 && (unsigned) INTVAL (operands[1]) < 8" 613 "* 614{ 615 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1])); 616 return output_btst (operands, operands[1], operands[0], insn, 7); 617}") 618 619(define_insn "" 620 [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do") 621 (const_int 1) 622 (match_operand:SI 1 "general_operand" "i")))] 623 "GET_CODE (operands[1]) == CONST_INT" 624 "* 625{ 626 if (GET_CODE (operands[0]) == MEM) 627 { 628 operands[0] = adj_offsettable_operand (operands[0], 629 INTVAL (operands[1]) / 8); 630 operands[1] = gen_rtx (CONST_INT, VOIDmode, 631 7 - INTVAL (operands[1]) % 8); 632 return output_btst (operands, operands[1], operands[0], insn, 7); 633 } 634 operands[1] = gen_rtx (CONST_INT, VOIDmode, 635 31 - INTVAL (operands[1])); 636 return output_btst (operands, operands[1], operands[0], insn, 31); 637}") 638 639 640;; move instructions 641 642;; A special case in which it is not desirable 643;; to reload the constant into a data register. 644(define_insn "" 645 [(set (match_operand:SI 0 "push_operand" "=m") 646 (match_operand:SI 1 "general_operand" "J"))] 647 "GET_CODE (operands[1]) == CONST_INT 648 && INTVAL (operands[1]) >= -0x8000 649 && INTVAL (operands[1]) < 0x8000" 650 "* 651{ 652 if (operands[1] == const0_rtx) 653 return \"clr%.l %0\"; 654 return \"pea %a1\"; 655}") 656 657;This is never used. 658;(define_insn "swapsi" 659; [(set (match_operand:SI 0 "general_operand" "+r") 660; (match_operand:SI 1 "general_operand" "+r")) 661; (set (match_dup 1) (match_dup 0))] 662; "" 663; "exg %1,%0") 664 665;; Special case of fullword move when source is zero. 666;; The reason this is special is to avoid loading a zero 667;; into a data reg with moveq in order to store it elsewhere. 668 669(define_insn "" 670 [(set (match_operand:SI 0 "general_operand" "=g") 671 (const_int 0))] 672 ;; clr insns on 68000 read before writing. 673 ;; This isn't so on the 68010, but we have no alternative for it. 674 "(TARGET_68020 675 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))" 676 "* 677{ 678 if (ADDRESS_REG_P (operands[0])) 679 return \"sub%.l %0,%0\"; 680 /* moveq is faster on the 68000. */ 681 if (DATA_REG_P (operands[0]) && !TARGET_68020) 682#if defined(MOTOROLA) && !defined(CRDS) 683 return \"moveq%.l %#0,%0\"; 684#else 685 return \"moveq %#0,%0\"; 686#endif 687 return \"clr%.l %0\"; 688}") 689 690;; General case of fullword move. 691;; 692;; This is the main "hook" for PIC code. When generating 693;; PIC, movsi is responsible for determining when the source address 694;; needs PIC relocation and appropriately calling legitimize_pic_address 695;; to perform the actual relocation. 696;; 697;; In both the PIC and non-PIC cases the patterns generated will 698;; matched by the next define_insn. 699(define_expand "movsi" 700 [(set (match_operand:SI 0 "general_operand" "") 701 (match_operand:SI 1 "general_operand" ""))] 702 "" 703 " 704{ 705 if (flag_pic && symbolic_operand (operands[1], SImode)) 706 { 707 /* The source is an address which requires PIC relocation. 708 Call legitimize_pic_address with the source, mode, and a relocation 709 register (a new pseudo, or the final destination if reload_in_progress 710 is set). Then fall through normally */ 711 extern rtx legitimize_pic_address(); 712 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); 713 operands[1] = legitimize_pic_address (operands[1], SImode, temp); 714 } 715}") 716 717;; General case of fullword move. The register constraints 718;; force integer constants in range for a moveq to be reloaded 719;; if they are headed for memory. 720(define_insn "" 721 ;; Notes: make sure no alternative allows g vs g. 722 ;; We don't allow f-regs since fixed point cannot go in them. 723 ;; We do allow y and x regs since fixed point is allowed in them. 724 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m") 725 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))] 726 "" 727 "* 728{ 729 if (which_alternative == 3) 730 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\"; 731 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0])) 732 return \"fpmove%.l %x1,%x0\"; 733 if (GET_CODE (operands[1]) == CONST_INT) 734 { 735 if (operands[1] == const0_rtx 736 && (DATA_REG_P (operands[0]) 737 || GET_CODE (operands[0]) == MEM) 738 /* clr insns on 68000 read before writing. 739 This isn't so on the 68010, but we have no alternative for it. */ 740 && (TARGET_68020 741 || !(GET_CODE (operands[0]) == MEM 742 && MEM_VOLATILE_P (operands[0])))) 743 return \"clr%.l %0\"; 744 else if (DATA_REG_P (operands[0]) 745 && INTVAL (operands[1]) < 128 746 && INTVAL (operands[1]) >= -128) 747 { 748#if defined(MOTOROLA) && !defined(CRDS) 749 return \"moveq%.l %1,%0\"; 750#else 751 return \"moveq %1,%0\"; 752#endif 753 } 754#ifndef NO_ADDSUB_Q 755 else if (DATA_REG_P (operands[0]) 756 /* Do this with a moveq #N-8, dreg; addq #8,dreg */ 757 && INTVAL (operands[1]) < 136 758 && INTVAL (operands[1]) >= 128) 759 { 760 operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); 761#if defined(MOTOROLA) && !defined(CRDS) 762 return \"moveq%.l %1,%0\;addq%.w %#8,%0\"; 763#else 764 return \"moveq %1,%0\;addq%.w %#8,%0\"; 765#endif 766 } 767 else if (DATA_REG_P (operands[0]) 768 /* Do this with a moveq #N+8, dreg; subq #8,dreg */ 769 && INTVAL (operands[1]) < -128 770 && INTVAL (operands[1]) >= -136) 771 { 772 operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 8); 773#if defined(MOTOROLA) && !defined(CRDS) 774 return \"moveq%.l %1,%0;subq%.w %#8,%0\"; 775#else 776 return \"moveq %1,%0;subq%.w %#8,%0\"; 777#endif 778 } 779#endif 780 else if (DATA_REG_P (operands[0]) 781 /* If N is in the right range and is even, then use 782 moveq #N/2, dreg; addl dreg,dreg */ 783 && INTVAL (operands[1]) > 127 784 && INTVAL (operands[1]) <= 254 785 && INTVAL (operands[1]) % 2 == 0) 786 { 787 operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) / 2); 788#if defined(MOTOROLA) && !defined(CRDS) 789 return \"moveq%.l %1,%0\;add%.w %0,%0\"; 790#else 791 return \"moveq %1,%0\;add%.w %0,%0\"; 792#endif 793 } 794 else if (ADDRESS_REG_P (operands[0]) 795 && INTVAL (operands[1]) < 0x8000 796 && INTVAL (operands[1]) >= -0x8000) 797 return \"move%.w %1,%0\"; 798 else if (push_operand (operands[0], SImode) 799 && INTVAL (operands[1]) < 0x8000 800 && INTVAL (operands[1]) >= -0x8000) 801 return \"pea %a1\"; 802 } 803 else if ((GET_CODE (operands[1]) == SYMBOL_REF 804 || GET_CODE (operands[1]) == CONST) 805 && push_operand (operands[0], SImode)) 806 return \"pea %a1\"; 807 else if ((GET_CODE (operands[1]) == SYMBOL_REF 808 || GET_CODE (operands[1]) == CONST) 809 && ADDRESS_REG_P (operands[0])) 810 return \"lea %a1,%0\"; 811 return \"move%.l %1,%0\"; 812}") 813 814(define_insn "movhi" 815 [(set (match_operand:HI 0 "general_operand" "=g") 816 (match_operand:HI 1 "general_operand" "g"))] 817 "" 818 "* 819{ 820 if (GET_CODE (operands[1]) == CONST_INT) 821 { 822 if (operands[1] == const0_rtx 823 && (DATA_REG_P (operands[0]) 824 || GET_CODE (operands[0]) == MEM) 825 /* clr insns on 68000 read before writing. 826 This isn't so on the 68010, but we have no alternative for it. */ 827 && (TARGET_68020 828 || !(GET_CODE (operands[0]) == MEM 829 && MEM_VOLATILE_P (operands[0])))) 830 return \"clr%.w %0\"; 831 else if (DATA_REG_P (operands[0]) 832 && INTVAL (operands[1]) < 128 833 && INTVAL (operands[1]) >= -128) 834 { 835#if defined(MOTOROLA) && !defined(CRDS) 836 return \"moveq%.l %1,%0\"; 837#else 838 return \"moveq %1,%0\"; 839#endif 840 } 841 else if (INTVAL (operands[1]) < 0x8000 842 && INTVAL (operands[1]) >= -0x8000) 843 return \"move%.w %1,%0\"; 844 } 845 else if (CONSTANT_P (operands[1])) 846 return \"move%.l %1,%0\"; 847#ifndef SGS_NO_LI 848 /* Recognize the insn before a tablejump, one that refers 849 to a table of offsets. Such an insn will need to refer 850 to a label on the insn. So output one. Use the label-number 851 of the table of offsets to generate this label. */ 852 if (GET_CODE (operands[1]) == MEM 853 && GET_CODE (XEXP (operands[1], 0)) == PLUS 854 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF 855 || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF) 856 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS 857 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS) 858 { 859 rtx labelref; 860 if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF) 861 labelref = XEXP (XEXP (operands[1], 0), 0); 862 else 863 labelref = XEXP (XEXP (operands[1], 0), 1); 864#if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES) 865#ifdef SGS 866 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\", 867 CODE_LABEL_NUMBER (XEXP (labelref, 0))); 868#else /* not SGS */ 869 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\", 870 CODE_LABEL_NUMBER (XEXP (labelref, 0))); 871#endif /* not SGS */ 872#else /* SGS_SWITCH_TABLES or not MOTOROLA */ 873 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", 874 CODE_LABEL_NUMBER (XEXP (labelref, 0))); 875#ifdef SGS_SWITCH_TABLES 876 /* Set flag saying we need to define the symbol 877 LD%n (with value L%n-LI%n) at the end of the switch table. */ 878 switch_table_difference_label_flag = 1; 879#endif /* SGS_SWITCH_TABLES */ 880#endif /* SGS_SWITCH_TABLES or not MOTOROLA */ 881 } 882#endif /* SGS_NO_LI */ 883 return \"move%.w %1,%0\"; 884}") 885 886(define_insn "movstricthi" 887 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) 888 (match_operand:HI 1 "general_operand" "rmn"))] 889 "" 890 "* 891{ 892 if (GET_CODE (operands[1]) == CONST_INT) 893 { 894 if (operands[1] == const0_rtx 895 && (DATA_REG_P (operands[0]) 896 || GET_CODE (operands[0]) == MEM) 897 /* clr insns on 68000 read before writing. 898 This isn't so on the 68010, but we have no alternative for it. */ 899 && (TARGET_68020 900 || !(GET_CODE (operands[0]) == MEM 901 && MEM_VOLATILE_P (operands[0])))) 902 return \"clr%.w %0\"; 903 } 904 return \"move%.w %1,%0\"; 905}") 906 907(define_insn "movqi" 908 [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a") 909 (match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))] 910 "" 911 "* 912{ 913 rtx xoperands[4]; 914 915 /* This is probably useless, since it loses for pushing a struct 916 of several bytes a byte at a time. */ 917 if (GET_CODE (operands[0]) == MEM 918 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC 919 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx) 920 { 921 xoperands[1] = operands[1]; 922 xoperands[2] 923 = gen_rtx (MEM, QImode, 924 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx)); 925 /* Just pushing a byte puts it in the high byte of the halfword. */ 926 /* We must put it in the low-order, high-numbered byte. */ 927 output_asm_insn (\"move%.b %1,%-\;move%.b %@,%2\", xoperands); 928 return \"\"; 929 } 930 931 /* HACK Alert. This is a quick fix while RMS makes up his 932 mind about what he wants to do about this case. */ 933 934 /* if d0 is used in the address calculation, use d1 */ 935 if (refers_to_regno_p (0, 1, PATTERN (insn), NULL_PTR)) 936 { 937 /* Moving a byte into an address register is not possible. */ 938 /* Use d1 as an intermediate, but don't clobber its contents. */ 939 if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM) 940 return \"exg %/d1,%0\;move%.b %1,%/d1\;exg %/d1,%0\"; 941 /* Likewise for moving from an address reg. */ 942 if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM) 943 return \"exg %/d1,%1\;move%.b %/d1,%0\;exg %/d1,%1\"; 944 } 945 else 946 { 947 /* Moving a byte into an address register is not possible. */ 948 /* Use d0 as an intermediate, but don't clobber its contents. */ 949 if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM) 950 return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\"; 951 /* Likewise for moving from an address reg. */ 952 if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM) 953 return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\"; 954 } 955 956 /* clr and st insns on 68000 read before writing. 957 This isn't so on the 68010, but we have no alternative for it. */ 958 if (TARGET_68020 959 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) 960 { 961 if (operands[1] == const0_rtx) 962 return \"clr%.b %0\"; 963 if (GET_CODE (operands[1]) == CONST_INT 964 && INTVAL (operands[1]) == -1) 965 { 966 CC_STATUS_INIT; 967 return \"st %0\"; 968 } 969 } 970 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) 971 return \"move%.l %1,%0\"; 972 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) 973 return \"move%.w %1,%0\"; 974 return \"move%.b %1,%0\"; 975}") 976 977(define_insn "movstrictqi" 978 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) 979 (match_operand:QI 1 "general_operand" "dmn"))] 980 "" 981 "* 982{ 983 if (operands[1] == const0_rtx 984 /* clr insns on 68000 read before writing. 985 This isn't so on the 68010, but we have no alternative for it. */ 986 && (TARGET_68020 987 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) 988 return \"clr%.b %0\"; 989 return \"move%.b %1,%0\"; 990}") 991 992(define_insn "movsf" 993 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm") 994 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))] 995; [(set (match_operand:SF 0 "general_operand" "=rmf") 996; (match_operand:SF 1 "general_operand" "rmfF"))] 997 "" 998 "* 999{ 1000 if (which_alternative >= 4) 1001 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\"; 1002 if (FPA_REG_P (operands[0])) 1003 { 1004 if (FPA_REG_P (operands[1])) 1005 return \"fpmove%.s %x1,%x0\"; 1006 else if (GET_CODE (operands[1]) == CONST_DOUBLE) 1007 return output_move_const_single (operands); 1008 else if (FP_REG_P (operands[1])) 1009 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\"; 1010 return \"fpmove%.s %x1,%x0\"; 1011 } 1012 if (FPA_REG_P (operands[1])) 1013 { 1014 if (FP_REG_P (operands[0])) 1015 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\"; 1016 else 1017 return \"fpmove%.s %x1,%x0\"; 1018 } 1019 if (FP_REG_P (operands[0])) 1020 { 1021 if (FP_REG_P (operands[1])) 1022 return \"f%$move%.x %1,%0\"; 1023 else if (ADDRESS_REG_P (operands[1])) 1024 return \"move%.l %1,%-\;f%$move%.s %+,%0\"; 1025 else if (GET_CODE (operands[1]) == CONST_DOUBLE) 1026 return output_move_const_single (operands); 1027 return \"f%$move%.s %f1,%0\"; 1028 } 1029 if (FP_REG_P (operands[1])) 1030 { 1031 if (ADDRESS_REG_P (operands[0])) 1032 return \"fmove%.s %1,%-\;move%.l %+,%0\"; 1033 return \"fmove%.s %f1,%0\"; 1034 } 1035 return \"move%.l %1,%0\"; 1036}") 1037 1038(define_insn "movdf" 1039 [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>,y,rm,x,!x,!rm") 1040 (match_operand:DF 1 "general_operand" "rf,m,rofE<>,rmE,y,xH,rm,x"))] 1041; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>") 1042; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))] 1043 "" 1044 "* 1045{ 1046 if (which_alternative == 6) 1047 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\"; 1048 if (FPA_REG_P (operands[0])) 1049 { 1050 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1051 return output_move_const_double (operands); 1052 if (FP_REG_P (operands[1])) 1053 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\"; 1054 return \"fpmove%.d %x1,%x0\"; 1055 } 1056 else if (FPA_REG_P (operands[1])) 1057 { 1058 if (FP_REG_P(operands[0])) 1059 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\"; 1060 else 1061 return \"fpmove%.d %x1,%x0\"; 1062 } 1063 if (FP_REG_P (operands[0])) 1064 { 1065 if (FP_REG_P (operands[1])) 1066 return \"f%&move%.x %1,%0\"; 1067 if (REG_P (operands[1])) 1068 { 1069 rtx xoperands[2]; 1070 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 1071 output_asm_insn (\"move%.l %1,%-\", xoperands); 1072 output_asm_insn (\"move%.l %1,%-\", operands); 1073 return \"f%&move%.d %+,%0\"; 1074 } 1075 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1076 return output_move_const_double (operands); 1077 return \"f%&move%.d %f1,%0\"; 1078 } 1079 else if (FP_REG_P (operands[1])) 1080 { 1081 if (REG_P (operands[0])) 1082 { 1083 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); 1084 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1085 return \"move%.l %+,%0\"; 1086 } 1087 else 1088 return \"fmove%.d %f1,%0\"; 1089 } 1090 return output_move_double (operands); 1091} 1092") 1093 1094;; movdi can apply to fp regs in some cases 1095(define_insn "movdi" 1096 ;; Let's see if it really still needs to handle fp regs, and, if so, why. 1097 [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,y,rm,!*x,!rm") 1098 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))] 1099; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm") 1100; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))] 1101; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f") 1102; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))] 1103 "" 1104 "* 1105{ 1106 if (which_alternative == 8) 1107 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\"; 1108 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1])) 1109 return \"fpmove%.d %x1,%x0\"; 1110 if (FP_REG_P (operands[0])) 1111 { 1112 if (FP_REG_P (operands[1])) 1113 return \"fmove%.x %1,%0\"; 1114 if (REG_P (operands[1])) 1115 { 1116 rtx xoperands[2]; 1117 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 1118 output_asm_insn (\"move%.l %1,%-\", xoperands); 1119 output_asm_insn (\"move%.l %1,%-\", operands); 1120 return \"fmove%.d %+,%0\"; 1121 } 1122 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1123 return output_move_const_double (operands); 1124 return \"fmove%.d %f1,%0\"; 1125 } 1126 else if (FP_REG_P (operands[1])) 1127 { 1128 if (REG_P (operands[0])) 1129 { 1130 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); 1131 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1132 return \"move%.l %+,%0\"; 1133 } 1134 else 1135 return \"fmove%.d %f1,%0\"; 1136 } 1137 return output_move_double (operands); 1138} 1139") 1140 1141;; Thus goes after the move instructions 1142;; because the move instructions are better (require no spilling) 1143;; when they can apply. It goes before the add/sub insns 1144;; so we will prefer it to them. 1145 1146(define_insn "pushasi" 1147 [(set (match_operand:SI 0 "push_operand" "=m") 1148 (match_operand:SI 1 "address_operand" "p"))] 1149 "" 1150 "pea %a1") 1151 1152;; truncation instructions 1153(define_insn "truncsiqi2" 1154 [(set (match_operand:QI 0 "general_operand" "=dm,d") 1155 (truncate:QI 1156 (match_operand:SI 1 "general_operand" "doJ,i")))] 1157 "" 1158 "* 1159{ 1160 if (GET_CODE (operands[0]) == REG) 1161 { 1162 /* Must clear condition codes, since the move.l bases them on 1163 the entire 32 bits, not just the desired 8 bits. */ 1164 CC_STATUS_INIT; 1165 return \"move%.l %1,%0\"; 1166 } 1167 if (GET_CODE (operands[1]) == MEM) 1168 operands[1] = adj_offsettable_operand (operands[1], 3); 1169 return \"move%.b %1,%0\"; 1170}") 1171 1172(define_insn "trunchiqi2" 1173 [(set (match_operand:QI 0 "general_operand" "=dm,d") 1174 (truncate:QI 1175 (match_operand:HI 1 "general_operand" "doJ,i")))] 1176 "" 1177 "* 1178{ 1179 if (GET_CODE (operands[0]) == REG 1180 && (GET_CODE (operands[1]) == MEM 1181 || GET_CODE (operands[1]) == CONST_INT)) 1182 { 1183 /* Must clear condition codes, since the move.w bases them on 1184 the entire 16 bits, not just the desired 8 bits. */ 1185 CC_STATUS_INIT; 1186 return \"move%.w %1,%0\"; 1187 } 1188 if (GET_CODE (operands[0]) == REG) 1189 { 1190 /* Must clear condition codes, since the move.l bases them on 1191 the entire 32 bits, not just the desired 8 bits. */ 1192 CC_STATUS_INIT; 1193 return \"move%.l %1,%0\"; 1194 } 1195 if (GET_CODE (operands[1]) == MEM) 1196 operands[1] = adj_offsettable_operand (operands[1], 1); 1197 return \"move%.b %1,%0\"; 1198}") 1199 1200(define_insn "truncsihi2" 1201 [(set (match_operand:HI 0 "general_operand" "=dm,d") 1202 (truncate:HI 1203 (match_operand:SI 1 "general_operand" "roJ,i")))] 1204 "" 1205 "* 1206{ 1207 if (GET_CODE (operands[0]) == REG) 1208 { 1209 /* Must clear condition codes, since the move.l bases them on 1210 the entire 32 bits, not just the desired 8 bits. */ 1211 CC_STATUS_INIT; 1212 return \"move%.l %1,%0\"; 1213 } 1214 if (GET_CODE (operands[1]) == MEM) 1215 operands[1] = adj_offsettable_operand (operands[1], 2); 1216 return \"move%.w %1,%0\"; 1217}") 1218 1219;; zero extension instructions 1220 1221(define_expand "zero_extendhisi2" 1222 [(set (match_operand:SI 0 "register_operand" "") 1223 (const_int 0)) 1224 (set (strict_low_part (match_dup 2)) 1225 (match_operand:HI 1 "general_operand" ""))] 1226 "" 1227 " 1228{ 1229 operands[1] = make_safe_from (operands[1], operands[0]); 1230 if (GET_CODE (operands[0]) == SUBREG) 1231 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]), 1232 SUBREG_WORD (operands[0])); 1233 else 1234 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0); 1235}") 1236 1237(define_expand "zero_extendqihi2" 1238 [(set (match_operand:HI 0 "register_operand" "") 1239 (const_int 0)) 1240 (set (strict_low_part (match_dup 2)) 1241 (match_operand:QI 1 "general_operand" ""))] 1242 "" 1243 " 1244{ 1245 operands[1] = make_safe_from (operands[1], operands[0]); 1246 if (GET_CODE (operands[0]) == SUBREG) 1247 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]), 1248 SUBREG_WORD (operands[0])); 1249 else 1250 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0); 1251}") 1252 1253(define_expand "zero_extendqisi2" 1254 [(set (match_operand:SI 0 "register_operand" "") 1255 (const_int 0)) 1256 (set (strict_low_part (match_dup 2)) 1257 (match_operand:QI 1 "general_operand" ""))] 1258 "" 1259 " 1260{ 1261 operands[1] = make_safe_from (operands[1], operands[0]); 1262 if (GET_CODE (operands[0]) == SUBREG) 1263 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]), 1264 SUBREG_WORD (operands[0])); 1265 else 1266 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0); 1267}") 1268 1269;; Patterns to recognize zero-extend insns produced by the combiner. 1270;; We don't allow both operands in memory, because of aliasing problems. 1271;; Explicitly disallow two memory operands via the condition since reloading 1272;; of this case will result in worse code than the uncombined patterns. 1273 1274(define_insn "" 1275 [(set (match_operand:SI 0 "general_operand" "=do<>,d<") 1276 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] 1277 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1278 "* 1279{ 1280 if (DATA_REG_P (operands[0])) 1281 { 1282 if (GET_CODE (operands[1]) == REG 1283 && REGNO (operands[0]) == REGNO (operands[1])) 1284 return \"and%.l %#0xFFFF,%0\"; 1285 if (reg_mentioned_p (operands[0], operands[1])) 1286 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\"; 1287 return \"clr%.l %0\;move%.w %1,%0\"; 1288 } 1289 else if (GET_CODE (operands[0]) == MEM 1290 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 1291 return \"move%.w %1,%0\;clr%.w %0\"; 1292 else if (GET_CODE (operands[0]) == MEM 1293 && GET_CODE (XEXP (operands[0], 0)) == POST_INC) 1294 return \"clr%.w %0\;move%.w %1,%0\"; 1295 else 1296 { 1297 output_asm_insn (\"clr%.w %0\", operands); 1298 operands[0] = adj_offsettable_operand (operands[0], 2); 1299 return \"move%.w %1,%0\"; 1300 } 1301}") 1302 1303(define_insn "" 1304 [(set (match_operand:HI 0 "general_operand" "=do<>,d") 1305 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 1306 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1307 "* 1308{ 1309 if (DATA_REG_P (operands[0])) 1310 { 1311 if (GET_CODE (operands[1]) == REG 1312 && REGNO (operands[0]) == REGNO (operands[1])) 1313 return \"and%.w %#0xFF,%0\"; 1314 if (reg_mentioned_p (operands[0], operands[1])) 1315 return \"move%.b %1,%0\;and%.w %#0xFF,%0\"; 1316 return \"clr%.w %0\;move%.b %1,%0\"; 1317 } 1318 else if (GET_CODE (operands[0]) == MEM 1319 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 1320 { 1321 if (REGNO (XEXP (XEXP (operands[0], 0), 0)) 1322 == STACK_POINTER_REGNUM) 1323 { 1324 output_asm_insn (\"clr%.w %-\", operands); 1325 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), 1326 plus_constant (stack_pointer_rtx, 1)); 1327 return \"move%.b %1,%0\"; 1328 } 1329 else 1330 return \"move%.b %1,%0\;clr%.b %0\"; 1331 } 1332 else if (GET_CODE (operands[0]) == MEM 1333 && GET_CODE (XEXP (operands[0], 0)) == POST_INC) 1334 return \"clr%.b %0\;move%.b %1,%0\"; 1335 else 1336 { 1337 output_asm_insn (\"clr%.b %0\", operands); 1338 operands[0] = adj_offsettable_operand (operands[0], 1); 1339 return \"move%.b %1,%0\"; 1340 } 1341}") 1342 1343(define_insn "" 1344 [(set (match_operand:SI 0 "general_operand" "=do<>,d") 1345 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 1346 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1347 "* 1348{ 1349 if (DATA_REG_P (operands[0])) 1350 { 1351 if (GET_CODE (operands[1]) == REG 1352 && REGNO (operands[0]) == REGNO (operands[1])) 1353 return \"and%.l %#0xFF,%0\"; 1354 if (reg_mentioned_p (operands[0], operands[1])) 1355 return \"move%.b %1,%0\;and%.l %#0xFF,%0\"; 1356 return \"clr%.l %0\;move%.b %1,%0\"; 1357 } 1358 else if (GET_CODE (operands[0]) == MEM 1359 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 1360 { 1361 operands[0] = XEXP (XEXP (operands[0], 0), 0); 1362#ifdef MOTOROLA 1363#ifdef SGS 1364 return \"clr%.l -(%0)\;move%.b %1,3(%0)\"; 1365#else 1366 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\"; 1367#endif 1368#else 1369 return \"clrl %0@-\;moveb %1,%0@(3)\"; 1370#endif 1371 } 1372 else if (GET_CODE (operands[0]) == MEM 1373 && GET_CODE (XEXP (operands[0], 0)) == POST_INC) 1374 { 1375 operands[0] = XEXP (XEXP (operands[0], 0), 0); 1376#ifdef MOTOROLA 1377#ifdef SGS 1378 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\"; 1379#else 1380 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\"; 1381#endif 1382#else 1383 return \"clrl %0@+\;moveb %1,%0@(-1)\"; 1384#endif 1385 } 1386 else 1387 { 1388 output_asm_insn (\"clr%.l %0\", operands); 1389 operands[0] = adj_offsettable_operand (operands[0], 3); 1390 return \"move%.b %1,%0\"; 1391 } 1392}") 1393 1394;; sign extension instructions 1395 1396(define_insn "extendhisi2" 1397 [(set (match_operand:SI 0 "general_operand" "=*d,a") 1398 (sign_extend:SI 1399 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))] 1400 "" 1401 "* 1402{ 1403 if (ADDRESS_REG_P (operands[0])) 1404 return \"move%.w %1,%0\"; 1405 return \"ext%.l %0\"; 1406}") 1407 1408(define_insn "extendqihi2" 1409 [(set (match_operand:HI 0 "general_operand" "=d") 1410 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))] 1411 "" 1412 "ext%.w %0") 1413 1414(define_insn "extendqisi2" 1415 [(set (match_operand:SI 0 "general_operand" "=d") 1416 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] 1417 "TARGET_68020" 1418 "extb%.l %0") 1419 1420;; Conversions between float and double. 1421 1422(define_expand "extendsfdf2" 1423 [(set (match_operand:DF 0 "general_operand" "") 1424 (float_extend:DF 1425 (match_operand:SF 1 "general_operand" "")))] 1426 "TARGET_68881 || TARGET_FPA" 1427 "") 1428 1429(define_insn "" 1430 [(set (match_operand:DF 0 "general_operand" "=x,y") 1431 (float_extend:DF 1432 (match_operand:SF 1 "general_operand" "xH,rmF")))] 1433 "TARGET_FPA" 1434 "fpstod %w1,%0") 1435 1436(define_insn "" 1437 [(set (match_operand:DF 0 "general_operand" "=*fdm,f") 1438 (float_extend:DF 1439 (match_operand:SF 1 "general_operand" "f,dmF")))] 1440 "TARGET_68881" 1441 "* 1442{ 1443 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) 1444 { 1445 if (REGNO (operands[0]) == REGNO (operands[1])) 1446 { 1447 /* Extending float to double in an fp-reg is a no-op. 1448 NOTICE_UPDATE_CC has already assumed that the 1449 cc will be set. So cancel what it did. */ 1450 cc_status = cc_prev_status; 1451 return \"\"; 1452 } 1453 return \"f%&move%.x %1,%0\"; 1454 } 1455 if (FP_REG_P (operands[0])) 1456 return \"f%&move%.s %f1,%0\"; 1457 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1])) 1458 { 1459 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); 1460 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1461 return \"move%.l %+,%0\"; 1462 } 1463 return \"fmove%.d %f1,%0\"; 1464}") 1465 1466;; This cannot output into an f-reg because there is no way to be 1467;; sure of truncating in that case. 1468;; But on the Sun FPA, we can be sure. 1469(define_expand "truncdfsf2" 1470 [(set (match_operand:SF 0 "general_operand" "") 1471 (float_truncate:SF 1472 (match_operand:DF 1 "general_operand" "")))] 1473 "TARGET_68881 || TARGET_FPA" 1474 "") 1475 1476(define_insn "" 1477 [(set (match_operand:SF 0 "general_operand" "=x,y") 1478 (float_truncate:SF 1479 (match_operand:DF 1 "general_operand" "xH,rmF")))] 1480 "TARGET_FPA" 1481 "fpdtos %y1,%0") 1482 1483;; On the '040 we can truncate in a register accurately and easily. 1484(define_insn "" 1485 [(set (match_operand:SF 0 "general_operand" "=f") 1486 (float_truncate:SF 1487 (match_operand:DF 1 "general_operand" "fmG")))] 1488 "TARGET_68040_ONLY" 1489 "* 1490{ 1491 if (FP_REG_P (operands[1])) 1492 return \"fsmove%.x %1,%0\"; 1493 return \"fsmove%.d %f1,%0\"; 1494}") 1495 1496(define_insn "" 1497 [(set (match_operand:SF 0 "general_operand" "=dm") 1498 (float_truncate:SF 1499 (match_operand:DF 1 "general_operand" "f")))] 1500 "TARGET_68881" 1501 "fmove%.s %f1,%0") 1502 1503;; Conversion between fixed point and floating point. 1504;; Note that among the fix-to-float insns 1505;; the ones that start with SImode come first. 1506;; That is so that an operand that is a CONST_INT 1507;; (and therefore lacks a specific machine mode). 1508;; will be recognized as SImode (which is always valid) 1509;; rather than as QImode or HImode. 1510 1511(define_expand "floatsisf2" 1512 [(set (match_operand:SF 0 "general_operand" "") 1513 (float:SF (match_operand:SI 1 "general_operand" "")))] 1514 "TARGET_68881 || TARGET_FPA" 1515 "") 1516 1517(define_insn "" 1518 [(set (match_operand:SF 0 "general_operand" "=y,x") 1519 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))] 1520 "TARGET_FPA" 1521 "fpltos %1,%0") 1522 1523(define_insn "" 1524 [(set (match_operand:SF 0 "general_operand" "=f") 1525 (float:SF (match_operand:SI 1 "general_operand" "dmi")))] 1526 "TARGET_68881" 1527 "f%$move%.l %1,%0") 1528 1529(define_expand "floatsidf2" 1530 [(set (match_operand:DF 0 "general_operand" "") 1531 (float:DF (match_operand:SI 1 "general_operand" "")))] 1532 "TARGET_68881 || TARGET_FPA" 1533 "") 1534 1535(define_insn "" 1536 [(set (match_operand:DF 0 "general_operand" "=y,x") 1537 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))] 1538 "TARGET_FPA" 1539 "fpltod %1,%0") 1540 1541(define_insn "" 1542 [(set (match_operand:DF 0 "general_operand" "=f") 1543 (float:DF (match_operand:SI 1 "general_operand" "dmi")))] 1544 "TARGET_68881" 1545 "f%&move%.l %1,%0") 1546 1547(define_insn "floathisf2" 1548 [(set (match_operand:SF 0 "general_operand" "=f") 1549 (float:SF (match_operand:HI 1 "general_operand" "dmn")))] 1550 "TARGET_68881" 1551 "f%$move%.w %1,%0") 1552 1553(define_insn "floathidf2" 1554 [(set (match_operand:DF 0 "general_operand" "=f") 1555 (float:DF (match_operand:HI 1 "general_operand" "dmn")))] 1556 "TARGET_68881" 1557 "fmove%.w %1,%0") 1558 1559(define_insn "floatqisf2" 1560 [(set (match_operand:SF 0 "general_operand" "=f") 1561 (float:SF (match_operand:QI 1 "general_operand" "dmn")))] 1562 "TARGET_68881" 1563 "fmove%.b %1,%0") 1564 1565(define_insn "floatqidf2" 1566 [(set (match_operand:DF 0 "general_operand" "=f") 1567 (float:DF (match_operand:QI 1 "general_operand" "dmn")))] 1568 "TARGET_68881" 1569 "f%&move%.b %1,%0") 1570 1571;; New routines to convert floating-point values to integers 1572;; to be used on the '040. These should be faster than trapping 1573;; into the kernel to emulate fintrz. They should also be faster 1574;; than calling the subroutines fixsfsi() or fixdfsi(). 1575 1576(define_insn "fix_truncdfsi2" 1577 [(set (match_operand:SI 0 "general_operand" "=dm") 1578 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 1579 (clobber (match_scratch:SI 2 "=d")) 1580 (clobber (match_scratch:SI 3 "=d"))] 1581 "TARGET_68040" 1582 "* 1583{ 1584 CC_STATUS_INIT; 1585 return \"fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\"; 1586}") 1587 1588(define_insn "fix_truncdfhi2" 1589 [(set (match_operand:HI 0 "general_operand" "=dm") 1590 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 1591 (clobber (match_scratch:SI 2 "=d")) 1592 (clobber (match_scratch:SI 3 "=d"))] 1593 "TARGET_68040" 1594 "* 1595{ 1596 CC_STATUS_INIT; 1597 return \"fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\"; 1598}") 1599 1600(define_insn "fix_truncdfqi2" 1601 [(set (match_operand:QI 0 "general_operand" "=dm") 1602 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 1603 (clobber (match_scratch:SI 2 "=d")) 1604 (clobber (match_scratch:SI 3 "=d"))] 1605 "TARGET_68040" 1606 "* 1607{ 1608 CC_STATUS_INIT; 1609 return \"fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\"; 1610}") 1611 1612;; Convert a float to a float whose value is an integer. 1613;; This is the first stage of converting it to an integer type. 1614 1615(define_insn "ftruncdf2" 1616 [(set (match_operand:DF 0 "general_operand" "=f") 1617 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))] 1618 "TARGET_68881 && !TARGET_68040" 1619 "* 1620{ 1621 if (FP_REG_P (operands[1])) 1622 return \"fintrz%.x %f1,%0\"; 1623 return \"fintrz%.d %f1,%0\"; 1624}") 1625 1626(define_insn "ftruncsf2" 1627 [(set (match_operand:SF 0 "general_operand" "=f") 1628 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))] 1629 "TARGET_68881 && !TARGET_68040" 1630 "* 1631{ 1632 if (FP_REG_P (operands[1])) 1633 return \"fintrz%.x %f1,%0\"; 1634 return \"fintrz%.s %f1,%0\"; 1635}") 1636 1637;; Convert a float whose value is an integer 1638;; to an actual integer. Second stage of converting float to integer type. 1639(define_insn "fixsfqi2" 1640 [(set (match_operand:QI 0 "general_operand" "=dm") 1641 (fix:QI (match_operand:SF 1 "general_operand" "f")))] 1642 "TARGET_68881" 1643 "fmove%.b %1,%0") 1644 1645(define_insn "fixsfhi2" 1646 [(set (match_operand:HI 0 "general_operand" "=dm") 1647 (fix:HI (match_operand:SF 1 "general_operand" "f")))] 1648 "TARGET_68881" 1649 "fmove%.w %1,%0") 1650 1651(define_insn "fixsfsi2" 1652 [(set (match_operand:SI 0 "general_operand" "=dm") 1653 (fix:SI (match_operand:SF 1 "general_operand" "f")))] 1654 "TARGET_68881" 1655 "fmove%.l %1,%0") 1656 1657(define_insn "fixdfqi2" 1658 [(set (match_operand:QI 0 "general_operand" "=dm") 1659 (fix:QI (match_operand:DF 1 "general_operand" "f")))] 1660 "TARGET_68881" 1661 "fmove%.b %1,%0") 1662 1663(define_insn "fixdfhi2" 1664 [(set (match_operand:HI 0 "general_operand" "=dm") 1665 (fix:HI (match_operand:DF 1 "general_operand" "f")))] 1666 "TARGET_68881" 1667 "fmove%.w %1,%0") 1668 1669(define_insn "fixdfsi2" 1670 [(set (match_operand:SI 0 "general_operand" "=dm") 1671 (fix:SI (match_operand:DF 1 "general_operand" "f")))] 1672 "TARGET_68881" 1673 "fmove%.l %1,%0") 1674 1675;; Convert a float to an integer. 1676;; On the Sun FPA, this is done in one step. 1677 1678(define_insn "" 1679 [(set (match_operand:SI 0 "general_operand" "=x,y") 1680 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))] 1681 "TARGET_FPA" 1682 "fpstol %w1,%0") 1683 1684(define_insn "" 1685 [(set (match_operand:SI 0 "general_operand" "=x,y") 1686 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))] 1687 "TARGET_FPA" 1688 "fpdtol %y1,%0") 1689 1690;; add instructions 1691 1692;; Note that the middle two alternatives are near-duplicates 1693;; in order to handle insns generated by reload. 1694;; This is needed since they are not themselves reloaded, 1695;; so commutativity won't apply to them. 1696(define_insn "addsi3" 1697 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r") 1698 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0") 1699 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))] 1700 "" 1701 "* 1702{ 1703 if (! operands_match_p (operands[0], operands[1])) 1704 { 1705 if (!ADDRESS_REG_P (operands[1])) 1706 { 1707 rtx tmp = operands[1]; 1708 1709 operands[1] = operands[2]; 1710 operands[2] = tmp; 1711 } 1712 1713 /* These insns can result from reloads to access 1714 stack slots over 64k from the frame pointer. */ 1715 if (GET_CODE (operands[2]) == CONST_INT 1716 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000) 1717 return \"move%.l %2,%0\;add%.l %1,%0\"; 1718#ifdef SGS 1719 if (GET_CODE (operands[2]) == REG) 1720 return \"lea 0(%1,%2.l),%0\"; 1721 else 1722 return \"lea %c2(%1),%0\"; 1723#else /* not SGS */ 1724#ifdef MOTOROLA 1725 if (GET_CODE (operands[2]) == REG) 1726 return \"lea (%1,%2.l),%0\"; 1727 else 1728 return \"lea (%c2,%1),%0\"; 1729#else /* not MOTOROLA (MIT syntax) */ 1730 if (GET_CODE (operands[2]) == REG) 1731 return \"lea %1@(0,%2:l),%0\"; 1732 else 1733 return \"lea %1@(%c2),%0\"; 1734#endif /* not MOTOROLA */ 1735#endif /* not SGS */ 1736 } 1737 if (GET_CODE (operands[2]) == CONST_INT) 1738 { 1739#ifndef NO_ADDSUB_Q 1740 if (INTVAL (operands[2]) > 0 1741 && INTVAL (operands[2]) <= 8) 1742 return (ADDRESS_REG_P (operands[0]) 1743 ? \"addq%.w %2,%0\" 1744 : \"addq%.l %2,%0\"); 1745 if (INTVAL (operands[2]) < 0 1746 && INTVAL (operands[2]) >= -8) 1747 { 1748 operands[2] = gen_rtx (CONST_INT, VOIDmode, 1749 - INTVAL (operands[2])); 1750 return (ADDRESS_REG_P (operands[0]) 1751 ? \"subq%.w %2,%0\" 1752 : \"subq%.l %2,%0\"); 1753 } 1754 /* On everything except the 68000 it is faster to use two 1755 addqw instructions to add a small integer (8 < N <= 16) 1756 to an address register. Likewise for subqw.*/ 1757 if (INTVAL (operands[2]) > 8 1758 && INTVAL (operands[2]) <= 16 1759 && ADDRESS_REG_P (operands[0]) 1760 && TARGET_68020) 1761 { 1762 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); 1763 return \"addq%.w %#8,%0\;addq%.w %2,%0\"; 1764 } 1765 if (INTVAL (operands[2]) < -8 1766 && INTVAL (operands[2]) >= -16 1767 && ADDRESS_REG_P (operands[0]) 1768 && TARGET_68020) 1769 { 1770 operands[2] = gen_rtx (CONST_INT, VOIDmode, 1771 - INTVAL (operands[2]) - 8); 1772 return \"subq%.w %#8,%0\;subq%.w %2,%0\"; 1773 } 1774#endif 1775 if (ADDRESS_REG_P (operands[0]) 1776 && INTVAL (operands[2]) >= -0x8000 1777 && INTVAL (operands[2]) < 0x8000) 1778 return \"add%.w %2,%0\"; 1779 } 1780 return \"add%.l %2,%0\"; 1781}") 1782 1783(define_insn "" 1784 [(set (match_operand:SI 0 "general_operand" "=a") 1785 (plus:SI (match_operand:SI 1 "general_operand" "0") 1786 (sign_extend:SI 1787 (match_operand:HI 2 "nonimmediate_operand" "rm"))))] 1788 "" 1789 "add%.w %2,%0") 1790 1791(define_insn "addhi3" 1792 [(set (match_operand:HI 0 "general_operand" "=m,r") 1793 (plus:HI (match_operand:HI 1 "general_operand" "%0,0") 1794 (match_operand:HI 2 "general_operand" "dn,rmn")))] 1795 "" 1796 "* 1797{ 1798#ifndef NO_ADDSUB_Q 1799 if (GET_CODE (operands[2]) == CONST_INT) 1800 { 1801 /* If the constant would be a negative number when interpreted as 1802 HImode, make it negative. This is usually, but not always, done 1803 elsewhere in the compiler. First check for constants out of range, 1804 which could confuse us. */ 1805 1806 if (INTVAL (operands[2]) >= 32768) 1807 operands[2] = gen_rtx (CONST_INT, VOIDmode, 1808 INTVAL (operands[2]) - 65536); 1809 1810 if (INTVAL (operands[2]) > 0 1811 && INTVAL (operands[2]) <= 8) 1812 return \"addq%.w %2,%0\"; 1813 if (INTVAL (operands[2]) < 0 1814 && INTVAL (operands[2]) >= -8) 1815 { 1816 operands[2] = gen_rtx (CONST_INT, VOIDmode, 1817 - INTVAL (operands[2])); 1818 return \"subq%.w %2,%0\"; 1819 } 1820 /* On everything except the 68000 it is faster to use two 1821 addqw instructions to add a small integer (8 < N <= 16) 1822 to an address register. Likewise for subqw. */ 1823 if (INTVAL (operands[2]) > 8 1824 && INTVAL (operands[2]) <= 16 1825 && ADDRESS_REG_P (operands[0]) 1826 && TARGET_68020) 1827 { 1828 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); 1829 return \"addq%.w %#8,%0\;addq%.w %2,%0\"; 1830 } 1831 if (INTVAL (operands[2]) < -8 1832 && INTVAL (operands[2]) >= -16 1833 && ADDRESS_REG_P (operands[0]) 1834 && TARGET_68020) 1835 { 1836 operands[2] = gen_rtx (CONST_INT, VOIDmode, 1837 - INTVAL (operands[2]) - 8); 1838 return \"subq%.w %#8,%0\;subq%.w %2,%0\"; 1839 } 1840 } 1841#endif 1842 return \"add%.w %2,%0\"; 1843}") 1844 1845;; These insns must use MATCH_DUP instead of the more expected 1846;; use of a matching constraint because the "output" here is also 1847;; an input, so you can't use the matching constraint. That also means 1848;; that you can't use the "%", so you need patterns with the matched 1849;; operand in both positions. 1850 1851(define_insn "" 1852 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 1853 (plus:HI (match_dup 0) 1854 (match_operand:HI 1 "general_operand" "dn,rmn")))] 1855 "" 1856 "* 1857{ 1858#ifndef NO_ADDSUB_Q 1859 if (GET_CODE (operands[1]) == CONST_INT) 1860 { 1861 /* If the constant would be a negative number when interpreted as 1862 HImode, make it negative. This is usually, but not always, done 1863 elsewhere in the compiler. First check for constants out of range, 1864 which could confuse us. */ 1865 1866 if (INTVAL (operands[1]) >= 32768) 1867 operands[1] = gen_rtx (CONST_INT, VOIDmode, 1868 INTVAL (operands[1]) - 65536); 1869 1870 if (INTVAL (operands[1]) > 0 1871 && INTVAL (operands[1]) <= 8) 1872 return \"addq%.w %1,%0\"; 1873 if (INTVAL (operands[1]) < 0 1874 && INTVAL (operands[1]) >= -8) 1875 { 1876 operands[1] = gen_rtx (CONST_INT, VOIDmode, 1877 - INTVAL (operands[1])); 1878 return \"subq%.w %1,%0\"; 1879 } 1880 /* On everything except the 68000 it is faster to use two 1881 addqw instructions to add a small integer (8 < N <= 16) 1882 to an address register. Likewise for subqw. */ 1883 if (INTVAL (operands[1]) > 8 1884 && INTVAL (operands[1]) <= 16 1885 && ADDRESS_REG_P (operands[0]) 1886 && TARGET_68020) 1887 { 1888 operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); 1889 return \"addq%.w %#8,%0\;addq%.w %1,%0\"; 1890 } 1891 if (INTVAL (operands[1]) < -8 1892 && INTVAL (operands[1]) >= -16 1893 && ADDRESS_REG_P (operands[0]) 1894 && TARGET_68020) 1895 { 1896 operands[1] = gen_rtx (CONST_INT, VOIDmode, 1897 - INTVAL (operands[1]) - 8); 1898 return \"subq%.w %#8,%0\;subq%.w %1,%0\"; 1899 } 1900 } 1901#endif 1902 return \"add%.w %1,%0\"; 1903}") 1904 1905(define_insn "" 1906 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 1907 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn") 1908 (match_dup 0)))] 1909 "" 1910 "* 1911{ 1912#ifndef NO_ADDSUB_Q 1913 if (GET_CODE (operands[1]) == CONST_INT) 1914 { 1915 /* If the constant would be a negative number when interpreted as 1916 HImode, make it negative. This is usually, but not always, done 1917 elsewhere in the compiler. First check for constants out of range, 1918 which could confuse us. */ 1919 1920 if (INTVAL (operands[1]) >= 32768) 1921 operands[1] = gen_rtx (CONST_INT, VOIDmode, 1922 INTVAL (operands[1]) - 65536); 1923 1924 if (INTVAL (operands[1]) > 0 1925 && INTVAL (operands[1]) <= 8) 1926 return \"addq%.w %1,%0\"; 1927 if (INTVAL (operands[1]) < 0 1928 && INTVAL (operands[1]) >= -8) 1929 { 1930 operands[1] = gen_rtx (CONST_INT, VOIDmode, 1931 - INTVAL (operands[1])); 1932 return \"subq%.w %1,%0\"; 1933 } 1934 /* On everything except the 68000 it is faster to use two 1935 addqw instructions to add a small integer (8 < N <= 16) 1936 to an address register. Likewise for subqw. */ 1937 if (INTVAL (operands[1]) > 8 1938 && INTVAL (operands[1]) <= 16 1939 && ADDRESS_REG_P (operands[0]) 1940 && TARGET_68020) 1941 { 1942 operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); 1943 return \"addq%.w %#8,%0\;addq%.w %1,%0\"; 1944 } 1945 if (INTVAL (operands[1]) < -8 1946 && INTVAL (operands[1]) >= -16 1947 && ADDRESS_REG_P (operands[0]) 1948 && TARGET_68020) 1949 { 1950 operands[1] = gen_rtx (CONST_INT, VOIDmode, 1951 - INTVAL (operands[1]) - 8); 1952 return \"subq%.w %#8,%0\;subq%.w %1,%0\"; 1953 } 1954 } 1955#endif 1956 return \"add%.w %1,%0\"; 1957}") 1958 1959(define_insn "addqi3" 1960 [(set (match_operand:QI 0 "general_operand" "=m,d") 1961 (plus:QI (match_operand:QI 1 "general_operand" "%0,0") 1962 (match_operand:QI 2 "general_operand" "dn,dmn")))] 1963 "" 1964 "* 1965{ 1966#ifndef NO_ADDSUB_Q 1967 if (GET_CODE (operands[2]) == CONST_INT) 1968 { 1969 if (INTVAL (operands[2]) >= 128) 1970 operands[2] = gen_rtx (CONST_INT, VOIDmode, 1971 INTVAL (operands[2]) - 256); 1972 1973 if (INTVAL (operands[2]) > 0 1974 && INTVAL (operands[2]) <= 8) 1975 return \"addq%.b %2,%0\"; 1976 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) 1977 { 1978 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); 1979 return \"subq%.b %2,%0\"; 1980 } 1981 } 1982#endif 1983 return \"add%.b %2,%0\"; 1984}") 1985 1986(define_insn "" 1987 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 1988 (plus:QI (match_dup 0) 1989 (match_operand:QI 1 "general_operand" "dn,dmn")))] 1990 "" 1991 "* 1992{ 1993#ifndef NO_ADDSUB_Q 1994 if (GET_CODE (operands[1]) == CONST_INT) 1995 { 1996 if (INTVAL (operands[1]) >= 128) 1997 operands[1] = gen_rtx (CONST_INT, VOIDmode, 1998 INTVAL (operands[1]) - 256); 1999 2000 if (INTVAL (operands[1]) > 0 2001 && INTVAL (operands[1]) <= 8) 2002 return \"addq%.b %1,%0\"; 2003 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) 2004 { 2005 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); 2006 return \"subq%.b %1,%0\"; 2007 } 2008 } 2009#endif 2010 return \"add%.b %1,%0\"; 2011}") 2012 2013(define_insn "" 2014 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 2015 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn") 2016 (match_dup 0)))] 2017 "" 2018 "* 2019{ 2020#ifndef NO_ADDSUB_Q 2021 if (GET_CODE (operands[1]) == CONST_INT) 2022 { 2023 if (INTVAL (operands[1]) >= 128) 2024 operands[1] = gen_rtx (CONST_INT, VOIDmode, 2025 INTVAL (operands[1]) - 256); 2026 2027 if (INTVAL (operands[1]) > 0 2028 && INTVAL (operands[1]) <= 8) 2029 return \"addq%.b %1,%0\"; 2030 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) 2031 { 2032 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); 2033 return \"subq%.b %1,%0\"; 2034 } 2035 } 2036#endif 2037 return \"add%.b %1,%0\"; 2038}") 2039 2040(define_expand "adddf3" 2041 [(set (match_operand:DF 0 "general_operand" "") 2042 (plus:DF (match_operand:DF 1 "general_operand" "") 2043 (match_operand:DF 2 "general_operand" "")))] 2044 "TARGET_68881 || TARGET_FPA" 2045 "") 2046 2047(define_insn "" 2048 [(set (match_operand:DF 0 "general_operand" "=x,y") 2049 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y") 2050 (match_operand:DF 2 "general_operand" "xH,dmF")))] 2051 "TARGET_FPA" 2052 "* 2053{ 2054 if (rtx_equal_p (operands[0], operands[1])) 2055 return \"fpadd%.d %y2,%0\"; 2056 if (rtx_equal_p (operands[0], operands[2])) 2057 return \"fpadd%.d %y1,%0\"; 2058 if (which_alternative == 0) 2059 return \"fpadd3%.d %w2,%w1,%0\"; 2060 return \"fpadd3%.d %x2,%x1,%0\"; 2061}") 2062 2063(define_insn "" 2064 [(set (match_operand:DF 0 "general_operand" "=f") 2065 (plus:DF (match_operand:DF 1 "general_operand" "%0") 2066 (match_operand:DF 2 "general_operand" "fmG")))] 2067 "TARGET_68881" 2068 "* 2069{ 2070 if (REG_P (operands[2])) 2071 return \"f%&add%.x %2,%0\"; 2072 return \"f%&add%.d %f2,%0\"; 2073}") 2074 2075(define_expand "addsf3" 2076 [(set (match_operand:SF 0 "general_operand" "") 2077 (plus:SF (match_operand:SF 1 "general_operand" "") 2078 (match_operand:SF 2 "general_operand" "")))] 2079 "TARGET_68881 || TARGET_FPA" 2080 "") 2081 2082(define_insn "" 2083 [(set (match_operand:SF 0 "general_operand" "=x,y") 2084 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y") 2085 (match_operand:SF 2 "general_operand" "xH,rmF")))] 2086 "TARGET_FPA" 2087 "* 2088{ 2089 if (rtx_equal_p (operands[0], operands[1])) 2090 return \"fpadd%.s %w2,%0\"; 2091 if (rtx_equal_p (operands[0], operands[2])) 2092 return \"fpadd%.s %w1,%0\"; 2093 if (which_alternative == 0) 2094 return \"fpadd3%.s %w2,%w1,%0\"; 2095 return \"fpadd3%.s %2,%1,%0\"; 2096}") 2097 2098(define_insn "" 2099 [(set (match_operand:SF 0 "general_operand" "=f") 2100 (plus:SF (match_operand:SF 1 "general_operand" "%0") 2101 (match_operand:SF 2 "general_operand" "fdmF")))] 2102 "TARGET_68881" 2103 "* 2104{ 2105 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2106 return \"f%$add%.x %2,%0\"; 2107 return \"f%$add%.s %f2,%0\"; 2108}") 2109 2110;; subtract instructions 2111 2112(define_insn "subsi3" 2113 [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d") 2114 (minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs") 2115 (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))] 2116 "" 2117 "* 2118{ 2119 if (! operands_match_p (operands[0], operands[1])) 2120 { 2121 if (operands_match_p (operands[0], operands[2])) 2122 { 2123#ifndef NO_ADDSUB_Q 2124 if (GET_CODE (operands[1]) == CONST_INT) 2125 { 2126 if (INTVAL (operands[1]) > 0 2127 && INTVAL (operands[1]) <= 8) 2128 return \"subq%.l %1,%0\;neg%.l %0\"; 2129 } 2130#endif 2131 return \"sub%.l %1,%0\;neg%.l %0\"; 2132 } 2133 /* This case is matched by J, but negating -0x8000 2134 in an lea would give an invalid displacement. 2135 So do this specially. */ 2136 if (INTVAL (operands[2]) == -0x8000) 2137 return \"move%.l %1,%0\;sub%.l %2,%0\"; 2138#ifdef SGS 2139 return \"lea %n2(%1),%0\"; 2140#else 2141#ifdef MOTOROLA 2142 return \"lea (%n2,%1),%0\"; 2143#else /* not MOTOROLA (MIT syntax) */ 2144 return \"lea %1@(%n2),%0\"; 2145#endif /* not MOTOROLA */ 2146#endif /* not SGS */ 2147 } 2148 if (GET_CODE (operands[2]) == CONST_INT) 2149 { 2150#ifndef NO_ADDSUB_Q 2151 if (INTVAL (operands[2]) > 0 2152 && INTVAL (operands[2]) <= 8) 2153 return \"subq%.l %2,%0\"; 2154 /* Using two subqw for 8 < N <= 16 being subtracted from an 2155 address register is faster on all but 68000 */ 2156 if (INTVAL (operands[2]) > 8 2157 && INTVAL (operands[2]) <= 16 2158 && ADDRESS_REG_P (operands[0]) 2159 && TARGET_68020) 2160 { 2161 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); 2162 return \"subq%.w %#8,%0\;subq%.w %2,%0\"; 2163 } 2164#endif 2165 if (ADDRESS_REG_P (operands[0]) 2166 && INTVAL (operands[2]) >= -0x8000 2167 && INTVAL (operands[2]) < 0x8000) 2168 return \"sub%.w %2,%0\"; 2169 } 2170 return \"sub%.l %2,%0\"; 2171}") 2172 2173(define_insn "" 2174 [(set (match_operand:SI 0 "general_operand" "=a") 2175 (minus:SI (match_operand:SI 1 "general_operand" "0") 2176 (sign_extend:SI 2177 (match_operand:HI 2 "nonimmediate_operand" "rm"))))] 2178 "" 2179 "sub%.w %2,%0") 2180 2181(define_insn "subhi3" 2182 [(set (match_operand:HI 0 "general_operand" "=m,r") 2183 (minus:HI (match_operand:HI 1 "general_operand" "0,0") 2184 (match_operand:HI 2 "general_operand" "dn,rmn")))] 2185 "" 2186 "sub%.w %2,%0") 2187 2188(define_insn "" 2189 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 2190 (minus:HI (match_dup 0) 2191 (match_operand:HI 1 "general_operand" "dn,rmn")))] 2192 "" 2193 "sub%.w %1,%0") 2194 2195(define_insn "subqi3" 2196 [(set (match_operand:QI 0 "general_operand" "=m,d") 2197 (minus:QI (match_operand:QI 1 "general_operand" "0,0") 2198 (match_operand:QI 2 "general_operand" "dn,dmn")))] 2199 "" 2200 "sub%.b %2,%0") 2201 2202(define_insn "" 2203 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 2204 (minus:QI (match_dup 0) 2205 (match_operand:QI 1 "general_operand" "dn,dmn")))] 2206 "" 2207 "sub%.b %1,%0") 2208 2209(define_expand "subdf3" 2210 [(set (match_operand:DF 0 "general_operand" "") 2211 (minus:DF (match_operand:DF 1 "general_operand" "") 2212 (match_operand:DF 2 "general_operand" "")))] 2213 "TARGET_68881 || TARGET_FPA" 2214 "") 2215 2216(define_insn "" 2217 [(set (match_operand:DF 0 "general_operand" "=x,y,y") 2218 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF") 2219 (match_operand:DF 2 "general_operand" "xH,dmF,0")))] 2220 "TARGET_FPA" 2221 "* 2222{ 2223 if (rtx_equal_p (operands[0], operands[2])) 2224 return \"fprsub%.d %y1,%0\"; 2225 if (rtx_equal_p (operands[0], operands[1])) 2226 return \"fpsub%.d %y2,%0\"; 2227 if (which_alternative == 0) 2228 return \"fpsub3%.d %w2,%w1,%0\"; 2229 return \"fpsub3%.d %x2,%x1,%0\"; 2230}") 2231 2232(define_insn "" 2233 [(set (match_operand:DF 0 "general_operand" "=f") 2234 (minus:DF (match_operand:DF 1 "general_operand" "0") 2235 (match_operand:DF 2 "general_operand" "fmG")))] 2236 "TARGET_68881" 2237 "* 2238{ 2239 if (REG_P (operands[2])) 2240 return \"f%&sub%.x %2,%0\"; 2241 return \"f%&sub%.d %f2,%0\"; 2242}") 2243 2244(define_expand "subsf3" 2245 [(set (match_operand:SF 0 "general_operand" "") 2246 (minus:SF (match_operand:SF 1 "general_operand" "") 2247 (match_operand:SF 2 "general_operand" "")))] 2248 "TARGET_68881 || TARGET_FPA" 2249 "") 2250 2251(define_insn "" 2252 [(set (match_operand:SF 0 "general_operand" "=x,y,y") 2253 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF") 2254 (match_operand:SF 2 "general_operand" "xH,rmF,0")))] 2255 "TARGET_FPA" 2256 "* 2257{ 2258 if (rtx_equal_p (operands[0], operands[2])) 2259 return \"fprsub%.s %w1,%0\"; 2260 if (rtx_equal_p (operands[0], operands[1])) 2261 return \"fpsub%.s %w2,%0\"; 2262 if (which_alternative == 0) 2263 return \"fpsub3%.s %w2,%w1,%0\"; 2264 return \"fpsub3%.s %2,%1,%0\"; 2265}") 2266 2267(define_insn "" 2268 [(set (match_operand:SF 0 "general_operand" "=f") 2269 (minus:SF (match_operand:SF 1 "general_operand" "0") 2270 (match_operand:SF 2 "general_operand" "fdmF")))] 2271 "TARGET_68881" 2272 "* 2273{ 2274 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2275 return \"f%$sub%.x %2,%0\"; 2276 return \"f%$sub%.s %f2,%0\"; 2277}") 2278 2279;; multiply instructions 2280 2281(define_insn "mulhi3" 2282 [(set (match_operand:HI 0 "general_operand" "=d") 2283 (mult:HI (match_operand:HI 1 "general_operand" "%0") 2284 (match_operand:HI 2 "general_operand" "dmn")))] 2285 "" 2286 "* 2287{ 2288#if defined(MOTOROLA) && !defined(CRDS) 2289 return \"muls%.w %2,%0\"; 2290#else 2291 return \"muls %2,%0\"; 2292#endif 2293}") 2294 2295(define_insn "mulhisi3" 2296 [(set (match_operand:SI 0 "general_operand" "=d") 2297 (mult:SI (sign_extend:SI 2298 (match_operand:HI 1 "nonimmediate_operand" "%0")) 2299 (sign_extend:SI 2300 (match_operand:HI 2 "nonimmediate_operand" "dm"))))] 2301 "" 2302 "* 2303{ 2304#if defined(MOTOROLA) && !defined(CRDS) 2305 return \"muls%.w %2,%0\"; 2306#else 2307 return \"muls %2,%0\"; 2308#endif 2309}") 2310 2311(define_insn "" 2312 [(set (match_operand:SI 0 "general_operand" "=d") 2313 (mult:SI (sign_extend:SI 2314 (match_operand:HI 1 "nonimmediate_operand" "%0")) 2315 (match_operand:SI 2 "const_int_operand" "n")))] 2316 "" 2317 "* 2318{ 2319#if defined(MOTOROLA) && !defined(CRDS) 2320 return \"muls%.w %2,%0\"; 2321#else 2322 return \"muls %2,%0\"; 2323#endif 2324}") 2325 2326(define_insn "mulsi3" 2327 [(set (match_operand:SI 0 "general_operand" "=d") 2328 (mult:SI (match_operand:SI 1 "general_operand" "%0") 2329 (match_operand:SI 2 "general_operand" "dmsK")))] 2330 "TARGET_68020" 2331 "muls%.l %2,%0") 2332 2333(define_insn "umulhisi3" 2334 [(set (match_operand:SI 0 "general_operand" "=d") 2335 (mult:SI (zero_extend:SI 2336 (match_operand:HI 1 "nonimmediate_operand" "%0")) 2337 (zero_extend:SI 2338 (match_operand:HI 2 "nonimmediate_operand" "dm"))))] 2339 "" 2340 "* 2341{ 2342#if defined(MOTOROLA) && !defined(CRDS) 2343 return \"mulu%.w %2,%0\"; 2344#else 2345 return \"mulu %2,%0\"; 2346#endif 2347}") 2348 2349(define_insn "" 2350 [(set (match_operand:SI 0 "general_operand" "=d") 2351 (mult:SI (zero_extend:SI 2352 (match_operand:HI 1 "nonimmediate_operand" "%0")) 2353 (match_operand:SI 2 "const_int_operand" "n")))] 2354 "" 2355 "* 2356{ 2357#if defined(MOTOROLA) && !defined(CRDS) 2358 return \"mulu%.w %2,%0\"; 2359#else 2360 return \"mulu %2,%0\"; 2361#endif 2362}") 2363 2364;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the 2365;; proper matching constraint. This is because the matching is between 2366;; the high-numbered word of the DImode operand[0] and operand[1]. 2367(define_expand "umulsidi3" 2368 [(parallel 2369 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) 2370 (subreg:SI 2371 (mult:DI (zero_extend:DI 2372 (match_operand:SI 1 "register_operand" "")) 2373 (zero_extend:DI 2374 (match_operand:SI 2 "nonimmediate_operand" ""))) 1)) 2375 (set (subreg:SI (match_dup 0) 0) 2376 (subreg:SI 2377 (mult:DI (zero_extend:DI 2378 (match_dup 1)) 2379 (zero_extend:DI 2380 (match_dup 2))) 0))])] 2381 "TARGET_68020" 2382 "") 2383 2384(define_insn "" 2385 [(set (match_operand:SI 0 "register_operand" "=d") 2386 (subreg:SI 2387 (mult:DI (zero_extend:DI 2388 (match_operand:SI 1 "register_operand" "%0")) 2389 (zero_extend:DI 2390 (match_operand:SI 2 "nonimmediate_operand" "dm"))) 1)) 2391 (set (match_operand:SI 3 "register_operand" "=d") 2392 (subreg:SI 2393 (mult:DI (zero_extend:DI 2394 (match_dup 1)) 2395 (zero_extend:DI 2396 (match_dup 2))) 0))] 2397 "TARGET_68020" 2398 "mulu%.l %2,%3:%0") 2399 2400(define_insn "" 2401 [(set (match_operand:SI 0 "register_operand" "=d") 2402 (subreg:SI 2403 (mult:DI (zero_extend:DI 2404 (match_operand:SI 1 "register_operand" "%0")) 2405 (match_operand:SI 2 "immediate_operand" "sK")) 1)) 2406 (set (match_operand:SI 3 "register_operand" "=d") 2407 (subreg:SI 2408 (mult:DI (zero_extend:DI 2409 (match_dup 1)) 2410 (match_dup 2)) 0))] 2411 "TARGET_68020 2412 && (GET_CODE (operands[2]) != CONST_INT 2413 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))" 2414 "mulu%.l %2,%3:%0") 2415 2416(define_expand "mulsidi3" 2417 [(parallel 2418 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) 2419 (subreg:SI 2420 (mult:DI (sign_extend:DI 2421 (match_operand:SI 1 "register_operand" "")) 2422 (sign_extend:DI 2423 (match_operand:SI 2 "nonimmediate_operand" ""))) 1)) 2424 (set (subreg:SI (match_dup 0) 0) 2425 (subreg:SI 2426 (mult:DI (sign_extend:DI 2427 (match_dup 1)) 2428 (sign_extend:DI 2429 (match_dup 2))) 0))])] 2430 "TARGET_68020" 2431 "") 2432 2433(define_insn "" 2434 [(set (match_operand:SI 0 "register_operand" "=d") 2435 (subreg:SI 2436 (mult:DI (sign_extend:DI 2437 (match_operand:SI 1 "register_operand" "%0")) 2438 (sign_extend:DI 2439 (match_operand:SI 2 "nonimmediate_operand" "dm"))) 1)) 2440 (set (match_operand:SI 3 "register_operand" "=d") 2441 (subreg:SI 2442 (mult:DI (sign_extend:DI 2443 (match_dup 1)) 2444 (sign_extend:DI 2445 (match_dup 2))) 0))] 2446 "TARGET_68020" 2447 "muls%.l %2,%3:%0") 2448 2449(define_insn "" 2450 [(set (match_operand:SI 0 "register_operand" "=d") 2451 (subreg:SI 2452 (mult:DI (sign_extend:DI 2453 (match_operand:SI 1 "register_operand" "%0")) 2454 (match_operand:SI 2 "immediate_operand" "sK")) 1)) 2455 (set (match_operand:SI 3 "register_operand" "=d") 2456 (subreg:SI 2457 (mult:DI (sign_extend:DI 2458 (match_dup 1)) 2459 (match_dup 2)) 0))] 2460 "TARGET_68020 2461 && (GET_CODE (operands[2]) != CONST_INT 2462 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))" 2463 "muls%.l %2,%3:%0") 2464 2465(define_expand "muldf3" 2466 [(set (match_operand:DF 0 "general_operand" "") 2467 (mult:DF (match_operand:DF 1 "general_operand" "") 2468 (match_operand:DF 2 "general_operand" "")))] 2469 "TARGET_68881 || TARGET_FPA" 2470 "") 2471 2472(define_insn "" 2473 [(set (match_operand:DF 0 "general_operand" "=x,y") 2474 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y") 2475 (match_operand:DF 2 "general_operand" "xH,rmF")))] 2476 "TARGET_FPA" 2477 "* 2478{ 2479 if (rtx_equal_p (operands[1], operands[2])) 2480 return \"fpsqr%.d %y1,%0\"; 2481 if (rtx_equal_p (operands[0], operands[1])) 2482 return \"fpmul%.d %y2,%0\"; 2483 if (rtx_equal_p (operands[0], operands[2])) 2484 return \"fpmul%.d %y1,%0\"; 2485 if (which_alternative == 0) 2486 return \"fpmul3%.d %w2,%w1,%0\"; 2487 return \"fpmul3%.d %x2,%x1,%0\"; 2488}") 2489 2490(define_insn "" 2491 [(set (match_operand:DF 0 "general_operand" "=f") 2492 (mult:DF (match_operand:DF 1 "general_operand" "%0") 2493 (match_operand:DF 2 "general_operand" "fmG")))] 2494 "TARGET_68881" 2495 "* 2496{ 2497 if (GET_CODE (operands[2]) == CONST_DOUBLE 2498 && floating_exact_log2 (operands[2]) && !TARGET_68040) 2499 { 2500 int i = floating_exact_log2 (operands[2]); 2501 operands[2] = gen_rtx (CONST_INT, VOIDmode, i); 2502 return \"fscale%.l %2,%0\"; 2503 } 2504 if (REG_P (operands[2])) 2505 return \"f%&mul%.x %2,%0\"; 2506 return \"f%&mul%.d %f2,%0\"; 2507}") 2508 2509(define_expand "mulsf3" 2510 [(set (match_operand:SF 0 "general_operand" "") 2511 (mult:SF (match_operand:SF 1 "general_operand" "") 2512 (match_operand:SF 2 "general_operand" "")))] 2513 "TARGET_68881 || TARGET_FPA" 2514 "") 2515 2516(define_insn "" 2517 [(set (match_operand:SF 0 "general_operand" "=x,y") 2518 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y") 2519 (match_operand:SF 2 "general_operand" "xH,rmF")))] 2520 "TARGET_FPA" 2521 "* 2522{ 2523 if (rtx_equal_p (operands[1], operands[2])) 2524 return \"fpsqr%.s %w1,%0\"; 2525 if (rtx_equal_p (operands[0], operands[1])) 2526 return \"fpmul%.s %w2,%0\"; 2527 if (rtx_equal_p (operands[0], operands[2])) 2528 return \"fpmul%.s %w1,%0\"; 2529 if (which_alternative == 0) 2530 return \"fpmul3%.s %w2,%w1,%0\"; 2531 return \"fpmul3%.s %2,%1,%0\"; 2532}") 2533 2534(define_insn "" 2535 [(set (match_operand:SF 0 "general_operand" "=f") 2536 (mult:SF (match_operand:SF 1 "general_operand" "%0") 2537 (match_operand:SF 2 "general_operand" "fdmF")))] 2538 "TARGET_68881" 2539 "* 2540{ 2541#ifdef FSGLMUL_USE_S 2542 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2543 return (TARGET_68040_ONLY 2544 ? \"fsmul%.s %2,%0\" 2545 : \"fsglmul%.s %2,%0\"); 2546#else 2547 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2548 return (TARGET_68040_ONLY 2549 ? \"fsmul%.x %2,%0\" 2550 : \"fsglmul%.x %2,%0\"); 2551#endif 2552 return (TARGET_68040_ONLY 2553 ? \"fsmul%.s %f2,%0\" 2554 : \"fsglmul%.s %f2,%0\"); 2555}") 2556 2557;; divide instructions 2558 2559(define_insn "divhi3" 2560 [(set (match_operand:HI 0 "general_operand" "=d") 2561 (div:HI (match_operand:HI 1 "general_operand" "0") 2562 (match_operand:HI 2 "general_operand" "dmn")))] 2563 "" 2564 "* 2565{ 2566#ifdef MOTOROLA 2567 return \"ext%.l %0\;divs%.w %2,%0\"; 2568#else 2569 return \"extl %0\;divs %2,%0\"; 2570#endif 2571}") 2572 2573(define_insn "divhisi3" 2574 [(set (match_operand:HI 0 "general_operand" "=d") 2575 (truncate:HI 2576 (div:SI 2577 (match_operand:SI 1 "general_operand" "0") 2578 (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] 2579 "" 2580 "* 2581{ 2582#ifdef MOTOROLA 2583 return \"divs%.w %2,%0\"; 2584#else 2585 return \"divs %2,%0\"; 2586#endif 2587}") 2588 2589(define_insn "" 2590 [(set (match_operand:HI 0 "general_operand" "=d") 2591 (truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0") 2592 (match_operand:SI 2 "const_int_operand" "n"))))] 2593 "" 2594 "* 2595{ 2596#ifdef MOTOROLA 2597 return \"divs%.w %2,%0\"; 2598#else 2599 return \"divs %2,%0\"; 2600#endif 2601}") 2602 2603(define_insn "udivhi3" 2604 [(set (match_operand:HI 0 "general_operand" "=d") 2605 (udiv:HI (match_operand:HI 1 "general_operand" "0") 2606 (match_operand:HI 2 "general_operand" "dmn")))] 2607 "" 2608 "* 2609{ 2610#ifdef MOTOROLA 2611 return \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\"; 2612#else 2613 return \"andl %#0xFFFF,%0\;divu %2,%0\"; 2614#endif 2615}") 2616 2617(define_insn "udivhisi3" 2618 [(set (match_operand:HI 0 "general_operand" "=d") 2619 (truncate:HI 2620 (udiv:SI 2621 (match_operand:SI 1 "general_operand" "0") 2622 (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] 2623 "" 2624 "* 2625{ 2626#ifdef MOTOROLA 2627 return \"divu%.w %2,%0\"; 2628#else 2629 return \"divu %2,%0\"; 2630#endif 2631}") 2632 2633(define_insn "" 2634 [(set (match_operand:HI 0 "general_operand" "=d") 2635 (truncate:HI (udiv:SI (match_operand:SI 1 "general_operand" "0") 2636 (match_operand:SI 2 "const_int_operand" "n"))))] 2637 "" 2638 "* 2639{ 2640#ifdef MOTOROLA 2641 return \"divu%.w %2,%0\"; 2642#else 2643 return \"divu %2,%0\"; 2644#endif 2645}") 2646 2647(define_expand "divdf3" 2648 [(set (match_operand:DF 0 "general_operand" "") 2649 (div:DF (match_operand:DF 1 "general_operand" "") 2650 (match_operand:DF 2 "general_operand" "")))] 2651 "TARGET_68881 || TARGET_FPA" 2652 "") 2653 2654(define_insn "" 2655 [(set (match_operand:DF 0 "general_operand" "=x,y,y") 2656 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF") 2657 (match_operand:DF 2 "general_operand" "xH,rmF,0")))] 2658 "TARGET_FPA" 2659 "* 2660{ 2661 if (rtx_equal_p (operands[0], operands[2])) 2662 return \"fprdiv%.d %y1,%0\"; 2663 if (rtx_equal_p (operands[0], operands[1])) 2664 return \"fpdiv%.d %y2,%0\"; 2665 if (which_alternative == 0) 2666 return \"fpdiv3%.d %w2,%w1,%0\"; 2667 return \"fpdiv3%.d %x2,%x1,%x0\"; 2668}") 2669 2670(define_insn "" 2671 [(set (match_operand:DF 0 "general_operand" "=f") 2672 (div:DF (match_operand:DF 1 "general_operand" "0") 2673 (match_operand:DF 2 "general_operand" "fmG")))] 2674 "TARGET_68881" 2675 "* 2676{ 2677 if (REG_P (operands[2])) 2678 return \"f%&div%.x %2,%0\"; 2679 return \"f%&div%.d %f2,%0\"; 2680}") 2681 2682(define_expand "divsf3" 2683 [(set (match_operand:SF 0 "general_operand" "") 2684 (div:SF (match_operand:SF 1 "general_operand" "") 2685 (match_operand:SF 2 "general_operand" "")))] 2686 "TARGET_68881 || TARGET_FPA" 2687 "") 2688 2689(define_insn "" 2690 [(set (match_operand:SF 0 "general_operand" "=x,y,y") 2691 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF") 2692 (match_operand:SF 2 "general_operand" "xH,rmF,0")))] 2693 "TARGET_FPA" 2694 "* 2695{ 2696 if (rtx_equal_p (operands[0], operands[1])) 2697 return \"fpdiv%.s %w2,%0\"; 2698 if (rtx_equal_p (operands[0], operands[2])) 2699 return \"fprdiv%.s %w1,%0\"; 2700 if (which_alternative == 0) 2701 return \"fpdiv3%.s %w2,%w1,%0\"; 2702 return \"fpdiv3%.s %2,%1,%0\"; 2703}") 2704 2705(define_insn "" 2706 [(set (match_operand:SF 0 "general_operand" "=f") 2707 (div:SF (match_operand:SF 1 "general_operand" "0") 2708 (match_operand:SF 2 "general_operand" "fdmF")))] 2709 "TARGET_68881" 2710 "* 2711{ 2712#ifdef FSGLDIV_USE_S 2713 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2714 return (TARGET_68040_ONLY 2715 ? \"fsdiv%.s %2,%0\" 2716 : \"fsgldiv%.s %2,%0\"); 2717#else 2718 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2719 return (TARGET_68040_ONLY 2720 ? \"fsdiv%.x %2,%0\" 2721 : \"fsgldiv%.x %2,%0\"); 2722#endif 2723 return (TARGET_68040_ONLY 2724 ? \"fsdiv%.s %f2,%0\" 2725 : \"fsgldiv%.s %f2,%0\"); 2726}") 2727 2728;; Remainder instructions. 2729 2730(define_insn "modhi3" 2731 [(set (match_operand:HI 0 "general_operand" "=d") 2732 (mod:HI (match_operand:HI 1 "general_operand" "0") 2733 (match_operand:HI 2 "general_operand" "dmn")))] 2734 "" 2735 "* 2736{ 2737 /* The swap insn produces cc's that don't correspond to the result. */ 2738 CC_STATUS_INIT; 2739#ifdef MOTOROLA 2740 return \"ext%.l %0\;divs%.w %2,%0\;swap %0\"; 2741#else 2742 return \"extl %0\;divs %2,%0\;swap %0\"; 2743#endif 2744}") 2745 2746(define_insn "modhisi3" 2747 [(set (match_operand:HI 0 "general_operand" "=d") 2748 (truncate:HI 2749 (mod:SI 2750 (match_operand:SI 1 "general_operand" "0") 2751 (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] 2752 "" 2753 "* 2754{ 2755 /* The swap insn produces cc's that don't correspond to the result. */ 2756 CC_STATUS_INIT; 2757#ifdef MOTOROLA 2758 return \"divs%.w %2,%0\;swap %0\"; 2759#else 2760 return \"divs %2,%0\;swap %0\"; 2761#endif 2762}") 2763 2764(define_insn "" 2765 [(set (match_operand:HI 0 "general_operand" "=d") 2766 (truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0") 2767 (match_operand:SI 2 "const_int_operand" "n"))))] 2768 "" 2769 "* 2770{ 2771 /* The swap insn produces cc's that don't correspond to the result. */ 2772 CC_STATUS_INIT; 2773#ifdef MOTOROLA 2774 return \"divs%.w %2,%0\;swap %0\"; 2775#else 2776 return \"divs %2,%0\;swap %0\"; 2777#endif 2778}") 2779 2780(define_insn "umodhi3" 2781 [(set (match_operand:HI 0 "general_operand" "=d") 2782 (umod:HI (match_operand:HI 1 "general_operand" "0") 2783 (match_operand:HI 2 "general_operand" "dmn")))] 2784 "" 2785 "* 2786{ 2787 /* The swap insn produces cc's that don't correspond to the result. */ 2788 CC_STATUS_INIT; 2789#ifdef MOTOROLA 2790 return \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\;swap %0\"; 2791#else 2792 return \"andl %#0xFFFF,%0\;divu %2,%0\;swap %0\"; 2793#endif 2794}") 2795 2796(define_insn "umodhisi3" 2797 [(set (match_operand:HI 0 "general_operand" "=d") 2798 (truncate:HI 2799 (umod:SI 2800 (match_operand:SI 1 "general_operand" "0") 2801 (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] 2802 "" 2803 "* 2804{ 2805 /* The swap insn produces cc's that don't correspond to the result. */ 2806 CC_STATUS_INIT; 2807#ifdef MOTOROLA 2808 return \"divu%.w %2,%0\;swap %0\"; 2809#else 2810 return \"divu %2,%0\;swap %0\"; 2811#endif 2812}") 2813 2814(define_insn "" 2815 [(set (match_operand:HI 0 "general_operand" "=d") 2816 (truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0") 2817 (match_operand:SI 2 "const_int_operand" "n"))))] 2818 "" 2819 "* 2820{ 2821 /* The swap insn produces cc's that don't correspond to the result. */ 2822 CC_STATUS_INIT; 2823#ifdef MOTOROLA 2824 return \"divu%.w %2,%0\;swap %0\"; 2825#else 2826 return \"divu %2,%0\;swap %0\"; 2827#endif 2828}") 2829 2830(define_insn "divmodsi4" 2831 [(set (match_operand:SI 0 "general_operand" "=d") 2832 (div:SI (match_operand:SI 1 "general_operand" "0") 2833 (match_operand:SI 2 "general_operand" "dmsK"))) 2834 (set (match_operand:SI 3 "general_operand" "=d") 2835 (mod:SI (match_dup 1) (match_dup 2)))] 2836 "TARGET_68020" 2837 "* 2838{ 2839 if (find_reg_note (insn, REG_UNUSED, operands[3])) 2840 return \"divs%.l %2,%0\"; 2841 else 2842 return \"divsl%.l %2,%3:%0\"; 2843}") 2844 2845(define_insn "udivmodsi4" 2846 [(set (match_operand:SI 0 "general_operand" "=d") 2847 (udiv:SI (match_operand:SI 1 "general_operand" "0") 2848 (match_operand:SI 2 "general_operand" "dmsK"))) 2849 (set (match_operand:SI 3 "general_operand" "=d") 2850 (umod:SI (match_dup 1) (match_dup 2)))] 2851 "TARGET_68020" 2852 "* 2853{ 2854 if (find_reg_note (insn, REG_UNUSED, operands[3])) 2855 return \"divu%.l %2,%0\"; 2856 else 2857 return \"divul%.l %2,%3:%0\"; 2858}") 2859 2860;; logical-and instructions 2861 2862;; Prevent AND from being made with sp. This doesn't exist in the machine 2863;; and reload will cause inefficient code. Since sp is a FIXED_REG, we 2864;; can't allocate pseudos into it. 2865(define_insn "andsi3" 2866 [(set (match_operand:SI 0 "not_sp_operand" "=m,d") 2867 (and:SI (match_operand:SI 1 "general_operand" "%0,0") 2868 (match_operand:SI 2 "general_operand" "dKs,dmKs")))] 2869 "" 2870 "* 2871{ 2872 int logval; 2873 if (GET_CODE (operands[2]) == CONST_INT 2874 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff 2875 && (DATA_REG_P (operands[0]) 2876 || offsettable_memref_p (operands[0]))) 2877 { 2878 if (GET_CODE (operands[0]) != REG) 2879 operands[0] = adj_offsettable_operand (operands[0], 2); 2880 operands[2] = gen_rtx (CONST_INT, VOIDmode, 2881 INTVAL (operands[2]) & 0xffff); 2882 /* Do not delete a following tstl %0 insn; that would be incorrect. */ 2883 CC_STATUS_INIT; 2884 if (operands[2] == const0_rtx) 2885 return \"clr%.w %0\"; 2886 return \"and%.w %2,%0\"; 2887 } 2888 if (GET_CODE (operands[2]) == CONST_INT 2889 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 2890 && (DATA_REG_P (operands[0]) 2891 || offsettable_memref_p (operands[0]))) 2892 { 2893 if (DATA_REG_P (operands[0])) 2894 { 2895 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); 2896 } 2897 else 2898 { 2899 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); 2900 } 2901 /* This does not set condition codes in a standard way. */ 2902 CC_STATUS_INIT; 2903 return \"bclr %1,%0\"; 2904 } 2905 return \"and%.l %2,%0\"; 2906}") 2907 2908(define_insn "andhi3" 2909 [(set (match_operand:HI 0 "general_operand" "=m,d") 2910 (and:HI (match_operand:HI 1 "general_operand" "%0,0") 2911 (match_operand:HI 2 "general_operand" "dn,dmn")))] 2912 "" 2913 "and%.w %2,%0") 2914 2915(define_insn "" 2916 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 2917 (and:HI (match_dup 0) 2918 (match_operand:HI 1 "general_operand" "dn,dmn")))] 2919 "" 2920 "and%.w %1,%0") 2921 2922(define_insn "" 2923 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 2924 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn") 2925 (match_dup 0)))] 2926 "" 2927 "and%.w %1,%0") 2928 2929(define_insn "andqi3" 2930 [(set (match_operand:QI 0 "general_operand" "=m,d") 2931 (and:QI (match_operand:QI 1 "general_operand" "%0,0") 2932 (match_operand:QI 2 "general_operand" "dn,dmn")))] 2933 "" 2934 "and%.b %2,%0") 2935 2936(define_insn "" 2937 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 2938 (and:QI (match_dup 0) 2939 (match_operand:QI 1 "general_operand" "dn,dmn")))] 2940 "" 2941 "and%.b %1,%0") 2942 2943(define_insn "" 2944 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 2945 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn") 2946 (match_dup 0)))] 2947 "" 2948 "and%.b %1,%0") 2949 2950;; inclusive-or instructions 2951 2952(define_insn "iorsi3" 2953 [(set (match_operand:SI 0 "general_operand" "=m,d") 2954 (ior:SI (match_operand:SI 1 "general_operand" "%0,0") 2955 (match_operand:SI 2 "general_operand" "dKs,dmKs")))] 2956 "" 2957 "* 2958{ 2959 register int logval; 2960 if (GET_CODE (operands[2]) == CONST_INT 2961 && INTVAL (operands[2]) >> 16 == 0 2962 && (DATA_REG_P (operands[0]) 2963 || offsettable_memref_p (operands[0]))) 2964 { 2965 if (GET_CODE (operands[0]) != REG) 2966 operands[0] = adj_offsettable_operand (operands[0], 2); 2967 /* Do not delete a following tstl %0 insn; that would be incorrect. */ 2968 CC_STATUS_INIT; 2969 return \"or%.w %2,%0\"; 2970 } 2971 if (GET_CODE (operands[2]) == CONST_INT 2972 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 2973 && (DATA_REG_P (operands[0]) 2974 || offsettable_memref_p (operands[0]))) 2975 { 2976 if (DATA_REG_P (operands[0])) 2977 { 2978 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); 2979 } 2980 else 2981 { 2982 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); 2983 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); 2984 } 2985 return \"bset %1,%0\"; 2986 } 2987 return \"or%.l %2,%0\"; 2988}") 2989 2990(define_insn "iorhi3" 2991 [(set (match_operand:HI 0 "general_operand" "=m,d") 2992 (ior:HI (match_operand:HI 1 "general_operand" "%0,0") 2993 (match_operand:HI 2 "general_operand" "dn,dmn")))] 2994 "" 2995 "or%.w %2,%0") 2996 2997(define_insn "" 2998 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 2999 (ior:HI (match_dup 0) 3000 (match_operand:HI 1 "general_operand" "dn,dmn")))] 3001 "" 3002 "or%.w %1,%0") 3003 3004(define_insn "" 3005 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 3006 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn") 3007 (match_dup 0)))] 3008 "" 3009 "or%.w %1,%0") 3010 3011(define_insn "iorqi3" 3012 [(set (match_operand:QI 0 "general_operand" "=m,d") 3013 (ior:QI (match_operand:QI 1 "general_operand" "%0,0") 3014 (match_operand:QI 2 "general_operand" "dn,dmn")))] 3015 "" 3016 "or%.b %2,%0") 3017 3018(define_insn "" 3019 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 3020 (ior:QI (match_dup 0) 3021 (match_operand:QI 1 "general_operand" "dn,dmn")))] 3022 "" 3023 "or%.b %1,%0") 3024 3025(define_insn "" 3026 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 3027 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn") 3028 (match_dup 0)))] 3029 "" 3030 "or%.b %1,%0") 3031 3032;; xor instructions 3033 3034(define_insn "xorsi3" 3035 [(set (match_operand:SI 0 "general_operand" "=do,m") 3036 (xor:SI (match_operand:SI 1 "general_operand" "%0,0") 3037 (match_operand:SI 2 "general_operand" "di,dKs")))] 3038 "" 3039 "* 3040{ 3041 if (GET_CODE (operands[2]) == CONST_INT 3042 && INTVAL (operands[2]) >> 16 == 0 3043 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))) 3044 { 3045 if (! DATA_REG_P (operands[0])) 3046 operands[0] = adj_offsettable_operand (operands[0], 2); 3047 /* Do not delete a following tstl %0 insn; that would be incorrect. */ 3048 CC_STATUS_INIT; 3049 return \"eor%.w %2,%0\"; 3050 } 3051 return \"eor%.l %2,%0\"; 3052}") 3053 3054(define_insn "xorhi3" 3055 [(set (match_operand:HI 0 "general_operand" "=dm") 3056 (xor:HI (match_operand:HI 1 "general_operand" "%0") 3057 (match_operand:HI 2 "general_operand" "dn")))] 3058 "" 3059 "eor%.w %2,%0") 3060 3061(define_insn "" 3062 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) 3063 (xor:HI (match_dup 0) 3064 (match_operand:HI 1 "general_operand" "dn")))] 3065 "" 3066 "eor%.w %1,%0") 3067 3068 3069(define_insn "" 3070 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) 3071 (xor:HI (match_operand:HI 1 "general_operand" "dn") 3072 (match_dup 0)))] 3073 "" 3074 "eor%.w %1,%0") 3075 3076(define_insn "xorqi3" 3077 [(set (match_operand:QI 0 "general_operand" "=dm") 3078 (xor:QI (match_operand:QI 1 "general_operand" "%0") 3079 (match_operand:QI 2 "general_operand" "dn")))] 3080 "" 3081 "eor%.b %2,%0") 3082 3083(define_insn "" 3084 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) 3085 (xor:QI (match_dup 0) 3086 (match_operand:QI 1 "general_operand" "dn")))] 3087 "" 3088 "eor%.b %1,%0") 3089 3090(define_insn "" 3091 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) 3092 (xor:QI (match_operand:QI 1 "general_operand" "dn") 3093 (match_dup 0)))] 3094 "" 3095 "eor%.b %1,%0") 3096 3097;; negation instructions 3098 3099(define_insn "negsi2" 3100 [(set (match_operand:SI 0 "general_operand" "=dm") 3101 (neg:SI (match_operand:SI 1 "general_operand" "0")))] 3102 "" 3103 "neg%.l %0") 3104 3105(define_insn "neghi2" 3106 [(set (match_operand:HI 0 "general_operand" "=dm") 3107 (neg:HI (match_operand:HI 1 "general_operand" "0")))] 3108 "" 3109 "neg%.w %0") 3110 3111(define_insn "" 3112 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) 3113 (neg:HI (match_dup 0)))] 3114 "" 3115 "neg%.w %0") 3116 3117(define_insn "negqi2" 3118 [(set (match_operand:QI 0 "general_operand" "=dm") 3119 (neg:QI (match_operand:QI 1 "general_operand" "0")))] 3120 "" 3121 "neg%.b %0") 3122 3123(define_insn "" 3124 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) 3125 (neg:QI (match_dup 0)))] 3126 "" 3127 "neg%.b %0") 3128 3129(define_expand "negsf2" 3130 [(set (match_operand:SF 0 "general_operand" "") 3131 (neg:SF (match_operand:SF 1 "general_operand" "")))] 3132 "TARGET_68881 || TARGET_FPA" 3133 "") 3134 3135(define_insn "" 3136 [(set (match_operand:SF 0 "general_operand" "=x,y") 3137 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))] 3138 "TARGET_FPA" 3139 "fpneg%.s %w1,%0") 3140 3141(define_insn "" 3142 [(set (match_operand:SF 0 "general_operand" "=f,d") 3143 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))] 3144 "TARGET_68881" 3145 "* 3146{ 3147 if (DATA_REG_P (operands[0])) 3148 { 3149 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31); 3150 return \"bchg %1,%0\"; 3151 } 3152 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) 3153 return \"f%$neg%.x %1,%0\"; 3154 return \"f%$neg%.s %f1,%0\"; 3155}") 3156 3157(define_expand "negdf2" 3158 [(set (match_operand:DF 0 "general_operand" "") 3159 (neg:DF (match_operand:DF 1 "general_operand" "")))] 3160 "TARGET_68881 || TARGET_FPA" 3161 "") 3162 3163(define_insn "" 3164 [(set (match_operand:DF 0 "general_operand" "=x,y") 3165 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))] 3166 "TARGET_FPA" 3167 "fpneg%.d %y1, %0") 3168 3169(define_insn "" 3170 [(set (match_operand:DF 0 "general_operand" "=f,d") 3171 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))] 3172 "TARGET_68881" 3173 "* 3174{ 3175 if (DATA_REG_P (operands[0])) 3176 { 3177 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31); 3178 return \"bchg %1,%0\"; 3179 } 3180 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) 3181 return \"f%&neg%.x %1,%0\"; 3182 return \"f%&neg%.d %f1,%0\"; 3183}") 3184 3185;; Sqrt instruction for the 68881 3186 3187(define_insn "sqrtdf2" 3188 [(set (match_operand:DF 0 "general_operand" "=f") 3189 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))] 3190 "TARGET_68881" 3191 "* 3192{ 3193 if (FP_REG_P (operands[1])) 3194 return \"fsqrt%.x %1,%0\"; 3195 else 3196 return \"fsqrt%.d %1,%0\"; 3197}") 3198 3199;; Absolute value instructions 3200 3201(define_expand "abssf2" 3202 [(set (match_operand:SF 0 "general_operand" "") 3203 (abs:SF (match_operand:SF 1 "general_operand" "")))] 3204 "TARGET_68881 || TARGET_FPA" 3205 "") 3206 3207(define_insn "" 3208 [(set (match_operand:SF 0 "general_operand" "=x,y") 3209 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))] 3210 "TARGET_FPA" 3211 "fpabs%.s %y1,%0") 3212 3213(define_insn "" 3214 [(set (match_operand:SF 0 "general_operand" "=f") 3215 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))] 3216 "TARGET_68881" 3217 "* 3218{ 3219 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) 3220 return \"f%$abs%.x %1,%0\"; 3221 return \"f%$abs%.s %f1,%0\"; 3222}") 3223 3224(define_expand "absdf2" 3225 [(set (match_operand:DF 0 "general_operand" "") 3226 (abs:DF (match_operand:DF 1 "general_operand" "")))] 3227 "TARGET_68881 || TARGET_FPA" 3228 "") 3229 3230(define_insn "" 3231 [(set (match_operand:DF 0 "general_operand" "=x,y") 3232 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))] 3233 "TARGET_FPA" 3234 "fpabs%.d %y1,%0") 3235 3236(define_insn "" 3237 [(set (match_operand:DF 0 "general_operand" "=f") 3238 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] 3239 "TARGET_68881" 3240 "* 3241{ 3242 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) 3243 return \"f%&abs%.x %1,%0\"; 3244 return \"f%&abs%.d %f1,%0\"; 3245}") 3246 3247;; one complement instructions 3248 3249(define_insn "one_cmplsi2" 3250 [(set (match_operand:SI 0 "general_operand" "=dm") 3251 (not:SI (match_operand:SI 1 "general_operand" "0")))] 3252 "" 3253 "not%.l %0") 3254 3255(define_insn "one_cmplhi2" 3256 [(set (match_operand:HI 0 "general_operand" "=dm") 3257 (not:HI (match_operand:HI 1 "general_operand" "0")))] 3258 "" 3259 "not%.w %0") 3260 3261(define_insn "" 3262 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) 3263 (not:HI (match_dup 0)))] 3264 "" 3265 "not%.w %0") 3266 3267(define_insn "one_cmplqi2" 3268 [(set (match_operand:QI 0 "general_operand" "=dm") 3269 (not:QI (match_operand:QI 1 "general_operand" "0")))] 3270 "" 3271 "not%.b %0") 3272 3273(define_insn "" 3274 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) 3275 (not:QI (match_dup 0)))] 3276 "" 3277 "not%.b %0") 3278 3279;; arithmetic shift instructions 3280;; We don't need the shift memory by 1 bit instruction 3281 3282;; On all 68k models, this makes faster code in a special case. 3283 3284(define_insn "" 3285 [(set (match_operand:SI 0 "register_operand" "=d") 3286 (ashift:SI (match_operand:SI 1 "register_operand" "0") 3287 (match_operand:SI 2 "immediate_operand" "i")))] 3288 "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" 3289 "* 3290{ 3291 CC_STATUS_INIT; 3292 return \"swap %0\;clr%.w %0\"; 3293}") 3294 3295;; On the 68000, this makes faster code in a special case. 3296 3297(define_insn "" 3298 [(set (match_operand:SI 0 "register_operand" "=d") 3299 (ashift:SI (match_operand:SI 1 "register_operand" "0") 3300 (match_operand:SI 2 "immediate_operand" "i")))] 3301 "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT 3302 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" 3303 "* 3304{ 3305 CC_STATUS_INIT; 3306 3307 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); 3308 return \"asl%.w %2,%0\;swap %0\;clr%.w %0\"; 3309}") 3310 3311(define_insn "ashlsi3" 3312 [(set (match_operand:SI 0 "register_operand" "=d") 3313 (ashift:SI (match_operand:SI 1 "register_operand" "0") 3314 (match_operand:SI 2 "general_operand" "dI")))] 3315 "" 3316 "* 3317{ 3318 if (operands[2] == const1_rtx) 3319 return \"add%.l %0,%0\"; 3320 return \"asl%.l %2,%0\"; 3321}") 3322 3323(define_insn "ashlhi3" 3324 [(set (match_operand:HI 0 "register_operand" "=d") 3325 (ashift:HI (match_operand:HI 1 "register_operand" "0") 3326 (match_operand:HI 2 "general_operand" "dI")))] 3327 "" 3328 "asl%.w %2,%0") 3329 3330(define_insn "" 3331 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3332 (ashift:HI (match_dup 0) 3333 (match_operand:HI 1 "general_operand" "dI")))] 3334 "" 3335 "asl%.w %1,%0") 3336 3337(define_insn "ashlqi3" 3338 [(set (match_operand:QI 0 "register_operand" "=d") 3339 (ashift:QI (match_operand:QI 1 "register_operand" "0") 3340 (match_operand:QI 2 "general_operand" "dI")))] 3341 "" 3342 "asl%.b %2,%0") 3343 3344(define_insn "" 3345 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3346 (ashift:QI (match_dup 0) 3347 (match_operand:QI 1 "general_operand" "dI")))] 3348 "" 3349 "asl%.b %1,%0") 3350 3351;; On all 68k models, this makes faster code in a special case. 3352 3353(define_insn "" 3354 [(set (match_operand:SI 0 "register_operand" "=d") 3355 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 3356 (match_operand:SI 2 "immediate_operand" "i")))] 3357 "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" 3358 "swap %0\;ext%.l %0") 3359 3360;; On the 68000, this makes faster code in a special case. 3361 3362(define_insn "" 3363 [(set (match_operand:SI 0 "register_operand" "=d") 3364 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 3365 (match_operand:SI 2 "immediate_operand" "i")))] 3366 "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT 3367 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" 3368 "* 3369{ 3370 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); 3371 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\"; 3372}") 3373 3374(define_insn "ashrsi3" 3375 [(set (match_operand:SI 0 "register_operand" "=d") 3376 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 3377 (match_operand:SI 2 "general_operand" "dI")))] 3378 "" 3379 "* 3380{ 3381 return \"asr%.l %2,%0\"; 3382}") 3383 3384(define_insn "ashrhi3" 3385 [(set (match_operand:HI 0 "register_operand" "=d") 3386 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") 3387 (match_operand:HI 2 "general_operand" "dI")))] 3388 "" 3389 "asr%.w %2,%0") 3390 3391(define_insn "" 3392 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3393 (ashiftrt:HI (match_dup 0) 3394 (match_operand:HI 1 "general_operand" "dI")))] 3395 "" 3396 "asr%.w %1,%0") 3397 3398(define_insn "ashrqi3" 3399 [(set (match_operand:QI 0 "register_operand" "=d") 3400 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") 3401 (match_operand:QI 2 "general_operand" "dI")))] 3402 "" 3403 "asr%.b %2,%0") 3404 3405(define_insn "" 3406 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3407 (ashiftrt:QI (match_dup 0) 3408 (match_operand:QI 1 "general_operand" "dI")))] 3409 "" 3410 "asr%.b %1,%0") 3411 3412;; logical shift instructions 3413 3414;; On all 68k models, this makes faster code in a special case. 3415 3416(define_insn "" 3417 [(set (match_operand:SI 0 "register_operand" "=d") 3418 (lshift:SI (match_operand:SI 1 "register_operand" "0") 3419 (match_operand:SI 2 "immediate_operand" "i")))] 3420 "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" 3421 "* 3422{ 3423 CC_STATUS_INIT; 3424 return \"swap %0\;clr%.w %0\"; 3425}") 3426 3427;; On the 68000, this makes faster code in a special case. 3428 3429(define_insn "" 3430 [(set (match_operand:SI 0 "register_operand" "=d") 3431 (lshift:SI (match_operand:SI 1 "register_operand" "0") 3432 (match_operand:SI 2 "immediate_operand" "i")))] 3433 "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT 3434 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" 3435 "* 3436{ 3437 CC_STATUS_INIT; 3438 3439 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); 3440 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\"; 3441}") 3442 3443(define_insn "lshlsi3" 3444 [(set (match_operand:SI 0 "register_operand" "=d") 3445 (lshift:SI (match_operand:SI 1 "register_operand" "0") 3446 (match_operand:SI 2 "general_operand" "dI")))] 3447 "" 3448 "* 3449{ 3450 if (operands[2] == const1_rtx) 3451 return \"add%.l %0,%0\"; 3452 return \"lsl%.l %2,%0\"; 3453}") 3454 3455(define_insn "lshlhi3" 3456 [(set (match_operand:HI 0 "register_operand" "=d") 3457 (lshift:HI (match_operand:HI 1 "register_operand" "0") 3458 (match_operand:HI 2 "general_operand" "dI")))] 3459 "" 3460 "lsl%.w %2,%0") 3461 3462(define_insn "" 3463 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3464 (lshift:HI (match_dup 0) 3465 (match_operand:HI 1 "general_operand" "dI")))] 3466 "" 3467 "lsl%.w %1,%0") 3468 3469(define_insn "lshlqi3" 3470 [(set (match_operand:QI 0 "register_operand" "=d") 3471 (lshift:QI (match_operand:QI 1 "register_operand" "0") 3472 (match_operand:QI 2 "general_operand" "dI")))] 3473 "" 3474 "lsl%.b %2,%0") 3475 3476(define_insn "" 3477 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3478 (lshift:QI (match_dup 0) 3479 (match_operand:QI 1 "general_operand" "dI")))] 3480 "" 3481 "lsl%.b %1,%0") 3482 3483;; On all 68k models, this makes faster code in a special case. 3484 3485(define_insn "" 3486 [(set (match_operand:SI 0 "register_operand" "=d") 3487 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 3488 (match_operand:SI 2 "immediate_operand" "i")))] 3489 "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" 3490 "* 3491{ 3492 CC_STATUS_INIT; 3493 return \"clr%.w %0\;swap %0\"; 3494}") 3495 3496;; On the 68000, this makes faster code in a special case. 3497 3498(define_insn "" 3499 [(set (match_operand:SI 0 "register_operand" "=d") 3500 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 3501 (match_operand:SI 2 "immediate_operand" "i")))] 3502 "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT 3503 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" 3504 "* 3505{ 3506 /* I think lsr%.w sets the CC properly. */ 3507 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); 3508 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\"; 3509}") 3510 3511(define_insn "lshrsi3" 3512 [(set (match_operand:SI 0 "register_operand" "=d") 3513 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 3514 (match_operand:SI 2 "general_operand" "dI")))] 3515 "" 3516 "* 3517{ 3518 return \"lsr%.l %2,%0\"; 3519}") 3520 3521(define_insn "lshrhi3" 3522 [(set (match_operand:HI 0 "register_operand" "=d") 3523 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") 3524 (match_operand:HI 2 "general_operand" "dI")))] 3525 "" 3526 "lsr%.w %2,%0") 3527 3528(define_insn "" 3529 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3530 (lshiftrt:HI (match_dup 0) 3531 (match_operand:HI 1 "general_operand" "dI")))] 3532 "" 3533 "lsr%.w %1,%0") 3534 3535(define_insn "lshrqi3" 3536 [(set (match_operand:QI 0 "register_operand" "=d") 3537 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") 3538 (match_operand:QI 2 "general_operand" "dI")))] 3539 "" 3540 "lsr%.b %2,%0") 3541 3542(define_insn "" 3543 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3544 (lshiftrt:QI (match_dup 0) 3545 (match_operand:QI 1 "general_operand" "dI")))] 3546 "" 3547 "lsr%.b %1,%0") 3548 3549;; rotate instructions 3550 3551(define_insn "rotlsi3" 3552 [(set (match_operand:SI 0 "register_operand" "=d") 3553 (rotate:SI (match_operand:SI 1 "register_operand" "0") 3554 (match_operand:SI 2 "general_operand" "dI")))] 3555 "" 3556 "rol%.l %2,%0") 3557 3558(define_insn "rotlhi3" 3559 [(set (match_operand:HI 0 "register_operand" "=d") 3560 (rotate:HI (match_operand:HI 1 "register_operand" "0") 3561 (match_operand:HI 2 "general_operand" "dI")))] 3562 "" 3563 "rol%.w %2,%0") 3564 3565 3566(define_insn "" 3567 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3568 (rotate:HI (match_dup 0) 3569 (match_operand:HI 1 "general_operand" "dI")))] 3570 "" 3571 "rol%.w %1,%0") 3572 3573(define_insn "rotlqi3" 3574 [(set (match_operand:QI 0 "register_operand" "=d") 3575 (rotate:QI (match_operand:QI 1 "register_operand" "0") 3576 (match_operand:QI 2 "general_operand" "dI")))] 3577 "" 3578 "rol%.b %2,%0") 3579 3580(define_insn "" 3581 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3582 (rotate:QI (match_dup 0) 3583 (match_operand:QI 1 "general_operand" "dI")))] 3584 "" 3585 "rol%.b %1,%0") 3586 3587(define_insn "rotrsi3" 3588 [(set (match_operand:SI 0 "register_operand" "=d") 3589 (rotatert:SI (match_operand:SI 1 "register_operand" "0") 3590 (match_operand:SI 2 "general_operand" "dI")))] 3591 "" 3592 "ror%.l %2,%0") 3593 3594(define_insn "rotrhi3" 3595 [(set (match_operand:HI 0 "register_operand" "=d") 3596 (rotatert:HI (match_operand:HI 1 "register_operand" "0") 3597 (match_operand:HI 2 "general_operand" "dI")))] 3598 "" 3599 "ror%.w %2,%0") 3600 3601(define_insn "" 3602 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3603 (rotatert:HI (match_dup 0) 3604 (match_operand:HI 1 "general_operand" "dI")))] 3605 "" 3606 "ror%.w %1,%0") 3607 3608(define_insn "rotrqi3" 3609 [(set (match_operand:QI 0 "register_operand" "=d") 3610 (rotatert:QI (match_operand:QI 1 "register_operand" "0") 3611 (match_operand:QI 2 "general_operand" "dI")))] 3612 "" 3613 "ror%.b %2,%0") 3614 3615(define_insn "" 3616 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3617 (rotatert:QI (match_dup 0) 3618 (match_operand:QI 1 "general_operand" "dI")))] 3619 "" 3620 "ror%.b %1,%0") 3621 3622;; Special cases of bit-field insns which we should 3623;; recognize in preference to the general case. 3624;; These handle aligned 8-bit and 16-bit fields, 3625;; which can usually be done with move instructions. 3626 3627; 3628; Special case for 32-bit field in memory. This only occurs when 32-bit 3629; alignment of structure members is specified. 3630; 3631; The move is allowed to be odd byte aligned, because that's still faster 3632; than an odd byte aligned bit field instruction. 3633; 3634(define_insn "" 3635 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o") 3636 (match_operand:SI 1 "immediate_operand" "i") 3637 (match_operand:SI 2 "immediate_operand" "i")) 3638 (match_operand:SI 3 "general_operand" "rmi"))] 3639 "TARGET_68020 && TARGET_BITFIELD 3640 && GET_CODE (operands[1]) == CONST_INT 3641 && (INTVAL (operands[1]) == 32) 3642 && GET_CODE (operands[2]) == CONST_INT 3643 && (INTVAL (operands[2]) % 8) == 0 3644 && ! mode_dependent_address_p (XEXP (operands[0], 0))" 3645 "* 3646{ 3647 operands[0] 3648 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); 3649 3650 return \"move%.l %3,%0\"; 3651}") 3652 3653(define_insn "" 3654 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do") 3655 (match_operand:SI 1 "immediate_operand" "i") 3656 (match_operand:SI 2 "immediate_operand" "i")) 3657 (match_operand:SI 3 "general_operand" "d"))] 3658 "TARGET_68020 && TARGET_BITFIELD 3659 && GET_CODE (operands[1]) == CONST_INT 3660 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 3661 && GET_CODE (operands[2]) == CONST_INT 3662 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 3663 && (GET_CODE (operands[0]) == REG 3664 || ! mode_dependent_address_p (XEXP (operands[0], 0)))" 3665 "* 3666{ 3667 if (REG_P (operands[0])) 3668 { 3669 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32) 3670 return \"bfins %3,%0{%b2:%b1}\"; 3671 } 3672 else 3673 operands[0] 3674 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); 3675 3676 if (GET_CODE (operands[3]) == MEM) 3677 operands[3] = adj_offsettable_operand (operands[3], 3678 (32 - INTVAL (operands[1])) / 8); 3679 if (INTVAL (operands[1]) == 8) 3680 return \"move%.b %3,%0\"; 3681 return \"move%.w %3,%0\"; 3682}") 3683 3684 3685; 3686; Special case for 32-bit field in memory. This only occurs when 32-bit 3687; alignment of structure members is specified. 3688; 3689; The move is allowed to be odd byte aligned, because that's still faster 3690; than an odd byte aligned bit field instruction. 3691; 3692(define_insn "" 3693 [(set (match_operand:SI 0 "general_operand" "=rm") 3694 (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o") 3695 (match_operand:SI 2 "immediate_operand" "i") 3696 (match_operand:SI 3 "immediate_operand" "i")))] 3697 "TARGET_68020 && TARGET_BITFIELD 3698 && GET_CODE (operands[2]) == CONST_INT 3699 && (INTVAL (operands[2]) == 32) 3700 && GET_CODE (operands[3]) == CONST_INT 3701 && (INTVAL (operands[3]) % 8) == 0 3702 && ! mode_dependent_address_p (XEXP (operands[1], 0))" 3703 "* 3704{ 3705 operands[1] 3706 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 3707 3708 return \"move%.l %1,%0\"; 3709}") 3710 3711(define_insn "" 3712 [(set (match_operand:SI 0 "general_operand" "=&d") 3713 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do") 3714 (match_operand:SI 2 "immediate_operand" "i") 3715 (match_operand:SI 3 "immediate_operand" "i")))] 3716 "TARGET_68020 && TARGET_BITFIELD 3717 && GET_CODE (operands[2]) == CONST_INT 3718 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 3719 && GET_CODE (operands[3]) == CONST_INT 3720 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 3721 && (GET_CODE (operands[1]) == REG 3722 || ! mode_dependent_address_p (XEXP (operands[1], 0)))" 3723 "* 3724{ 3725 cc_status.flags |= CC_NOT_NEGATIVE; 3726 if (REG_P (operands[1])) 3727 { 3728 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) 3729 return \"bfextu %1{%b3:%b2},%0\"; 3730 } 3731 else 3732 operands[1] 3733 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 3734 3735 output_asm_insn (\"clr%.l %0\", operands); 3736 if (GET_CODE (operands[0]) == MEM) 3737 operands[0] = adj_offsettable_operand (operands[0], 3738 (32 - INTVAL (operands[1])) / 8); 3739 if (INTVAL (operands[2]) == 8) 3740 return \"move%.b %1,%0\"; 3741 return \"move%.w %1,%0\"; 3742}") 3743 3744; 3745; Special case for 32-bit field in memory. This only occurs when 32-bit 3746; alignment of structure members is specified. 3747; 3748; The move is allowed to be odd byte aligned, because that's still faster 3749; than an odd byte aligned bit field instruction. 3750; 3751(define_insn "" 3752 [(set (match_operand:SI 0 "general_operand" "=rm") 3753 (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o") 3754 (match_operand:SI 2 "immediate_operand" "i") 3755 (match_operand:SI 3 "immediate_operand" "i")))] 3756 "TARGET_68020 && TARGET_BITFIELD 3757 && GET_CODE (operands[2]) == CONST_INT 3758 && (INTVAL (operands[2]) == 32) 3759 && GET_CODE (operands[3]) == CONST_INT 3760 && (INTVAL (operands[3]) % 8) == 0 3761 && ! mode_dependent_address_p (XEXP (operands[1], 0))" 3762 "* 3763{ 3764 operands[1] 3765 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 3766 3767 return \"move%.l %1,%0\"; 3768}") 3769 3770(define_insn "" 3771 [(set (match_operand:SI 0 "general_operand" "=d") 3772 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do") 3773 (match_operand:SI 2 "immediate_operand" "i") 3774 (match_operand:SI 3 "immediate_operand" "i")))] 3775 "TARGET_68020 && TARGET_BITFIELD 3776 && GET_CODE (operands[2]) == CONST_INT 3777 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 3778 && GET_CODE (operands[3]) == CONST_INT 3779 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 3780 && (GET_CODE (operands[1]) == REG 3781 || ! mode_dependent_address_p (XEXP (operands[1], 0)))" 3782 "* 3783{ 3784 if (REG_P (operands[1])) 3785 { 3786 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) 3787 return \"bfexts %1{%b3:%b2},%0\"; 3788 } 3789 else 3790 operands[1] 3791 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 3792 3793 if (INTVAL (operands[2]) == 8) 3794 return \"move%.b %1,%0\;extb%.l %0\"; 3795 return \"move%.w %1,%0\;ext%.l %0\"; 3796}") 3797 3798;; Bit field instructions, general cases. 3799;; "o,d" constraint causes a nonoffsettable memref to match the "o" 3800;; so that its address is reloaded. 3801 3802(define_insn "extv" 3803 [(set (match_operand:SI 0 "general_operand" "=d,d") 3804 (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d") 3805 (match_operand:SI 2 "general_operand" "di,di") 3806 (match_operand:SI 3 "general_operand" "di,di")))] 3807 "TARGET_68020 && TARGET_BITFIELD" 3808 "bfexts %1{%b3:%b2},%0") 3809 3810(define_insn "extzv" 3811 [(set (match_operand:SI 0 "general_operand" "=d,d") 3812 (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d") 3813 (match_operand:SI 2 "general_operand" "di,di") 3814 (match_operand:SI 3 "general_operand" "di,di")))] 3815 "TARGET_68020 && TARGET_BITFIELD" 3816 "* 3817{ 3818 cc_status.flags |= CC_NOT_NEGATIVE; 3819 return \"bfextu %1{%b3:%b2},%0\"; 3820}") 3821 3822(define_insn "" 3823 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") 3824 (match_operand:SI 1 "general_operand" "di,di") 3825 (match_operand:SI 2 "general_operand" "di,di")) 3826 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)) 3827 (match_operand 3 "immediate_operand" "i,i")))] 3828 "TARGET_68020 && TARGET_BITFIELD 3829 && GET_CODE (operands[3]) == CONST_INT 3830 && (INTVAL (operands[3]) == -1 3831 || (GET_CODE (operands[1]) == CONST_INT 3832 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))" 3833 "* 3834{ 3835 CC_STATUS_INIT; 3836 return \"bfchg %0{%b2:%b1}\"; 3837}") 3838 3839(define_insn "" 3840 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") 3841 (match_operand:SI 1 "general_operand" "di,di") 3842 (match_operand:SI 2 "general_operand" "di,di")) 3843 (const_int 0))] 3844 "TARGET_68020 && TARGET_BITFIELD" 3845 "* 3846{ 3847 CC_STATUS_INIT; 3848 return \"bfclr %0{%b2:%b1}\"; 3849}") 3850 3851(define_insn "" 3852 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") 3853 (match_operand:SI 1 "general_operand" "di,di") 3854 (match_operand:SI 2 "general_operand" "di,di")) 3855 (const_int -1))] 3856 "TARGET_68020 && TARGET_BITFIELD" 3857 "* 3858{ 3859 CC_STATUS_INIT; 3860 return \"bfset %0{%b2:%b1}\"; 3861}") 3862 3863(define_insn "insv" 3864 [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") 3865 (match_operand:SI 1 "general_operand" "di,di") 3866 (match_operand:SI 2 "general_operand" "di,di")) 3867 (match_operand:SI 3 "general_operand" "d,d"))] 3868 "TARGET_68020 && TARGET_BITFIELD" 3869 "bfins %3,%0{%b2:%b1}") 3870 3871;; Now recognize bit field insns that operate on registers 3872;; (or at least were intended to do so). 3873 3874(define_insn "" 3875 [(set (match_operand:SI 0 "general_operand" "=d") 3876 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d") 3877 (match_operand:SI 2 "general_operand" "di") 3878 (match_operand:SI 3 "general_operand" "di")))] 3879 "TARGET_68020 && TARGET_BITFIELD" 3880 "bfexts %1{%b3:%b2},%0") 3881 3882(define_insn "" 3883 [(set (match_operand:SI 0 "general_operand" "=d") 3884 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d") 3885 (match_operand:SI 2 "general_operand" "di") 3886 (match_operand:SI 3 "general_operand" "di")))] 3887 "TARGET_68020 && TARGET_BITFIELD" 3888 "* 3889{ 3890 cc_status.flags |= CC_NOT_NEGATIVE; 3891 return \"bfextu %1{%b3:%b2},%0\"; 3892}") 3893 3894(define_insn "" 3895 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") 3896 (match_operand:SI 1 "general_operand" "di") 3897 (match_operand:SI 2 "general_operand" "di")) 3898 (const_int 0))] 3899 "TARGET_68020 && TARGET_BITFIELD" 3900 "* 3901{ 3902 CC_STATUS_INIT; 3903 return \"bfclr %0{%b2:%b1}\"; 3904}") 3905 3906(define_insn "" 3907 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") 3908 (match_operand:SI 1 "general_operand" "di") 3909 (match_operand:SI 2 "general_operand" "di")) 3910 (const_int -1))] 3911 "TARGET_68020 && TARGET_BITFIELD" 3912 "* 3913{ 3914 CC_STATUS_INIT; 3915 return \"bfset %0{%b2:%b1}\"; 3916}") 3917 3918(define_insn "" 3919 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") 3920 (match_operand:SI 1 "general_operand" "di") 3921 (match_operand:SI 2 "general_operand" "di")) 3922 (match_operand:SI 3 "general_operand" "d"))] 3923 "TARGET_68020 && TARGET_BITFIELD" 3924 "* 3925{ 3926#if 0 3927 /* These special cases are now recognized by a specific pattern. */ 3928 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT 3929 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16) 3930 return \"move%.w %3,%0\"; 3931 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT 3932 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8) 3933 return \"move%.b %3,%0\"; 3934#endif 3935 return \"bfins %3,%0{%b2:%b1}\"; 3936}") 3937 3938;; Special patterns for optimizing bit-field instructions. 3939 3940(define_insn "" 3941 [(set (cc0) 3942 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") 3943 (match_operand:SI 1 "general_operand" "di") 3944 (match_operand:SI 2 "general_operand" "di")))] 3945 "TARGET_68020 && TARGET_BITFIELD 3946 && GET_CODE (operands[1]) == CONST_INT" 3947 "* 3948{ 3949 if (operands[1] == const1_rtx 3950 && GET_CODE (operands[2]) == CONST_INT) 3951 { 3952 int width = GET_CODE (operands[0]) == REG ? 31 : 7; 3953 return output_btst (operands, 3954 gen_rtx (CONST_INT, VOIDmode, 3955 width - INTVAL (operands[2])), 3956 operands[0], 3957 insn, 1000); 3958 /* Pass 1000 as SIGNPOS argument so that btst will 3959 not think we are testing the sign bit for an `and' 3960 and assume that nonzero implies a negative result. */ 3961 } 3962 if (INTVAL (operands[1]) != 32) 3963 cc_status.flags = CC_NOT_NEGATIVE; 3964 return \"bftst %0{%b2:%b1}\"; 3965}") 3966 3967 3968;;; now handle the register cases 3969(define_insn "" 3970 [(set (cc0) 3971 (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d") 3972 (match_operand:SI 1 "general_operand" "di") 3973 (match_operand:SI 2 "general_operand" "di")))] 3974 "TARGET_68020 && TARGET_BITFIELD 3975 && GET_CODE (operands[1]) == CONST_INT" 3976 "* 3977{ 3978 if (operands[1] == const1_rtx 3979 && GET_CODE (operands[2]) == CONST_INT) 3980 { 3981 int width = GET_CODE (operands[0]) == REG ? 31 : 7; 3982 return output_btst (operands, 3983 gen_rtx (CONST_INT, VOIDmode, 3984 width - INTVAL (operands[2])), 3985 operands[0], 3986 insn, 1000); 3987 /* Pass 1000 as SIGNPOS argument so that btst will 3988 not think we are testing the sign bit for an `and' 3989 and assume that nonzero implies a negative result. */ 3990 } 3991 if (INTVAL (operands[1]) != 32) 3992 cc_status.flags = CC_NOT_NEGATIVE; 3993 return \"bftst %0{%b2:%b1}\"; 3994}") 3995 3996(define_insn "seq" 3997 [(set (match_operand:QI 0 "general_operand" "=d") 3998 (eq:QI (cc0) (const_int 0)))] 3999 "" 4000 "* 4001 cc_status = cc_prev_status; 4002 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\"); 4003") 4004 4005(define_insn "sne" 4006 [(set (match_operand:QI 0 "general_operand" "=d") 4007 (ne:QI (cc0) (const_int 0)))] 4008 "" 4009 "* 4010 cc_status = cc_prev_status; 4011 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\"); 4012") 4013 4014(define_insn "sgt" 4015 [(set (match_operand:QI 0 "general_operand" "=d") 4016 (gt:QI (cc0) (const_int 0)))] 4017 "" 4018 "* 4019 cc_status = cc_prev_status; 4020 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0); 4021") 4022 4023(define_insn "sgtu" 4024 [(set (match_operand:QI 0 "general_operand" "=d") 4025 (gtu:QI (cc0) (const_int 0)))] 4026 "" 4027 "* cc_status = cc_prev_status; 4028 return \"shi %0\"; ") 4029 4030(define_insn "slt" 4031 [(set (match_operand:QI 0 "general_operand" "=d") 4032 (lt:QI (cc0) (const_int 0)))] 4033 "" 4034 "* cc_status = cc_prev_status; 4035 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ") 4036 4037(define_insn "sltu" 4038 [(set (match_operand:QI 0 "general_operand" "=d") 4039 (ltu:QI (cc0) (const_int 0)))] 4040 "" 4041 "* cc_status = cc_prev_status; 4042 return \"scs %0\"; ") 4043 4044(define_insn "sge" 4045 [(set (match_operand:QI 0 "general_operand" "=d") 4046 (ge:QI (cc0) (const_int 0)))] 4047 "" 4048 "* cc_status = cc_prev_status; 4049 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ") 4050 4051(define_insn "sgeu" 4052 [(set (match_operand:QI 0 "general_operand" "=d") 4053 (geu:QI (cc0) (const_int 0)))] 4054 "" 4055 "* cc_status = cc_prev_status; 4056 return \"scc %0\"; ") 4057 4058(define_insn "sle" 4059 [(set (match_operand:QI 0 "general_operand" "=d") 4060 (le:QI (cc0) (const_int 0)))] 4061 "" 4062 "* 4063 cc_status = cc_prev_status; 4064 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0); 4065") 4066 4067(define_insn "sleu" 4068 [(set (match_operand:QI 0 "general_operand" "=d") 4069 (leu:QI (cc0) (const_int 0)))] 4070 "" 4071 "* cc_status = cc_prev_status; 4072 return \"sls %0\"; ") 4073 4074;; Basic conditional jump instructions. 4075 4076(define_insn "beq" 4077 [(set (pc) 4078 (if_then_else (eq (cc0) 4079 (const_int 0)) 4080 (label_ref (match_operand 0 "" "")) 4081 (pc)))] 4082 "" 4083 "* 4084{ 4085#ifdef MOTOROLA 4086 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\"); 4087#else 4088 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\"); 4089#endif 4090}") 4091 4092(define_insn "bne" 4093 [(set (pc) 4094 (if_then_else (ne (cc0) 4095 (const_int 0)) 4096 (label_ref (match_operand 0 "" "")) 4097 (pc)))] 4098 "" 4099 "* 4100{ 4101#ifdef MOTOROLA 4102 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\"); 4103#else 4104 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\"); 4105#endif 4106}") 4107 4108(define_insn "bgt" 4109 [(set (pc) 4110 (if_then_else (gt (cc0) 4111 (const_int 0)) 4112 (label_ref (match_operand 0 "" "")) 4113 (pc)))] 4114 "" 4115 "* 4116#ifdef MOTOROLA 4117 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0); 4118#else 4119 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0); 4120#endif 4121") 4122 4123(define_insn "bgtu" 4124 [(set (pc) 4125 (if_then_else (gtu (cc0) 4126 (const_int 0)) 4127 (label_ref (match_operand 0 "" "")) 4128 (pc)))] 4129 "" 4130 "* 4131#ifdef MOTOROLA 4132 return \"jbhi %l0\"; 4133#else 4134 return \"jhi %l0\"; 4135#endif 4136") 4137 4138(define_insn "blt" 4139 [(set (pc) 4140 (if_then_else (lt (cc0) 4141 (const_int 0)) 4142 (label_ref (match_operand 0 "" "")) 4143 (pc)))] 4144 "" 4145 "* 4146#ifdef MOTOROLA 4147 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\"); 4148#else 4149 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\"); 4150#endif 4151") 4152 4153(define_insn "bltu" 4154 [(set (pc) 4155 (if_then_else (ltu (cc0) 4156 (const_int 0)) 4157 (label_ref (match_operand 0 "" "")) 4158 (pc)))] 4159 "" 4160 "* 4161#ifdef MOTOROLA 4162 return \"jbcs %l0\"; 4163#else 4164 return \"jcs %l0\"; 4165#endif 4166") 4167 4168(define_insn "bge" 4169 [(set (pc) 4170 (if_then_else (ge (cc0) 4171 (const_int 0)) 4172 (label_ref (match_operand 0 "" "")) 4173 (pc)))] 4174 "" 4175 "* 4176#ifdef MOTOROLA 4177 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\"); 4178#else 4179 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\"); 4180#endif 4181") 4182 4183(define_insn "bgeu" 4184 [(set (pc) 4185 (if_then_else (geu (cc0) 4186 (const_int 0)) 4187 (label_ref (match_operand 0 "" "")) 4188 (pc)))] 4189 "" 4190 "* 4191#ifdef MOTOROLA 4192 return \"jbcc %l0\"; 4193#else 4194 return \"jcc %l0\"; 4195#endif 4196") 4197 4198(define_insn "ble" 4199 [(set (pc) 4200 (if_then_else (le (cc0) 4201 (const_int 0)) 4202 (label_ref (match_operand 0 "" "")) 4203 (pc)))] 4204 "" 4205 "* 4206#ifdef MOTOROLA 4207 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0); 4208#else 4209 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0); 4210#endif 4211") 4212 4213(define_insn "bleu" 4214 [(set (pc) 4215 (if_then_else (leu (cc0) 4216 (const_int 0)) 4217 (label_ref (match_operand 0 "" "")) 4218 (pc)))] 4219 "" 4220 "* 4221#ifdef MOTOROLA 4222 return \"jbls %l0\"; 4223#else 4224 return \"jls %l0\"; 4225#endif 4226") 4227 4228;; Negated conditional jump instructions. 4229 4230(define_insn "" 4231 [(set (pc) 4232 (if_then_else (eq (cc0) 4233 (const_int 0)) 4234 (pc) 4235 (label_ref (match_operand 0 "" ""))))] 4236 "" 4237 "* 4238{ 4239#ifdef MOTOROLA 4240 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\"); 4241#else 4242 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\"); 4243#endif 4244}") 4245 4246(define_insn "" 4247 [(set (pc) 4248 (if_then_else (ne (cc0) 4249 (const_int 0)) 4250 (pc) 4251 (label_ref (match_operand 0 "" ""))))] 4252 "" 4253 "* 4254{ 4255#ifdef MOTOROLA 4256 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\"); 4257#else 4258 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\"); 4259#endif 4260}") 4261 4262(define_insn "" 4263 [(set (pc) 4264 (if_then_else (gt (cc0) 4265 (const_int 0)) 4266 (pc) 4267 (label_ref (match_operand 0 "" ""))))] 4268 "" 4269 "* 4270#ifdef MOTOROLA 4271 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0); 4272#else 4273 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0); 4274#endif 4275") 4276 4277(define_insn "" 4278 [(set (pc) 4279 (if_then_else (gtu (cc0) 4280 (const_int 0)) 4281 (pc) 4282 (label_ref (match_operand 0 "" ""))))] 4283 "" 4284 "* 4285#ifdef MOTOROLA 4286 return \"jbls %l0\"; 4287#else 4288 return \"jls %l0\"; 4289#endif 4290") 4291 4292(define_insn "" 4293 [(set (pc) 4294 (if_then_else (lt (cc0) 4295 (const_int 0)) 4296 (pc) 4297 (label_ref (match_operand 0 "" ""))))] 4298 "" 4299 "* 4300#ifdef MOTOROLA 4301 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\"); 4302#else 4303 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\"); 4304#endif 4305") 4306 4307(define_insn "" 4308 [(set (pc) 4309 (if_then_else (ltu (cc0) 4310 (const_int 0)) 4311 (pc) 4312 (label_ref (match_operand 0 "" ""))))] 4313 "" 4314 "* 4315#ifdef MOTOROLA 4316 return \"jbcc %l0\"; 4317#else 4318 return \"jcc %l0\"; 4319#endif 4320") 4321 4322(define_insn "" 4323 [(set (pc) 4324 (if_then_else (ge (cc0) 4325 (const_int 0)) 4326 (pc) 4327 (label_ref (match_operand 0 "" ""))))] 4328 "" 4329 "* 4330#ifdef MOTOROLA 4331 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\"); 4332#else 4333 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\"); 4334#endif 4335") 4336 4337(define_insn "" 4338 [(set (pc) 4339 (if_then_else (geu (cc0) 4340 (const_int 0)) 4341 (pc) 4342 (label_ref (match_operand 0 "" ""))))] 4343 "" 4344 "* 4345#ifdef MOTOROLA 4346 return \"jbcs %l0\"; 4347#else 4348 return \"jcs %l0\"; 4349#endif 4350") 4351 4352(define_insn "" 4353 [(set (pc) 4354 (if_then_else (le (cc0) 4355 (const_int 0)) 4356 (pc) 4357 (label_ref (match_operand 0 "" ""))))] 4358 "" 4359 "* 4360#ifdef MOTOROLA 4361 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0); 4362#else 4363 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0); 4364#endif 4365") 4366 4367(define_insn "" 4368 [(set (pc) 4369 (if_then_else (leu (cc0) 4370 (const_int 0)) 4371 (pc) 4372 (label_ref (match_operand 0 "" ""))))] 4373 "" 4374 "* 4375#ifdef MOTOROLA 4376 return \"jbhi %l0\"; 4377#else 4378 return \"jhi %l0\"; 4379#endif 4380") 4381 4382;; Unconditional and other jump instructions 4383(define_insn "jump" 4384 [(set (pc) 4385 (label_ref (match_operand 0 "" "")))] 4386 "" 4387 "* 4388#ifdef MOTOROLA 4389 return \"jbra %l0\"; 4390#else 4391 return \"jra %l0\"; 4392#endif 4393") 4394 4395;; We support two different ways of handling dispatch tables. 4396;; The NeXT uses absolute tables, and other machines use relative. 4397;; This define_expand can generate either kind. 4398(define_expand "tablejump" 4399 [(parallel [(set (pc) (match_operand 0 "" "")) 4400 (use (label_ref (match_operand 1 "" "")))])] 4401 "" 4402 " 4403{ 4404#ifdef CASE_VECTOR_PC_RELATIVE 4405 operands[0] = gen_rtx (PLUS, SImode, pc_rtx, operands[0]); 4406#endif 4407}") 4408 4409;; Jump to variable address from dispatch table of absolute addresses. 4410(define_insn "" 4411 [(set (pc) (match_operand:SI 0 "register_operand" "a")) 4412 (use (label_ref (match_operand 1 "" "")))] 4413 "" 4414 "* 4415#ifdef MOTOROLA 4416 return \"jmp (%0)\"; 4417#else 4418 return \"jmp %0@\"; 4419#endif 4420") 4421 4422;; Jump to variable address from dispatch table of relative addresses. 4423(define_insn "" 4424 [(set (pc) 4425 (plus:SI (pc) (match_operand:HI 0 "register_operand" "r"))) 4426 (use (label_ref (match_operand 1 "" "")))] 4427 "" 4428 "* 4429#ifdef ASM_RETURN_CASE_JUMP 4430 ASM_RETURN_CASE_JUMP; 4431#else 4432#ifdef SGS 4433#ifdef ASM_OUTPUT_CASE_LABEL 4434 return \"jmp 6(%%pc,%0.w)\"; 4435#else 4436#ifdef CRDS 4437 return \"jmp 2(pc,%0.w)\"; 4438#else 4439 return \"jmp 2(%%pc,%0.w)\"; 4440#endif /* end !CRDS */ 4441#endif 4442#else /* not SGS */ 4443#ifdef MOTOROLA 4444 return \"jmp (2,pc,%0.w)\"; 4445#else 4446 return \"jmp pc@(2,%0:w)\"; 4447#endif 4448#endif 4449#endif 4450") 4451 4452;; Decrement-and-branch insns. 4453(define_insn "" 4454 [(set (pc) 4455 (if_then_else 4456 (ne (match_operand:HI 0 "general_operand" "+g") 4457 (const_int 0)) 4458 (label_ref (match_operand 1 "" "")) 4459 (pc))) 4460 (set (match_dup 0) 4461 (plus:HI (match_dup 0) 4462 (const_int -1)))] 4463 "" 4464 "* 4465{ 4466 CC_STATUS_INIT; 4467 if (DATA_REG_P (operands[0])) 4468 return \"dbra %0,%l1\"; 4469 if (GET_CODE (operands[0]) == MEM) 4470 { 4471#ifdef MOTOROLA 4472#ifdef NO_ADDSUB_Q 4473 return \"sub%.w %#1,%0\;jbcc %l1\"; 4474#else 4475 return \"subq%.w %#1,%0\;jbcc %l1\"; 4476#endif 4477#else /* not MOTOROLA */ 4478 return \"subqw %#1,%0\;jcc %l1\"; 4479#endif 4480 } 4481#ifdef MOTOROLA 4482#ifdef SGS_CMP_ORDER 4483#ifdef NO_ADDSUB_Q 4484 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\"; 4485#else 4486 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\"; 4487#endif 4488#else /* not SGS_CMP_ORDER */ 4489 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\"; 4490#endif 4491#else /* not MOTOROLA */ 4492 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\"; 4493#endif 4494}") 4495 4496(define_insn "" 4497 [(set (pc) 4498 (if_then_else 4499 (ne (match_operand:SI 0 "general_operand" "+g") 4500 (const_int 0)) 4501 (label_ref (match_operand 1 "" "")) 4502 (pc))) 4503 (set (match_dup 0) 4504 (plus:SI (match_dup 0) 4505 (const_int -1)))] 4506 "" 4507 "* 4508{ 4509 CC_STATUS_INIT; 4510#ifdef MOTOROLA 4511#ifdef NO_ADDSUB_Q 4512 if (DATA_REG_P (operands[0])) 4513 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\"; 4514 if (GET_CODE (operands[0]) == MEM) 4515 return \"sub%.l %#1,%0\;jbcc %l1\"; 4516#else 4517 if (DATA_REG_P (operands[0])) 4518 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\"; 4519 if (GET_CODE (operands[0]) == MEM) 4520 return \"subq%.l %#1,%0\;jbcc %l1\"; 4521#endif /* NO_ADDSUB_Q */ 4522#ifdef SGS_CMP_ORDER 4523#ifdef NO_ADDSUB_Q 4524 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; 4525#else 4526 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; 4527#endif 4528#else /* not SGS_CMP_ORDER */ 4529 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\"; 4530#endif /* not SGS_CMP_ORDER */ 4531#else /* not MOTOROLA */ 4532 if (DATA_REG_P (operands[0])) 4533 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\"; 4534 if (GET_CODE (operands[0]) == MEM) 4535 return \"subql %#1,%0\;jcc %l1\"; 4536 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\"; 4537#endif /* not MOTOROLA */ 4538}") 4539 4540;; Two dbra patterns that use REG_NOTES info generated by strength_reduce. 4541 4542(define_insn "" 4543 [(set (pc) 4544 (if_then_else 4545 (ge (plus:HI (match_operand:HI 0 "general_operand" "+g") 4546 (const_int -1)) 4547 (const_int 0)) 4548 (label_ref (match_operand 1 "" "")) 4549 (pc))) 4550 (set (match_dup 0) 4551 (plus:HI (match_dup 0) 4552 (const_int -1)))] 4553 "find_reg_note (insn, REG_NONNEG, 0)" 4554 "* 4555{ 4556 CC_STATUS_INIT; 4557#ifdef MOTOROLA 4558#ifdef NO_ADDSUB_Q 4559 if (DATA_REG_P (operands[0])) 4560 return \"dbra %0,%l1\"; 4561 if (GET_CODE (operands[0]) == MEM) 4562 return \"sub%.w %#1,%0\;jbcc %l1\"; 4563#else 4564 if (DATA_REG_P (operands[0])) 4565 return \"dbra %0,%l1\"; 4566 if (GET_CODE (operands[0]) == MEM) 4567 return \"subq%.w %#1,%0\;jbcc %l1\"; 4568#endif 4569#ifdef SGS_CMP_ORDER 4570#ifdef NO_ADDSUB_Q 4571 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\"; 4572#else 4573 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\"; 4574#endif 4575#else /* not SGS_CMP_ORDER */ 4576 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\"; 4577#endif /* not SGS_CMP_ORDER */ 4578#else /* not MOTOROLA */ 4579 if (DATA_REG_P (operands[0])) 4580 return \"dbra %0,%l1\"; 4581 if (GET_CODE (operands[0]) == MEM) 4582 return \"subqw %#1,%0\;jcc %l1\"; 4583 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\"; 4584#endif /* not MOTOROLA */ 4585}") 4586 4587(define_insn "decrement_and_branch_until_zero" 4588 [(set (pc) 4589 (if_then_else 4590 (ge (plus:SI (match_operand:SI 0 "general_operand" "+g") 4591 (const_int -1)) 4592 (const_int 0)) 4593 (label_ref (match_operand 1 "" "")) 4594 (pc))) 4595 (set (match_dup 0) 4596 (plus:SI (match_dup 0) 4597 (const_int -1)))] 4598 "find_reg_note (insn, REG_NONNEG, 0)" 4599 "* 4600{ 4601 CC_STATUS_INIT; 4602#ifdef MOTOROLA 4603#ifdef NO_ADDSUB_Q 4604 if (DATA_REG_P (operands[0])) 4605 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\"; 4606 if (GET_CODE (operands[0]) == MEM) 4607 return \"sub%.l %#1,%0\;jbcc %l1\"; 4608#else 4609 if (DATA_REG_P (operands[0])) 4610 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\"; 4611 if (GET_CODE (operands[0]) == MEM) 4612 return \"subq%.l %#1,%0\;jbcc %l1\"; 4613#endif 4614#ifdef SGS_CMP_ORDER 4615#ifdef NO_ADDSUB_Q 4616 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; 4617#else 4618 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; 4619#endif 4620#else /* not SGS_CMP_ORDER */ 4621 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\"; 4622#endif /* not SGS_CMP_ORDER */ 4623#else /* not MOTOROLA */ 4624 if (DATA_REG_P (operands[0])) 4625 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\"; 4626 if (GET_CODE (operands[0]) == MEM) 4627 return \"subql %#1,%0\;jcc %l1\"; 4628 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\"; 4629#endif /* not MOTOROLA */ 4630}") 4631 4632 4633;; PIC calls are handled by loading the address of the function into a 4634;; register (via movsi), then emitting a register indirect call using 4635;; the "jsr" function call syntax. 4636;; 4637;; It is important to note that the "jsr" syntax is always used for 4638;; PIC calls, even on machines in which GCC normally uses the "jbsr" 4639;; syntax for non-PIC calls. This keeps at least 1 assembler (Sun) 4640;; from emitting incorrect code for a PIC call. 4641;; 4642;; We have different patterns for PIC calls and non-PIC calls. The 4643;; different patterns are only used to choose the right syntax 4644;; ("jsr" vs "jbsr"). 4645 4646;; Call subroutine with no return value. 4647(define_expand "call" 4648 [(call (match_operand:QI 0 "memory_operand" "") 4649 (match_operand:SI 1 "general_operand" ""))] 4650 ;; Operand 1 not really used on the m68000. 4651 4652 "" 4653 " 4654{ 4655 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) 4656 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), 4657 force_reg (Pmode, XEXP (operands[0], 0))); 4658}") 4659 4660;; This is a normal call sequence. 4661(define_insn "" 4662 [(call (match_operand:QI 0 "memory_operand" "o") 4663 (match_operand:SI 1 "general_operand" "g"))] 4664 ;; Operand 1 not really used on the m68000. 4665 4666 "! flag_pic" 4667 "* 4668#ifdef MOTOROLA 4669 return \"jsr %0\"; 4670#else 4671 return \"jbsr %0\"; 4672#endif 4673") 4674 4675;; This is a PIC call sequence. 4676(define_insn "" 4677 [(call (match_operand:QI 0 "memory_operand" "o") 4678 (match_operand:SI 1 "general_operand" "g"))] 4679 ;; Operand 1 not really used on the m68000. 4680 4681 "flag_pic" 4682 "* 4683 return \"jsr %0\"; 4684") 4685 4686;; Call subroutine, returning value in operand 0 4687;; (which must be a hard register). 4688;; See comments before "call" regarding PIC calls. 4689(define_expand "call_value" 4690 [(set (match_operand 0 "" "") 4691 (call (match_operand:QI 1 "memory_operand" "") 4692 (match_operand:SI 2 "general_operand" "")))] 4693 ;; Operand 2 not really used on the m68000. 4694 "" 4695 " 4696{ 4697 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) 4698 operands[1] = gen_rtx (MEM, GET_MODE (operands[1]), 4699 force_reg (Pmode, XEXP (operands[1], 0))); 4700}") 4701 4702;; This is a normal call_value 4703(define_insn "" 4704 [(set (match_operand 0 "" "=rf") 4705 (call (match_operand:QI 1 "memory_operand" "o") 4706 (match_operand:SI 2 "general_operand" "g")))] 4707 ;; Operand 2 not really used on the m68000. 4708 "! flag_pic" 4709 "* 4710#ifdef MOTOROLA 4711 return \"jsr %1\"; 4712#else 4713 return \"jbsr %1\"; 4714#endif 4715") 4716 4717;; This is a PIC call_value 4718(define_insn "" 4719 [(set (match_operand 0 "" "=rf") 4720 (call (match_operand:QI 1 "memory_operand" "o") 4721 (match_operand:SI 2 "general_operand" "g")))] 4722 ;; Operand 2 not really used on the m68000. 4723 "flag_pic" 4724 "* 4725 return \"jsr %1\"; 4726") 4727 4728(define_insn "nop" 4729 [(const_int 0)] 4730 "" 4731 "nop") 4732 4733(define_insn "probe" 4734 [(reg:SI 15)] 4735 "NEED_PROBE" 4736 "* 4737{ 4738 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx, 4739 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE)); 4740 return \"tstl %a0\"; 4741}") 4742 4743;; Used for frameless functions which save no regs and allocate no locals. 4744(define_insn "return" 4745 [(return)] 4746 "USE_RETURN_INSN" 4747 "* 4748{ 4749 if (current_function_pops_args == 0) 4750 return \"rts\"; 4751 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args); 4752 return \"rtd %0\"; 4753}") 4754 4755(define_insn "indirect_jump" 4756 [(set (pc) (match_operand:SI 0 "address_operand" "p"))] 4757 "" 4758 "jmp %a0") 4759 4760;; This should not be used unless the add/sub insns can't be. 4761 4762(define_insn "" 4763 [(set (match_operand:SI 0 "general_operand" "=a") 4764 (match_operand:QI 1 "address_operand" "p"))] 4765 "" 4766 "lea %a1,%0") 4767 4768;; This is the first machine-dependent peephole optimization. 4769;; It is useful when a floating value is returned from a function call 4770;; and then is moved into an FP register. 4771;; But it is mainly intended to test the support for these optimizations. 4772 4773(define_peephole 4774 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) 4775 (set (match_operand:DF 0 "register_operand" "=f") 4776 (match_operand:DF 1 "register_operand" "ad"))] 4777 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" 4778 "* 4779{ 4780 rtx xoperands[2]; 4781 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 4782 output_asm_insn (\"move%.l %1,%@\", xoperands); 4783 output_asm_insn (\"move%.l %1,%-\", operands); 4784 return \"fmove%.d %+,%0\"; 4785} 4786") 4787 4788;; Optimize a stack-adjust followed by a push of an argument. 4789;; This is said to happen frequently with -msoft-float 4790;; when there are consecutive library calls. 4791 4792(define_peephole 4793 [(set (reg:SI 15) (plus:SI (reg:SI 15) 4794 (match_operand:SI 0 "immediate_operand" "n"))) 4795 (set (match_operand:SF 1 "push_operand" "=m") 4796 (match_operand:SF 2 "general_operand" "rmfF"))] 4797 "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) >= 4 4798 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])" 4799 "* 4800{ 4801 if (INTVAL (operands[0]) > 4) 4802 { 4803 rtx xoperands[2]; 4804 xoperands[0] = stack_pointer_rtx; 4805 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4); 4806#ifndef NO_ADDSUB_Q 4807 if (INTVAL (xoperands[1]) <= 8) 4808 output_asm_insn (\"addq%.w %1,%0\", xoperands); 4809 else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020) 4810 { 4811 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, 4812 INTVAL (xoperands[1]) - 8); 4813 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); 4814 } 4815 else 4816#endif 4817 if (INTVAL (xoperands[1]) <= 0x7FFF) 4818 output_asm_insn (\"add%.w %1,%0\", xoperands); 4819 else 4820 output_asm_insn (\"add%.l %1,%0\", xoperands); 4821 } 4822 if (FP_REG_P (operands[2])) 4823 return \"fmove%.s %2,%@\"; 4824 return \"move%.l %2,%@\"; 4825}") 4826 4827;; Speed up stack adjust followed by a fullword fixedpoint push. 4828 4829(define_peephole 4830 [(set (reg:SI 15) (plus:SI (reg:SI 15) 4831 (match_operand:SI 0 "immediate_operand" "n"))) 4832 (set (match_operand:SI 1 "push_operand" "=m") 4833 (match_operand:SI 2 "general_operand" "g"))] 4834 "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) >= 4 4835 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])" 4836 "* 4837{ 4838 if (INTVAL (operands[0]) > 4) 4839 { 4840 rtx xoperands[2]; 4841 xoperands[0] = stack_pointer_rtx; 4842 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4); 4843#ifndef NO_ADDSUB_Q 4844 if (INTVAL (xoperands[1]) <= 8) 4845 output_asm_insn (\"addq%.w %1,%0\", xoperands); 4846 else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020) 4847 { 4848 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, 4849 INTVAL (xoperands[1]) - 8); 4850 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); 4851 } 4852 else 4853#endif 4854 if (INTVAL (xoperands[1]) <= 0x7FFF) 4855 output_asm_insn (\"add%.w %1,%0\", xoperands); 4856 else 4857 output_asm_insn (\"add%.l %1,%0\", xoperands); 4858 } 4859 if (operands[2] == const0_rtx) 4860 return \"clr%.l %@\"; 4861 return \"move%.l %2,%@\"; 4862}") 4863 4864;; Speed up pushing a single byte but leaving four bytes of space. 4865 4866(define_peephole 4867 [(set (mem:QI (pre_dec:SI (reg:SI 15))) 4868 (match_operand:QI 1 "general_operand" "dami")) 4869 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))] 4870 "! reg_mentioned_p (stack_pointer_rtx, operands[1])" 4871 "* 4872{ 4873 rtx xoperands[4]; 4874 4875 if (GET_CODE (operands[1]) == REG) 4876 return \"move%.l %1,%-\"; 4877 4878 xoperands[1] = operands[1]; 4879 xoperands[2] 4880 = gen_rtx (MEM, QImode, 4881 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, 4882 gen_rtx (CONST_INT, VOIDmode, 3))); 4883 xoperands[3] = stack_pointer_rtx; 4884 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands); 4885 return \"\"; 4886}") 4887 4888;; dbCC peepholes 4889;; 4890;; Turns 4891;; loop: 4892;; [ ... ] 4893;; jCC label ; abnormal loop termination 4894;; dbra dN, loop ; normal loop termination 4895;; 4896;; Into 4897;; loop: 4898;; [ ... ] 4899;; dbCC dN, loop 4900;; jCC label 4901;; 4902;; Which moves the jCC condition outside the inner loop for free. 4903;; 4904(define_peephole 4905 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" 4906 [(cc0) (const_int 0)]) 4907 (label_ref (match_operand 2 "" "")) 4908 (pc))) 4909 (parallel 4910 [(set (pc) 4911 (if_then_else 4912 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d") 4913 (const_int -1)) 4914 (const_int 0)) 4915 (label_ref (match_operand 1 "" "")) 4916 (pc))) 4917 (set (match_dup 0) 4918 (plus:HI (match_dup 0) 4919 (const_int -1)))])] 4920 "DATA_REG_P (operands[0])" 4921 "* 4922{ 4923 CC_STATUS_INIT; 4924 output_dbcc_and_branch (operands); 4925 return \"\"; 4926}") 4927 4928(define_peephole 4929 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" 4930 [(cc0) (const_int 0)]) 4931 (label_ref (match_operand 2 "" "")) 4932 (pc))) 4933 (parallel 4934 [(set (pc) 4935 (if_then_else 4936 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d") 4937 (const_int -1)) 4938 (const_int 0)) 4939 (label_ref (match_operand 1 "" "")) 4940 (pc))) 4941 (set (match_dup 0) 4942 (plus:SI (match_dup 0) 4943 (const_int -1)))])] 4944 "DATA_REG_P (operands[0])" 4945 "* 4946{ 4947 CC_STATUS_INIT; 4948 output_dbcc_and_branch (operands); 4949 return \"\"; 4950}") 4951 4952 4953;; FPA multiply and add. 4954(define_insn "" 4955 [(set (match_operand:DF 0 "register_operand" "=x,y,y") 4956 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y") 4957 (match_operand:DF 2 "general_operand" "xH,y,y")) 4958 (match_operand:DF 3 "general_operand" "xH,y,dmF")))] 4959 "TARGET_FPA" 4960 "@ 4961 fpma%.d %1,%w2,%w3,%0 4962 fpma%.d %x1,%x2,%x3,%0 4963 fpma%.d %x1,%x2,%x3,%0") 4964 4965(define_insn "" 4966 [(set (match_operand:SF 0 "register_operand" "=x,y,y") 4967 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y") 4968 (match_operand:SF 2 "general_operand" "xH,y,ydmF")) 4969 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))] 4970 "TARGET_FPA" 4971 "@ 4972 fpma%.s %1,%w2,%w3,%0 4973 fpma%.s %1,%2,%3,%0 4974 fpma%.s %1,%2,%3,%0") 4975 4976;; FPA Multiply and subtract 4977(define_insn "" 4978 [(set (match_operand:DF 0 "register_operand" "=x,y,y") 4979 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y") 4980 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y") 4981 (match_operand:DF 3 "general_operand" "x,y,rmF"))))] 4982 "TARGET_FPA" 4983 "@ 4984 fpms%.d %3,%w2,%w1,%0 4985 fpms%.d %x3,%2,%x1,%0 4986 fpms%.d %x3,%2,%x1,%0") 4987 4988(define_insn "" 4989 [(set (match_operand:SF 0 "register_operand" "=x,y,y") 4990 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF") 4991 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y") 4992 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))] 4993 "TARGET_FPA" 4994 "@ 4995 fpms%.s %3,%w2,%w1,%0 4996 fpms%.s %3,%2,%1,%0 4997 fpms%.s %3,%2,%1,%0") 4998 4999(define_insn "" 5000 [(set (match_operand:DF 0 "register_operand" "=x,y,y") 5001 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y") 5002 (match_operand:DF 2 "general_operand" "x,y,rmF")) 5003 (match_operand:DF 3 "general_operand" "xH,rmF,y")))] 5004 "TARGET_FPA" 5005 "@ 5006 fpmr%.d %2,%w1,%w3,%0 5007 fpmr%.d %x2,%1,%x3,%0 5008 fpmr%.d %x2,%1,%x3,%0") 5009 5010(define_insn "" 5011 [(set (match_operand:SF 0 "register_operand" "=x,y,y") 5012 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y") 5013 (match_operand:SF 2 "general_operand" "x,y,yrmF")) 5014 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] 5015 "TARGET_FPA" 5016 "@ 5017 fpmr%.s %2,%w1,%w3,%0 5018 fpmr%.s %x2,%1,%x3,%0 5019 fpmr%.s %x2,%1,%x3,%0") 5020 5021;; FPA Add and multiply 5022(define_insn "" 5023 [(set (match_operand:DF 0 "register_operand" "=x,y,y") 5024 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y") 5025 (match_operand:DF 2 "general_operand" "x,y,rmF")) 5026 (match_operand:DF 3 "general_operand" "xH,rmF,y")))] 5027 "TARGET_FPA" 5028 "@ 5029 fpam%.d %2,%w1,%w3,%0 5030 fpam%.d %x2,%1,%x3,%0 5031 fpam%.d %x2,%1,%x3,%0") 5032 5033(define_insn "" 5034 [(set (match_operand:SF 0 "register_operand" "=x,y,y") 5035 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y") 5036 (match_operand:SF 2 "general_operand" "x,y,yrmF")) 5037 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] 5038 "TARGET_FPA" 5039 "@ 5040 fpam%.s %2,%w1,%w3,%0 5041 fpam%.s %x2,%1,%x3,%0 5042 fpam%.s %x2,%1,%x3,%0") 5043 5044;;FPA Subtract and multiply 5045(define_insn "" 5046 [(set (match_operand:DF 0 "register_operand" "=x,y,y") 5047 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y") 5048 (match_operand:DF 2 "general_operand" "x,y,rmF")) 5049 (match_operand:DF 3 "general_operand" "xH,rmF,y")))] 5050 "TARGET_FPA" 5051 "@ 5052 fpsm%.d %2,%w1,%w3,%0 5053 fpsm%.d %x2,%1,%x3,%0 5054 fpsm%.d %x2,%1,%x3,%0") 5055 5056(define_insn "" 5057 [(set (match_operand:DF 0 "register_operand" "=x,y,y") 5058 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y") 5059 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y") 5060 (match_operand:DF 3 "general_operand" "x,y,rmF"))))] 5061 "TARGET_FPA" 5062 "@ 5063 fpsm%.d %3,%w2,%w1,%0 5064 fpsm%.d %x3,%2,%x1,%0 5065 fpsm%.d %x3,%2,%x1,%0") 5066 5067(define_insn "" 5068 [(set (match_operand:SF 0 "register_operand" "=x,y,y") 5069 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y") 5070 (match_operand:SF 2 "general_operand" "x,y,yrmF")) 5071 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] 5072 "TARGET_FPA" 5073 "@ 5074 fpsm%.s %2,%w1,%w3,%0 5075 fpsm%.s %x2,%1,%x3,%0 5076 fpsm%.s %x2,%1,%x3,%0") 5077 5078(define_insn "" 5079 [(set (match_operand:SF 0 "register_operand" "=x,y,y") 5080 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF") 5081 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y") 5082 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))] 5083 "TARGET_FPA" 5084 "@ 5085 fpsm%.s %3,%w2,%w1,%0 5086 fpsm%.s %x3,%2,%x1,%0 5087 fpsm%.s %x3,%2,%x1,%0") 5088 5089;;- Local variables: 5090;;- mode:emacs-lisp 5091;;- comment-start: ";;- " 5092;;- comment-start-skip: ";+- *" 5093;;- eval: (set-syntax-table (copy-sequence (syntax-table))) 5094;;- eval: (modify-syntax-entry ?[ "(]") 5095;;- eval: (modify-syntax-entry ?] ")[") 5096;;- eval: (modify-syntax-entry ?{ "(}") 5097;;- eval: (modify-syntax-entry ?} "){") 5098;;- End: 5099