1 /* 2 * Copyright (c) 1982, 1986, 1990 Regents of the University of California. 3 * All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * @(#)dcareg.h 7.3 (Berkeley) 05/07/91 8 */ 9 10 struct dcadevice { 11 u_char dca_pad0; 12 volatile u_char dca_irid; 13 volatile short dca_ic; 14 volatile short dca_ocbrc; 15 volatile short dca_lcsm; 16 short dca_pad1[4]; 17 u_char dca_pad2; 18 volatile u_char dca_data; 19 volatile short dca_ier; 20 u_char dca_pad4; 21 volatile u_char dca_iir; /* read-only */ 22 #define dca_fifo dca_iir /* write-only */ 23 volatile short dca_cfcr; 24 volatile short dca_mcr; 25 volatile short dca_lsr; 26 u_char dca_pad3; 27 volatile u_char dca_msr; 28 }; 29 30 /* interface reset/id */ 31 #define DCAID0 0x02 32 #define DCAREMID0 0x82 33 #define DCAID1 0x42 34 #define DCAREMID1 0xC2 35 36 /* interrupt control */ 37 #define DCAIPL(x) ((((x) >> 4) & 3) + 3) 38 #define IC_IR 0x40 39 #define IC_IE 0x80 40 41 /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */ 42 #define DCABRD(x) (153600 / (x)) 43 44 /* interrupt enable register */ 45 #define IER_ERXRDY 0x1 46 #define IER_ETXRDY 0x2 47 #define IER_ERLS 0x4 48 #define IER_EMSC 0x8 49 50 /* interrupt identification register */ 51 #define IIR_IMASK 0xf 52 #define IIR_RXTOUT 0xc 53 #define IIR_RLS 0x6 54 #define IIR_RXRDY 0x4 55 #define IIR_TXRDY 0x2 56 #define IIR_NOPEND 0x1 57 #define IIR_MLSC 0x0 58 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 59 60 /* fifo control register */ 61 #define FIFO_ENABLE 0x01 62 #define FIFO_RCV_RST 0x02 63 #define FIFO_XMT_RST 0x04 64 #define FIFO_DMA_MODE 0x08 65 #define FIFO_TRIGGER_1 0x00 66 #define FIFO_TRIGGER_4 0x40 67 #define FIFO_TRIGGER_8 0x80 68 #define FIFO_TRIGGER_14 0xc0 69 70 /* character format control register */ 71 #define CFCR_DLAB 0x80 72 #define CFCR_SBREAK 0x40 73 #define CFCR_PZERO 0x30 74 #define CFCR_PONE 0x20 75 #define CFCR_PEVEN 0x10 76 #define CFCR_PODD 0x00 77 #define CFCR_PENAB 0x08 78 #define CFCR_STOPB 0x04 79 #define CFCR_8BITS 0x03 80 #define CFCR_7BITS 0x02 81 #define CFCR_6BITS 0x01 82 #define CFCR_5BITS 0x00 83 84 /* modem control register */ 85 #define MCR_LOOPBACK 0x10 86 #define MCR_SRTS 0x08 87 #define MCR_DRS 0x04 88 #define MCR_RTS 0x02 89 #define MCR_DTR 0x01 90 91 /* line status register */ 92 #define LSR_RCV_FIFO 0x80 93 #define LSR_TSRE 0x40 94 #define LSR_TXRDY 0x20 95 #define LSR_BI 0x10 96 #define LSR_FE 0x08 97 #define LSR_PE 0x04 98 #define LSR_OE 0x02 99 #define LSR_RXRDY 0x01 100 #define LSR_RCV_MASK 0x1f 101 102 /* modem status register */ 103 #define MSR_DCD 0x80 104 #define MSR_RI 0x40 105 #define MSR_DSR 0x20 106 #define MSR_CTS 0x10 107 #define MSR_DDCD 0x08 108 #define MSR_TERI 0x04 109 #define MSR_DDSR 0x02 110 #define MSR_DCTS 0x01 111 112 /* 113 * WARNING: Serial console is assumed to be at SC9 114 * and CONUNIT must be 0. 115 */ 116 #define CONSCODE (9) 117 #define CONUNIT (0) 118