11. Create and use an interrupt stack. 2 Well actually, use the master SP for kernel stacks instead of 3 the interrupt SP. Right now we use the interrupt stack for 4 everything. Allows for more accurate accounting of systime. 5 In theory, could also allow for smaller kernel stacks but we 6 only use one page anyway. 7 82. Copy/clear primitives could be tuned. 9 What is best is highly CPU and cache dependent. One thing to look 10 at are the copyin/copyout primitives. Rather than looping using 11 MOVS instructions, you could map an entire page at a time and use 12 bcopy, MOVE16, or whatever. This would lose big on the VAC models 13 however. 14 153. Sendsig/sigreturn are pretty bogus. 16 Currently we can call a signal handler even if an excpetion 17 occurs in the middle of an instruction. This causes the handler 18 to return right back to the middle of the offending instruction 19 which will most likely lead to another exception/signal. 20 Technically, I feel this is the correct behavior but it requires 21 saving a lot of state on the user's stack, state that we don't 22 really want the user messing with. Other 68k implementations 23 (e.g. Sun) will delay signals or abort execution of the current 24 instruction to reduce saved state. Even if we stick with the 25 current philosophy, the code could be cleaned up. 26 274. Ditto for AST and software interrupt emulation. 28 Both are possibly over-elaborate and inefficiently implemented. 29 We could possibly handle them by using an appropriately planted 30 PS trace bit. 31 325. Make use of transparent translation registers on 030/040 MMU. 33 With a little rearranging of the KVA space we could use one to 34 map the entire external IO space [ 600000 - 20000000 ). Since 35 the translation must be 1-1, this would limit the kernel to 6mb 36 (some would say that is hardly a limit) or divide it into two 37 pieces. Another promising use would be to map physical memory 38 within the kernel. This allows a much simpler and more efficient 39 implementation of /dev/mem, pmap_zero_page, pmap_copy_page and 40 possible even kernel-user cross address space copies. However, 41 it does eat up a significant piece of kernel address space. 42 436. Create a 32-bit timer. 44 Timers 2 and 3 on the MC6840 clock chip can be concatonated together to 45 get a 32-bit countdown timer. There are at least three uses for this: 46 1. Monitoring the interval timer ("clock") to detect lost "ticks". 47 (Idea from Scott Marovich) 48 2. Implement the DELAY macro properly instead of approximating with 49 the current "while (--count);" loop. Because of caches, the current 50 method is potentially way off. 51 3. Export as a user-mappable timer for high-precision (4us) timing. 52 Note that by doing this we can no longer use timer 3 as a separate 53 statistics/profiling timer. Should be able to compile-time (runtime?) 54 select between the two. 55 567. Conditional MMU code sould be restructured. 57 Right now it reflects the evolutionary path of the code: 320/350 MMU 58 was supported and PMMU support was glued on. The latter can be ifdef'ed 59 out when not needed, but not all of the former (e.g. ``mmutype'' tests). 60 Also, PMMU is made to look like the HP MMU somewhat ham-stringing it. 61 Since HP MMU models are dead, the excess baggage should be there (though 62 it could be argued that they benefit more from the minor performance 63 impact). MMU code should probably not be ifdef'ed on model type, but 64 rather on more relevant tags (e.g. MMU_HP, MMU_MOTO). 65 668. Redo cache handling. 67 There are way too many routines which are specific to particular 68 cache types. We should be able to come up with a more coherent 69 scheme (though HP 68k boxes have just about every caching scheme 70 imaginable: internal/external, physical/virtual, writeback/writethrough) 71 See, for example, Wheeler and Bershad in ASPLOS 92. For more efficient 72 handling of physical caches see also Kessler and Hill in Nov. 92 TOCS. 73 749. Sort the free page list. 75 The DMA hardware on the 300 cannot do scatter/gather IO. For example, 76 if an 8k system buffer consists of two non-contiguous physical pages 77 it will require two DMA transfers (and hence two interrupts) to do the 78 operation. It would take only one transfer if they were physically 79 contiguous. By keeping the free list ordered we could potentially 80 allocate contiguous pages and reduce the number of interrupts. We can 81 consider doing this since pages in the free list are not reclaimed and 82 thus we don't have to worry about distorting any LRU behavior. 83---- 84Mike Hibler 85University of Utah CSS group 86mike@cs.utah.edu 87