1 /* 2 * Copyright (c) 1982, 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * @(#)if_lereg.h 7.4 (Berkeley) 07/06/92 8 */ 9 10 #ifdef KERNEL 11 #include "hp/dev/iotypes.h" /* XXX */ 12 #else 13 #include <hp/dev/iotypes.h> /* XXX */ 14 #endif 15 16 #define LEID 21 17 18 #define LEMTU 1518 19 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 20 #define LERBUF 8 21 #define LERBUFLOG2 3 22 #define LE_RLEN (LERBUFLOG2 << 13) 23 #define LETBUF 2 24 #define LETBUFLOG2 1 25 #define LE_TLEN (LETBUFLOG2 << 13) 26 27 /* 28 * LANCE registers. 29 */ 30 struct lereg0 { 31 u_char ler0_pad0; 32 vu_char ler0_id; /* ID */ 33 u_char ler0_pad1; 34 vu_char ler0_status; /* interrupt enable/status */ 35 }; 36 37 struct lereg1 { 38 u_short ler1_rdp; /* data port */ 39 u_short ler1_rap; /* register select port */ 40 }; 41 42 /* 43 * Overlayed on 16K dual-port RAM. 44 * Current size is 15,284 bytes with 8 x 1518 receive buffers and 45 * 2 x 1518 transmit buffers. 46 */ 47 struct lereg2 { 48 /* init block */ 49 u_short ler2_mode; /* +0x0000 */ 50 u_char ler2_padr[6]; /* +0x0002 */ 51 u_long ler2_ladrf[2]; /* +0x0008 */ 52 u_short ler2_rdra; /* +0x0010 */ 53 u_short ler2_rlen; /* +0x0012 */ 54 u_short ler2_tdra; /* +0x0014 */ 55 u_short ler2_tlen; /* +0x0016 */ 56 /* receive message descriptors */ 57 struct lermd { /* +0x0018 */ 58 u_short rmd0; 59 u_short rmd1; 60 short rmd2; 61 u_short rmd3; 62 } ler2_rmd[LERBUF]; 63 /* transmit message descriptors */ 64 struct letmd { /* +0x0058 */ 65 u_short tmd0; 66 u_short tmd1; 67 short tmd2; 68 u_short tmd3; 69 } ler2_tmd[LETBUF]; 70 char ler2_rbuf[LERBUF][LEMTU]; /* +0x0068 */ 71 char ler2_tbuf[LETBUF][LEMTU]; /* +0x2FD8 */ 72 }; 73 74 /* 75 * Control and status bits -- lereg0 76 */ 77 #define LE_IE 0x80 /* interrupt enable */ 78 #define LE_IR 0x40 /* interrupt requested */ 79 #define LE_LOCK 0x08 /* lock status register */ 80 #define LE_ACK 0x04 /* ack of lock */ 81 #define LE_JAB 0x02 /* loss of tx clock (???) */ 82 #define LE_IPL(x) ((((x) >> 4) & 0x3) + 3) 83 84 /* 85 * Control and status bits -- lereg1 86 */ 87 #define LE_CSR0 0 88 #define LE_CSR1 1 89 #define LE_CSR2 2 90 #define LE_CSR3 3 91 92 #define LE_SERR 0x8000 93 #define LE_BABL 0x4000 94 #define LE_CERR 0x2000 95 #define LE_MISS 0x1000 96 #define LE_MERR 0x0800 97 #define LE_RINT 0x0400 98 #define LE_TINT 0x0200 99 #define LE_IDON 0x0100 100 #define LE_INTR 0x0080 101 #define LE_INEA 0x0040 102 #define LE_RXON 0x0020 103 #define LE_TXON 0x0010 104 #define LE_TDMD 0x0008 105 #define LE_STOP 0x0004 106 #define LE_STRT 0x0002 107 #define LE_INIT 0x0001 108 109 #define LE_BSWP 0x4 110 #define LE_MODE 0x0 111 112 /* 113 * Control and status bits -- lereg2 114 */ 115 #define LE_OWN 0x8000 116 #define LE_ERR 0x4000 117 #define LE_STP 0x0200 118 #define LE_ENP 0x0100 119 120 #define LE_FRAM 0x2000 121 #define LE_OFLO 0x1000 122 #define LE_CRC 0x0800 123 #define LE_RBUFF 0x0400 124 #define LE_MORE 0x1000 125 #define LE_ONE 0x0800 126 #define LE_DEF 0x0400 127 #define LE_TBUFF 0x8000 128 #define LE_UFLO 0x4000 129 #define LE_LCOL 0x1000 130 #define LE_LCAR 0x0800 131 #define LE_RTRY 0x0400 132