1 /* 2 * Copyright (c) 1982, 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * @(#)if_lereg.h 7.5 (Berkeley) 10/11/92 8 */ 9 10 #include <hp/dev/iotypes.h> /* XXX */ 11 12 #define LEID 21 13 14 #define LEMTU 1518 15 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 16 #define LERBUF 8 17 #define LERBUFLOG2 3 18 #define LE_RLEN (LERBUFLOG2 << 13) 19 #define LETBUF 2 20 #define LETBUFLOG2 1 21 #define LE_TLEN (LETBUFLOG2 << 13) 22 23 /* 24 * LANCE registers. 25 */ 26 struct lereg0 { 27 u_char ler0_pad0; 28 vu_char ler0_id; /* ID */ 29 u_char ler0_pad1; 30 vu_char ler0_status; /* interrupt enable/status */ 31 }; 32 33 struct lereg1 { 34 u_short ler1_rdp; /* data port */ 35 u_short ler1_rap; /* register select port */ 36 }; 37 38 /* 39 * Overlayed on 16K dual-port RAM. 40 * Current size is 15,284 bytes with 8 x 1518 receive buffers and 41 * 2 x 1518 transmit buffers. 42 */ 43 struct lereg2 { 44 /* init block */ 45 u_short ler2_mode; /* +0x0000 */ 46 u_char ler2_padr[6]; /* +0x0002 */ 47 u_long ler2_ladrf[2]; /* +0x0008 */ 48 u_short ler2_rdra; /* +0x0010 */ 49 u_short ler2_rlen; /* +0x0012 */ 50 u_short ler2_tdra; /* +0x0014 */ 51 u_short ler2_tlen; /* +0x0016 */ 52 /* receive message descriptors */ 53 struct lermd { /* +0x0018 */ 54 u_short rmd0; 55 u_short rmd1; 56 short rmd2; 57 u_short rmd3; 58 } ler2_rmd[LERBUF]; 59 /* transmit message descriptors */ 60 struct letmd { /* +0x0058 */ 61 u_short tmd0; 62 u_short tmd1; 63 short tmd2; 64 u_short tmd3; 65 } ler2_tmd[LETBUF]; 66 char ler2_rbuf[LERBUF][LEMTU]; /* +0x0068 */ 67 char ler2_tbuf[LETBUF][LEMTU]; /* +0x2FD8 */ 68 }; 69 70 /* 71 * Control and status bits -- lereg0 72 */ 73 #define LE_IE 0x80 /* interrupt enable */ 74 #define LE_IR 0x40 /* interrupt requested */ 75 #define LE_LOCK 0x08 /* lock status register */ 76 #define LE_ACK 0x04 /* ack of lock */ 77 #define LE_JAB 0x02 /* loss of tx clock (???) */ 78 #define LE_IPL(x) ((((x) >> 4) & 0x3) + 3) 79 80 /* 81 * Control and status bits -- lereg1 82 */ 83 #define LE_CSR0 0 84 #define LE_CSR1 1 85 #define LE_CSR2 2 86 #define LE_CSR3 3 87 88 #define LE_SERR 0x8000 89 #define LE_BABL 0x4000 90 #define LE_CERR 0x2000 91 #define LE_MISS 0x1000 92 #define LE_MERR 0x0800 93 #define LE_RINT 0x0400 94 #define LE_TINT 0x0200 95 #define LE_IDON 0x0100 96 #define LE_INTR 0x0080 97 #define LE_INEA 0x0040 98 #define LE_RXON 0x0020 99 #define LE_TXON 0x0010 100 #define LE_TDMD 0x0008 101 #define LE_STOP 0x0004 102 #define LE_STRT 0x0002 103 #define LE_INIT 0x0001 104 105 #define LE_BSWP 0x4 106 #define LE_MODE 0x0 107 108 /* 109 * Control and status bits -- lereg2 110 */ 111 #define LE_OWN 0x8000 112 #define LE_ERR 0x4000 113 #define LE_STP 0x0200 114 #define LE_ENP 0x0100 115 116 #define LE_FRAM 0x2000 117 #define LE_OFLO 0x1000 118 #define LE_CRC 0x0800 119 #define LE_RBUFF 0x0400 120 #define LE_MORE 0x1000 121 #define LE_ONE 0x0800 122 #define LE_DEF 0x0400 123 #define LE_TBUFF 0x8000 124 #define LE_UFLO 0x4000 125 #define LE_LCOL 0x1000 126 #define LE_LCAR 0x0800 127 #define LE_RTRY 0x0400 128