1 /* 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Van Jacobson of Lawrence Berkeley Laboratory. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)scsi.c 7.4 (Berkeley) 02/05/91 11 */ 12 13 /* 14 * HP9000/3xx 98658 SCSI host adaptor driver. 15 */ 16 #include "scsi.h" 17 #if NSCSI > 0 18 19 #ifndef lint 20 static char rcsid[] = "$Header: scsi.c,v 1.4 91/01/17 12:50:18 mike Exp $"; 21 #endif 22 23 #include "sys/param.h" 24 #include "sys/systm.h" 25 #include "sys/buf.h" 26 #include "device.h" 27 28 #include "scsivar.h" 29 #include "scsireg.h" 30 #include "dmavar.h" 31 32 #include "../include/cpu.h" 33 #include "../hp300/isr.h" 34 35 /* 36 * SCSI delays 37 * In u-seconds, primarily for state changes on the SPC. 38 */ 39 #define SCSI_CMD_WAIT 1000 /* wait per step of 'immediate' cmds */ 40 #define SCSI_DATA_WAIT 1000 /* wait per data in/out step */ 41 #define SCSI_INIT_WAIT 50000 /* wait per step (both) during init */ 42 43 extern void isrlink(); 44 extern void printf(); 45 extern void _insque(); 46 extern void _remque(); 47 extern void bzero(); 48 49 int scsiinit(), scsigo(), scsiintr(), scsixfer(); 50 void scsistart(), scsidone(), scsifree(), scsireset(); 51 struct driver scsidriver = { 52 scsiinit, "scsi", (int (*)())scsistart, scsigo, scsiintr, 53 (int (*)())scsidone, 54 }; 55 56 struct scsi_softc scsi_softc[NSCSI]; 57 struct isr scsi_isr[NSCSI]; 58 59 int scsi_cmd_wait = SCSI_CMD_WAIT; 60 int scsi_data_wait = SCSI_DATA_WAIT; 61 int scsi_init_wait = SCSI_INIT_WAIT; 62 63 int scsi_nosync = 1; /* inhibit sync xfers if 1 */ 64 int scsi_pridma = 0; /* use "priority" dma */ 65 66 #ifdef DEBUG 67 int scsi_debug = 0; 68 #define WAITHIST 69 #endif 70 71 #ifdef WAITHIST 72 #define MAXWAIT 1022 73 u_int ixstart_wait[MAXWAIT+2]; 74 u_int ixin_wait[MAXWAIT+2]; 75 u_int ixout_wait[MAXWAIT+2]; 76 u_int mxin_wait[MAXWAIT+2]; 77 u_int mxin2_wait[MAXWAIT+2]; 78 u_int cxin_wait[MAXWAIT+2]; 79 u_int fxfr_wait[MAXWAIT+2]; 80 u_int sgo_wait[MAXWAIT+2]; 81 #define HIST(h,w) (++h[((w)>MAXWAIT? MAXWAIT : ((w) < 0 ? -1 : (w))) + 1]); 82 #else 83 #define HIST(h,w) 84 #endif 85 86 #define b_cylin b_resid 87 88 static void 89 scsiabort(hs, hd, where) 90 register struct scsi_softc *hs; 91 volatile register struct scsidevice *hd; 92 char *where; 93 { 94 int len; 95 u_char junk; 96 97 printf("scsi%d: abort from %s: phase=0x%x, ssts=0x%x, ints=0x%x\n", 98 hs->sc_hc->hp_unit, where, hd->scsi_psns, hd->scsi_ssts, 99 hd->scsi_ints); 100 101 hd->scsi_ints = hd->scsi_ints; 102 hd->scsi_csr = 0; 103 if (hd->scsi_psns == 0 || (hd->scsi_ssts & SSTS_INITIATOR) == 0) 104 /* no longer connected to scsi target */ 105 return; 106 107 /* get the number of bytes remaining in current xfer + fudge */ 108 len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | hd->scsi_tcl; 109 110 /* for that many bus cycles, try to send an abort msg */ 111 for (len += 1024; (hd->scsi_ssts & SSTS_INITIATOR) && --len >= 0; ) { 112 hd->scsi_scmd = SCMD_SET_ATN; 113 while ((hd->scsi_psns & PSNS_REQ) == 0) { 114 if (! (hd->scsi_ssts & SSTS_INITIATOR)) 115 goto out; 116 DELAY(1); 117 } 118 if ((hd->scsi_psns & PHASE) == MESG_OUT_PHASE) 119 hd->scsi_scmd = SCMD_RST_ATN; 120 hd->scsi_pctl = hd->scsi_psns & PHASE; 121 if (hd->scsi_psns & PHASE_IO) { 122 /* one of the input phases - read & discard a byte */ 123 hd->scsi_scmd = SCMD_SET_ACK; 124 if (hd->scsi_tmod == 0) 125 while (hd->scsi_psns & PSNS_REQ) 126 DELAY(1); 127 junk = hd->scsi_temp; 128 } else { 129 /* one of the output phases - send an abort msg */ 130 hd->scsi_temp = MSG_ABORT; 131 hd->scsi_scmd = SCMD_SET_ACK; 132 if (hd->scsi_tmod == 0) 133 while (hd->scsi_psns & PSNS_REQ) 134 DELAY(1); 135 } 136 hd->scsi_scmd = SCMD_RST_ACK; 137 } 138 out: 139 /* 140 * Either the abort was successful & the bus is disconnected or 141 * the device didn't listen. If the latter, announce the problem. 142 * Either way, reset the card & the SPC. 143 */ 144 if (len < 0 && hs) 145 printf("scsi%d: abort failed. phase=0x%x, ssts=0x%x\n", 146 hs->sc_hc->hp_unit, hd->scsi_psns, hd->scsi_ssts); 147 148 if (! ((junk = hd->scsi_ints) & INTS_RESEL)) { 149 hd->scsi_sctl |= SCTL_CTRLRST; 150 DELAY(1); 151 hd->scsi_sctl &=~ SCTL_CTRLRST; 152 hd->scsi_hconf = 0; 153 hd->scsi_ints = hd->scsi_ints; 154 } 155 } 156 157 /* 158 * XXX Set/reset long delays. 159 * 160 * if delay == 0, reset default delays 161 * if delay < 0, set both delays to default long initialization values 162 * if delay > 0, set both delays to this value 163 * 164 * Used when a devices is expected to respond slowly (e.g. during 165 * initialization). 166 */ 167 void 168 scsi_delay(delay) 169 int delay; 170 { 171 static int saved_cmd_wait, saved_data_wait; 172 173 if (delay) { 174 saved_cmd_wait = scsi_cmd_wait; 175 saved_data_wait = scsi_data_wait; 176 if (delay > 0) 177 scsi_cmd_wait = scsi_data_wait = delay; 178 else 179 scsi_cmd_wait = scsi_data_wait = scsi_init_wait; 180 } else { 181 scsi_cmd_wait = saved_cmd_wait; 182 scsi_data_wait = saved_data_wait; 183 } 184 } 185 186 int 187 scsiinit(hc) 188 register struct hp_ctlr *hc; 189 { 190 register struct scsi_softc *hs = &scsi_softc[hc->hp_unit]; 191 register struct scsidevice *hd = (struct scsidevice *)hc->hp_addr; 192 193 if ((hd->scsi_id & ID_MASK) != SCSI_ID) 194 return(0); 195 hc->hp_ipl = SCSI_IPL(hd->scsi_csr); 196 hs->sc_hc = hc; 197 hs->sc_dq.dq_unit = hc->hp_unit; 198 hs->sc_dq.dq_driver = &scsidriver; 199 hs->sc_sq.dq_forw = hs->sc_sq.dq_back = &hs->sc_sq; 200 scsi_isr[hc->hp_unit].isr_intr = scsiintr; 201 scsi_isr[hc->hp_unit].isr_ipl = hc->hp_ipl; 202 scsi_isr[hc->hp_unit].isr_arg = hc->hp_unit; 203 isrlink(&scsi_isr[hc->hp_unit]); 204 scsireset(hc->hp_unit); 205 return(1); 206 } 207 208 void 209 scsireset(unit) 210 register int unit; 211 { 212 register struct scsi_softc *hs = &scsi_softc[unit]; 213 volatile register struct scsidevice *hd = 214 (struct scsidevice *)hs->sc_hc->hp_addr; 215 u_int i; 216 217 if (hs->sc_flags & SCSI_ALIVE) 218 scsiabort(hs, hd, "reset"); 219 220 printf("scsi%d: ", unit); 221 222 hd->scsi_id = 0xFF; 223 DELAY(100); 224 /* 225 * Disable interrupts then reset the FUJI chip. 226 */ 227 hd->scsi_csr = 0; 228 hd->scsi_sctl = SCTL_DISABLE | SCTL_CTRLRST; 229 hd->scsi_scmd = 0; 230 hd->scsi_tmod = 0; 231 hd->scsi_pctl = 0; 232 hd->scsi_temp = 0; 233 hd->scsi_tch = 0; 234 hd->scsi_tcm = 0; 235 hd->scsi_tcl = 0; 236 hd->scsi_ints = 0; 237 238 if ((hd->scsi_id & ID_WORD_DMA) == 0) { 239 hs->sc_flags |= SCSI_DMA32; 240 printf("32 bit dma, "); 241 } 242 243 /* Determine Max Synchronous Transfer Rate */ 244 if (scsi_nosync) 245 i = 3; 246 else 247 i = SCSI_SYNC_XFER(hd->scsi_hconf); 248 switch (i) { 249 case 0: 250 hs->sc_sync = TMOD_SYNC | 0x3e; /* 250 nsecs */ 251 printf("250ns sync"); 252 break; 253 case 1: 254 hs->sc_sync = TMOD_SYNC | 0x5e; /* 375 nsecs */ 255 printf("375ns sync"); 256 break; 257 case 2: 258 hs->sc_sync = TMOD_SYNC | 0x7d; /* 500 nsecs */ 259 printf("500ns sync"); 260 break; 261 case 3: 262 hs->sc_sync = 0; 263 printf("async"); 264 break; 265 } 266 267 /* 268 * Configure the FUJI chip with its SCSI address, all 269 * interrupts enabled & appropriate parity. 270 */ 271 i = (~hd->scsi_hconf) & 0x7; 272 hs->sc_scsi_addr = 1 << i; 273 hd->scsi_bdid = i; 274 if (hd->scsi_hconf & HCONF_PARITY) 275 hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | 276 SCTL_SEL_ENAB | SCTL_RESEL_ENAB | 277 SCTL_INTR_ENAB | SCTL_PARITY_ENAB; 278 else { 279 hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | 280 SCTL_SEL_ENAB | SCTL_RESEL_ENAB | 281 SCTL_INTR_ENAB; 282 printf(", no parity"); 283 } 284 hd->scsi_sctl &=~ SCTL_DISABLE; 285 286 printf(", scsi id %d\n", i); 287 hs->sc_flags |= SCSI_ALIVE; 288 } 289 290 static void 291 scsierror(hs, hd, ints) 292 register struct scsi_softc *hs; 293 volatile register struct scsidevice *hd; 294 u_char ints; 295 { 296 int unit = hs->sc_hc->hp_unit; 297 char *sep = ""; 298 299 printf("scsi%d: ", unit); 300 if (ints & INTS_RST) { 301 DELAY(100); 302 if (hd->scsi_hconf & HCONF_SD) 303 printf("spurious RST interrupt"); 304 else 305 printf("hardware error - check fuse"); 306 sep = ", "; 307 } 308 if ((ints & INTS_HARD_ERR) || hd->scsi_serr) { 309 if (hd->scsi_serr & SERR_SCSI_PAR) { 310 printf("%sparity err", sep); 311 sep = ", "; 312 } 313 if (hd->scsi_serr & SERR_SPC_PAR) { 314 printf("%sSPC parity err", sep); 315 sep = ", "; 316 } 317 if (hd->scsi_serr & SERR_TC_PAR) { 318 printf("%sTC parity err", sep); 319 sep = ", "; 320 } 321 if (hd->scsi_serr & SERR_PHASE_ERR) { 322 printf("%sphase err", sep); 323 sep = ", "; 324 } 325 if (hd->scsi_serr & SERR_SHORT_XFR) { 326 printf("%ssync short transfer err", sep); 327 sep = ", "; 328 } 329 if (hd->scsi_serr & SERR_OFFSET) { 330 printf("%ssync offset error", sep); 331 sep = ", "; 332 } 333 } 334 if (ints & INTS_TIMEOUT) 335 printf("%sSPC select timeout error", sep); 336 if (ints & INTS_SRV_REQ) 337 printf("%sspurious SRV_REQ interrupt", sep); 338 if (ints & INTS_CMD_DONE) 339 printf("%sspurious CMD_DONE interrupt", sep); 340 if (ints & INTS_DISCON) 341 printf("%sspurious disconnect interrupt", sep); 342 if (ints & INTS_RESEL) 343 printf("%sspurious reselect interrupt", sep); 344 if (ints & INTS_SEL) 345 printf("%sspurious select interrupt", sep); 346 printf("\n"); 347 } 348 349 static int 350 issue_select(hd, target, our_addr) 351 volatile register struct scsidevice *hd; 352 u_char target, our_addr; 353 { 354 if (hd->scsi_ssts & (SSTS_INITIATOR|SSTS_TARGET|SSTS_BUSY)) 355 return (1); 356 357 if (hd->scsi_ints & INTS_DISCON) 358 hd->scsi_ints = INTS_DISCON; 359 360 hd->scsi_pctl = 0; 361 hd->scsi_temp = (1 << target) | our_addr; 362 /* select timeout is hardcoded to 2ms */ 363 hd->scsi_tch = 0; 364 hd->scsi_tcm = 32; 365 hd->scsi_tcl = 4; 366 367 hd->scsi_scmd = SCMD_SELECT; 368 return (0); 369 } 370 371 static int 372 wait_for_select(hd) 373 volatile register struct scsidevice *hd; 374 { 375 u_char ints; 376 377 while ((ints = hd->scsi_ints) == 0) 378 DELAY(1); 379 hd->scsi_ints = ints; 380 return (!(hd->scsi_ssts & SSTS_INITIATOR)); 381 } 382 383 static int 384 ixfer_start(hd, len, phase, wait) 385 volatile register struct scsidevice *hd; 386 int len; 387 u_char phase; 388 register int wait; 389 { 390 391 hd->scsi_tch = len >> 16; 392 hd->scsi_tcm = len >> 8; 393 hd->scsi_tcl = len; 394 hd->scsi_pctl = phase; 395 hd->scsi_tmod = 0; /*XXX*/ 396 hd->scsi_scmd = SCMD_XFR | SCMD_PROG_XFR; 397 398 /* wait for xfer to start or svc_req interrupt */ 399 while ((hd->scsi_ssts & SSTS_BUSY) == 0) { 400 if (hd->scsi_ints || --wait < 0) { 401 #ifdef DEBUG 402 if (scsi_debug) 403 printf("ixfer_start fail: i%x, w%d\n", 404 hd->scsi_ints, wait); 405 #endif 406 HIST(ixstart_wait, wait) 407 return (0); 408 } 409 DELAY(1); 410 } 411 HIST(ixstart_wait, wait) 412 return (1); 413 } 414 415 static int 416 ixfer_out(hd, len, buf) 417 volatile register struct scsidevice *hd; 418 int len; 419 register u_char *buf; 420 { 421 register int wait = scsi_data_wait; 422 423 for (; len > 0; --len) { 424 while (hd->scsi_ssts & SSTS_DREG_FULL) { 425 if (hd->scsi_ints || --wait < 0) { 426 #ifdef DEBUG 427 if (scsi_debug) 428 printf("ixfer_out fail: l%d i%x w%d\n", 429 len, hd->scsi_ints, wait); 430 #endif 431 HIST(ixout_wait, wait) 432 return (len); 433 } 434 DELAY(1); 435 } 436 hd->scsi_dreg = *buf++; 437 } 438 HIST(ixout_wait, wait) 439 return (0); 440 } 441 442 static void 443 ixfer_in(hd, len, buf) 444 volatile register struct scsidevice *hd; 445 int len; 446 register u_char *buf; 447 { 448 register int wait = scsi_data_wait; 449 450 for (; len > 0; --len) { 451 while (hd->scsi_ssts & SSTS_DREG_EMPTY) { 452 if (hd->scsi_ints || --wait < 0) { 453 while (! (hd->scsi_ssts & SSTS_DREG_EMPTY)) { 454 *buf++ = hd->scsi_dreg; 455 --len; 456 } 457 #ifdef DEBUG 458 if (scsi_debug) 459 printf("ixfer_in fail: l%d i%x w%d\n", 460 len, hd->scsi_ints, wait); 461 #endif 462 HIST(ixin_wait, wait) 463 return; 464 } 465 DELAY(1); 466 } 467 *buf++ = hd->scsi_dreg; 468 } 469 HIST(ixin_wait, wait) 470 } 471 472 static int 473 mxfer_in(hd, len, buf, phase) 474 volatile register struct scsidevice *hd; 475 register int len; 476 register u_char *buf; 477 register u_char phase; 478 { 479 register int wait = scsi_cmd_wait; 480 register int i; 481 482 hd->scsi_tmod = 0; 483 for (i = 0; i < len; ++i) { 484 /* 485 * manual sez: reset ATN before ACK is sent. 486 */ 487 if (hd->scsi_psns & PSNS_ATN) 488 hd->scsi_scmd = SCMD_RST_ATN; 489 /* 490 * wait for the request line (which says the target 491 * wants to give us data). If the phase changes while 492 * we're waiting, we're done. 493 */ 494 while ((hd->scsi_psns & PSNS_REQ) == 0) { 495 if (--wait < 0) { 496 HIST(mxin_wait, wait) 497 return (-1); 498 } 499 if ((hd->scsi_psns & PHASE) != phase || 500 (hd->scsi_ssts & SSTS_INITIATOR) == 0) 501 goto out; 502 503 DELAY(1); 504 } 505 /* 506 * set ack (which says we're ready for the data, wait for 507 * req to go away (target says data is available), grab the 508 * data, then reset ack (say we've got the data). 509 */ 510 hd->scsi_pctl = phase; 511 hd->scsi_scmd = SCMD_SET_ACK; 512 while (hd->scsi_psns & PSNS_REQ) { 513 if (--wait < 0) { 514 HIST(mxin_wait, wait) 515 return (-2); 516 } 517 DELAY(1); 518 } 519 *buf++ = hd->scsi_temp; 520 hd->scsi_scmd = SCMD_RST_ACK; 521 } 522 out: 523 HIST(mxin_wait, wait) 524 /* 525 * Wait for manual transfer to finish. 526 * Avoids occasional "unexpected phase" errors in finishxfer 527 * formerly addressed by per-slave delays. 528 */ 529 wait = scsi_cmd_wait; 530 while ((hd->scsi_ssts & SSTS_ACTIVE) == SSTS_INITIATOR) { 531 if (--wait < 0) 532 break; 533 DELAY(1); 534 } 535 HIST(mxin2_wait, wait) 536 return (i); 537 } 538 539 /* 540 * SCSI 'immediate' command: issue a command to some SCSI device 541 * and get back an 'immediate' response (i.e., do programmed xfer 542 * to get the response data). 'cbuf' is a buffer containing a scsi 543 * command of length clen bytes. 'buf' is a buffer of length 'len' 544 * bytes for data. The transfer direction is determined by the device 545 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 546 * command must supply no data. 'xferphase' is the bus phase the 547 * caller expects to happen after the command is issued. It should 548 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 549 */ 550 static int 551 scsiicmd(hs, target, cbuf, clen, buf, len, xferphase) 552 struct scsi_softc *hs; 553 int target; 554 u_char *cbuf; 555 int clen; 556 u_char *buf; 557 int len; 558 u_char xferphase; 559 { 560 volatile register struct scsidevice *hd = 561 (struct scsidevice *)hs->sc_hc->hp_addr; 562 u_char phase, ints; 563 register int wait; 564 565 /* select the SCSI bus (it's an error if bus isn't free) */ 566 if (issue_select(hd, target, hs->sc_scsi_addr)) 567 return (-1); 568 if (wait_for_select(hd)) 569 return (-1); 570 /* 571 * Wait for a phase change (or error) then let the device 572 * sequence us through the various SCSI phases. 573 */ 574 hs->sc_stat[0] = 0xff; 575 hs->sc_msg[0] = 0xff; 576 phase = CMD_PHASE; 577 while (1) { 578 wait = scsi_cmd_wait; 579 switch (phase) { 580 581 case CMD_PHASE: 582 if (ixfer_start(hd, clen, phase, wait)) 583 if (ixfer_out(hd, clen, cbuf)) 584 goto abort; 585 phase = xferphase; 586 break; 587 588 case DATA_IN_PHASE: 589 if (len <= 0) 590 goto abort; 591 wait = scsi_data_wait; 592 if (ixfer_start(hd, len, phase, wait) || 593 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) 594 ixfer_in(hd, len, buf); 595 phase = STATUS_PHASE; 596 break; 597 598 case DATA_OUT_PHASE: 599 if (len <= 0) 600 goto abort; 601 wait = scsi_data_wait; 602 if (ixfer_start(hd, len, phase, wait)) { 603 if (ixfer_out(hd, len, buf)) 604 goto abort; 605 } 606 phase = STATUS_PHASE; 607 break; 608 609 case STATUS_PHASE: 610 wait = scsi_data_wait; 611 if (ixfer_start(hd, sizeof(hs->sc_stat), phase, wait) || 612 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) 613 ixfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat); 614 phase = MESG_IN_PHASE; 615 break; 616 617 case MESG_IN_PHASE: 618 if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait) || 619 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { 620 ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); 621 hd->scsi_scmd = SCMD_RST_ACK; 622 } 623 phase = BUS_FREE_PHASE; 624 break; 625 626 case BUS_FREE_PHASE: 627 goto out; 628 629 default: 630 printf("scsi%d: unexpected phase %d in icmd from %d\n", 631 hs->sc_hc->hp_unit, phase, target); 632 goto abort; 633 } 634 /* wait for last command to complete */ 635 while ((ints = hd->scsi_ints) == 0) { 636 if (--wait < 0) { 637 HIST(cxin_wait, wait) 638 goto abort; 639 } 640 DELAY(1); 641 } 642 HIST(cxin_wait, wait) 643 hd->scsi_ints = ints; 644 if (ints & INTS_SRV_REQ) 645 phase = hd->scsi_psns & PHASE; 646 else if (ints & INTS_DISCON) 647 goto out; 648 else if ((ints & INTS_CMD_DONE) == 0) { 649 scsierror(hs, hd, ints); 650 goto abort; 651 } 652 } 653 abort: 654 scsiabort(hs, hd, "icmd"); 655 out: 656 return (hs->sc_stat[0]); 657 } 658 659 /* 660 * Finish SCSI xfer command: After the completion interrupt from 661 * a read/write operation, sequence through the final phases in 662 * programmed i/o. This routine is a lot like scsiicmd except we 663 * skip (and don't allow) the select, cmd out and data in/out phases. 664 */ 665 static void 666 finishxfer(hs, hd, target) 667 struct scsi_softc *hs; 668 volatile register struct scsidevice *hd; 669 int target; 670 { 671 u_char phase, ints; 672 673 /* 674 * We specified padding xfer so we ended with either a phase 675 * change interrupt (normal case) or an error interrupt (handled 676 * elsewhere). Reset the board dma logic then try to get the 677 * completion status & command done msg. The reset confuses 678 * the SPC REQ/ACK logic so we have to do any status/msg input 679 * operations via 'manual xfer'. 680 */ 681 if (hd->scsi_ssts & SSTS_BUSY) { 682 int wait = scsi_cmd_wait; 683 684 /* wait for dma operation to finish */ 685 while (hd->scsi_ssts & SSTS_BUSY) { 686 if (--wait < 0) { 687 #ifdef DEBUG 688 if (scsi_debug) 689 printf("finishxfer fail: ssts %x\n", 690 hd->scsi_ssts); 691 #endif 692 HIST(fxfr_wait, wait) 693 goto abort; 694 } 695 } 696 HIST(fxfr_wait, wait) 697 } 698 hd->scsi_scmd |= SCMD_PROG_XFR; 699 hd->scsi_sctl |= SCTL_CTRLRST; 700 DELAY(1); 701 hd->scsi_sctl &=~ SCTL_CTRLRST; 702 hd->scsi_hconf = 0; 703 hs->sc_stat[0] = 0xff; 704 hs->sc_msg[0] = 0xff; 705 hd->scsi_csr = 0; 706 hd->scsi_ints = ints = hd->scsi_ints; 707 while (1) { 708 phase = hd->scsi_psns & PHASE; 709 switch (phase) { 710 711 case STATUS_PHASE: 712 if (mxfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat, 713 phase) <= 0) 714 goto abort; 715 break; 716 717 case MESG_IN_PHASE: 718 if (mxfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg, 719 phase) < 0) 720 goto abort; 721 break; 722 723 case BUS_FREE_PHASE: 724 return; 725 726 default: 727 printf("scsi%d: unexpected phase %d in finishxfer from %d\n", 728 hs->sc_hc->hp_unit, phase, target); 729 goto abort; 730 } 731 if (ints = hd->scsi_ints) { 732 hd->scsi_ints = ints; 733 if (ints & INTS_DISCON) 734 return; 735 else if (ints & ~(INTS_SRV_REQ|INTS_CMD_DONE)) { 736 scsierror(hs, hd, ints); 737 break; 738 } 739 } 740 if ((hd->scsi_ssts & SSTS_INITIATOR) == 0) 741 return; 742 } 743 abort: 744 scsiabort(hs, hd, "finishxfer"); 745 hs->sc_stat[0] = 0xfe; 746 } 747 748 int 749 scsi_test_unit_rdy(ctlr, slave, unit) 750 int ctlr, slave, unit; 751 { 752 register struct scsi_softc *hs = &scsi_softc[ctlr]; 753 static struct scsi_cdb6 cdb = { CMD_TEST_UNIT_READY }; 754 755 cdb.lun = unit; 756 return (scsiicmd(hs, slave, &cdb, sizeof(cdb), (u_char *)0, 0, 757 STATUS_PHASE)); 758 } 759 760 int 761 scsi_request_sense(ctlr, slave, unit, buf, len) 762 int ctlr, slave, unit; 763 u_char *buf; 764 unsigned len; 765 { 766 register struct scsi_softc *hs = &scsi_softc[ctlr]; 767 static struct scsi_cdb6 cdb = { CMD_REQUEST_SENSE }; 768 769 cdb.lun = unit; 770 cdb.len = len; 771 return (scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE)); 772 } 773 774 int 775 scsi_immed_command(ctlr, slave, unit, cdb, buf, len, rd) 776 int ctlr, slave, unit; 777 struct scsi_fmt_cdb *cdb; 778 u_char *buf; 779 unsigned len; 780 { 781 register struct scsi_softc *hs = &scsi_softc[ctlr]; 782 783 cdb->cdb[1] |= unit << 5; 784 return (scsiicmd(hs, slave, cdb->cdb, cdb->len, buf, len, 785 rd != 0? DATA_IN_PHASE : DATA_OUT_PHASE)); 786 } 787 788 /* 789 * The following routines are test-and-transfer i/o versions of read/write 790 * for things like reading disk labels and writing core dumps. The 791 * routine scsigo should be used for normal data transfers, NOT these 792 * routines. 793 */ 794 int 795 scsi_tt_read(ctlr, slave, unit, buf, len, blk, bshift) 796 int ctlr, slave, unit; 797 u_char *buf; 798 u_int len; 799 daddr_t blk; 800 int bshift; 801 { 802 register struct scsi_softc *hs = &scsi_softc[ctlr]; 803 struct scsi_cdb10 cdb; 804 int stat; 805 int old_wait = scsi_data_wait; 806 807 scsi_data_wait = 300000; 808 bzero(&cdb, sizeof(cdb)); 809 cdb.cmd = CMD_READ_EXT; 810 cdb.lun = unit; 811 blk >>= bshift; 812 cdb.lbah = blk >> 24; 813 cdb.lbahm = blk >> 16; 814 cdb.lbalm = blk >> 8; 815 cdb.lbal = blk; 816 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 817 cdb.lenl = len >> (DEV_BSHIFT + bshift); 818 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE); 819 scsi_data_wait = old_wait; 820 return (stat); 821 } 822 823 int 824 scsi_tt_write(ctlr, slave, unit, buf, len, blk, bshift) 825 int ctlr, slave, unit; 826 u_char *buf; 827 u_int len; 828 daddr_t blk; 829 int bshift; 830 { 831 register struct scsi_softc *hs = &scsi_softc[ctlr]; 832 struct scsi_cdb10 cdb; 833 int stat; 834 int old_wait = scsi_data_wait; 835 836 scsi_data_wait = 300000; 837 838 bzero(&cdb, sizeof(cdb)); 839 cdb.cmd = CMD_WRITE_EXT; 840 cdb.lun = unit; 841 blk >>= bshift; 842 cdb.lbah = blk >> 24; 843 cdb.lbahm = blk >> 16; 844 cdb.lbalm = blk >> 8; 845 cdb.lbal = blk; 846 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 847 cdb.lenl = len >> (DEV_BSHIFT + bshift); 848 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_OUT_PHASE); 849 scsi_data_wait = old_wait; 850 return (stat); 851 } 852 853 int 854 scsireq(dq) 855 register struct devqueue *dq; 856 { 857 register struct devqueue *hq; 858 859 hq = &scsi_softc[dq->dq_ctlr].sc_sq; 860 insque(dq, hq->dq_back); 861 if (dq->dq_back == hq) 862 return(1); 863 return(0); 864 } 865 866 int 867 scsiustart(unit) 868 int unit; 869 { 870 register struct scsi_softc *hs = &scsi_softc[unit]; 871 872 hs->sc_dq.dq_ctlr = DMA0 | DMA1; 873 if (dmareq(&hs->sc_dq)) 874 return(1); 875 return(0); 876 } 877 878 void 879 scsistart(unit) 880 int unit; 881 { 882 register struct devqueue *dq; 883 884 dq = scsi_softc[unit].sc_sq.dq_forw; 885 (dq->dq_driver->d_go)(dq->dq_unit); 886 } 887 888 int 889 scsigo(ctlr, slave, unit, bp, cdb, pad) 890 int ctlr, slave, unit; 891 struct buf *bp; 892 struct scsi_fmt_cdb *cdb; 893 int pad; 894 { 895 register struct scsi_softc *hs = &scsi_softc[ctlr]; 896 volatile register struct scsidevice *hd = 897 (struct scsidevice *)hs->sc_hc->hp_addr; 898 int i, dmaflags; 899 u_char phase, ints, cmd; 900 901 cdb->cdb[1] |= unit << 5; 902 903 /* select the SCSI bus (it's an error if bus isn't free) */ 904 if (issue_select(hd, slave, hs->sc_scsi_addr) || wait_for_select(hd)) { 905 dmafree(&hs->sc_dq); 906 return (1); 907 } 908 /* 909 * Wait for a phase change (or error) then let the device 910 * sequence us through command phase (we may have to take 911 * a msg in/out before doing the command). If the disk has 912 * to do a seek, it may be a long time until we get a change 913 * to data phase so, in the absense of an explicit phase 914 * change, we assume data phase will be coming up and tell 915 * the SPC to start a transfer whenever it does. We'll get 916 * a service required interrupt later if this assumption is 917 * wrong. Otherwise we'll get a service required int when 918 * the transfer changes to status phase. 919 */ 920 phase = CMD_PHASE; 921 while (1) { 922 register int wait = scsi_cmd_wait; 923 924 switch (phase) { 925 926 case CMD_PHASE: 927 if (ixfer_start(hd, cdb->len, phase, wait)) 928 if (ixfer_out(hd, cdb->len, cdb->cdb)) 929 goto abort; 930 break; 931 932 case MESG_IN_PHASE: 933 if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait)|| 934 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { 935 ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); 936 hd->scsi_scmd = SCMD_RST_ACK; 937 } 938 phase = BUS_FREE_PHASE; 939 break; 940 941 case DATA_IN_PHASE: 942 case DATA_OUT_PHASE: 943 goto out; 944 945 default: 946 printf("scsi%d: unexpected phase %d in go from %d\n", 947 hs->sc_hc->hp_unit, phase, slave); 948 goto abort; 949 } 950 while ((ints = hd->scsi_ints) == 0) { 951 if (--wait < 0) { 952 HIST(sgo_wait, wait) 953 goto abort; 954 } 955 DELAY(1); 956 } 957 HIST(sgo_wait, wait) 958 hd->scsi_ints = ints; 959 if (ints & INTS_SRV_REQ) 960 phase = hd->scsi_psns & PHASE; 961 else if (ints & INTS_CMD_DONE) 962 goto out; 963 else { 964 scsierror(hs, hd, ints); 965 goto abort; 966 } 967 } 968 out: 969 /* 970 * Reset the card dma logic, setup the dma channel then 971 * get the dio part of the card set for a dma xfer. 972 */ 973 hd->scsi_hconf = 0; 974 cmd = CSR_IE; 975 dmaflags = DMAGO_NOINT; 976 if (scsi_pridma) 977 dmaflags |= DMAGO_PRI; 978 if (bp->b_flags & B_READ) 979 dmaflags |= DMAGO_READ; 980 if ((hs->sc_flags & SCSI_DMA32) && 981 ((int)bp->b_un.b_addr & 3) == 0 && (bp->b_bcount & 3) == 0) { 982 cmd |= CSR_DMA32; 983 dmaflags |= DMAGO_LWORD; 984 } else 985 dmaflags |= DMAGO_WORD; 986 dmago(hs->sc_dq.dq_ctlr, bp->b_un.b_addr, bp->b_bcount, dmaflags); 987 988 if (bp->b_flags & B_READ) { 989 cmd |= CSR_DMAIN; 990 phase = DATA_IN_PHASE; 991 } else 992 phase = DATA_OUT_PHASE; 993 /* 994 * DMA enable bits must be set after size and direction bits. 995 */ 996 hd->scsi_csr = cmd; 997 hd->scsi_csr |= (CSR_DE0 << hs->sc_dq.dq_ctlr); 998 /* 999 * Setup the SPC for the transfer. We don't want to take 1000 * first a command complete then a service required interrupt 1001 * at the end of the transfer so we try to disable the cmd 1002 * complete by setting the transfer counter to more bytes 1003 * than we expect. (XXX - This strategy may have to be 1004 * modified to deal with devices that return variable length 1005 * blocks, e.g., some tape drives.) 1006 */ 1007 cmd = SCMD_XFR; 1008 i = (unsigned)bp->b_bcount; 1009 if (pad) { 1010 cmd |= SCMD_PAD; 1011 /* 1012 * XXX - If we don't do this, the last 2 or 4 bytes 1013 * (depending on word/lword DMA) of a read get trashed. 1014 * It looks like it is necessary for the DMA to complete 1015 * before the SPC goes into "pad mode"??? Note: if we 1016 * also do this on a write, the request never completes. 1017 */ 1018 if (bp->b_flags & B_READ) 1019 i += 2; 1020 #ifdef DEBUG 1021 hs->sc_flags |= SCSI_PAD; 1022 if (i & 1) 1023 printf("scsi%d: odd byte count: %d bytes @ %d\n", 1024 ctlr, i, bp->b_cylin); 1025 #endif 1026 } else 1027 i += 4; 1028 hd->scsi_tch = i >> 16; 1029 hd->scsi_tcm = i >> 8; 1030 hd->scsi_tcl = i; 1031 hd->scsi_pctl = phase; 1032 hd->scsi_tmod = 0; 1033 hd->scsi_scmd = cmd; 1034 hs->sc_flags |= SCSI_IO; 1035 return (0); 1036 abort: 1037 scsiabort(hs, hd, "go"); 1038 dmafree(&hs->sc_dq); 1039 return (1); 1040 } 1041 1042 void 1043 scsidone(unit) 1044 register int unit; 1045 { 1046 volatile register struct scsidevice *hd = 1047 (struct scsidevice *)scsi_softc[unit].sc_hc->hp_addr; 1048 1049 #ifdef DEBUG 1050 if (scsi_debug) 1051 printf("scsi%d: done called!\n"); 1052 #endif 1053 /* dma operation is done -- turn off card dma */ 1054 hd->scsi_csr &=~ (CSR_DE1|CSR_DE0); 1055 } 1056 1057 int 1058 scsiintr(unit) 1059 register int unit; 1060 { 1061 register struct scsi_softc *hs = &scsi_softc[unit]; 1062 volatile register struct scsidevice *hd = 1063 (struct scsidevice *)hs->sc_hc->hp_addr; 1064 register u_char ints; 1065 register struct devqueue *dq; 1066 1067 if ((hd->scsi_csr & (CSR_IE|CSR_IR)) != (CSR_IE|CSR_IR)) 1068 return (0); 1069 1070 ints = hd->scsi_ints; 1071 if ((ints & INTS_SRV_REQ) && (hs->sc_flags & SCSI_IO)) { 1072 /* 1073 * this should be the normal i/o completion case. 1074 * get the status & cmd complete msg then let the 1075 * device driver look at what happened. 1076 */ 1077 #ifdef DEBUG 1078 int len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | 1079 hd->scsi_tcl; 1080 if (!(hs->sc_flags & SCSI_PAD)) 1081 len -= 4; 1082 hs->sc_flags &=~ SCSI_PAD; 1083 #endif 1084 dq = hs->sc_sq.dq_forw; 1085 finishxfer(hs, hd, dq->dq_slave); 1086 hs->sc_flags &=~ SCSI_IO; 1087 dmafree(&hs->sc_dq); 1088 (dq->dq_driver->d_intr)(dq->dq_unit, hs->sc_stat[0]); 1089 } else { 1090 /* Something unexpected happened -- deal with it. */ 1091 hd->scsi_ints = ints; 1092 hd->scsi_csr = 0; 1093 scsierror(hs, hd, ints); 1094 scsiabort(hs, hd, "intr"); 1095 if (hs->sc_flags & SCSI_IO) { 1096 hs->sc_flags &=~ SCSI_IO; 1097 dmafree(&hs->sc_dq); 1098 dq = hs->sc_sq.dq_forw; 1099 (dq->dq_driver->d_intr)(dq->dq_unit, -1); 1100 } 1101 } 1102 return(1); 1103 } 1104 1105 void 1106 scsifree(dq) 1107 register struct devqueue *dq; 1108 { 1109 register struct devqueue *hq; 1110 1111 hq = &scsi_softc[dq->dq_ctlr].sc_sq; 1112 remque(dq); 1113 if ((dq = hq->dq_forw) != hq) 1114 (dq->dq_driver->d_start)(dq->dq_unit); 1115 } 1116 1117 /* 1118 * (XXX) The following routine is needed for the SCSI tape driver 1119 * to read odd-size records. 1120 */ 1121 1122 #include "st.h" 1123 #if NST > 0 1124 int 1125 scsi_tt_oddio(ctlr, slave, unit, buf, len, b_flags, freedma) 1126 int ctlr, slave, unit, b_flags; 1127 u_char *buf; 1128 u_int len; 1129 { 1130 register struct scsi_softc *hs = &scsi_softc[ctlr]; 1131 struct scsi_cdb6 cdb; 1132 u_char iphase; 1133 int stat; 1134 1135 /* 1136 * First free any DMA channel that was allocated. 1137 * We can't use DMA to do this transfer. 1138 */ 1139 if (freedma) 1140 dmafree(hs->sc_dq); 1141 /* 1142 * Initialize command block 1143 */ 1144 bzero(&cdb, sizeof(cdb)); 1145 cdb.lun = unit; 1146 cdb.lbam = (len >> 16) & 0xff; 1147 cdb.lbal = (len >> 8) & 0xff; 1148 cdb.len = len & 0xff; 1149 if (buf == 0) { 1150 cdb.cmd = CMD_SPACE; 1151 cdb.lun |= 0x00; 1152 len = 0; 1153 iphase = MESG_IN_PHASE; 1154 } else if (b_flags & B_READ) { 1155 cdb.cmd = CMD_READ; 1156 iphase = DATA_IN_PHASE; 1157 } else { 1158 cdb.cmd = CMD_WRITE; 1159 iphase = DATA_OUT_PHASE; 1160 } 1161 /* 1162 * Perform command (with very long delays) 1163 */ 1164 scsi_delay(30000000); 1165 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, iphase); 1166 scsi_delay(0); 1167 return (stat); 1168 } 1169 #endif 1170 #endif 1171