1 #ifndef DEBUG 2 #define DEBUG 3 #endif 4 /* 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * %sccs.include.redist.c% 12 * 13 * @(#)scsi.c 7.7 (Berkeley) 06/05/92 14 */ 15 16 /* 17 * HP9000/3xx 98658 SCSI host adaptor driver. 18 */ 19 #include "scsi.h" 20 #if NSCSI > 0 21 22 #ifndef lint 23 static char rcsid[] = "$Header: /usr/src/sys/hp300/dev/RCS/scsi.c,v 1.2 92/04/10 20:48:29 mike Exp $"; 24 #endif 25 26 #include "sys/param.h" 27 #include "sys/systm.h" 28 #include "sys/buf.h" 29 #include "hp/dev/device.h" 30 31 #include "scsivar.h" 32 #include "scsireg.h" 33 #include "dmavar.h" 34 35 #include "../include/cpu.h" 36 #include "../hp300/isr.h" 37 38 /* 39 * SCSI delays 40 * In u-seconds, primarily for state changes on the SPC. 41 */ 42 #define SCSI_CMD_WAIT 1000 /* wait per step of 'immediate' cmds */ 43 #define SCSI_DATA_WAIT 1000 /* wait per data in/out step */ 44 #define SCSI_INIT_WAIT 50000 /* wait per step (both) during init */ 45 46 extern void isrlink(); 47 extern void _insque(); 48 extern void _remque(); 49 50 int scsiinit(), scsigo(), scsiintr(), scsixfer(); 51 void scsistart(), scsidone(), scsifree(), scsireset(); 52 struct driver scsidriver = { 53 scsiinit, "scsi", (int (*)())scsistart, scsigo, scsiintr, 54 (int (*)())scsidone, 55 }; 56 57 struct scsi_softc scsi_softc[NSCSI]; 58 struct isr scsi_isr[NSCSI]; 59 60 int scsi_cmd_wait = SCSI_CMD_WAIT; 61 int scsi_data_wait = SCSI_DATA_WAIT; 62 int scsi_init_wait = SCSI_INIT_WAIT; 63 64 int scsi_nosync = 1; /* inhibit sync xfers if 1 */ 65 int scsi_pridma = 0; /* use "priority" dma */ 66 67 #ifdef DEBUG 68 int scsi_debug = 0; 69 #define WAITHIST 70 #endif 71 72 #ifdef WAITHIST 73 #define MAXWAIT 1022 74 u_int ixstart_wait[MAXWAIT+2]; 75 u_int ixin_wait[MAXWAIT+2]; 76 u_int ixout_wait[MAXWAIT+2]; 77 u_int mxin_wait[MAXWAIT+2]; 78 u_int mxin2_wait[MAXWAIT+2]; 79 u_int cxin_wait[MAXWAIT+2]; 80 u_int fxfr_wait[MAXWAIT+2]; 81 u_int sgo_wait[MAXWAIT+2]; 82 #define HIST(h,w) (++h[((w)>MAXWAIT? MAXWAIT : ((w) < 0 ? -1 : (w))) + 1]); 83 #else 84 #define HIST(h,w) 85 #endif 86 87 #define b_cylin b_resid 88 89 static void 90 scsiabort(hs, hd, where) 91 register struct scsi_softc *hs; 92 volatile register struct scsidevice *hd; 93 char *where; 94 { 95 int len; 96 int maxtries; /* XXX - kludge till I understand whats *supposed* to happen */ 97 int startlen; /* XXX - kludge till I understand whats *supposed* to happen */ 98 u_char junk; 99 100 printf("scsi%d: abort from %s: phase=0x%x, ssts=0x%x, ints=0x%x\n", 101 hs->sc_hc->hp_unit, where, hd->scsi_psns, hd->scsi_ssts, 102 hd->scsi_ints); 103 104 hd->scsi_ints = hd->scsi_ints; 105 hd->scsi_csr = 0; 106 if (hd->scsi_psns == 0 || (hd->scsi_ssts & SSTS_INITIATOR) == 0) 107 /* no longer connected to scsi target */ 108 return; 109 110 /* get the number of bytes remaining in current xfer + fudge */ 111 len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | hd->scsi_tcl; 112 113 /* for that many bus cycles, try to send an abort msg */ 114 for (startlen = (len += 1024); (hd->scsi_ssts & SSTS_INITIATOR) && --len >= 0; ) { 115 hd->scsi_scmd = SCMD_SET_ATN; 116 maxtries = 1000; 117 while ((hd->scsi_psns & PSNS_REQ) == 0) { 118 if (! (hd->scsi_ssts & SSTS_INITIATOR)) 119 goto out; 120 DELAY(1); 121 if (--maxtries == 0) { 122 printf("-- scsiabort gave up after 1000 tries (startlen = %d len = %d)\n", 123 startlen, len); 124 goto out2; 125 } 126 127 } 128 out2: 129 if ((hd->scsi_psns & PHASE) == MESG_OUT_PHASE) 130 hd->scsi_scmd = SCMD_RST_ATN; 131 hd->scsi_pctl = hd->scsi_psns & PHASE; 132 if (hd->scsi_psns & PHASE_IO) { 133 /* one of the input phases - read & discard a byte */ 134 hd->scsi_scmd = SCMD_SET_ACK; 135 if (hd->scsi_tmod == 0) 136 while (hd->scsi_psns & PSNS_REQ) 137 DELAY(1); 138 junk = hd->scsi_temp; 139 } else { 140 /* one of the output phases - send an abort msg */ 141 hd->scsi_temp = MSG_ABORT; 142 hd->scsi_scmd = SCMD_SET_ACK; 143 if (hd->scsi_tmod == 0) 144 while (hd->scsi_psns & PSNS_REQ) 145 DELAY(1); 146 } 147 hd->scsi_scmd = SCMD_RST_ACK; 148 } 149 out: 150 /* 151 * Either the abort was successful & the bus is disconnected or 152 * the device didn't listen. If the latter, announce the problem. 153 * Either way, reset the card & the SPC. 154 */ 155 if (len < 0 && hs) 156 printf("scsi%d: abort failed. phase=0x%x, ssts=0x%x\n", 157 hs->sc_hc->hp_unit, hd->scsi_psns, hd->scsi_ssts); 158 159 if (! ((junk = hd->scsi_ints) & INTS_RESEL)) { 160 hd->scsi_sctl |= SCTL_CTRLRST; 161 DELAY(1); 162 hd->scsi_sctl &=~ SCTL_CTRLRST; 163 hd->scsi_hconf = 0; 164 hd->scsi_ints = hd->scsi_ints; 165 } 166 } 167 168 /* 169 * XXX Set/reset long delays. 170 * 171 * if delay == 0, reset default delays 172 * if delay < 0, set both delays to default long initialization values 173 * if delay > 0, set both delays to this value 174 * 175 * Used when a devices is expected to respond slowly (e.g. during 176 * initialization). 177 */ 178 void 179 scsi_delay(delay) 180 int delay; 181 { 182 static int saved_cmd_wait, saved_data_wait; 183 184 if (delay) { 185 saved_cmd_wait = scsi_cmd_wait; 186 saved_data_wait = scsi_data_wait; 187 if (delay > 0) 188 scsi_cmd_wait = scsi_data_wait = delay; 189 else 190 scsi_cmd_wait = scsi_data_wait = scsi_init_wait; 191 } else { 192 scsi_cmd_wait = saved_cmd_wait; 193 scsi_data_wait = saved_data_wait; 194 } 195 } 196 197 int 198 scsiinit(hc) 199 register struct hp_ctlr *hc; 200 { 201 register struct scsi_softc *hs = &scsi_softc[hc->hp_unit]; 202 register struct scsidevice *hd = (struct scsidevice *)hc->hp_addr; 203 204 if ((hd->scsi_id & ID_MASK) != SCSI_ID) 205 return(0); 206 hc->hp_ipl = SCSI_IPL(hd->scsi_csr); 207 hs->sc_hc = hc; 208 hs->sc_dq.dq_unit = hc->hp_unit; 209 hs->sc_dq.dq_driver = &scsidriver; 210 hs->sc_sq.dq_forw = hs->sc_sq.dq_back = &hs->sc_sq; 211 scsi_isr[hc->hp_unit].isr_intr = scsiintr; 212 scsi_isr[hc->hp_unit].isr_ipl = hc->hp_ipl; 213 scsi_isr[hc->hp_unit].isr_arg = hc->hp_unit; 214 isrlink(&scsi_isr[hc->hp_unit]); 215 scsireset(hc->hp_unit); 216 /* 217 * XXX scale initialization wait according to CPU speed. 218 * Should we do this for all wait? Should we do this at all? 219 */ 220 scsi_init_wait *= cpuspeed; 221 return(1); 222 } 223 224 void 225 scsireset(unit) 226 register int unit; 227 { 228 register struct scsi_softc *hs = &scsi_softc[unit]; 229 volatile register struct scsidevice *hd = 230 (struct scsidevice *)hs->sc_hc->hp_addr; 231 u_int i; 232 233 if (hs->sc_flags & SCSI_ALIVE) 234 scsiabort(hs, hd, "reset"); 235 236 printf("scsi%d: ", unit); 237 238 hd->scsi_id = 0xFF; 239 DELAY(100); 240 /* 241 * Disable interrupts then reset the FUJI chip. 242 */ 243 hd->scsi_csr = 0; 244 hd->scsi_sctl = SCTL_DISABLE | SCTL_CTRLRST; 245 hd->scsi_scmd = 0; 246 hd->scsi_tmod = 0; 247 hd->scsi_pctl = 0; 248 hd->scsi_temp = 0; 249 hd->scsi_tch = 0; 250 hd->scsi_tcm = 0; 251 hd->scsi_tcl = 0; 252 hd->scsi_ints = 0; 253 254 if ((hd->scsi_id & ID_WORD_DMA) == 0) { 255 hs->sc_flags |= SCSI_DMA32; 256 printf("32 bit dma, "); 257 } 258 259 /* Determine Max Synchronous Transfer Rate */ 260 if (scsi_nosync) 261 i = 3; 262 else 263 i = SCSI_SYNC_XFER(hd->scsi_hconf); 264 switch (i) { 265 case 0: 266 hs->sc_sync = TMOD_SYNC | 0x3e; /* 250 nsecs */ 267 printf("250ns sync"); 268 break; 269 case 1: 270 hs->sc_sync = TMOD_SYNC | 0x5e; /* 375 nsecs */ 271 printf("375ns sync"); 272 break; 273 case 2: 274 hs->sc_sync = TMOD_SYNC | 0x7d; /* 500 nsecs */ 275 printf("500ns sync"); 276 break; 277 case 3: 278 hs->sc_sync = 0; 279 printf("async"); 280 break; 281 } 282 283 /* 284 * Configure the FUJI chip with its SCSI address, all 285 * interrupts enabled & appropriate parity. 286 */ 287 i = (~hd->scsi_hconf) & 0x7; 288 hs->sc_scsi_addr = 1 << i; 289 hd->scsi_bdid = i; 290 if (hd->scsi_hconf & HCONF_PARITY) 291 hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | 292 SCTL_SEL_ENAB | SCTL_RESEL_ENAB | 293 SCTL_INTR_ENAB | SCTL_PARITY_ENAB; 294 else { 295 hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | 296 SCTL_SEL_ENAB | SCTL_RESEL_ENAB | 297 SCTL_INTR_ENAB; 298 printf(", no parity"); 299 } 300 hd->scsi_sctl &=~ SCTL_DISABLE; 301 302 printf(", scsi id %d\n", i); 303 hs->sc_flags |= SCSI_ALIVE; 304 } 305 306 static void 307 scsierror(hs, hd, ints) 308 register struct scsi_softc *hs; 309 volatile register struct scsidevice *hd; 310 u_char ints; 311 { 312 int unit = hs->sc_hc->hp_unit; 313 char *sep = ""; 314 315 printf("scsi%d: ", unit); 316 if (ints & INTS_RST) { 317 DELAY(100); 318 if (hd->scsi_hconf & HCONF_SD) 319 printf("spurious RST interrupt"); 320 else 321 printf("hardware error - check fuse"); 322 sep = ", "; 323 } 324 if ((ints & INTS_HARD_ERR) || hd->scsi_serr) { 325 if (hd->scsi_serr & SERR_SCSI_PAR) { 326 printf("%sparity err", sep); 327 sep = ", "; 328 } 329 if (hd->scsi_serr & SERR_SPC_PAR) { 330 printf("%sSPC parity err", sep); 331 sep = ", "; 332 } 333 if (hd->scsi_serr & SERR_TC_PAR) { 334 printf("%sTC parity err", sep); 335 sep = ", "; 336 } 337 if (hd->scsi_serr & SERR_PHASE_ERR) { 338 printf("%sphase err", sep); 339 sep = ", "; 340 } 341 if (hd->scsi_serr & SERR_SHORT_XFR) { 342 printf("%ssync short transfer err", sep); 343 sep = ", "; 344 } 345 if (hd->scsi_serr & SERR_OFFSET) { 346 printf("%ssync offset error", sep); 347 sep = ", "; 348 } 349 } 350 if (ints & INTS_TIMEOUT) 351 printf("%sSPC select timeout error", sep); 352 if (ints & INTS_SRV_REQ) 353 printf("%sspurious SRV_REQ interrupt", sep); 354 if (ints & INTS_CMD_DONE) 355 printf("%sspurious CMD_DONE interrupt", sep); 356 if (ints & INTS_DISCON) 357 printf("%sspurious disconnect interrupt", sep); 358 if (ints & INTS_RESEL) 359 printf("%sspurious reselect interrupt", sep); 360 if (ints & INTS_SEL) 361 printf("%sspurious select interrupt", sep); 362 printf("\n"); 363 } 364 365 static int 366 issue_select(hd, target, our_addr) 367 volatile register struct scsidevice *hd; 368 u_char target, our_addr; 369 { 370 if (hd->scsi_ssts & (SSTS_INITIATOR|SSTS_TARGET|SSTS_BUSY)) 371 return (1); 372 373 if (hd->scsi_ints & INTS_DISCON) 374 hd->scsi_ints = INTS_DISCON; 375 376 hd->scsi_pctl = 0; 377 hd->scsi_temp = (1 << target) | our_addr; 378 /* select timeout is hardcoded to 2ms */ 379 hd->scsi_tch = 0; 380 hd->scsi_tcm = 32; 381 hd->scsi_tcl = 4; 382 383 hd->scsi_scmd = SCMD_SELECT; 384 return (0); 385 } 386 387 static int 388 wait_for_select(hd) 389 volatile register struct scsidevice *hd; 390 { 391 u_char ints; 392 393 while ((ints = hd->scsi_ints) == 0) 394 DELAY(1); 395 hd->scsi_ints = ints; 396 return (!(hd->scsi_ssts & SSTS_INITIATOR)); 397 } 398 399 static int 400 ixfer_start(hd, len, phase, wait) 401 volatile register struct scsidevice *hd; 402 int len; 403 u_char phase; 404 register int wait; 405 { 406 407 hd->scsi_tch = len >> 16; 408 hd->scsi_tcm = len >> 8; 409 hd->scsi_tcl = len; 410 hd->scsi_pctl = phase; 411 hd->scsi_tmod = 0; /*XXX*/ 412 hd->scsi_scmd = SCMD_XFR | SCMD_PROG_XFR; 413 414 /* wait for xfer to start or svc_req interrupt */ 415 while ((hd->scsi_ssts & SSTS_BUSY) == 0) { 416 if (hd->scsi_ints || --wait < 0) { 417 #ifdef DEBUG 418 if (scsi_debug) 419 printf("ixfer_start fail: i%x, w%d\n", 420 hd->scsi_ints, wait); 421 #endif 422 HIST(ixstart_wait, wait) 423 return (0); 424 } 425 DELAY(1); 426 } 427 HIST(ixstart_wait, wait) 428 return (1); 429 } 430 431 static int 432 ixfer_out(hd, len, buf) 433 volatile register struct scsidevice *hd; 434 int len; 435 register u_char *buf; 436 { 437 register int wait = scsi_data_wait; 438 439 for (; len > 0; --len) { 440 while (hd->scsi_ssts & SSTS_DREG_FULL) { 441 if (hd->scsi_ints || --wait < 0) { 442 #ifdef DEBUG 443 if (scsi_debug) 444 printf("ixfer_out fail: l%d i%x w%d\n", 445 len, hd->scsi_ints, wait); 446 #endif 447 HIST(ixout_wait, wait) 448 return (len); 449 } 450 DELAY(1); 451 } 452 hd->scsi_dreg = *buf++; 453 } 454 HIST(ixout_wait, wait) 455 return (0); 456 } 457 458 static void 459 ixfer_in(hd, len, buf) 460 volatile register struct scsidevice *hd; 461 int len; 462 register u_char *buf; 463 { 464 register int wait = scsi_data_wait; 465 466 for (; len > 0; --len) { 467 while (hd->scsi_ssts & SSTS_DREG_EMPTY) { 468 if (hd->scsi_ints || --wait < 0) { 469 while (! (hd->scsi_ssts & SSTS_DREG_EMPTY)) { 470 *buf++ = hd->scsi_dreg; 471 --len; 472 } 473 #ifdef DEBUG 474 if (scsi_debug) 475 printf("ixfer_in fail: l%d i%x w%d\n", 476 len, hd->scsi_ints, wait); 477 #endif 478 HIST(ixin_wait, wait) 479 return; 480 } 481 DELAY(1); 482 } 483 *buf++ = hd->scsi_dreg; 484 } 485 HIST(ixin_wait, wait) 486 } 487 488 static int 489 mxfer_in(hd, len, buf, phase) 490 volatile register struct scsidevice *hd; 491 register int len; 492 register u_char *buf; 493 register u_char phase; 494 { 495 register int wait = scsi_cmd_wait; 496 register int i; 497 498 hd->scsi_tmod = 0; 499 for (i = 0; i < len; ++i) { 500 /* 501 * manual sez: reset ATN before ACK is sent. 502 */ 503 if (hd->scsi_psns & PSNS_ATN) 504 hd->scsi_scmd = SCMD_RST_ATN; 505 /* 506 * wait for the request line (which says the target 507 * wants to give us data). If the phase changes while 508 * we're waiting, we're done. 509 */ 510 while ((hd->scsi_psns & PSNS_REQ) == 0) { 511 if (--wait < 0) { 512 HIST(mxin_wait, wait) 513 return (-1); 514 } 515 if ((hd->scsi_psns & PHASE) != phase || 516 (hd->scsi_ssts & SSTS_INITIATOR) == 0) 517 goto out; 518 519 DELAY(1); 520 } 521 /* 522 * set ack (which says we're ready for the data, wait for 523 * req to go away (target says data is available), grab the 524 * data, then reset ack (say we've got the data). 525 */ 526 hd->scsi_pctl = phase; 527 hd->scsi_scmd = SCMD_SET_ACK; 528 while (hd->scsi_psns & PSNS_REQ) { 529 if (--wait < 0) { 530 HIST(mxin_wait, wait) 531 return (-2); 532 } 533 DELAY(1); 534 } 535 *buf++ = hd->scsi_temp; 536 hd->scsi_scmd = SCMD_RST_ACK; 537 } 538 out: 539 HIST(mxin_wait, wait) 540 /* 541 * Wait for manual transfer to finish. 542 * Avoids occasional "unexpected phase" errors in finishxfer 543 * formerly addressed by per-slave delays. 544 */ 545 wait = scsi_cmd_wait; 546 while ((hd->scsi_ssts & SSTS_ACTIVE) == SSTS_INITIATOR) { 547 if (--wait < 0) 548 break; 549 DELAY(1); 550 } 551 HIST(mxin2_wait, wait) 552 return (i); 553 } 554 555 /* 556 * SCSI 'immediate' command: issue a command to some SCSI device 557 * and get back an 'immediate' response (i.e., do programmed xfer 558 * to get the response data). 'cbuf' is a buffer containing a scsi 559 * command of length clen bytes. 'buf' is a buffer of length 'len' 560 * bytes for data. The transfer direction is determined by the device 561 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 562 * command must supply no data. 'xferphase' is the bus phase the 563 * caller expects to happen after the command is issued. It should 564 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 565 */ 566 static int 567 scsiicmd(hs, target, cbuf, clen, buf, len, xferphase) 568 struct scsi_softc *hs; 569 int target; 570 u_char *cbuf; 571 int clen; 572 u_char *buf; 573 int len; 574 u_char xferphase; 575 { 576 volatile register struct scsidevice *hd = 577 (struct scsidevice *)hs->sc_hc->hp_addr; 578 u_char phase, ints; 579 register int wait; 580 581 /* select the SCSI bus (it's an error if bus isn't free) */ 582 if (issue_select(hd, target, hs->sc_scsi_addr)) 583 return (-1); 584 if (wait_for_select(hd)) 585 return (-1); 586 /* 587 * Wait for a phase change (or error) then let the device 588 * sequence us through the various SCSI phases. 589 */ 590 hs->sc_stat[0] = 0xff; 591 hs->sc_msg[0] = 0xff; 592 phase = CMD_PHASE; 593 while (1) { 594 wait = scsi_cmd_wait; 595 switch (phase) { 596 597 case CMD_PHASE: 598 if (ixfer_start(hd, clen, phase, wait)) 599 if (ixfer_out(hd, clen, cbuf)) 600 goto abort; 601 phase = xferphase; 602 break; 603 604 case DATA_IN_PHASE: 605 if (len <= 0) 606 goto abort; 607 wait = scsi_data_wait; 608 if (ixfer_start(hd, len, phase, wait) || 609 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) 610 ixfer_in(hd, len, buf); 611 phase = STATUS_PHASE; 612 break; 613 614 case DATA_OUT_PHASE: 615 if (len <= 0) 616 goto abort; 617 wait = scsi_data_wait; 618 if (ixfer_start(hd, len, phase, wait)) { 619 if (ixfer_out(hd, len, buf)) 620 goto abort; 621 } 622 phase = STATUS_PHASE; 623 break; 624 625 case STATUS_PHASE: 626 wait = scsi_data_wait; 627 if (ixfer_start(hd, sizeof(hs->sc_stat), phase, wait) || 628 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) 629 ixfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat); 630 phase = MESG_IN_PHASE; 631 break; 632 633 case MESG_IN_PHASE: 634 if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait) || 635 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { 636 ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); 637 hd->scsi_scmd = SCMD_RST_ACK; 638 } 639 phase = BUS_FREE_PHASE; 640 break; 641 642 case BUS_FREE_PHASE: 643 goto out; 644 645 default: 646 printf("scsi%d: unexpected phase %d in icmd from %d\n", 647 hs->sc_hc->hp_unit, phase, target); 648 goto abort; 649 } 650 /* wait for last command to complete */ 651 while ((ints = hd->scsi_ints) == 0) { 652 if (--wait < 0) { 653 HIST(cxin_wait, wait) 654 goto abort; 655 } 656 DELAY(1); 657 } 658 HIST(cxin_wait, wait) 659 hd->scsi_ints = ints; 660 if (ints & INTS_SRV_REQ) 661 phase = hd->scsi_psns & PHASE; 662 else if (ints & INTS_DISCON) 663 goto out; 664 else if ((ints & INTS_CMD_DONE) == 0) { 665 scsierror(hs, hd, ints); 666 goto abort; 667 } 668 } 669 abort: 670 scsiabort(hs, hd, "icmd"); 671 out: 672 return (hs->sc_stat[0]); 673 } 674 675 /* 676 * Finish SCSI xfer command: After the completion interrupt from 677 * a read/write operation, sequence through the final phases in 678 * programmed i/o. This routine is a lot like scsiicmd except we 679 * skip (and don't allow) the select, cmd out and data in/out phases. 680 */ 681 static void 682 finishxfer(hs, hd, target) 683 struct scsi_softc *hs; 684 volatile register struct scsidevice *hd; 685 int target; 686 { 687 u_char phase, ints; 688 689 /* 690 * We specified padding xfer so we ended with either a phase 691 * change interrupt (normal case) or an error interrupt (handled 692 * elsewhere). Reset the board dma logic then try to get the 693 * completion status & command done msg. The reset confuses 694 * the SPC REQ/ACK logic so we have to do any status/msg input 695 * operations via 'manual xfer'. 696 */ 697 if (hd->scsi_ssts & SSTS_BUSY) { 698 int wait = scsi_cmd_wait; 699 700 /* wait for dma operation to finish */ 701 while (hd->scsi_ssts & SSTS_BUSY) { 702 if (--wait < 0) { 703 #ifdef DEBUG 704 if (scsi_debug) 705 printf("finishxfer fail: ssts %x\n", 706 hd->scsi_ssts); 707 #endif 708 HIST(fxfr_wait, wait) 709 goto abort; 710 } 711 } 712 HIST(fxfr_wait, wait) 713 } 714 hd->scsi_scmd |= SCMD_PROG_XFR; 715 hd->scsi_sctl |= SCTL_CTRLRST; 716 DELAY(1); 717 hd->scsi_sctl &=~ SCTL_CTRLRST; 718 hd->scsi_hconf = 0; 719 /* 720 * The following delay is definitely needed when trying to 721 * write on a write protected disk (in the optical jukebox anyways), 722 * but we shall see if other unexplained machine freezeups 723 * also stop occuring... A value of 5 seems to work but 724 * 10 seems safer considering the potential consequences. 725 */ 726 DELAY(10); 727 hs->sc_stat[0] = 0xff; 728 hs->sc_msg[0] = 0xff; 729 hd->scsi_csr = 0; 730 hd->scsi_ints = ints = hd->scsi_ints; 731 while (1) { 732 phase = hd->scsi_psns & PHASE; 733 switch (phase) { 734 735 case STATUS_PHASE: 736 if (mxfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat, 737 phase) <= 0) 738 goto abort; 739 break; 740 741 case MESG_IN_PHASE: 742 if (mxfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg, 743 phase) < 0) 744 goto abort; 745 break; 746 747 case BUS_FREE_PHASE: 748 return; 749 750 default: 751 printf("scsi%d: unexpected phase %d in finishxfer from %d\n", 752 hs->sc_hc->hp_unit, phase, target); 753 goto abort; 754 } 755 if (ints = hd->scsi_ints) { 756 hd->scsi_ints = ints; 757 if (ints & INTS_DISCON) 758 return; 759 else if (ints & ~(INTS_SRV_REQ|INTS_CMD_DONE)) { 760 scsierror(hs, hd, ints); 761 break; 762 } 763 } 764 if ((hd->scsi_ssts & SSTS_INITIATOR) == 0) 765 return; 766 } 767 abort: 768 scsiabort(hs, hd, "finishxfer"); 769 hs->sc_stat[0] = 0xfe; 770 } 771 772 int 773 scsi_test_unit_rdy(ctlr, slave, unit) 774 int ctlr, slave, unit; 775 { 776 register struct scsi_softc *hs = &scsi_softc[ctlr]; 777 static struct scsi_cdb6 cdb = { CMD_TEST_UNIT_READY }; 778 779 cdb.lun = unit; 780 return (scsiicmd(hs, slave, &cdb, sizeof(cdb), (u_char *)0, 0, 781 STATUS_PHASE)); 782 } 783 784 int 785 scsi_request_sense(ctlr, slave, unit, buf, len) 786 int ctlr, slave, unit; 787 u_char *buf; 788 unsigned len; 789 { 790 register struct scsi_softc *hs = &scsi_softc[ctlr]; 791 static struct scsi_cdb6 cdb = { CMD_REQUEST_SENSE }; 792 793 cdb.lun = unit; 794 cdb.len = len; 795 return (scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE)); 796 } 797 798 int 799 scsi_immed_command(ctlr, slave, unit, cdb, buf, len, rd) 800 int ctlr, slave, unit; 801 struct scsi_fmt_cdb *cdb; 802 u_char *buf; 803 unsigned len; 804 { 805 register struct scsi_softc *hs = &scsi_softc[ctlr]; 806 807 cdb->cdb[1] |= unit << 5; 808 return (scsiicmd(hs, slave, cdb->cdb, cdb->len, buf, len, 809 rd != 0? DATA_IN_PHASE : DATA_OUT_PHASE)); 810 } 811 812 /* 813 * The following routines are test-and-transfer i/o versions of read/write 814 * for things like reading disk labels and writing core dumps. The 815 * routine scsigo should be used for normal data transfers, NOT these 816 * routines. 817 */ 818 int 819 scsi_tt_read(ctlr, slave, unit, buf, len, blk, bshift) 820 int ctlr, slave, unit; 821 u_char *buf; 822 u_int len; 823 daddr_t blk; 824 int bshift; 825 { 826 register struct scsi_softc *hs = &scsi_softc[ctlr]; 827 struct scsi_cdb10 cdb; 828 int stat; 829 int old_wait = scsi_data_wait; 830 831 scsi_data_wait = 300000; 832 bzero(&cdb, sizeof(cdb)); 833 cdb.cmd = CMD_READ_EXT; 834 cdb.lun = unit; 835 blk >>= bshift; 836 cdb.lbah = blk >> 24; 837 cdb.lbahm = blk >> 16; 838 cdb.lbalm = blk >> 8; 839 cdb.lbal = blk; 840 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 841 cdb.lenl = len >> (DEV_BSHIFT + bshift); 842 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE); 843 scsi_data_wait = old_wait; 844 return (stat); 845 } 846 847 int 848 scsi_tt_write(ctlr, slave, unit, buf, len, blk, bshift) 849 int ctlr, slave, unit; 850 u_char *buf; 851 u_int len; 852 daddr_t blk; 853 int bshift; 854 { 855 register struct scsi_softc *hs = &scsi_softc[ctlr]; 856 struct scsi_cdb10 cdb; 857 int stat; 858 int old_wait = scsi_data_wait; 859 860 scsi_data_wait = 300000; 861 862 bzero(&cdb, sizeof(cdb)); 863 cdb.cmd = CMD_WRITE_EXT; 864 cdb.lun = unit; 865 blk >>= bshift; 866 cdb.lbah = blk >> 24; 867 cdb.lbahm = blk >> 16; 868 cdb.lbalm = blk >> 8; 869 cdb.lbal = blk; 870 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 871 cdb.lenl = len >> (DEV_BSHIFT + bshift); 872 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_OUT_PHASE); 873 scsi_data_wait = old_wait; 874 return (stat); 875 } 876 877 int 878 scsireq(dq) 879 register struct devqueue *dq; 880 { 881 register struct devqueue *hq; 882 883 hq = &scsi_softc[dq->dq_ctlr].sc_sq; 884 insque(dq, hq->dq_back); 885 if (dq->dq_back == hq) 886 return(1); 887 return(0); 888 } 889 890 int 891 scsiustart(unit) 892 int unit; 893 { 894 register struct scsi_softc *hs = &scsi_softc[unit]; 895 896 hs->sc_dq.dq_ctlr = DMA0 | DMA1; 897 hs->sc_flags |= SCSI_HAVEDMA; 898 if (dmareq(&hs->sc_dq)) 899 return(1); 900 return(0); 901 } 902 903 void 904 scsistart(unit) 905 int unit; 906 { 907 register struct devqueue *dq; 908 909 dq = scsi_softc[unit].sc_sq.dq_forw; 910 (dq->dq_driver->d_go)(dq->dq_unit); 911 } 912 913 int 914 scsigo(ctlr, slave, unit, bp, cdb, pad) 915 int ctlr, slave, unit; 916 struct buf *bp; 917 struct scsi_fmt_cdb *cdb; 918 int pad; 919 { 920 register struct scsi_softc *hs = &scsi_softc[ctlr]; 921 volatile register struct scsidevice *hd = 922 (struct scsidevice *)hs->sc_hc->hp_addr; 923 int i, dmaflags; 924 u_char phase, ints, cmd; 925 926 cdb->cdb[1] |= unit << 5; 927 928 /* select the SCSI bus (it's an error if bus isn't free) */ 929 if (issue_select(hd, slave, hs->sc_scsi_addr) || wait_for_select(hd)) { 930 if (hs->sc_flags & SCSI_HAVEDMA) { 931 hs->sc_flags &=~ SCSI_HAVEDMA; 932 dmafree(&hs->sc_dq); 933 } 934 return (1); 935 } 936 /* 937 * Wait for a phase change (or error) then let the device 938 * sequence us through command phase (we may have to take 939 * a msg in/out before doing the command). If the disk has 940 * to do a seek, it may be a long time until we get a change 941 * to data phase so, in the absense of an explicit phase 942 * change, we assume data phase will be coming up and tell 943 * the SPC to start a transfer whenever it does. We'll get 944 * a service required interrupt later if this assumption is 945 * wrong. Otherwise we'll get a service required int when 946 * the transfer changes to status phase. 947 */ 948 phase = CMD_PHASE; 949 while (1) { 950 register int wait = scsi_cmd_wait; 951 952 switch (phase) { 953 954 case CMD_PHASE: 955 if (ixfer_start(hd, cdb->len, phase, wait)) 956 if (ixfer_out(hd, cdb->len, cdb->cdb)) 957 goto abort; 958 break; 959 960 case MESG_IN_PHASE: 961 if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait)|| 962 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { 963 ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); 964 hd->scsi_scmd = SCMD_RST_ACK; 965 } 966 phase = BUS_FREE_PHASE; 967 break; 968 969 case DATA_IN_PHASE: 970 case DATA_OUT_PHASE: 971 goto out; 972 973 default: 974 printf("scsi%d: unexpected phase %d in go from %d\n", 975 hs->sc_hc->hp_unit, phase, slave); 976 goto abort; 977 } 978 while ((ints = hd->scsi_ints) == 0) { 979 if (--wait < 0) { 980 HIST(sgo_wait, wait) 981 goto abort; 982 } 983 DELAY(1); 984 } 985 HIST(sgo_wait, wait) 986 hd->scsi_ints = ints; 987 if (ints & INTS_SRV_REQ) 988 phase = hd->scsi_psns & PHASE; 989 else if (ints & INTS_CMD_DONE) 990 goto out; 991 else { 992 scsierror(hs, hd, ints); 993 goto abort; 994 } 995 } 996 out: 997 /* 998 * Reset the card dma logic, setup the dma channel then 999 * get the dio part of the card set for a dma xfer. 1000 */ 1001 hd->scsi_hconf = 0; 1002 cmd = CSR_IE; 1003 dmaflags = DMAGO_NOINT; 1004 if (scsi_pridma) 1005 dmaflags |= DMAGO_PRI; 1006 if (bp->b_flags & B_READ) 1007 dmaflags |= DMAGO_READ; 1008 if ((hs->sc_flags & SCSI_DMA32) && 1009 ((int)bp->b_un.b_addr & 3) == 0 && (bp->b_bcount & 3) == 0) { 1010 cmd |= CSR_DMA32; 1011 dmaflags |= DMAGO_LWORD; 1012 } else 1013 dmaflags |= DMAGO_WORD; 1014 dmago(hs->sc_dq.dq_ctlr, bp->b_un.b_addr, bp->b_bcount, dmaflags); 1015 1016 if (bp->b_flags & B_READ) { 1017 cmd |= CSR_DMAIN; 1018 phase = DATA_IN_PHASE; 1019 } else 1020 phase = DATA_OUT_PHASE; 1021 /* 1022 * DMA enable bits must be set after size and direction bits. 1023 */ 1024 hd->scsi_csr = cmd; 1025 hd->scsi_csr |= (CSR_DE0 << hs->sc_dq.dq_ctlr); 1026 /* 1027 * Setup the SPC for the transfer. We don't want to take 1028 * first a command complete then a service required interrupt 1029 * at the end of the transfer so we try to disable the cmd 1030 * complete by setting the transfer counter to more bytes 1031 * than we expect. (XXX - This strategy may have to be 1032 * modified to deal with devices that return variable length 1033 * blocks, e.g., some tape drives.) 1034 */ 1035 cmd = SCMD_XFR; 1036 i = (unsigned)bp->b_bcount; 1037 if (pad) { 1038 cmd |= SCMD_PAD; 1039 /* 1040 * XXX - If we don't do this, the last 2 or 4 bytes 1041 * (depending on word/lword DMA) of a read get trashed. 1042 * It looks like it is necessary for the DMA to complete 1043 * before the SPC goes into "pad mode"??? Note: if we 1044 * also do this on a write, the request never completes. 1045 */ 1046 if (bp->b_flags & B_READ) 1047 i += 2; 1048 #ifdef DEBUG 1049 hs->sc_flags |= SCSI_PAD; 1050 if (i & 1) 1051 printf("scsi%d: odd byte count: %d bytes @ %d\n", 1052 ctlr, i, bp->b_cylin); 1053 #endif 1054 } else 1055 i += 4; 1056 hd->scsi_tch = i >> 16; 1057 hd->scsi_tcm = i >> 8; 1058 hd->scsi_tcl = i; 1059 hd->scsi_pctl = phase; 1060 hd->scsi_tmod = 0; 1061 hd->scsi_scmd = cmd; 1062 hs->sc_flags |= SCSI_IO; 1063 return (0); 1064 abort: 1065 scsiabort(hs, hd, "go"); 1066 hs->sc_flags &=~ SCSI_HAVEDMA; 1067 dmafree(&hs->sc_dq); 1068 return (1); 1069 } 1070 1071 void 1072 scsidone(unit) 1073 register int unit; 1074 { 1075 volatile register struct scsidevice *hd = 1076 (struct scsidevice *)scsi_softc[unit].sc_hc->hp_addr; 1077 1078 #ifdef DEBUG 1079 if (scsi_debug) 1080 printf("scsi%d: done called!\n"); 1081 #endif 1082 /* dma operation is done -- turn off card dma */ 1083 hd->scsi_csr &=~ (CSR_DE1|CSR_DE0); 1084 } 1085 1086 int 1087 scsiintr(unit) 1088 register int unit; 1089 { 1090 register struct scsi_softc *hs = &scsi_softc[unit]; 1091 volatile register struct scsidevice *hd = 1092 (struct scsidevice *)hs->sc_hc->hp_addr; 1093 register u_char ints; 1094 register struct devqueue *dq; 1095 1096 if ((hd->scsi_csr & (CSR_IE|CSR_IR)) != (CSR_IE|CSR_IR)) 1097 return (0); 1098 1099 ints = hd->scsi_ints; 1100 if ((ints & INTS_SRV_REQ) && (hs->sc_flags & SCSI_IO)) { 1101 /* 1102 * this should be the normal i/o completion case. 1103 * get the status & cmd complete msg then let the 1104 * device driver look at what happened. 1105 */ 1106 #ifdef DEBUG 1107 int len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | 1108 hd->scsi_tcl; 1109 if (!(hs->sc_flags & SCSI_PAD)) 1110 len -= 4; 1111 hs->sc_flags &=~ SCSI_PAD; 1112 #endif 1113 dq = hs->sc_sq.dq_forw; 1114 finishxfer(hs, hd, dq->dq_slave); 1115 hs->sc_flags &=~ (SCSI_IO|SCSI_HAVEDMA); 1116 dmafree(&hs->sc_dq); 1117 (dq->dq_driver->d_intr)(dq->dq_unit, hs->sc_stat[0]); 1118 } else { 1119 /* Something unexpected happened -- deal with it. */ 1120 hd->scsi_ints = ints; 1121 hd->scsi_csr = 0; 1122 scsierror(hs, hd, ints); 1123 scsiabort(hs, hd, "intr"); 1124 if (hs->sc_flags & SCSI_IO) { 1125 hs->sc_flags &=~ (SCSI_IO|SCSI_HAVEDMA); 1126 dmafree(&hs->sc_dq); 1127 dq = hs->sc_sq.dq_forw; 1128 (dq->dq_driver->d_intr)(dq->dq_unit, -1); 1129 } 1130 } 1131 return(1); 1132 } 1133 1134 void 1135 scsifree(dq) 1136 register struct devqueue *dq; 1137 { 1138 register struct devqueue *hq; 1139 1140 hq = &scsi_softc[dq->dq_ctlr].sc_sq; 1141 remque(dq); 1142 if ((dq = hq->dq_forw) != hq) 1143 (dq->dq_driver->d_start)(dq->dq_unit); 1144 } 1145 1146 /* 1147 * (XXX) The following routine is needed for the SCSI tape driver 1148 * to read odd-size records. 1149 */ 1150 1151 #include "st.h" 1152 #if NST > 0 1153 int 1154 scsi_tt_oddio(ctlr, slave, unit, buf, len, b_flags, freedma) 1155 int ctlr, slave, unit, b_flags; 1156 u_char *buf; 1157 u_int len; 1158 { 1159 register struct scsi_softc *hs = &scsi_softc[ctlr]; 1160 struct scsi_cdb6 cdb; 1161 u_char iphase; 1162 int stat; 1163 1164 #ifdef DEBUG 1165 if (freedma && (hs->sc_flags & SCSI_HAVEDMA) == 0 || 1166 !freedma && (hs->sc_flags & SCSI_HAVEDMA)) 1167 printf("oddio: freedma (%d) inconsistency (flags=%x)\n", 1168 freedma, hs->sc_flags); 1169 #endif 1170 /* 1171 * First free any DMA channel that was allocated. 1172 * We can't use DMA to do this transfer. 1173 */ 1174 if (freedma) { 1175 hs->sc_flags &=~ SCSI_HAVEDMA; 1176 dmafree(hs->sc_dq); 1177 } 1178 /* 1179 * Initialize command block 1180 */ 1181 bzero(&cdb, sizeof(cdb)); 1182 cdb.lun = unit; 1183 cdb.lbam = (len >> 16) & 0xff; 1184 cdb.lbal = (len >> 8) & 0xff; 1185 cdb.len = len & 0xff; 1186 if (buf == 0) { 1187 cdb.cmd = CMD_SPACE; 1188 cdb.lun |= 0x00; 1189 len = 0; 1190 iphase = MESG_IN_PHASE; 1191 } else if (b_flags & B_READ) { 1192 cdb.cmd = CMD_READ; 1193 iphase = DATA_IN_PHASE; 1194 } else { 1195 cdb.cmd = CMD_WRITE; 1196 iphase = DATA_OUT_PHASE; 1197 } 1198 /* 1199 * Perform command (with very long delays) 1200 */ 1201 scsi_delay(30000000); 1202 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, iphase); 1203 scsi_delay(0); 1204 return (stat); 1205 } 1206 #endif 1207 #endif 1208