1 #ifndef DEBUG 2 #define DEBUG 3 #endif 4 /* 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * %sccs.include.redist.c% 12 * 13 * @(#)scsi.c 7.6 (Berkeley) 03/19/92 14 */ 15 16 /* 17 * HP9000/3xx 98658 SCSI host adaptor driver. 18 */ 19 #include "scsi.h" 20 #if NSCSI > 0 21 22 #ifndef lint 23 static char rcsid[] = "$Header: scsi.c,v 1.4 91/01/17 12:50:18 mike Exp $"; 24 #endif 25 26 #include "sys/param.h" 27 #include "sys/systm.h" 28 #include "sys/buf.h" 29 #include "device.h" 30 31 #include "scsivar.h" 32 #include "scsireg.h" 33 #include "dmavar.h" 34 35 #include "../include/cpu.h" 36 #include "../hp300/isr.h" 37 38 /* 39 * SCSI delays 40 * In u-seconds, primarily for state changes on the SPC. 41 */ 42 #define SCSI_CMD_WAIT 1000 /* wait per step of 'immediate' cmds */ 43 #define SCSI_DATA_WAIT 1000 /* wait per data in/out step */ 44 #define SCSI_INIT_WAIT 50000 /* wait per step (both) during init */ 45 46 extern void isrlink(); 47 extern void _insque(); 48 extern void _remque(); 49 50 int scsiinit(), scsigo(), scsiintr(), scsixfer(); 51 void scsistart(), scsidone(), scsifree(), scsireset(); 52 struct driver scsidriver = { 53 scsiinit, "scsi", (int (*)())scsistart, scsigo, scsiintr, 54 (int (*)())scsidone, 55 }; 56 57 struct scsi_softc scsi_softc[NSCSI]; 58 struct isr scsi_isr[NSCSI]; 59 60 int scsi_cmd_wait = SCSI_CMD_WAIT; 61 int scsi_data_wait = SCSI_DATA_WAIT; 62 int scsi_init_wait = SCSI_INIT_WAIT; 63 64 int scsi_nosync = 1; /* inhibit sync xfers if 1 */ 65 int scsi_pridma = 0; /* use "priority" dma */ 66 67 #ifdef DEBUG 68 int scsi_debug = 0; 69 #define WAITHIST 70 #endif 71 72 #ifdef WAITHIST 73 #define MAXWAIT 1022 74 u_int ixstart_wait[MAXWAIT+2]; 75 u_int ixin_wait[MAXWAIT+2]; 76 u_int ixout_wait[MAXWAIT+2]; 77 u_int mxin_wait[MAXWAIT+2]; 78 u_int mxin2_wait[MAXWAIT+2]; 79 u_int cxin_wait[MAXWAIT+2]; 80 u_int fxfr_wait[MAXWAIT+2]; 81 u_int sgo_wait[MAXWAIT+2]; 82 #define HIST(h,w) (++h[((w)>MAXWAIT? MAXWAIT : ((w) < 0 ? -1 : (w))) + 1]); 83 #else 84 #define HIST(h,w) 85 #endif 86 87 #define b_cylin b_resid 88 89 static void 90 scsiabort(hs, hd, where) 91 register struct scsi_softc *hs; 92 volatile register struct scsidevice *hd; 93 char *where; 94 { 95 int len; 96 int maxtries; /* XXX - kludge till I understand whats *supposed* to happen */ 97 int startlen; /* XXX - kludge till I understand whats *supposed* to happen */ 98 u_char junk; 99 100 printf("scsi%d: abort from %s: phase=0x%x, ssts=0x%x, ints=0x%x\n", 101 hs->sc_hc->hp_unit, where, hd->scsi_psns, hd->scsi_ssts, 102 hd->scsi_ints); 103 104 hd->scsi_ints = hd->scsi_ints; 105 hd->scsi_csr = 0; 106 if (hd->scsi_psns == 0 || (hd->scsi_ssts & SSTS_INITIATOR) == 0) 107 /* no longer connected to scsi target */ 108 return; 109 110 /* get the number of bytes remaining in current xfer + fudge */ 111 len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | hd->scsi_tcl; 112 113 /* for that many bus cycles, try to send an abort msg */ 114 for (startlen = (len += 1024); (hd->scsi_ssts & SSTS_INITIATOR) && --len >= 0; ) { 115 hd->scsi_scmd = SCMD_SET_ATN; 116 maxtries = 1000; 117 while ((hd->scsi_psns & PSNS_REQ) == 0) { 118 if (! (hd->scsi_ssts & SSTS_INITIATOR)) 119 goto out; 120 DELAY(1); 121 if (--maxtries == 0) { 122 printf("-- scsiabort gave up after 1000 tries (startlen = %d len = %d)\n", 123 startlen, len); 124 goto out2; 125 } 126 127 } 128 out2: 129 if ((hd->scsi_psns & PHASE) == MESG_OUT_PHASE) 130 hd->scsi_scmd = SCMD_RST_ATN; 131 hd->scsi_pctl = hd->scsi_psns & PHASE; 132 if (hd->scsi_psns & PHASE_IO) { 133 /* one of the input phases - read & discard a byte */ 134 hd->scsi_scmd = SCMD_SET_ACK; 135 if (hd->scsi_tmod == 0) 136 while (hd->scsi_psns & PSNS_REQ) 137 DELAY(1); 138 junk = hd->scsi_temp; 139 } else { 140 /* one of the output phases - send an abort msg */ 141 hd->scsi_temp = MSG_ABORT; 142 hd->scsi_scmd = SCMD_SET_ACK; 143 if (hd->scsi_tmod == 0) 144 while (hd->scsi_psns & PSNS_REQ) 145 DELAY(1); 146 } 147 hd->scsi_scmd = SCMD_RST_ACK; 148 } 149 out: 150 /* 151 * Either the abort was successful & the bus is disconnected or 152 * the device didn't listen. If the latter, announce the problem. 153 * Either way, reset the card & the SPC. 154 */ 155 if (len < 0 && hs) 156 printf("scsi%d: abort failed. phase=0x%x, ssts=0x%x\n", 157 hs->sc_hc->hp_unit, hd->scsi_psns, hd->scsi_ssts); 158 159 if (! ((junk = hd->scsi_ints) & INTS_RESEL)) { 160 hd->scsi_sctl |= SCTL_CTRLRST; 161 DELAY(1); 162 hd->scsi_sctl &=~ SCTL_CTRLRST; 163 hd->scsi_hconf = 0; 164 hd->scsi_ints = hd->scsi_ints; 165 } 166 } 167 168 /* 169 * XXX Set/reset long delays. 170 * 171 * if delay == 0, reset default delays 172 * if delay < 0, set both delays to default long initialization values 173 * if delay > 0, set both delays to this value 174 * 175 * Used when a devices is expected to respond slowly (e.g. during 176 * initialization). 177 */ 178 void 179 scsi_delay(delay) 180 int delay; 181 { 182 static int saved_cmd_wait, saved_data_wait; 183 184 if (delay) { 185 saved_cmd_wait = scsi_cmd_wait; 186 saved_data_wait = scsi_data_wait; 187 if (delay > 0) 188 scsi_cmd_wait = scsi_data_wait = delay; 189 else 190 scsi_cmd_wait = scsi_data_wait = scsi_init_wait; 191 } else { 192 scsi_cmd_wait = saved_cmd_wait; 193 scsi_data_wait = saved_data_wait; 194 } 195 } 196 197 int 198 scsiinit(hc) 199 register struct hp_ctlr *hc; 200 { 201 register struct scsi_softc *hs = &scsi_softc[hc->hp_unit]; 202 register struct scsidevice *hd = (struct scsidevice *)hc->hp_addr; 203 204 if ((hd->scsi_id & ID_MASK) != SCSI_ID) 205 return(0); 206 hc->hp_ipl = SCSI_IPL(hd->scsi_csr); 207 hs->sc_hc = hc; 208 hs->sc_dq.dq_unit = hc->hp_unit; 209 hs->sc_dq.dq_driver = &scsidriver; 210 hs->sc_sq.dq_forw = hs->sc_sq.dq_back = &hs->sc_sq; 211 scsi_isr[hc->hp_unit].isr_intr = scsiintr; 212 scsi_isr[hc->hp_unit].isr_ipl = hc->hp_ipl; 213 scsi_isr[hc->hp_unit].isr_arg = hc->hp_unit; 214 isrlink(&scsi_isr[hc->hp_unit]); 215 scsireset(hc->hp_unit); 216 return(1); 217 } 218 219 void 220 scsireset(unit) 221 register int unit; 222 { 223 register struct scsi_softc *hs = &scsi_softc[unit]; 224 volatile register struct scsidevice *hd = 225 (struct scsidevice *)hs->sc_hc->hp_addr; 226 u_int i; 227 228 if (hs->sc_flags & SCSI_ALIVE) 229 scsiabort(hs, hd, "reset"); 230 231 printf("scsi%d: ", unit); 232 233 hd->scsi_id = 0xFF; 234 DELAY(100); 235 /* 236 * Disable interrupts then reset the FUJI chip. 237 */ 238 hd->scsi_csr = 0; 239 hd->scsi_sctl = SCTL_DISABLE | SCTL_CTRLRST; 240 hd->scsi_scmd = 0; 241 hd->scsi_tmod = 0; 242 hd->scsi_pctl = 0; 243 hd->scsi_temp = 0; 244 hd->scsi_tch = 0; 245 hd->scsi_tcm = 0; 246 hd->scsi_tcl = 0; 247 hd->scsi_ints = 0; 248 249 if ((hd->scsi_id & ID_WORD_DMA) == 0) { 250 hs->sc_flags |= SCSI_DMA32; 251 printf("32 bit dma, "); 252 } 253 254 /* Determine Max Synchronous Transfer Rate */ 255 if (scsi_nosync) 256 i = 3; 257 else 258 i = SCSI_SYNC_XFER(hd->scsi_hconf); 259 switch (i) { 260 case 0: 261 hs->sc_sync = TMOD_SYNC | 0x3e; /* 250 nsecs */ 262 printf("250ns sync"); 263 break; 264 case 1: 265 hs->sc_sync = TMOD_SYNC | 0x5e; /* 375 nsecs */ 266 printf("375ns sync"); 267 break; 268 case 2: 269 hs->sc_sync = TMOD_SYNC | 0x7d; /* 500 nsecs */ 270 printf("500ns sync"); 271 break; 272 case 3: 273 hs->sc_sync = 0; 274 printf("async"); 275 break; 276 } 277 278 /* 279 * Configure the FUJI chip with its SCSI address, all 280 * interrupts enabled & appropriate parity. 281 */ 282 i = (~hd->scsi_hconf) & 0x7; 283 hs->sc_scsi_addr = 1 << i; 284 hd->scsi_bdid = i; 285 if (hd->scsi_hconf & HCONF_PARITY) 286 hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | 287 SCTL_SEL_ENAB | SCTL_RESEL_ENAB | 288 SCTL_INTR_ENAB | SCTL_PARITY_ENAB; 289 else { 290 hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | 291 SCTL_SEL_ENAB | SCTL_RESEL_ENAB | 292 SCTL_INTR_ENAB; 293 printf(", no parity"); 294 } 295 hd->scsi_sctl &=~ SCTL_DISABLE; 296 297 printf(", scsi id %d\n", i); 298 hs->sc_flags |= SCSI_ALIVE; 299 } 300 301 static void 302 scsierror(hs, hd, ints) 303 register struct scsi_softc *hs; 304 volatile register struct scsidevice *hd; 305 u_char ints; 306 { 307 int unit = hs->sc_hc->hp_unit; 308 char *sep = ""; 309 310 printf("scsi%d: ", unit); 311 if (ints & INTS_RST) { 312 DELAY(100); 313 if (hd->scsi_hconf & HCONF_SD) 314 printf("spurious RST interrupt"); 315 else 316 printf("hardware error - check fuse"); 317 sep = ", "; 318 } 319 if ((ints & INTS_HARD_ERR) || hd->scsi_serr) { 320 if (hd->scsi_serr & SERR_SCSI_PAR) { 321 printf("%sparity err", sep); 322 sep = ", "; 323 } 324 if (hd->scsi_serr & SERR_SPC_PAR) { 325 printf("%sSPC parity err", sep); 326 sep = ", "; 327 } 328 if (hd->scsi_serr & SERR_TC_PAR) { 329 printf("%sTC parity err", sep); 330 sep = ", "; 331 } 332 if (hd->scsi_serr & SERR_PHASE_ERR) { 333 printf("%sphase err", sep); 334 sep = ", "; 335 } 336 if (hd->scsi_serr & SERR_SHORT_XFR) { 337 printf("%ssync short transfer err", sep); 338 sep = ", "; 339 } 340 if (hd->scsi_serr & SERR_OFFSET) { 341 printf("%ssync offset error", sep); 342 sep = ", "; 343 } 344 } 345 if (ints & INTS_TIMEOUT) 346 printf("%sSPC select timeout error", sep); 347 if (ints & INTS_SRV_REQ) 348 printf("%sspurious SRV_REQ interrupt", sep); 349 if (ints & INTS_CMD_DONE) 350 printf("%sspurious CMD_DONE interrupt", sep); 351 if (ints & INTS_DISCON) 352 printf("%sspurious disconnect interrupt", sep); 353 if (ints & INTS_RESEL) 354 printf("%sspurious reselect interrupt", sep); 355 if (ints & INTS_SEL) 356 printf("%sspurious select interrupt", sep); 357 printf("\n"); 358 } 359 360 static int 361 issue_select(hd, target, our_addr) 362 volatile register struct scsidevice *hd; 363 u_char target, our_addr; 364 { 365 if (hd->scsi_ssts & (SSTS_INITIATOR|SSTS_TARGET|SSTS_BUSY)) 366 return (1); 367 368 if (hd->scsi_ints & INTS_DISCON) 369 hd->scsi_ints = INTS_DISCON; 370 371 hd->scsi_pctl = 0; 372 hd->scsi_temp = (1 << target) | our_addr; 373 /* select timeout is hardcoded to 2ms */ 374 hd->scsi_tch = 0; 375 hd->scsi_tcm = 32; 376 hd->scsi_tcl = 4; 377 378 hd->scsi_scmd = SCMD_SELECT; 379 return (0); 380 } 381 382 static int 383 wait_for_select(hd) 384 volatile register struct scsidevice *hd; 385 { 386 u_char ints; 387 388 while ((ints = hd->scsi_ints) == 0) 389 DELAY(1); 390 hd->scsi_ints = ints; 391 return (!(hd->scsi_ssts & SSTS_INITIATOR)); 392 } 393 394 static int 395 ixfer_start(hd, len, phase, wait) 396 volatile register struct scsidevice *hd; 397 int len; 398 u_char phase; 399 register int wait; 400 { 401 402 hd->scsi_tch = len >> 16; 403 hd->scsi_tcm = len >> 8; 404 hd->scsi_tcl = len; 405 hd->scsi_pctl = phase; 406 hd->scsi_tmod = 0; /*XXX*/ 407 hd->scsi_scmd = SCMD_XFR | SCMD_PROG_XFR; 408 409 /* wait for xfer to start or svc_req interrupt */ 410 while ((hd->scsi_ssts & SSTS_BUSY) == 0) { 411 if (hd->scsi_ints || --wait < 0) { 412 #ifdef DEBUG 413 if (scsi_debug) 414 printf("ixfer_start fail: i%x, w%d\n", 415 hd->scsi_ints, wait); 416 #endif 417 HIST(ixstart_wait, wait) 418 return (0); 419 } 420 DELAY(1); 421 } 422 HIST(ixstart_wait, wait) 423 return (1); 424 } 425 426 static int 427 ixfer_out(hd, len, buf) 428 volatile register struct scsidevice *hd; 429 int len; 430 register u_char *buf; 431 { 432 register int wait = scsi_data_wait; 433 434 for (; len > 0; --len) { 435 while (hd->scsi_ssts & SSTS_DREG_FULL) { 436 if (hd->scsi_ints || --wait < 0) { 437 #ifdef DEBUG 438 if (scsi_debug) 439 printf("ixfer_out fail: l%d i%x w%d\n", 440 len, hd->scsi_ints, wait); 441 #endif 442 HIST(ixout_wait, wait) 443 return (len); 444 } 445 DELAY(1); 446 } 447 hd->scsi_dreg = *buf++; 448 } 449 HIST(ixout_wait, wait) 450 return (0); 451 } 452 453 static void 454 ixfer_in(hd, len, buf) 455 volatile register struct scsidevice *hd; 456 int len; 457 register u_char *buf; 458 { 459 register int wait = scsi_data_wait; 460 461 for (; len > 0; --len) { 462 while (hd->scsi_ssts & SSTS_DREG_EMPTY) { 463 if (hd->scsi_ints || --wait < 0) { 464 while (! (hd->scsi_ssts & SSTS_DREG_EMPTY)) { 465 *buf++ = hd->scsi_dreg; 466 --len; 467 } 468 #ifdef DEBUG 469 if (scsi_debug) 470 printf("ixfer_in fail: l%d i%x w%d\n", 471 len, hd->scsi_ints, wait); 472 #endif 473 HIST(ixin_wait, wait) 474 return; 475 } 476 DELAY(1); 477 } 478 *buf++ = hd->scsi_dreg; 479 } 480 HIST(ixin_wait, wait) 481 } 482 483 static int 484 mxfer_in(hd, len, buf, phase) 485 volatile register struct scsidevice *hd; 486 register int len; 487 register u_char *buf; 488 register u_char phase; 489 { 490 register int wait = scsi_cmd_wait; 491 register int i; 492 493 hd->scsi_tmod = 0; 494 for (i = 0; i < len; ++i) { 495 /* 496 * manual sez: reset ATN before ACK is sent. 497 */ 498 if (hd->scsi_psns & PSNS_ATN) 499 hd->scsi_scmd = SCMD_RST_ATN; 500 /* 501 * wait for the request line (which says the target 502 * wants to give us data). If the phase changes while 503 * we're waiting, we're done. 504 */ 505 while ((hd->scsi_psns & PSNS_REQ) == 0) { 506 if (--wait < 0) { 507 HIST(mxin_wait, wait) 508 return (-1); 509 } 510 if ((hd->scsi_psns & PHASE) != phase || 511 (hd->scsi_ssts & SSTS_INITIATOR) == 0) 512 goto out; 513 514 DELAY(1); 515 } 516 /* 517 * set ack (which says we're ready for the data, wait for 518 * req to go away (target says data is available), grab the 519 * data, then reset ack (say we've got the data). 520 */ 521 hd->scsi_pctl = phase; 522 hd->scsi_scmd = SCMD_SET_ACK; 523 while (hd->scsi_psns & PSNS_REQ) { 524 if (--wait < 0) { 525 HIST(mxin_wait, wait) 526 return (-2); 527 } 528 DELAY(1); 529 } 530 *buf++ = hd->scsi_temp; 531 hd->scsi_scmd = SCMD_RST_ACK; 532 } 533 out: 534 HIST(mxin_wait, wait) 535 /* 536 * Wait for manual transfer to finish. 537 * Avoids occasional "unexpected phase" errors in finishxfer 538 * formerly addressed by per-slave delays. 539 */ 540 wait = scsi_cmd_wait; 541 while ((hd->scsi_ssts & SSTS_ACTIVE) == SSTS_INITIATOR) { 542 if (--wait < 0) 543 break; 544 DELAY(1); 545 } 546 HIST(mxin2_wait, wait) 547 return (i); 548 } 549 550 /* 551 * SCSI 'immediate' command: issue a command to some SCSI device 552 * and get back an 'immediate' response (i.e., do programmed xfer 553 * to get the response data). 'cbuf' is a buffer containing a scsi 554 * command of length clen bytes. 'buf' is a buffer of length 'len' 555 * bytes for data. The transfer direction is determined by the device 556 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 557 * command must supply no data. 'xferphase' is the bus phase the 558 * caller expects to happen after the command is issued. It should 559 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 560 */ 561 static int 562 scsiicmd(hs, target, cbuf, clen, buf, len, xferphase) 563 struct scsi_softc *hs; 564 int target; 565 u_char *cbuf; 566 int clen; 567 u_char *buf; 568 int len; 569 u_char xferphase; 570 { 571 volatile register struct scsidevice *hd = 572 (struct scsidevice *)hs->sc_hc->hp_addr; 573 u_char phase, ints; 574 register int wait; 575 576 /* select the SCSI bus (it's an error if bus isn't free) */ 577 if (issue_select(hd, target, hs->sc_scsi_addr)) 578 return (-1); 579 if (wait_for_select(hd)) 580 return (-1); 581 /* 582 * Wait for a phase change (or error) then let the device 583 * sequence us through the various SCSI phases. 584 */ 585 hs->sc_stat[0] = 0xff; 586 hs->sc_msg[0] = 0xff; 587 phase = CMD_PHASE; 588 while (1) { 589 wait = scsi_cmd_wait; 590 switch (phase) { 591 592 case CMD_PHASE: 593 if (ixfer_start(hd, clen, phase, wait)) 594 if (ixfer_out(hd, clen, cbuf)) 595 goto abort; 596 phase = xferphase; 597 break; 598 599 case DATA_IN_PHASE: 600 if (len <= 0) 601 goto abort; 602 wait = scsi_data_wait; 603 if (ixfer_start(hd, len, phase, wait) || 604 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) 605 ixfer_in(hd, len, buf); 606 phase = STATUS_PHASE; 607 break; 608 609 case DATA_OUT_PHASE: 610 if (len <= 0) 611 goto abort; 612 wait = scsi_data_wait; 613 if (ixfer_start(hd, len, phase, wait)) { 614 if (ixfer_out(hd, len, buf)) 615 goto abort; 616 } 617 phase = STATUS_PHASE; 618 break; 619 620 case STATUS_PHASE: 621 wait = scsi_data_wait; 622 if (ixfer_start(hd, sizeof(hs->sc_stat), phase, wait) || 623 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) 624 ixfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat); 625 phase = MESG_IN_PHASE; 626 break; 627 628 case MESG_IN_PHASE: 629 if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait) || 630 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { 631 ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); 632 hd->scsi_scmd = SCMD_RST_ACK; 633 } 634 phase = BUS_FREE_PHASE; 635 break; 636 637 case BUS_FREE_PHASE: 638 goto out; 639 640 default: 641 printf("scsi%d: unexpected phase %d in icmd from %d\n", 642 hs->sc_hc->hp_unit, phase, target); 643 goto abort; 644 } 645 /* wait for last command to complete */ 646 while ((ints = hd->scsi_ints) == 0) { 647 if (--wait < 0) { 648 HIST(cxin_wait, wait) 649 goto abort; 650 } 651 DELAY(1); 652 } 653 HIST(cxin_wait, wait) 654 hd->scsi_ints = ints; 655 if (ints & INTS_SRV_REQ) 656 phase = hd->scsi_psns & PHASE; 657 else if (ints & INTS_DISCON) 658 goto out; 659 else if ((ints & INTS_CMD_DONE) == 0) { 660 scsierror(hs, hd, ints); 661 goto abort; 662 } 663 } 664 abort: 665 scsiabort(hs, hd, "icmd"); 666 out: 667 return (hs->sc_stat[0]); 668 } 669 670 /* 671 * Finish SCSI xfer command: After the completion interrupt from 672 * a read/write operation, sequence through the final phases in 673 * programmed i/o. This routine is a lot like scsiicmd except we 674 * skip (and don't allow) the select, cmd out and data in/out phases. 675 */ 676 static void 677 finishxfer(hs, hd, target) 678 struct scsi_softc *hs; 679 volatile register struct scsidevice *hd; 680 int target; 681 { 682 u_char phase, ints; 683 684 /* 685 * We specified padding xfer so we ended with either a phase 686 * change interrupt (normal case) or an error interrupt (handled 687 * elsewhere). Reset the board dma logic then try to get the 688 * completion status & command done msg. The reset confuses 689 * the SPC REQ/ACK logic so we have to do any status/msg input 690 * operations via 'manual xfer'. 691 */ 692 if (hd->scsi_ssts & SSTS_BUSY) { 693 int wait = scsi_cmd_wait; 694 695 /* wait for dma operation to finish */ 696 while (hd->scsi_ssts & SSTS_BUSY) { 697 if (--wait < 0) { 698 #ifdef DEBUG 699 if (scsi_debug) 700 printf("finishxfer fail: ssts %x\n", 701 hd->scsi_ssts); 702 #endif 703 HIST(fxfr_wait, wait) 704 goto abort; 705 } 706 } 707 HIST(fxfr_wait, wait) 708 } 709 hd->scsi_scmd |= SCMD_PROG_XFR; 710 hd->scsi_sctl |= SCTL_CTRLRST; 711 DELAY(1); 712 hd->scsi_sctl &=~ SCTL_CTRLRST; 713 hd->scsi_hconf = 0; 714 /* 715 * The following delay is definitely needed when trying to 716 * write on a write protected disk (in the optical jukebox anyways), 717 * but we shall see if other unexplained machine freezeups 718 * also stop occuring... A value of 5 seems to work but 719 * 10 seems safer considering the potential consequences. 720 */ 721 DELAY(10); 722 hs->sc_stat[0] = 0xff; 723 hs->sc_msg[0] = 0xff; 724 hd->scsi_csr = 0; 725 hd->scsi_ints = ints = hd->scsi_ints; 726 while (1) { 727 phase = hd->scsi_psns & PHASE; 728 switch (phase) { 729 730 case STATUS_PHASE: 731 if (mxfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat, 732 phase) <= 0) 733 goto abort; 734 break; 735 736 case MESG_IN_PHASE: 737 if (mxfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg, 738 phase) < 0) 739 goto abort; 740 break; 741 742 case BUS_FREE_PHASE: 743 return; 744 745 default: 746 printf("scsi%d: unexpected phase %d in finishxfer from %d\n", 747 hs->sc_hc->hp_unit, phase, target); 748 goto abort; 749 } 750 if (ints = hd->scsi_ints) { 751 hd->scsi_ints = ints; 752 if (ints & INTS_DISCON) 753 return; 754 else if (ints & ~(INTS_SRV_REQ|INTS_CMD_DONE)) { 755 scsierror(hs, hd, ints); 756 break; 757 } 758 } 759 if ((hd->scsi_ssts & SSTS_INITIATOR) == 0) 760 return; 761 } 762 abort: 763 scsiabort(hs, hd, "finishxfer"); 764 hs->sc_stat[0] = 0xfe; 765 } 766 767 int 768 scsi_test_unit_rdy(ctlr, slave, unit) 769 int ctlr, slave, unit; 770 { 771 register struct scsi_softc *hs = &scsi_softc[ctlr]; 772 static struct scsi_cdb6 cdb = { CMD_TEST_UNIT_READY }; 773 774 cdb.lun = unit; 775 return (scsiicmd(hs, slave, &cdb, sizeof(cdb), (u_char *)0, 0, 776 STATUS_PHASE)); 777 } 778 779 int 780 scsi_request_sense(ctlr, slave, unit, buf, len) 781 int ctlr, slave, unit; 782 u_char *buf; 783 unsigned len; 784 { 785 register struct scsi_softc *hs = &scsi_softc[ctlr]; 786 static struct scsi_cdb6 cdb = { CMD_REQUEST_SENSE }; 787 788 cdb.lun = unit; 789 cdb.len = len; 790 return (scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE)); 791 } 792 793 int 794 scsi_immed_command(ctlr, slave, unit, cdb, buf, len, rd) 795 int ctlr, slave, unit; 796 struct scsi_fmt_cdb *cdb; 797 u_char *buf; 798 unsigned len; 799 { 800 register struct scsi_softc *hs = &scsi_softc[ctlr]; 801 802 cdb->cdb[1] |= unit << 5; 803 return (scsiicmd(hs, slave, cdb->cdb, cdb->len, buf, len, 804 rd != 0? DATA_IN_PHASE : DATA_OUT_PHASE)); 805 } 806 807 /* 808 * The following routines are test-and-transfer i/o versions of read/write 809 * for things like reading disk labels and writing core dumps. The 810 * routine scsigo should be used for normal data transfers, NOT these 811 * routines. 812 */ 813 int 814 scsi_tt_read(ctlr, slave, unit, buf, len, blk, bshift) 815 int ctlr, slave, unit; 816 u_char *buf; 817 u_int len; 818 daddr_t blk; 819 int bshift; 820 { 821 register struct scsi_softc *hs = &scsi_softc[ctlr]; 822 struct scsi_cdb10 cdb; 823 int stat; 824 int old_wait = scsi_data_wait; 825 826 scsi_data_wait = 300000; 827 bzero(&cdb, sizeof(cdb)); 828 cdb.cmd = CMD_READ_EXT; 829 cdb.lun = unit; 830 blk >>= bshift; 831 cdb.lbah = blk >> 24; 832 cdb.lbahm = blk >> 16; 833 cdb.lbalm = blk >> 8; 834 cdb.lbal = blk; 835 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 836 cdb.lenl = len >> (DEV_BSHIFT + bshift); 837 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE); 838 scsi_data_wait = old_wait; 839 return (stat); 840 } 841 842 int 843 scsi_tt_write(ctlr, slave, unit, buf, len, blk, bshift) 844 int ctlr, slave, unit; 845 u_char *buf; 846 u_int len; 847 daddr_t blk; 848 int bshift; 849 { 850 register struct scsi_softc *hs = &scsi_softc[ctlr]; 851 struct scsi_cdb10 cdb; 852 int stat; 853 int old_wait = scsi_data_wait; 854 855 scsi_data_wait = 300000; 856 857 bzero(&cdb, sizeof(cdb)); 858 cdb.cmd = CMD_WRITE_EXT; 859 cdb.lun = unit; 860 blk >>= bshift; 861 cdb.lbah = blk >> 24; 862 cdb.lbahm = blk >> 16; 863 cdb.lbalm = blk >> 8; 864 cdb.lbal = blk; 865 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 866 cdb.lenl = len >> (DEV_BSHIFT + bshift); 867 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_OUT_PHASE); 868 scsi_data_wait = old_wait; 869 return (stat); 870 } 871 872 int 873 scsireq(dq) 874 register struct devqueue *dq; 875 { 876 register struct devqueue *hq; 877 878 hq = &scsi_softc[dq->dq_ctlr].sc_sq; 879 insque(dq, hq->dq_back); 880 if (dq->dq_back == hq) 881 return(1); 882 return(0); 883 } 884 885 int 886 scsiustart(unit) 887 int unit; 888 { 889 register struct scsi_softc *hs = &scsi_softc[unit]; 890 891 hs->sc_dq.dq_ctlr = DMA0 | DMA1; 892 if (dmareq(&hs->sc_dq)) 893 return(1); 894 return(0); 895 } 896 897 void 898 scsistart(unit) 899 int unit; 900 { 901 register struct devqueue *dq; 902 903 dq = scsi_softc[unit].sc_sq.dq_forw; 904 (dq->dq_driver->d_go)(dq->dq_unit); 905 } 906 907 int 908 scsigo(ctlr, slave, unit, bp, cdb, pad) 909 int ctlr, slave, unit; 910 struct buf *bp; 911 struct scsi_fmt_cdb *cdb; 912 int pad; 913 { 914 register struct scsi_softc *hs = &scsi_softc[ctlr]; 915 volatile register struct scsidevice *hd = 916 (struct scsidevice *)hs->sc_hc->hp_addr; 917 int i, dmaflags; 918 u_char phase, ints, cmd; 919 920 cdb->cdb[1] |= unit << 5; 921 922 /* select the SCSI bus (it's an error if bus isn't free) */ 923 if (issue_select(hd, slave, hs->sc_scsi_addr) || wait_for_select(hd)) { 924 dmafree(&hs->sc_dq); 925 return (1); 926 } 927 /* 928 * Wait for a phase change (or error) then let the device 929 * sequence us through command phase (we may have to take 930 * a msg in/out before doing the command). If the disk has 931 * to do a seek, it may be a long time until we get a change 932 * to data phase so, in the absense of an explicit phase 933 * change, we assume data phase will be coming up and tell 934 * the SPC to start a transfer whenever it does. We'll get 935 * a service required interrupt later if this assumption is 936 * wrong. Otherwise we'll get a service required int when 937 * the transfer changes to status phase. 938 */ 939 phase = CMD_PHASE; 940 while (1) { 941 register int wait = scsi_cmd_wait; 942 943 switch (phase) { 944 945 case CMD_PHASE: 946 if (ixfer_start(hd, cdb->len, phase, wait)) 947 if (ixfer_out(hd, cdb->len, cdb->cdb)) 948 goto abort; 949 break; 950 951 case MESG_IN_PHASE: 952 if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait)|| 953 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { 954 ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); 955 hd->scsi_scmd = SCMD_RST_ACK; 956 } 957 phase = BUS_FREE_PHASE; 958 break; 959 960 case DATA_IN_PHASE: 961 case DATA_OUT_PHASE: 962 goto out; 963 964 default: 965 printf("scsi%d: unexpected phase %d in go from %d\n", 966 hs->sc_hc->hp_unit, phase, slave); 967 goto abort; 968 } 969 while ((ints = hd->scsi_ints) == 0) { 970 if (--wait < 0) { 971 HIST(sgo_wait, wait) 972 goto abort; 973 } 974 DELAY(1); 975 } 976 HIST(sgo_wait, wait) 977 hd->scsi_ints = ints; 978 if (ints & INTS_SRV_REQ) 979 phase = hd->scsi_psns & PHASE; 980 else if (ints & INTS_CMD_DONE) 981 goto out; 982 else { 983 scsierror(hs, hd, ints); 984 goto abort; 985 } 986 } 987 out: 988 /* 989 * Reset the card dma logic, setup the dma channel then 990 * get the dio part of the card set for a dma xfer. 991 */ 992 hd->scsi_hconf = 0; 993 cmd = CSR_IE; 994 dmaflags = DMAGO_NOINT; 995 if (scsi_pridma) 996 dmaflags |= DMAGO_PRI; 997 if (bp->b_flags & B_READ) 998 dmaflags |= DMAGO_READ; 999 if ((hs->sc_flags & SCSI_DMA32) && 1000 ((int)bp->b_un.b_addr & 3) == 0 && (bp->b_bcount & 3) == 0) { 1001 cmd |= CSR_DMA32; 1002 dmaflags |= DMAGO_LWORD; 1003 } else 1004 dmaflags |= DMAGO_WORD; 1005 dmago(hs->sc_dq.dq_ctlr, bp->b_un.b_addr, bp->b_bcount, dmaflags); 1006 1007 if (bp->b_flags & B_READ) { 1008 cmd |= CSR_DMAIN; 1009 phase = DATA_IN_PHASE; 1010 } else 1011 phase = DATA_OUT_PHASE; 1012 /* 1013 * DMA enable bits must be set after size and direction bits. 1014 */ 1015 hd->scsi_csr = cmd; 1016 hd->scsi_csr |= (CSR_DE0 << hs->sc_dq.dq_ctlr); 1017 /* 1018 * Setup the SPC for the transfer. We don't want to take 1019 * first a command complete then a service required interrupt 1020 * at the end of the transfer so we try to disable the cmd 1021 * complete by setting the transfer counter to more bytes 1022 * than we expect. (XXX - This strategy may have to be 1023 * modified to deal with devices that return variable length 1024 * blocks, e.g., some tape drives.) 1025 */ 1026 cmd = SCMD_XFR; 1027 i = (unsigned)bp->b_bcount; 1028 if (pad) { 1029 cmd |= SCMD_PAD; 1030 /* 1031 * XXX - If we don't do this, the last 2 or 4 bytes 1032 * (depending on word/lword DMA) of a read get trashed. 1033 * It looks like it is necessary for the DMA to complete 1034 * before the SPC goes into "pad mode"??? Note: if we 1035 * also do this on a write, the request never completes. 1036 */ 1037 if (bp->b_flags & B_READ) 1038 i += 2; 1039 #ifdef DEBUG 1040 hs->sc_flags |= SCSI_PAD; 1041 if (i & 1) 1042 printf("scsi%d: odd byte count: %d bytes @ %d\n", 1043 ctlr, i, bp->b_cylin); 1044 #endif 1045 } else 1046 i += 4; 1047 hd->scsi_tch = i >> 16; 1048 hd->scsi_tcm = i >> 8; 1049 hd->scsi_tcl = i; 1050 hd->scsi_pctl = phase; 1051 hd->scsi_tmod = 0; 1052 hd->scsi_scmd = cmd; 1053 hs->sc_flags |= SCSI_IO; 1054 return (0); 1055 abort: 1056 scsiabort(hs, hd, "go"); 1057 dmafree(&hs->sc_dq); 1058 return (1); 1059 } 1060 1061 void 1062 scsidone(unit) 1063 register int unit; 1064 { 1065 volatile register struct scsidevice *hd = 1066 (struct scsidevice *)scsi_softc[unit].sc_hc->hp_addr; 1067 1068 #ifdef DEBUG 1069 if (scsi_debug) 1070 printf("scsi%d: done called!\n"); 1071 #endif 1072 /* dma operation is done -- turn off card dma */ 1073 hd->scsi_csr &=~ (CSR_DE1|CSR_DE0); 1074 } 1075 1076 int 1077 scsiintr(unit) 1078 register int unit; 1079 { 1080 register struct scsi_softc *hs = &scsi_softc[unit]; 1081 volatile register struct scsidevice *hd = 1082 (struct scsidevice *)hs->sc_hc->hp_addr; 1083 register u_char ints; 1084 register struct devqueue *dq; 1085 1086 if ((hd->scsi_csr & (CSR_IE|CSR_IR)) != (CSR_IE|CSR_IR)) 1087 return (0); 1088 1089 ints = hd->scsi_ints; 1090 if ((ints & INTS_SRV_REQ) && (hs->sc_flags & SCSI_IO)) { 1091 /* 1092 * this should be the normal i/o completion case. 1093 * get the status & cmd complete msg then let the 1094 * device driver look at what happened. 1095 */ 1096 #ifdef DEBUG 1097 int len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | 1098 hd->scsi_tcl; 1099 if (!(hs->sc_flags & SCSI_PAD)) 1100 len -= 4; 1101 hs->sc_flags &=~ SCSI_PAD; 1102 #endif 1103 dq = hs->sc_sq.dq_forw; 1104 finishxfer(hs, hd, dq->dq_slave); 1105 hs->sc_flags &=~ SCSI_IO; 1106 dmafree(&hs->sc_dq); 1107 (dq->dq_driver->d_intr)(dq->dq_unit, hs->sc_stat[0]); 1108 } else { 1109 /* Something unexpected happened -- deal with it. */ 1110 hd->scsi_ints = ints; 1111 hd->scsi_csr = 0; 1112 scsierror(hs, hd, ints); 1113 scsiabort(hs, hd, "intr"); 1114 if (hs->sc_flags & SCSI_IO) { 1115 hs->sc_flags &=~ SCSI_IO; 1116 dmafree(&hs->sc_dq); 1117 dq = hs->sc_sq.dq_forw; 1118 (dq->dq_driver->d_intr)(dq->dq_unit, -1); 1119 } 1120 } 1121 return(1); 1122 } 1123 1124 void 1125 scsifree(dq) 1126 register struct devqueue *dq; 1127 { 1128 register struct devqueue *hq; 1129 1130 hq = &scsi_softc[dq->dq_ctlr].sc_sq; 1131 remque(dq); 1132 if ((dq = hq->dq_forw) != hq) 1133 (dq->dq_driver->d_start)(dq->dq_unit); 1134 } 1135 1136 /* 1137 * (XXX) The following routine is needed for the SCSI tape driver 1138 * to read odd-size records. 1139 */ 1140 1141 #include "st.h" 1142 #if NST > 0 1143 int 1144 scsi_tt_oddio(ctlr, slave, unit, buf, len, b_flags, freedma) 1145 int ctlr, slave, unit, b_flags; 1146 u_char *buf; 1147 u_int len; 1148 { 1149 register struct scsi_softc *hs = &scsi_softc[ctlr]; 1150 struct scsi_cdb6 cdb; 1151 u_char iphase; 1152 int stat; 1153 1154 /* 1155 * First free any DMA channel that was allocated. 1156 * We can't use DMA to do this transfer. 1157 */ 1158 if (freedma) 1159 dmafree(hs->sc_dq); 1160 /* 1161 * Initialize command block 1162 */ 1163 bzero(&cdb, sizeof(cdb)); 1164 cdb.lun = unit; 1165 cdb.lbam = (len >> 16) & 0xff; 1166 cdb.lbal = (len >> 8) & 0xff; 1167 cdb.len = len & 0xff; 1168 if (buf == 0) { 1169 cdb.cmd = CMD_SPACE; 1170 cdb.lun |= 0x00; 1171 len = 0; 1172 iphase = MESG_IN_PHASE; 1173 } else if (b_flags & B_READ) { 1174 cdb.cmd = CMD_READ; 1175 iphase = DATA_IN_PHASE; 1176 } else { 1177 cdb.cmd = CMD_WRITE; 1178 iphase = DATA_OUT_PHASE; 1179 } 1180 /* 1181 * Perform command (with very long delays) 1182 */ 1183 scsi_delay(30000000); 1184 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, iphase); 1185 scsi_delay(0); 1186 return (stat); 1187 } 1188 #endif 1189 #endif 1190