1 /* 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Van Jacobson of Lawrence Berkeley Laboratory. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)scsi.c 7.3 (Berkeley) 12/16/90 11 */ 12 13 /* 14 * HP9000/3xx 98658 SCSI host adaptor driver. 15 */ 16 #include "scsi.h" 17 #if NSCSI > 0 18 19 #ifndef lint 20 static char rcsid[] = "$Header: scsi.c,v 1.3 90/10/10 14:55:08 mike Exp $"; 21 #endif 22 23 #include "sys/param.h" 24 #include "sys/systm.h" 25 #include "sys/buf.h" 26 #include "device.h" 27 28 #include "scsivar.h" 29 #include "scsireg.h" 30 #include "dmavar.h" 31 32 #include "../include/cpu.h" 33 #include "../hp300/isr.h" 34 35 extern void isrlink(); 36 extern void printf(); 37 extern void _insque(); 38 extern void _remque(); 39 extern void bzero(); 40 41 int scsiinit(), scsigo(), scsiintr(), scsixfer(); 42 void scsistart(), scsidone(), scsifree(), scsireset(); 43 struct driver scsidriver = { 44 scsiinit, "scsi", (int (*)())scsistart, scsigo, scsiintr, 45 (int (*)())scsidone, 46 }; 47 48 struct scsi_softc scsi_softc[NSCSI]; 49 struct isr scsi_isr[NSCSI]; 50 51 int scsi_cmd_wait = 512; /* microsec wait per step of 'immediate' cmds */ 52 int scsi_data_wait = 512; /* wait per data in/out step */ 53 int scsi_nosync = 1; /* inhibit sync xfers if 1 */ 54 int scsi_pridma = 0; /* use "priority" dma */ 55 56 #ifdef DEBUG 57 int scsi_debug = 0; 58 #define WAITHIST 59 #endif 60 61 #ifdef WAITHIST 62 #define MAXWAIT 1022 63 u_int ixstart_wait[MAXWAIT+2]; 64 u_int ixin_wait[MAXWAIT+2]; 65 u_int ixout_wait[MAXWAIT+2]; 66 u_int mxin_wait[MAXWAIT+2]; 67 u_int cxin_wait[MAXWAIT+2]; 68 u_int fxfr_wait[MAXWAIT+2]; 69 u_int sgo_wait[MAXWAIT+2]; 70 #define HIST(h,w) (++h[((w)>MAXWAIT? MAXWAIT : ((w) < 0 ? -1 : (w))) + 1]); 71 #else 72 #define HIST(h,w) 73 #endif 74 75 #define b_cylin b_resid 76 77 static void 78 scsiabort(hs, hd, where) 79 register struct scsi_softc *hs; 80 volatile register struct scsidevice *hd; 81 char *where; 82 { 83 int len; 84 u_char junk; 85 86 printf("scsi%d: abort from %s: phase=0x%x, ssts=0x%x, ints=0x%x\n", 87 hs->sc_hc->hp_unit, where, hd->scsi_psns, hd->scsi_ssts, 88 hd->scsi_ints); 89 90 hd->scsi_ints = hd->scsi_ints; 91 hd->scsi_csr = 0; 92 if (hd->scsi_psns == 0 || (hd->scsi_ssts & SSTS_INITIATOR) == 0) 93 /* no longer connected to scsi target */ 94 return; 95 96 /* get the number of bytes remaining in current xfer + fudge */ 97 len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | hd->scsi_tcl; 98 99 /* for that many bus cycles, try to send an abort msg */ 100 for (len += 1024; (hd->scsi_ssts & SSTS_INITIATOR) && --len >= 0; ) { 101 hd->scsi_scmd = SCMD_SET_ATN; 102 while ((hd->scsi_psns & PSNS_REQ) == 0) { 103 if (! (hd->scsi_ssts & SSTS_INITIATOR)) 104 goto out; 105 DELAY(1); 106 } 107 if ((hd->scsi_psns & PHASE) == MESG_OUT_PHASE) 108 hd->scsi_scmd = SCMD_RST_ATN; 109 hd->scsi_pctl = hd->scsi_psns & PHASE; 110 if (hd->scsi_psns & PHASE_IO) { 111 /* one of the input phases - read & discard a byte */ 112 hd->scsi_scmd = SCMD_SET_ACK; 113 if (hd->scsi_tmod == 0) 114 while (hd->scsi_psns & PSNS_REQ) 115 DELAY(1); 116 junk = hd->scsi_temp; 117 } else { 118 /* one of the output phases - send an abort msg */ 119 hd->scsi_temp = MSG_ABORT; 120 hd->scsi_scmd = SCMD_SET_ACK; 121 if (hd->scsi_tmod == 0) 122 while (hd->scsi_psns & PSNS_REQ) 123 DELAY(1); 124 } 125 hd->scsi_scmd = SCMD_RST_ACK; 126 } 127 out: 128 /* 129 * Either the abort was successful & the bus is disconnected or 130 * the device didn't listen. If the latter, announce the problem. 131 * Either way, reset the card & the SPC. 132 */ 133 if (len < 0 && hs) 134 printf("scsi%d: abort failed. phase=0x%x, ssts=0x%x\n", 135 hs->sc_hc->hp_unit, hd->scsi_psns, hd->scsi_ssts); 136 137 if (! ((junk = hd->scsi_ints) & INTS_RESEL)) { 138 hd->scsi_sctl |= SCTL_CTRLRST; 139 DELAY(1); 140 hd->scsi_sctl &=~ SCTL_CTRLRST; 141 hd->scsi_hconf = 0; 142 hd->scsi_ints = hd->scsi_ints; 143 } 144 } 145 146 int 147 scsiinit(hc) 148 register struct hp_ctlr *hc; 149 { 150 register struct scsi_softc *hs = &scsi_softc[hc->hp_unit]; 151 register struct scsidevice *hd = (struct scsidevice *)hc->hp_addr; 152 153 if ((hd->scsi_id & ID_MASK) != SCSI_ID) 154 return(0); 155 hc->hp_ipl = SCSI_IPL(hd->scsi_csr); 156 hs->sc_hc = hc; 157 hs->sc_dq.dq_unit = hc->hp_unit; 158 hs->sc_dq.dq_driver = &scsidriver; 159 hs->sc_sq.dq_forw = hs->sc_sq.dq_back = &hs->sc_sq; 160 scsi_isr[hc->hp_unit].isr_intr = scsiintr; 161 scsi_isr[hc->hp_unit].isr_ipl = hc->hp_ipl; 162 scsi_isr[hc->hp_unit].isr_arg = hc->hp_unit; 163 isrlink(&scsi_isr[hc->hp_unit]); 164 scsireset(hc->hp_unit); 165 return(1); 166 } 167 168 void 169 scsireset(unit) 170 register int unit; 171 { 172 register struct scsi_softc *hs = &scsi_softc[unit]; 173 volatile register struct scsidevice *hd = 174 (struct scsidevice *)hs->sc_hc->hp_addr; 175 u_int i; 176 177 if (hs->sc_flags & SCSI_ALIVE) 178 scsiabort(hs, hd, "reset"); 179 180 printf("scsi%d: ", unit); 181 182 hd->scsi_id = 0xFF; 183 DELAY(100); 184 /* 185 * Disable interrupts then reset the FUJI chip. 186 */ 187 hd->scsi_csr = 0; 188 hd->scsi_sctl = SCTL_DISABLE | SCTL_CTRLRST; 189 hd->scsi_scmd = 0; 190 hd->scsi_tmod = 0; 191 hd->scsi_pctl = 0; 192 hd->scsi_temp = 0; 193 hd->scsi_tch = 0; 194 hd->scsi_tcm = 0; 195 hd->scsi_tcl = 0; 196 hd->scsi_ints = 0; 197 198 if ((hd->scsi_id & ID_WORD_DMA) == 0) { 199 hs->sc_flags |= SCSI_DMA32; 200 printf("32 bit dma, "); 201 } 202 203 /* Determine Max Synchronous Transfer Rate */ 204 if (scsi_nosync) 205 i = 3; 206 else 207 i = SCSI_SYNC_XFER(hd->scsi_hconf); 208 switch (i) { 209 case 0: 210 hs->sc_sync = TMOD_SYNC | 0x3e; /* 250 nsecs */ 211 printf("250ns sync"); 212 break; 213 case 1: 214 hs->sc_sync = TMOD_SYNC | 0x5e; /* 375 nsecs */ 215 printf("375ns sync"); 216 break; 217 case 2: 218 hs->sc_sync = TMOD_SYNC | 0x7d; /* 500 nsecs */ 219 printf("500ns sync"); 220 break; 221 case 3: 222 hs->sc_sync = 0; 223 printf("async"); 224 break; 225 } 226 227 /* 228 * Configure the FUJI chip with its SCSI address, all 229 * interrupts enabled & appropriate parity. 230 */ 231 i = (~hd->scsi_hconf) & 0x7; 232 hs->sc_scsi_addr = 1 << i; 233 hd->scsi_bdid = i; 234 if (hd->scsi_hconf & HCONF_PARITY) 235 hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | 236 SCTL_SEL_ENAB | SCTL_RESEL_ENAB | 237 SCTL_INTR_ENAB | SCTL_PARITY_ENAB; 238 else { 239 hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | 240 SCTL_SEL_ENAB | SCTL_RESEL_ENAB | 241 SCTL_INTR_ENAB; 242 printf(", no parity"); 243 } 244 hd->scsi_sctl &=~ SCTL_DISABLE; 245 246 printf(", scsi id %d\n", i); 247 hs->sc_flags |= SCSI_ALIVE; 248 } 249 250 static void 251 scsierror(hs, hd, ints) 252 register struct scsi_softc *hs; 253 volatile register struct scsidevice *hd; 254 u_char ints; 255 { 256 int unit = hs->sc_hc->hp_unit; 257 char *sep = ""; 258 259 printf("scsi%d: ", unit); 260 if (ints & INTS_RST) { 261 DELAY(100); 262 if (hd->scsi_hconf & HCONF_SD) 263 printf("spurious RST interrupt"); 264 else 265 printf("hardware error - check fuse"); 266 sep = ", "; 267 } 268 if ((ints & INTS_HARD_ERR) || hd->scsi_serr) { 269 if (hd->scsi_serr & SERR_SCSI_PAR) { 270 printf("%sparity err", sep); 271 sep = ", "; 272 } 273 if (hd->scsi_serr & SERR_SPC_PAR) { 274 printf("%sSPC parity err", sep); 275 sep = ", "; 276 } 277 if (hd->scsi_serr & SERR_TC_PAR) { 278 printf("%sTC parity err", sep); 279 sep = ", "; 280 } 281 if (hd->scsi_serr & SERR_PHASE_ERR) { 282 printf("%sphase err", sep); 283 sep = ", "; 284 } 285 if (hd->scsi_serr & SERR_SHORT_XFR) { 286 printf("%ssync short transfer err", sep); 287 sep = ", "; 288 } 289 if (hd->scsi_serr & SERR_OFFSET) { 290 printf("%ssync offset error", sep); 291 sep = ", "; 292 } 293 } 294 if (ints & INTS_TIMEOUT) 295 printf("%sSPC select timeout error", sep); 296 if (ints & INTS_SRV_REQ) 297 printf("%sspurious SRV_REQ interrupt", sep); 298 if (ints & INTS_CMD_DONE) 299 printf("%sspurious CMD_DONE interrupt", sep); 300 if (ints & INTS_DISCON) 301 printf("%sspurious disconnect interrupt", sep); 302 if (ints & INTS_RESEL) 303 printf("%sspurious reselect interrupt", sep); 304 if (ints & INTS_SEL) 305 printf("%sspurious select interrupt", sep); 306 printf("\n"); 307 } 308 309 static int 310 issue_select(hd, target, our_addr) 311 volatile register struct scsidevice *hd; 312 u_char target, our_addr; 313 { 314 if (hd->scsi_ssts & (SSTS_INITIATOR|SSTS_TARGET|SSTS_BUSY)) 315 return (1); 316 317 if (hd->scsi_ints & INTS_DISCON) 318 hd->scsi_ints = INTS_DISCON; 319 320 hd->scsi_pctl = 0; 321 hd->scsi_temp = (1 << target) | our_addr; 322 /* select timeout is hardcoded to 2ms */ 323 hd->scsi_tch = 0; 324 hd->scsi_tcm = 32; 325 hd->scsi_tcl = 4; 326 327 hd->scsi_scmd = SCMD_SELECT; 328 return (0); 329 } 330 331 static int 332 wait_for_select(hd) 333 volatile register struct scsidevice *hd; 334 { 335 u_char ints; 336 337 while ((ints = hd->scsi_ints) == 0) 338 DELAY(1); 339 hd->scsi_ints = ints; 340 return (!(hd->scsi_ssts & SSTS_INITIATOR)); 341 } 342 343 static int 344 ixfer_start(hd, len, phase, wait) 345 volatile register struct scsidevice *hd; 346 int len; 347 u_char phase; 348 register int wait; 349 { 350 351 hd->scsi_tch = len >> 16; 352 hd->scsi_tcm = len >> 8; 353 hd->scsi_tcl = len; 354 hd->scsi_pctl = phase; 355 hd->scsi_tmod = 0; /*XXX*/ 356 hd->scsi_scmd = SCMD_XFR | SCMD_PROG_XFR; 357 358 /* wait for xfer to start or svc_req interrupt */ 359 while ((hd->scsi_ssts & SSTS_BUSY) == 0) { 360 if (hd->scsi_ints || --wait < 0) { 361 #ifdef DEBUG 362 if (scsi_debug) 363 printf("ixfer_start fail: i%x, w%d\n", 364 hd->scsi_ints, wait); 365 #endif 366 HIST(ixstart_wait, wait) 367 return (0); 368 } 369 DELAY(1); 370 } 371 HIST(ixstart_wait, wait) 372 return (1); 373 } 374 375 static int 376 ixfer_out(hd, len, buf) 377 volatile register struct scsidevice *hd; 378 int len; 379 register u_char *buf; 380 { 381 register int wait = scsi_data_wait; 382 383 for (; len > 0; --len) { 384 while (hd->scsi_ssts & SSTS_DREG_FULL) { 385 if (hd->scsi_ints || --wait < 0) { 386 #ifdef DEBUG 387 if (scsi_debug) 388 printf("ixfer_out fail: l%d i%x w%d\n", 389 len, hd->scsi_ints, wait); 390 #endif 391 HIST(ixout_wait, wait) 392 return (len); 393 } 394 DELAY(1); 395 } 396 hd->scsi_dreg = *buf++; 397 } 398 HIST(ixout_wait, wait) 399 return (0); 400 } 401 402 static void 403 ixfer_in(hd, len, buf) 404 volatile register struct scsidevice *hd; 405 int len; 406 register u_char *buf; 407 { 408 register int wait = scsi_data_wait; 409 410 for (; len > 0; --len) { 411 while (hd->scsi_ssts & SSTS_DREG_EMPTY) { 412 if (hd->scsi_ints || --wait < 0) { 413 while (! (hd->scsi_ssts & SSTS_DREG_EMPTY)) { 414 *buf++ = hd->scsi_dreg; 415 --len; 416 } 417 #ifdef DEBUG 418 if (scsi_debug) 419 printf("ixfer_in fail: l%d i%x w%d\n", 420 len, hd->scsi_ints, wait); 421 #endif 422 HIST(ixin_wait, wait) 423 return; 424 } 425 DELAY(1); 426 } 427 *buf++ = hd->scsi_dreg; 428 } 429 HIST(ixin_wait, wait) 430 } 431 432 static int 433 mxfer_in(hd, len, buf, phase) 434 volatile register struct scsidevice *hd; 435 register int len; 436 register u_char *buf; 437 register u_char phase; 438 { 439 register int wait = scsi_cmd_wait; 440 register int i; 441 442 hd->scsi_tmod = 0; 443 for (i = 0; i < len; ++i) { 444 /* 445 * wait for the request line (which says the target 446 * wants to give us data). If the phase changes while 447 * we're waiting, we're done. 448 */ 449 while ((hd->scsi_psns & PSNS_REQ) == 0) { 450 if (--wait < 0) { 451 HIST(mxin_wait, wait) 452 return (-1); 453 } 454 if ((hd->scsi_psns & PHASE) != phase || 455 (hd->scsi_ssts & SSTS_INITIATOR) == 0) 456 goto out; 457 458 DELAY(1); 459 } 460 /* 461 * set ack (which says we're ready for the data, wait for 462 * req to go away (target says data is available), grab the 463 * data, then reset ack (say we've got the data). 464 */ 465 hd->scsi_pctl = phase; 466 hd->scsi_scmd = SCMD_SET_ACK; 467 while (hd->scsi_psns & PSNS_REQ) { 468 if (--wait < 0) { 469 HIST(mxin_wait, wait) 470 return (-2); 471 } 472 DELAY(1); 473 } 474 *buf++ = hd->scsi_temp; 475 hd->scsi_scmd = SCMD_RST_ACK; 476 if (hd->scsi_psns & PSNS_ATN) 477 hd->scsi_scmd = SCMD_RST_ATN; 478 } 479 out: 480 HIST(mxin_wait, wait) 481 return (i); 482 } 483 484 /* 485 * SCSI 'immediate' command: issue a command to some SCSI device 486 * and get back an 'immediate' response (i.e., do programmed xfer 487 * to get the response data). 'cbuf' is a buffer containing a scsi 488 * command of length clen bytes. 'buf' is a buffer of length 'len' 489 * bytes for data. The transfer direction is determined by the device 490 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 491 * command must supply no data. 'xferphase' is the bus phase the 492 * caller expects to happen after the command is issued. It should 493 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 494 */ 495 static int 496 scsiicmd(hs, target, cbuf, clen, buf, len, xferphase) 497 struct scsi_softc *hs; 498 int target; 499 u_char *cbuf; 500 int clen; 501 u_char *buf; 502 int len; 503 u_char xferphase; 504 { 505 volatile register struct scsidevice *hd = 506 (struct scsidevice *)hs->sc_hc->hp_addr; 507 u_char phase, ints; 508 register int wait; 509 510 /* select the SCSI bus (it's an error if bus isn't free) */ 511 if (issue_select(hd, target, hs->sc_scsi_addr)) 512 return (-1); 513 if (wait_for_select(hd)) 514 return (-1); 515 /* 516 * Wait for a phase change (or error) then let the device 517 * sequence us through the various SCSI phases. 518 */ 519 hs->sc_stat[0] = 0xff; 520 hs->sc_msg[0] = 0xff; 521 phase = CMD_PHASE; 522 while (1) { 523 wait = scsi_cmd_wait; 524 switch (phase) { 525 526 case CMD_PHASE: 527 if (ixfer_start(hd, clen, phase, wait)) 528 if (ixfer_out(hd, clen, cbuf)) 529 goto abort; 530 phase = xferphase; 531 break; 532 533 case DATA_IN_PHASE: 534 if (len <= 0) 535 goto abort; 536 wait = scsi_data_wait; 537 if (ixfer_start(hd, len, phase, wait) || 538 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) 539 ixfer_in(hd, len, buf); 540 phase = STATUS_PHASE; 541 break; 542 543 case DATA_OUT_PHASE: 544 if (len <= 0) 545 goto abort; 546 wait = scsi_data_wait; 547 if (ixfer_start(hd, len, phase, wait)) { 548 if (ixfer_out(hd, len, buf)) 549 goto abort; 550 } 551 phase = STATUS_PHASE; 552 break; 553 554 case STATUS_PHASE: 555 wait = scsi_data_wait; 556 if (ixfer_start(hd, sizeof(hs->sc_stat), phase, wait) || 557 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) 558 ixfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat); 559 phase = MESG_IN_PHASE; 560 break; 561 562 case MESG_IN_PHASE: 563 if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait) || 564 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { 565 ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); 566 hd->scsi_scmd = SCMD_RST_ACK; 567 } 568 phase = BUS_FREE_PHASE; 569 break; 570 571 case BUS_FREE_PHASE: 572 goto out; 573 574 default: 575 printf("scsi%d: unexpected phase %d in icmd from %d\n", 576 hs->sc_hc->hp_unit, phase, target); 577 goto abort; 578 } 579 /* wait for last command to complete */ 580 while ((ints = hd->scsi_ints) == 0) { 581 if (--wait < 0) { 582 HIST(cxin_wait, wait) 583 goto abort; 584 } 585 DELAY(1); 586 } 587 HIST(cxin_wait, wait) 588 hd->scsi_ints = ints; 589 if (ints & INTS_SRV_REQ) 590 phase = hd->scsi_psns & PHASE; 591 else if (ints & INTS_DISCON) 592 goto out; 593 else if ((ints & INTS_CMD_DONE) == 0) { 594 scsierror(hs, hd, ints); 595 goto abort; 596 } 597 } 598 abort: 599 scsiabort(hs, hd, "icmd"); 600 out: 601 return (hs->sc_stat[0]); 602 } 603 604 /* 605 * Finish SCSI xfer command: After the completion interrupt from 606 * a read/write operation, sequence through the final phases in 607 * programmed i/o. This routine is a lot like scsiicmd except we 608 * skip (and don't allow) the select, cmd out and data in/out phases. 609 */ 610 static void 611 finishxfer(hs, hd, target) 612 struct scsi_softc *hs; 613 volatile register struct scsidevice *hd; 614 int target; 615 { 616 u_char phase, ints; 617 618 /* 619 * We specified padding xfer so we ended with either a phase 620 * change interrupt (normal case) or an error interrupt (handled 621 * elsewhere). Reset the board dma logic then try to get the 622 * completion status & command done msg. The reset confuses 623 * the SPC REQ/ACK logic so we have to do any status/msg input 624 * operations via 'manual xfer'. 625 */ 626 if (hd->scsi_ssts & SSTS_BUSY) { 627 int wait = scsi_cmd_wait; 628 629 /* wait for dma operation to finish */ 630 while (hd->scsi_ssts & SSTS_BUSY) { 631 if (--wait < 0) { 632 #ifdef DEBUG 633 if (scsi_debug) 634 printf("finishxfer fail: ssts %x\n", 635 hd->scsi_ssts); 636 #endif 637 HIST(fxfr_wait, wait) 638 goto abort; 639 } 640 } 641 HIST(fxfr_wait, wait) 642 } 643 hd->scsi_scmd |= SCMD_PROG_XFR; 644 hd->scsi_sctl |= SCTL_CTRLRST; 645 DELAY(1); 646 hd->scsi_sctl &=~ SCTL_CTRLRST; 647 hd->scsi_hconf = 0; 648 hs->sc_stat[0] = 0xff; 649 hs->sc_msg[0] = 0xff; 650 hd->scsi_csr = 0; 651 hd->scsi_ints = ints = hd->scsi_ints; 652 while (1) { 653 phase = hd->scsi_psns & PHASE; 654 switch (phase) { 655 656 case STATUS_PHASE: 657 if (mxfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat, 658 phase) <= 0) 659 goto abort; 660 break; 661 662 case MESG_IN_PHASE: 663 if (mxfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg, 664 phase) < 0) 665 goto abort; 666 break; 667 668 case BUS_FREE_PHASE: 669 return; 670 671 default: 672 printf("scsi%d: unexpected phase %d in finishxfer from %d\n", 673 hs->sc_hc->hp_unit, phase, target); 674 goto abort; 675 } 676 if (ints = hd->scsi_ints) { 677 hd->scsi_ints = ints; 678 if (ints & INTS_DISCON) 679 return; 680 else if (ints & ~(INTS_SRV_REQ|INTS_CMD_DONE)) { 681 scsierror(hs, hd, ints); 682 break; 683 } 684 } 685 if ((hd->scsi_ssts & SSTS_INITIATOR) == 0) 686 return; 687 } 688 abort: 689 scsiabort(hs, hd, "finishxfer"); 690 hs->sc_stat[0] = 0xfe; 691 } 692 693 int 694 scsi_test_unit_rdy(ctlr, slave, unit) 695 int ctlr, slave, unit; 696 { 697 register struct scsi_softc *hs = &scsi_softc[ctlr]; 698 static struct scsi_cdb6 cdb = { CMD_TEST_UNIT_READY }; 699 700 cdb.lun = unit; 701 return (scsiicmd(hs, slave, &cdb, sizeof(cdb), (u_char *)0, 0, 702 STATUS_PHASE)); 703 } 704 705 int 706 scsi_request_sense(ctlr, slave, unit, buf, len) 707 int ctlr, slave, unit; 708 u_char *buf; 709 unsigned len; 710 { 711 register struct scsi_softc *hs = &scsi_softc[ctlr]; 712 static struct scsi_cdb6 cdb = { CMD_REQUEST_SENSE }; 713 714 cdb.lun = unit; 715 cdb.len = len; 716 return (scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE)); 717 } 718 719 int 720 scsi_immed_command(ctlr, slave, unit, cdb, buf, len, rd) 721 int ctlr, slave, unit; 722 struct scsi_fmt_cdb *cdb; 723 u_char *buf; 724 unsigned len; 725 { 726 register struct scsi_softc *hs = &scsi_softc[ctlr]; 727 728 cdb->cdb[1] |= unit << 5; 729 return (scsiicmd(hs, slave, cdb->cdb, cdb->len, buf, len, 730 rd != 0? DATA_IN_PHASE : DATA_OUT_PHASE)); 731 } 732 733 /* 734 * The following routines are test-and-transfer i/o versions of read/write 735 * for things like reading disk labels and writing core dumps. The 736 * routine scsigo should be used for normal data transfers, NOT these 737 * routines. 738 */ 739 int 740 scsi_tt_read(ctlr, slave, unit, buf, len, blk, bshift) 741 int ctlr, slave, unit; 742 u_char *buf; 743 u_int len; 744 daddr_t blk; 745 int bshift; 746 { 747 register struct scsi_softc *hs = &scsi_softc[ctlr]; 748 struct scsi_cdb10 cdb; 749 int stat; 750 int old_wait = scsi_data_wait; 751 752 scsi_data_wait = 300000; 753 bzero(&cdb, sizeof(cdb)); 754 cdb.cmd = CMD_READ_EXT; 755 cdb.lun = unit; 756 blk >>= bshift; 757 cdb.lbah = blk >> 24; 758 cdb.lbahm = blk >> 16; 759 cdb.lbalm = blk >> 8; 760 cdb.lbal = blk; 761 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 762 cdb.lenl = len >> (DEV_BSHIFT + bshift); 763 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE); 764 scsi_data_wait = old_wait; 765 return (stat); 766 } 767 768 int 769 scsi_tt_write(ctlr, slave, unit, buf, len, blk, bshift) 770 int ctlr, slave, unit; 771 u_char *buf; 772 u_int len; 773 daddr_t blk; 774 int bshift; 775 { 776 register struct scsi_softc *hs = &scsi_softc[ctlr]; 777 struct scsi_cdb10 cdb; 778 int stat; 779 int old_wait = scsi_data_wait; 780 781 scsi_data_wait = 300000; 782 783 bzero(&cdb, sizeof(cdb)); 784 cdb.cmd = CMD_WRITE_EXT; 785 cdb.lun = unit; 786 blk >>= bshift; 787 cdb.lbah = blk >> 24; 788 cdb.lbahm = blk >> 16; 789 cdb.lbalm = blk >> 8; 790 cdb.lbal = blk; 791 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 792 cdb.lenl = len >> (DEV_BSHIFT + bshift); 793 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_OUT_PHASE); 794 scsi_data_wait = old_wait; 795 return (stat); 796 } 797 798 int 799 scsireq(dq) 800 register struct devqueue *dq; 801 { 802 register struct devqueue *hq; 803 804 hq = &scsi_softc[dq->dq_ctlr].sc_sq; 805 insque(dq, hq->dq_back); 806 if (dq->dq_back == hq) 807 return(1); 808 return(0); 809 } 810 811 int 812 scsiustart(unit) 813 int unit; 814 { 815 register struct scsi_softc *hs = &scsi_softc[unit]; 816 817 hs->sc_dq.dq_ctlr = DMA0 | DMA1; 818 if (dmareq(&hs->sc_dq)) 819 return(1); 820 return(0); 821 } 822 823 void 824 scsistart(unit) 825 int unit; 826 { 827 register struct devqueue *dq; 828 829 dq = scsi_softc[unit].sc_sq.dq_forw; 830 (dq->dq_driver->d_go)(dq->dq_unit); 831 } 832 833 int 834 scsigo(ctlr, slave, unit, bp, cdb, pad) 835 int ctlr, slave, unit; 836 struct buf *bp; 837 struct scsi_fmt_cdb *cdb; 838 int pad; 839 { 840 register struct scsi_softc *hs = &scsi_softc[ctlr]; 841 volatile register struct scsidevice *hd = 842 (struct scsidevice *)hs->sc_hc->hp_addr; 843 int i, dmaflags; 844 u_char phase, ints, cmd; 845 846 cdb->cdb[1] |= unit << 5; 847 848 /* select the SCSI bus (it's an error if bus isn't free) */ 849 if (issue_select(hd, slave, hs->sc_scsi_addr) || wait_for_select(hd)) { 850 dmafree(&hs->sc_dq); 851 return (1); 852 } 853 /* 854 * Wait for a phase change (or error) then let the device 855 * sequence us through command phase (we may have to take 856 * a msg in/out before doing the command). If the disk has 857 * to do a seek, it may be a long time until we get a change 858 * to data phase so, in the absense of an explicit phase 859 * change, we assume data phase will be coming up and tell 860 * the SPC to start a transfer whenever it does. We'll get 861 * a service required interrupt later if this assumption is 862 * wrong. Otherwise we'll get a service required int when 863 * the transfer changes to status phase. 864 */ 865 phase = CMD_PHASE; 866 while (1) { 867 register int wait = scsi_cmd_wait; 868 869 switch (phase) { 870 871 case CMD_PHASE: 872 if (ixfer_start(hd, cdb->len, phase, wait)) 873 if (ixfer_out(hd, cdb->len, cdb->cdb)) 874 goto abort; 875 break; 876 877 case MESG_IN_PHASE: 878 if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait)|| 879 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { 880 ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); 881 hd->scsi_scmd = SCMD_RST_ACK; 882 } 883 phase = BUS_FREE_PHASE; 884 break; 885 886 case DATA_IN_PHASE: 887 case DATA_OUT_PHASE: 888 goto out; 889 890 default: 891 printf("scsi%d: unexpected phase %d in go from %d\n", 892 hs->sc_hc->hp_unit, phase, slave); 893 goto abort; 894 } 895 while ((ints = hd->scsi_ints) == 0) { 896 if (--wait < 0) { 897 HIST(sgo_wait, wait) 898 goto abort; 899 } 900 DELAY(1); 901 } 902 HIST(sgo_wait, wait) 903 hd->scsi_ints = ints; 904 if (ints & INTS_SRV_REQ) 905 phase = hd->scsi_psns & PHASE; 906 else if (ints & INTS_CMD_DONE) 907 goto out; 908 else { 909 scsierror(hs, hd, ints); 910 goto abort; 911 } 912 } 913 out: 914 /* 915 * Reset the card dma logic, setup the dma channel then 916 * get the dio part of the card set for a dma xfer. 917 */ 918 hd->scsi_hconf = 0; 919 cmd = CSR_IE; 920 dmaflags = DMAGO_NOINT; 921 if (scsi_pridma) 922 dmaflags |= DMAGO_PRI; 923 if (bp->b_flags & B_READ) 924 dmaflags |= DMAGO_READ; 925 if ((hs->sc_flags & SCSI_DMA32) && 926 ((int)bp->b_un.b_addr & 3) == 0 && (bp->b_bcount & 3) == 0) { 927 cmd |= CSR_DMA32; 928 dmaflags |= DMAGO_LWORD; 929 } else 930 dmaflags |= DMAGO_WORD; 931 dmago(hs->sc_dq.dq_ctlr, bp->b_un.b_addr, bp->b_bcount, dmaflags); 932 933 if (bp->b_flags & B_READ) { 934 cmd |= CSR_DMAIN; 935 phase = DATA_IN_PHASE; 936 } else 937 phase = DATA_OUT_PHASE; 938 /* 939 * DMA enable bits must be set after size and direction bits. 940 */ 941 hd->scsi_csr = cmd; 942 hd->scsi_csr |= (CSR_DE0 << hs->sc_dq.dq_ctlr); 943 /* 944 * Setup the SPC for the transfer. We don't want to take 945 * first a command complete then a service required interrupt 946 * at the end of the transfer so we try to disable the cmd 947 * complete by setting the transfer counter to more bytes 948 * than we expect. (XXX - This strategy may have to be 949 * modified to deal with devices that return variable length 950 * blocks, e.g., some tape drives.) 951 */ 952 cmd = SCMD_XFR; 953 i = (unsigned)bp->b_bcount; 954 if (pad) { 955 cmd |= SCMD_PAD; 956 /* 957 * XXX - If we don't do this, the last 2 or 4 bytes 958 * (depending on word/lword DMA) of a read get trashed. 959 * It looks like it is necessary for the DMA to complete 960 * before the SPC goes into "pad mode"??? Note: if we 961 * also do this on a write, the request never completes. 962 */ 963 if (bp->b_flags & B_READ) 964 i += 2; 965 #ifdef DEBUG 966 hs->sc_flags |= SCSI_PAD; 967 if (i & 1) 968 printf("scsi%d: odd byte count: %d bytes @ %d\n", 969 ctlr, i, bp->b_cylin); 970 #endif 971 } else 972 i += 4; 973 hd->scsi_tch = i >> 16; 974 hd->scsi_tcm = i >> 8; 975 hd->scsi_tcl = i; 976 hd->scsi_pctl = phase; 977 hd->scsi_tmod = 0; 978 hd->scsi_scmd = cmd; 979 hs->sc_flags |= SCSI_IO; 980 return (0); 981 abort: 982 scsiabort(hs, hd, "go"); 983 dmafree(&hs->sc_dq); 984 return (1); 985 } 986 987 void 988 scsidone(unit) 989 register int unit; 990 { 991 volatile register struct scsidevice *hd = 992 (struct scsidevice *)scsi_softc[unit].sc_hc->hp_addr; 993 994 #ifdef DEBUG 995 if (scsi_debug) 996 printf("scsi%d: done called!\n"); 997 #endif 998 /* dma operation is done -- turn off card dma */ 999 hd->scsi_csr &=~ (CSR_DE1|CSR_DE0); 1000 } 1001 1002 int 1003 scsiintr(unit) 1004 register int unit; 1005 { 1006 register struct scsi_softc *hs = &scsi_softc[unit]; 1007 volatile register struct scsidevice *hd = 1008 (struct scsidevice *)hs->sc_hc->hp_addr; 1009 register u_char ints; 1010 register struct devqueue *dq; 1011 1012 if ((hd->scsi_csr & (CSR_IE|CSR_IR)) != (CSR_IE|CSR_IR)) 1013 return (0); 1014 1015 ints = hd->scsi_ints; 1016 if ((ints & INTS_SRV_REQ) && (hs->sc_flags & SCSI_IO)) { 1017 /* 1018 * this should be the normal i/o completion case. 1019 * get the status & cmd complete msg then let the 1020 * device driver look at what happened. 1021 */ 1022 #ifdef DEBUG 1023 int len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | 1024 hd->scsi_tcl; 1025 if (!(hs->sc_flags & SCSI_PAD)) 1026 len -= 4; 1027 hs->sc_flags &=~ SCSI_PAD; 1028 #endif 1029 dq = hs->sc_sq.dq_forw; 1030 finishxfer(hs, hd, dq->dq_unit); 1031 hs->sc_flags &=~ SCSI_IO; 1032 dmafree(&hs->sc_dq); 1033 (dq->dq_driver->d_intr)(dq->dq_unit, hs->sc_stat[0]); 1034 } else { 1035 /* Something unexpected happened -- deal with it. */ 1036 hd->scsi_ints = ints; 1037 hd->scsi_csr = 0; 1038 scsierror(hs, hd, ints); 1039 scsiabort(hs, hd, "intr"); 1040 if (hs->sc_flags & SCSI_IO) { 1041 hs->sc_flags &=~ SCSI_IO; 1042 dmafree(&hs->sc_dq); 1043 dq = hs->sc_sq.dq_forw; 1044 (dq->dq_driver->d_intr)(dq->dq_unit, -1); 1045 } 1046 } 1047 return(1); 1048 } 1049 1050 void 1051 scsifree(dq) 1052 register struct devqueue *dq; 1053 { 1054 register struct devqueue *hq; 1055 1056 hq = &scsi_softc[dq->dq_ctlr].sc_sq; 1057 remque(dq); 1058 if ((dq = hq->dq_forw) != hq) 1059 (dq->dq_driver->d_start)(dq->dq_unit); 1060 } 1061 #endif 1062