1 /* 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Van Jacobson of Lawrence Berkeley Laboratory. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)scsi.c 7.5 (Berkeley) 05/04/91 11 */ 12 13 /* 14 * HP9000/3xx 98658 SCSI host adaptor driver. 15 */ 16 #include "scsi.h" 17 #if NSCSI > 0 18 19 #ifndef lint 20 static char rcsid[] = "$Header: scsi.c,v 1.4 91/01/17 12:50:18 mike Exp $"; 21 #endif 22 23 #include "sys/param.h" 24 #include "sys/systm.h" 25 #include "sys/buf.h" 26 #include "device.h" 27 28 #include "scsivar.h" 29 #include "scsireg.h" 30 #include "dmavar.h" 31 32 #include "../include/cpu.h" 33 #include "../hp300/isr.h" 34 35 /* 36 * SCSI delays 37 * In u-seconds, primarily for state changes on the SPC. 38 */ 39 #define SCSI_CMD_WAIT 1000 /* wait per step of 'immediate' cmds */ 40 #define SCSI_DATA_WAIT 1000 /* wait per data in/out step */ 41 #define SCSI_INIT_WAIT 50000 /* wait per step (both) during init */ 42 43 extern void isrlink(); 44 extern void _insque(); 45 extern void _remque(); 46 47 int scsiinit(), scsigo(), scsiintr(), scsixfer(); 48 void scsistart(), scsidone(), scsifree(), scsireset(); 49 struct driver scsidriver = { 50 scsiinit, "scsi", (int (*)())scsistart, scsigo, scsiintr, 51 (int (*)())scsidone, 52 }; 53 54 struct scsi_softc scsi_softc[NSCSI]; 55 struct isr scsi_isr[NSCSI]; 56 57 int scsi_cmd_wait = SCSI_CMD_WAIT; 58 int scsi_data_wait = SCSI_DATA_WAIT; 59 int scsi_init_wait = SCSI_INIT_WAIT; 60 61 int scsi_nosync = 1; /* inhibit sync xfers if 1 */ 62 int scsi_pridma = 0; /* use "priority" dma */ 63 64 #ifdef DEBUG 65 int scsi_debug = 0; 66 #define WAITHIST 67 #endif 68 69 #ifdef WAITHIST 70 #define MAXWAIT 1022 71 u_int ixstart_wait[MAXWAIT+2]; 72 u_int ixin_wait[MAXWAIT+2]; 73 u_int ixout_wait[MAXWAIT+2]; 74 u_int mxin_wait[MAXWAIT+2]; 75 u_int mxin2_wait[MAXWAIT+2]; 76 u_int cxin_wait[MAXWAIT+2]; 77 u_int fxfr_wait[MAXWAIT+2]; 78 u_int sgo_wait[MAXWAIT+2]; 79 #define HIST(h,w) (++h[((w)>MAXWAIT? MAXWAIT : ((w) < 0 ? -1 : (w))) + 1]); 80 #else 81 #define HIST(h,w) 82 #endif 83 84 #define b_cylin b_resid 85 86 static void 87 scsiabort(hs, hd, where) 88 register struct scsi_softc *hs; 89 volatile register struct scsidevice *hd; 90 char *where; 91 { 92 int len; 93 u_char junk; 94 95 printf("scsi%d: abort from %s: phase=0x%x, ssts=0x%x, ints=0x%x\n", 96 hs->sc_hc->hp_unit, where, hd->scsi_psns, hd->scsi_ssts, 97 hd->scsi_ints); 98 99 hd->scsi_ints = hd->scsi_ints; 100 hd->scsi_csr = 0; 101 if (hd->scsi_psns == 0 || (hd->scsi_ssts & SSTS_INITIATOR) == 0) 102 /* no longer connected to scsi target */ 103 return; 104 105 /* get the number of bytes remaining in current xfer + fudge */ 106 len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | hd->scsi_tcl; 107 108 /* for that many bus cycles, try to send an abort msg */ 109 for (len += 1024; (hd->scsi_ssts & SSTS_INITIATOR) && --len >= 0; ) { 110 hd->scsi_scmd = SCMD_SET_ATN; 111 while ((hd->scsi_psns & PSNS_REQ) == 0) { 112 if (! (hd->scsi_ssts & SSTS_INITIATOR)) 113 goto out; 114 DELAY(1); 115 } 116 if ((hd->scsi_psns & PHASE) == MESG_OUT_PHASE) 117 hd->scsi_scmd = SCMD_RST_ATN; 118 hd->scsi_pctl = hd->scsi_psns & PHASE; 119 if (hd->scsi_psns & PHASE_IO) { 120 /* one of the input phases - read & discard a byte */ 121 hd->scsi_scmd = SCMD_SET_ACK; 122 if (hd->scsi_tmod == 0) 123 while (hd->scsi_psns & PSNS_REQ) 124 DELAY(1); 125 junk = hd->scsi_temp; 126 } else { 127 /* one of the output phases - send an abort msg */ 128 hd->scsi_temp = MSG_ABORT; 129 hd->scsi_scmd = SCMD_SET_ACK; 130 if (hd->scsi_tmod == 0) 131 while (hd->scsi_psns & PSNS_REQ) 132 DELAY(1); 133 } 134 hd->scsi_scmd = SCMD_RST_ACK; 135 } 136 out: 137 /* 138 * Either the abort was successful & the bus is disconnected or 139 * the device didn't listen. If the latter, announce the problem. 140 * Either way, reset the card & the SPC. 141 */ 142 if (len < 0 && hs) 143 printf("scsi%d: abort failed. phase=0x%x, ssts=0x%x\n", 144 hs->sc_hc->hp_unit, hd->scsi_psns, hd->scsi_ssts); 145 146 if (! ((junk = hd->scsi_ints) & INTS_RESEL)) { 147 hd->scsi_sctl |= SCTL_CTRLRST; 148 DELAY(1); 149 hd->scsi_sctl &=~ SCTL_CTRLRST; 150 hd->scsi_hconf = 0; 151 hd->scsi_ints = hd->scsi_ints; 152 } 153 } 154 155 /* 156 * XXX Set/reset long delays. 157 * 158 * if delay == 0, reset default delays 159 * if delay < 0, set both delays to default long initialization values 160 * if delay > 0, set both delays to this value 161 * 162 * Used when a devices is expected to respond slowly (e.g. during 163 * initialization). 164 */ 165 void 166 scsi_delay(delay) 167 int delay; 168 { 169 static int saved_cmd_wait, saved_data_wait; 170 171 if (delay) { 172 saved_cmd_wait = scsi_cmd_wait; 173 saved_data_wait = scsi_data_wait; 174 if (delay > 0) 175 scsi_cmd_wait = scsi_data_wait = delay; 176 else 177 scsi_cmd_wait = scsi_data_wait = scsi_init_wait; 178 } else { 179 scsi_cmd_wait = saved_cmd_wait; 180 scsi_data_wait = saved_data_wait; 181 } 182 } 183 184 int 185 scsiinit(hc) 186 register struct hp_ctlr *hc; 187 { 188 register struct scsi_softc *hs = &scsi_softc[hc->hp_unit]; 189 register struct scsidevice *hd = (struct scsidevice *)hc->hp_addr; 190 191 if ((hd->scsi_id & ID_MASK) != SCSI_ID) 192 return(0); 193 hc->hp_ipl = SCSI_IPL(hd->scsi_csr); 194 hs->sc_hc = hc; 195 hs->sc_dq.dq_unit = hc->hp_unit; 196 hs->sc_dq.dq_driver = &scsidriver; 197 hs->sc_sq.dq_forw = hs->sc_sq.dq_back = &hs->sc_sq; 198 scsi_isr[hc->hp_unit].isr_intr = scsiintr; 199 scsi_isr[hc->hp_unit].isr_ipl = hc->hp_ipl; 200 scsi_isr[hc->hp_unit].isr_arg = hc->hp_unit; 201 isrlink(&scsi_isr[hc->hp_unit]); 202 scsireset(hc->hp_unit); 203 return(1); 204 } 205 206 void 207 scsireset(unit) 208 register int unit; 209 { 210 register struct scsi_softc *hs = &scsi_softc[unit]; 211 volatile register struct scsidevice *hd = 212 (struct scsidevice *)hs->sc_hc->hp_addr; 213 u_int i; 214 215 if (hs->sc_flags & SCSI_ALIVE) 216 scsiabort(hs, hd, "reset"); 217 218 printf("scsi%d: ", unit); 219 220 hd->scsi_id = 0xFF; 221 DELAY(100); 222 /* 223 * Disable interrupts then reset the FUJI chip. 224 */ 225 hd->scsi_csr = 0; 226 hd->scsi_sctl = SCTL_DISABLE | SCTL_CTRLRST; 227 hd->scsi_scmd = 0; 228 hd->scsi_tmod = 0; 229 hd->scsi_pctl = 0; 230 hd->scsi_temp = 0; 231 hd->scsi_tch = 0; 232 hd->scsi_tcm = 0; 233 hd->scsi_tcl = 0; 234 hd->scsi_ints = 0; 235 236 if ((hd->scsi_id & ID_WORD_DMA) == 0) { 237 hs->sc_flags |= SCSI_DMA32; 238 printf("32 bit dma, "); 239 } 240 241 /* Determine Max Synchronous Transfer Rate */ 242 if (scsi_nosync) 243 i = 3; 244 else 245 i = SCSI_SYNC_XFER(hd->scsi_hconf); 246 switch (i) { 247 case 0: 248 hs->sc_sync = TMOD_SYNC | 0x3e; /* 250 nsecs */ 249 printf("250ns sync"); 250 break; 251 case 1: 252 hs->sc_sync = TMOD_SYNC | 0x5e; /* 375 nsecs */ 253 printf("375ns sync"); 254 break; 255 case 2: 256 hs->sc_sync = TMOD_SYNC | 0x7d; /* 500 nsecs */ 257 printf("500ns sync"); 258 break; 259 case 3: 260 hs->sc_sync = 0; 261 printf("async"); 262 break; 263 } 264 265 /* 266 * Configure the FUJI chip with its SCSI address, all 267 * interrupts enabled & appropriate parity. 268 */ 269 i = (~hd->scsi_hconf) & 0x7; 270 hs->sc_scsi_addr = 1 << i; 271 hd->scsi_bdid = i; 272 if (hd->scsi_hconf & HCONF_PARITY) 273 hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | 274 SCTL_SEL_ENAB | SCTL_RESEL_ENAB | 275 SCTL_INTR_ENAB | SCTL_PARITY_ENAB; 276 else { 277 hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB | 278 SCTL_SEL_ENAB | SCTL_RESEL_ENAB | 279 SCTL_INTR_ENAB; 280 printf(", no parity"); 281 } 282 hd->scsi_sctl &=~ SCTL_DISABLE; 283 284 printf(", scsi id %d\n", i); 285 hs->sc_flags |= SCSI_ALIVE; 286 } 287 288 static void 289 scsierror(hs, hd, ints) 290 register struct scsi_softc *hs; 291 volatile register struct scsidevice *hd; 292 u_char ints; 293 { 294 int unit = hs->sc_hc->hp_unit; 295 char *sep = ""; 296 297 printf("scsi%d: ", unit); 298 if (ints & INTS_RST) { 299 DELAY(100); 300 if (hd->scsi_hconf & HCONF_SD) 301 printf("spurious RST interrupt"); 302 else 303 printf("hardware error - check fuse"); 304 sep = ", "; 305 } 306 if ((ints & INTS_HARD_ERR) || hd->scsi_serr) { 307 if (hd->scsi_serr & SERR_SCSI_PAR) { 308 printf("%sparity err", sep); 309 sep = ", "; 310 } 311 if (hd->scsi_serr & SERR_SPC_PAR) { 312 printf("%sSPC parity err", sep); 313 sep = ", "; 314 } 315 if (hd->scsi_serr & SERR_TC_PAR) { 316 printf("%sTC parity err", sep); 317 sep = ", "; 318 } 319 if (hd->scsi_serr & SERR_PHASE_ERR) { 320 printf("%sphase err", sep); 321 sep = ", "; 322 } 323 if (hd->scsi_serr & SERR_SHORT_XFR) { 324 printf("%ssync short transfer err", sep); 325 sep = ", "; 326 } 327 if (hd->scsi_serr & SERR_OFFSET) { 328 printf("%ssync offset error", sep); 329 sep = ", "; 330 } 331 } 332 if (ints & INTS_TIMEOUT) 333 printf("%sSPC select timeout error", sep); 334 if (ints & INTS_SRV_REQ) 335 printf("%sspurious SRV_REQ interrupt", sep); 336 if (ints & INTS_CMD_DONE) 337 printf("%sspurious CMD_DONE interrupt", sep); 338 if (ints & INTS_DISCON) 339 printf("%sspurious disconnect interrupt", sep); 340 if (ints & INTS_RESEL) 341 printf("%sspurious reselect interrupt", sep); 342 if (ints & INTS_SEL) 343 printf("%sspurious select interrupt", sep); 344 printf("\n"); 345 } 346 347 static int 348 issue_select(hd, target, our_addr) 349 volatile register struct scsidevice *hd; 350 u_char target, our_addr; 351 { 352 if (hd->scsi_ssts & (SSTS_INITIATOR|SSTS_TARGET|SSTS_BUSY)) 353 return (1); 354 355 if (hd->scsi_ints & INTS_DISCON) 356 hd->scsi_ints = INTS_DISCON; 357 358 hd->scsi_pctl = 0; 359 hd->scsi_temp = (1 << target) | our_addr; 360 /* select timeout is hardcoded to 2ms */ 361 hd->scsi_tch = 0; 362 hd->scsi_tcm = 32; 363 hd->scsi_tcl = 4; 364 365 hd->scsi_scmd = SCMD_SELECT; 366 return (0); 367 } 368 369 static int 370 wait_for_select(hd) 371 volatile register struct scsidevice *hd; 372 { 373 u_char ints; 374 375 while ((ints = hd->scsi_ints) == 0) 376 DELAY(1); 377 hd->scsi_ints = ints; 378 return (!(hd->scsi_ssts & SSTS_INITIATOR)); 379 } 380 381 static int 382 ixfer_start(hd, len, phase, wait) 383 volatile register struct scsidevice *hd; 384 int len; 385 u_char phase; 386 register int wait; 387 { 388 389 hd->scsi_tch = len >> 16; 390 hd->scsi_tcm = len >> 8; 391 hd->scsi_tcl = len; 392 hd->scsi_pctl = phase; 393 hd->scsi_tmod = 0; /*XXX*/ 394 hd->scsi_scmd = SCMD_XFR | SCMD_PROG_XFR; 395 396 /* wait for xfer to start or svc_req interrupt */ 397 while ((hd->scsi_ssts & SSTS_BUSY) == 0) { 398 if (hd->scsi_ints || --wait < 0) { 399 #ifdef DEBUG 400 if (scsi_debug) 401 printf("ixfer_start fail: i%x, w%d\n", 402 hd->scsi_ints, wait); 403 #endif 404 HIST(ixstart_wait, wait) 405 return (0); 406 } 407 DELAY(1); 408 } 409 HIST(ixstart_wait, wait) 410 return (1); 411 } 412 413 static int 414 ixfer_out(hd, len, buf) 415 volatile register struct scsidevice *hd; 416 int len; 417 register u_char *buf; 418 { 419 register int wait = scsi_data_wait; 420 421 for (; len > 0; --len) { 422 while (hd->scsi_ssts & SSTS_DREG_FULL) { 423 if (hd->scsi_ints || --wait < 0) { 424 #ifdef DEBUG 425 if (scsi_debug) 426 printf("ixfer_out fail: l%d i%x w%d\n", 427 len, hd->scsi_ints, wait); 428 #endif 429 HIST(ixout_wait, wait) 430 return (len); 431 } 432 DELAY(1); 433 } 434 hd->scsi_dreg = *buf++; 435 } 436 HIST(ixout_wait, wait) 437 return (0); 438 } 439 440 static void 441 ixfer_in(hd, len, buf) 442 volatile register struct scsidevice *hd; 443 int len; 444 register u_char *buf; 445 { 446 register int wait = scsi_data_wait; 447 448 for (; len > 0; --len) { 449 while (hd->scsi_ssts & SSTS_DREG_EMPTY) { 450 if (hd->scsi_ints || --wait < 0) { 451 while (! (hd->scsi_ssts & SSTS_DREG_EMPTY)) { 452 *buf++ = hd->scsi_dreg; 453 --len; 454 } 455 #ifdef DEBUG 456 if (scsi_debug) 457 printf("ixfer_in fail: l%d i%x w%d\n", 458 len, hd->scsi_ints, wait); 459 #endif 460 HIST(ixin_wait, wait) 461 return; 462 } 463 DELAY(1); 464 } 465 *buf++ = hd->scsi_dreg; 466 } 467 HIST(ixin_wait, wait) 468 } 469 470 static int 471 mxfer_in(hd, len, buf, phase) 472 volatile register struct scsidevice *hd; 473 register int len; 474 register u_char *buf; 475 register u_char phase; 476 { 477 register int wait = scsi_cmd_wait; 478 register int i; 479 480 hd->scsi_tmod = 0; 481 for (i = 0; i < len; ++i) { 482 /* 483 * manual sez: reset ATN before ACK is sent. 484 */ 485 if (hd->scsi_psns & PSNS_ATN) 486 hd->scsi_scmd = SCMD_RST_ATN; 487 /* 488 * wait for the request line (which says the target 489 * wants to give us data). If the phase changes while 490 * we're waiting, we're done. 491 */ 492 while ((hd->scsi_psns & PSNS_REQ) == 0) { 493 if (--wait < 0) { 494 HIST(mxin_wait, wait) 495 return (-1); 496 } 497 if ((hd->scsi_psns & PHASE) != phase || 498 (hd->scsi_ssts & SSTS_INITIATOR) == 0) 499 goto out; 500 501 DELAY(1); 502 } 503 /* 504 * set ack (which says we're ready for the data, wait for 505 * req to go away (target says data is available), grab the 506 * data, then reset ack (say we've got the data). 507 */ 508 hd->scsi_pctl = phase; 509 hd->scsi_scmd = SCMD_SET_ACK; 510 while (hd->scsi_psns & PSNS_REQ) { 511 if (--wait < 0) { 512 HIST(mxin_wait, wait) 513 return (-2); 514 } 515 DELAY(1); 516 } 517 *buf++ = hd->scsi_temp; 518 hd->scsi_scmd = SCMD_RST_ACK; 519 } 520 out: 521 HIST(mxin_wait, wait) 522 /* 523 * Wait for manual transfer to finish. 524 * Avoids occasional "unexpected phase" errors in finishxfer 525 * formerly addressed by per-slave delays. 526 */ 527 wait = scsi_cmd_wait; 528 while ((hd->scsi_ssts & SSTS_ACTIVE) == SSTS_INITIATOR) { 529 if (--wait < 0) 530 break; 531 DELAY(1); 532 } 533 HIST(mxin2_wait, wait) 534 return (i); 535 } 536 537 /* 538 * SCSI 'immediate' command: issue a command to some SCSI device 539 * and get back an 'immediate' response (i.e., do programmed xfer 540 * to get the response data). 'cbuf' is a buffer containing a scsi 541 * command of length clen bytes. 'buf' is a buffer of length 'len' 542 * bytes for data. The transfer direction is determined by the device 543 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 544 * command must supply no data. 'xferphase' is the bus phase the 545 * caller expects to happen after the command is issued. It should 546 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 547 */ 548 static int 549 scsiicmd(hs, target, cbuf, clen, buf, len, xferphase) 550 struct scsi_softc *hs; 551 int target; 552 u_char *cbuf; 553 int clen; 554 u_char *buf; 555 int len; 556 u_char xferphase; 557 { 558 volatile register struct scsidevice *hd = 559 (struct scsidevice *)hs->sc_hc->hp_addr; 560 u_char phase, ints; 561 register int wait; 562 563 /* select the SCSI bus (it's an error if bus isn't free) */ 564 if (issue_select(hd, target, hs->sc_scsi_addr)) 565 return (-1); 566 if (wait_for_select(hd)) 567 return (-1); 568 /* 569 * Wait for a phase change (or error) then let the device 570 * sequence us through the various SCSI phases. 571 */ 572 hs->sc_stat[0] = 0xff; 573 hs->sc_msg[0] = 0xff; 574 phase = CMD_PHASE; 575 while (1) { 576 wait = scsi_cmd_wait; 577 switch (phase) { 578 579 case CMD_PHASE: 580 if (ixfer_start(hd, clen, phase, wait)) 581 if (ixfer_out(hd, clen, cbuf)) 582 goto abort; 583 phase = xferphase; 584 break; 585 586 case DATA_IN_PHASE: 587 if (len <= 0) 588 goto abort; 589 wait = scsi_data_wait; 590 if (ixfer_start(hd, len, phase, wait) || 591 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) 592 ixfer_in(hd, len, buf); 593 phase = STATUS_PHASE; 594 break; 595 596 case DATA_OUT_PHASE: 597 if (len <= 0) 598 goto abort; 599 wait = scsi_data_wait; 600 if (ixfer_start(hd, len, phase, wait)) { 601 if (ixfer_out(hd, len, buf)) 602 goto abort; 603 } 604 phase = STATUS_PHASE; 605 break; 606 607 case STATUS_PHASE: 608 wait = scsi_data_wait; 609 if (ixfer_start(hd, sizeof(hs->sc_stat), phase, wait) || 610 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) 611 ixfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat); 612 phase = MESG_IN_PHASE; 613 break; 614 615 case MESG_IN_PHASE: 616 if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait) || 617 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { 618 ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); 619 hd->scsi_scmd = SCMD_RST_ACK; 620 } 621 phase = BUS_FREE_PHASE; 622 break; 623 624 case BUS_FREE_PHASE: 625 goto out; 626 627 default: 628 printf("scsi%d: unexpected phase %d in icmd from %d\n", 629 hs->sc_hc->hp_unit, phase, target); 630 goto abort; 631 } 632 /* wait for last command to complete */ 633 while ((ints = hd->scsi_ints) == 0) { 634 if (--wait < 0) { 635 HIST(cxin_wait, wait) 636 goto abort; 637 } 638 DELAY(1); 639 } 640 HIST(cxin_wait, wait) 641 hd->scsi_ints = ints; 642 if (ints & INTS_SRV_REQ) 643 phase = hd->scsi_psns & PHASE; 644 else if (ints & INTS_DISCON) 645 goto out; 646 else if ((ints & INTS_CMD_DONE) == 0) { 647 scsierror(hs, hd, ints); 648 goto abort; 649 } 650 } 651 abort: 652 scsiabort(hs, hd, "icmd"); 653 out: 654 return (hs->sc_stat[0]); 655 } 656 657 /* 658 * Finish SCSI xfer command: After the completion interrupt from 659 * a read/write operation, sequence through the final phases in 660 * programmed i/o. This routine is a lot like scsiicmd except we 661 * skip (and don't allow) the select, cmd out and data in/out phases. 662 */ 663 static void 664 finishxfer(hs, hd, target) 665 struct scsi_softc *hs; 666 volatile register struct scsidevice *hd; 667 int target; 668 { 669 u_char phase, ints; 670 671 /* 672 * We specified padding xfer so we ended with either a phase 673 * change interrupt (normal case) or an error interrupt (handled 674 * elsewhere). Reset the board dma logic then try to get the 675 * completion status & command done msg. The reset confuses 676 * the SPC REQ/ACK logic so we have to do any status/msg input 677 * operations via 'manual xfer'. 678 */ 679 if (hd->scsi_ssts & SSTS_BUSY) { 680 int wait = scsi_cmd_wait; 681 682 /* wait for dma operation to finish */ 683 while (hd->scsi_ssts & SSTS_BUSY) { 684 if (--wait < 0) { 685 #ifdef DEBUG 686 if (scsi_debug) 687 printf("finishxfer fail: ssts %x\n", 688 hd->scsi_ssts); 689 #endif 690 HIST(fxfr_wait, wait) 691 goto abort; 692 } 693 } 694 HIST(fxfr_wait, wait) 695 } 696 hd->scsi_scmd |= SCMD_PROG_XFR; 697 hd->scsi_sctl |= SCTL_CTRLRST; 698 DELAY(1); 699 hd->scsi_sctl &=~ SCTL_CTRLRST; 700 hd->scsi_hconf = 0; 701 hs->sc_stat[0] = 0xff; 702 hs->sc_msg[0] = 0xff; 703 hd->scsi_csr = 0; 704 hd->scsi_ints = ints = hd->scsi_ints; 705 while (1) { 706 phase = hd->scsi_psns & PHASE; 707 switch (phase) { 708 709 case STATUS_PHASE: 710 if (mxfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat, 711 phase) <= 0) 712 goto abort; 713 break; 714 715 case MESG_IN_PHASE: 716 if (mxfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg, 717 phase) < 0) 718 goto abort; 719 break; 720 721 case BUS_FREE_PHASE: 722 return; 723 724 default: 725 printf("scsi%d: unexpected phase %d in finishxfer from %d\n", 726 hs->sc_hc->hp_unit, phase, target); 727 goto abort; 728 } 729 if (ints = hd->scsi_ints) { 730 hd->scsi_ints = ints; 731 if (ints & INTS_DISCON) 732 return; 733 else if (ints & ~(INTS_SRV_REQ|INTS_CMD_DONE)) { 734 scsierror(hs, hd, ints); 735 break; 736 } 737 } 738 if ((hd->scsi_ssts & SSTS_INITIATOR) == 0) 739 return; 740 } 741 abort: 742 scsiabort(hs, hd, "finishxfer"); 743 hs->sc_stat[0] = 0xfe; 744 } 745 746 int 747 scsi_test_unit_rdy(ctlr, slave, unit) 748 int ctlr, slave, unit; 749 { 750 register struct scsi_softc *hs = &scsi_softc[ctlr]; 751 static struct scsi_cdb6 cdb = { CMD_TEST_UNIT_READY }; 752 753 cdb.lun = unit; 754 return (scsiicmd(hs, slave, &cdb, sizeof(cdb), (u_char *)0, 0, 755 STATUS_PHASE)); 756 } 757 758 int 759 scsi_request_sense(ctlr, slave, unit, buf, len) 760 int ctlr, slave, unit; 761 u_char *buf; 762 unsigned len; 763 { 764 register struct scsi_softc *hs = &scsi_softc[ctlr]; 765 static struct scsi_cdb6 cdb = { CMD_REQUEST_SENSE }; 766 767 cdb.lun = unit; 768 cdb.len = len; 769 return (scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE)); 770 } 771 772 int 773 scsi_immed_command(ctlr, slave, unit, cdb, buf, len, rd) 774 int ctlr, slave, unit; 775 struct scsi_fmt_cdb *cdb; 776 u_char *buf; 777 unsigned len; 778 { 779 register struct scsi_softc *hs = &scsi_softc[ctlr]; 780 781 cdb->cdb[1] |= unit << 5; 782 return (scsiicmd(hs, slave, cdb->cdb, cdb->len, buf, len, 783 rd != 0? DATA_IN_PHASE : DATA_OUT_PHASE)); 784 } 785 786 /* 787 * The following routines are test-and-transfer i/o versions of read/write 788 * for things like reading disk labels and writing core dumps. The 789 * routine scsigo should be used for normal data transfers, NOT these 790 * routines. 791 */ 792 int 793 scsi_tt_read(ctlr, slave, unit, buf, len, blk, bshift) 794 int ctlr, slave, unit; 795 u_char *buf; 796 u_int len; 797 daddr_t blk; 798 int bshift; 799 { 800 register struct scsi_softc *hs = &scsi_softc[ctlr]; 801 struct scsi_cdb10 cdb; 802 int stat; 803 int old_wait = scsi_data_wait; 804 805 scsi_data_wait = 300000; 806 bzero(&cdb, sizeof(cdb)); 807 cdb.cmd = CMD_READ_EXT; 808 cdb.lun = unit; 809 blk >>= bshift; 810 cdb.lbah = blk >> 24; 811 cdb.lbahm = blk >> 16; 812 cdb.lbalm = blk >> 8; 813 cdb.lbal = blk; 814 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 815 cdb.lenl = len >> (DEV_BSHIFT + bshift); 816 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE); 817 scsi_data_wait = old_wait; 818 return (stat); 819 } 820 821 int 822 scsi_tt_write(ctlr, slave, unit, buf, len, blk, bshift) 823 int ctlr, slave, unit; 824 u_char *buf; 825 u_int len; 826 daddr_t blk; 827 int bshift; 828 { 829 register struct scsi_softc *hs = &scsi_softc[ctlr]; 830 struct scsi_cdb10 cdb; 831 int stat; 832 int old_wait = scsi_data_wait; 833 834 scsi_data_wait = 300000; 835 836 bzero(&cdb, sizeof(cdb)); 837 cdb.cmd = CMD_WRITE_EXT; 838 cdb.lun = unit; 839 blk >>= bshift; 840 cdb.lbah = blk >> 24; 841 cdb.lbahm = blk >> 16; 842 cdb.lbalm = blk >> 8; 843 cdb.lbal = blk; 844 cdb.lenh = len >> (8 + DEV_BSHIFT + bshift); 845 cdb.lenl = len >> (DEV_BSHIFT + bshift); 846 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_OUT_PHASE); 847 scsi_data_wait = old_wait; 848 return (stat); 849 } 850 851 int 852 scsireq(dq) 853 register struct devqueue *dq; 854 { 855 register struct devqueue *hq; 856 857 hq = &scsi_softc[dq->dq_ctlr].sc_sq; 858 insque(dq, hq->dq_back); 859 if (dq->dq_back == hq) 860 return(1); 861 return(0); 862 } 863 864 int 865 scsiustart(unit) 866 int unit; 867 { 868 register struct scsi_softc *hs = &scsi_softc[unit]; 869 870 hs->sc_dq.dq_ctlr = DMA0 | DMA1; 871 if (dmareq(&hs->sc_dq)) 872 return(1); 873 return(0); 874 } 875 876 void 877 scsistart(unit) 878 int unit; 879 { 880 register struct devqueue *dq; 881 882 dq = scsi_softc[unit].sc_sq.dq_forw; 883 (dq->dq_driver->d_go)(dq->dq_unit); 884 } 885 886 int 887 scsigo(ctlr, slave, unit, bp, cdb, pad) 888 int ctlr, slave, unit; 889 struct buf *bp; 890 struct scsi_fmt_cdb *cdb; 891 int pad; 892 { 893 register struct scsi_softc *hs = &scsi_softc[ctlr]; 894 volatile register struct scsidevice *hd = 895 (struct scsidevice *)hs->sc_hc->hp_addr; 896 int i, dmaflags; 897 u_char phase, ints, cmd; 898 899 cdb->cdb[1] |= unit << 5; 900 901 /* select the SCSI bus (it's an error if bus isn't free) */ 902 if (issue_select(hd, slave, hs->sc_scsi_addr) || wait_for_select(hd)) { 903 dmafree(&hs->sc_dq); 904 return (1); 905 } 906 /* 907 * Wait for a phase change (or error) then let the device 908 * sequence us through command phase (we may have to take 909 * a msg in/out before doing the command). If the disk has 910 * to do a seek, it may be a long time until we get a change 911 * to data phase so, in the absense of an explicit phase 912 * change, we assume data phase will be coming up and tell 913 * the SPC to start a transfer whenever it does. We'll get 914 * a service required interrupt later if this assumption is 915 * wrong. Otherwise we'll get a service required int when 916 * the transfer changes to status phase. 917 */ 918 phase = CMD_PHASE; 919 while (1) { 920 register int wait = scsi_cmd_wait; 921 922 switch (phase) { 923 924 case CMD_PHASE: 925 if (ixfer_start(hd, cdb->len, phase, wait)) 926 if (ixfer_out(hd, cdb->len, cdb->cdb)) 927 goto abort; 928 break; 929 930 case MESG_IN_PHASE: 931 if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait)|| 932 !(hd->scsi_ssts & SSTS_DREG_EMPTY)) { 933 ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg); 934 hd->scsi_scmd = SCMD_RST_ACK; 935 } 936 phase = BUS_FREE_PHASE; 937 break; 938 939 case DATA_IN_PHASE: 940 case DATA_OUT_PHASE: 941 goto out; 942 943 default: 944 printf("scsi%d: unexpected phase %d in go from %d\n", 945 hs->sc_hc->hp_unit, phase, slave); 946 goto abort; 947 } 948 while ((ints = hd->scsi_ints) == 0) { 949 if (--wait < 0) { 950 HIST(sgo_wait, wait) 951 goto abort; 952 } 953 DELAY(1); 954 } 955 HIST(sgo_wait, wait) 956 hd->scsi_ints = ints; 957 if (ints & INTS_SRV_REQ) 958 phase = hd->scsi_psns & PHASE; 959 else if (ints & INTS_CMD_DONE) 960 goto out; 961 else { 962 scsierror(hs, hd, ints); 963 goto abort; 964 } 965 } 966 out: 967 /* 968 * Reset the card dma logic, setup the dma channel then 969 * get the dio part of the card set for a dma xfer. 970 */ 971 hd->scsi_hconf = 0; 972 cmd = CSR_IE; 973 dmaflags = DMAGO_NOINT; 974 if (scsi_pridma) 975 dmaflags |= DMAGO_PRI; 976 if (bp->b_flags & B_READ) 977 dmaflags |= DMAGO_READ; 978 if ((hs->sc_flags & SCSI_DMA32) && 979 ((int)bp->b_un.b_addr & 3) == 0 && (bp->b_bcount & 3) == 0) { 980 cmd |= CSR_DMA32; 981 dmaflags |= DMAGO_LWORD; 982 } else 983 dmaflags |= DMAGO_WORD; 984 dmago(hs->sc_dq.dq_ctlr, bp->b_un.b_addr, bp->b_bcount, dmaflags); 985 986 if (bp->b_flags & B_READ) { 987 cmd |= CSR_DMAIN; 988 phase = DATA_IN_PHASE; 989 } else 990 phase = DATA_OUT_PHASE; 991 /* 992 * DMA enable bits must be set after size and direction bits. 993 */ 994 hd->scsi_csr = cmd; 995 hd->scsi_csr |= (CSR_DE0 << hs->sc_dq.dq_ctlr); 996 /* 997 * Setup the SPC for the transfer. We don't want to take 998 * first a command complete then a service required interrupt 999 * at the end of the transfer so we try to disable the cmd 1000 * complete by setting the transfer counter to more bytes 1001 * than we expect. (XXX - This strategy may have to be 1002 * modified to deal with devices that return variable length 1003 * blocks, e.g., some tape drives.) 1004 */ 1005 cmd = SCMD_XFR; 1006 i = (unsigned)bp->b_bcount; 1007 if (pad) { 1008 cmd |= SCMD_PAD; 1009 /* 1010 * XXX - If we don't do this, the last 2 or 4 bytes 1011 * (depending on word/lword DMA) of a read get trashed. 1012 * It looks like it is necessary for the DMA to complete 1013 * before the SPC goes into "pad mode"??? Note: if we 1014 * also do this on a write, the request never completes. 1015 */ 1016 if (bp->b_flags & B_READ) 1017 i += 2; 1018 #ifdef DEBUG 1019 hs->sc_flags |= SCSI_PAD; 1020 if (i & 1) 1021 printf("scsi%d: odd byte count: %d bytes @ %d\n", 1022 ctlr, i, bp->b_cylin); 1023 #endif 1024 } else 1025 i += 4; 1026 hd->scsi_tch = i >> 16; 1027 hd->scsi_tcm = i >> 8; 1028 hd->scsi_tcl = i; 1029 hd->scsi_pctl = phase; 1030 hd->scsi_tmod = 0; 1031 hd->scsi_scmd = cmd; 1032 hs->sc_flags |= SCSI_IO; 1033 return (0); 1034 abort: 1035 scsiabort(hs, hd, "go"); 1036 dmafree(&hs->sc_dq); 1037 return (1); 1038 } 1039 1040 void 1041 scsidone(unit) 1042 register int unit; 1043 { 1044 volatile register struct scsidevice *hd = 1045 (struct scsidevice *)scsi_softc[unit].sc_hc->hp_addr; 1046 1047 #ifdef DEBUG 1048 if (scsi_debug) 1049 printf("scsi%d: done called!\n"); 1050 #endif 1051 /* dma operation is done -- turn off card dma */ 1052 hd->scsi_csr &=~ (CSR_DE1|CSR_DE0); 1053 } 1054 1055 int 1056 scsiintr(unit) 1057 register int unit; 1058 { 1059 register struct scsi_softc *hs = &scsi_softc[unit]; 1060 volatile register struct scsidevice *hd = 1061 (struct scsidevice *)hs->sc_hc->hp_addr; 1062 register u_char ints; 1063 register struct devqueue *dq; 1064 1065 if ((hd->scsi_csr & (CSR_IE|CSR_IR)) != (CSR_IE|CSR_IR)) 1066 return (0); 1067 1068 ints = hd->scsi_ints; 1069 if ((ints & INTS_SRV_REQ) && (hs->sc_flags & SCSI_IO)) { 1070 /* 1071 * this should be the normal i/o completion case. 1072 * get the status & cmd complete msg then let the 1073 * device driver look at what happened. 1074 */ 1075 #ifdef DEBUG 1076 int len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | 1077 hd->scsi_tcl; 1078 if (!(hs->sc_flags & SCSI_PAD)) 1079 len -= 4; 1080 hs->sc_flags &=~ SCSI_PAD; 1081 #endif 1082 dq = hs->sc_sq.dq_forw; 1083 finishxfer(hs, hd, dq->dq_slave); 1084 hs->sc_flags &=~ SCSI_IO; 1085 dmafree(&hs->sc_dq); 1086 (dq->dq_driver->d_intr)(dq->dq_unit, hs->sc_stat[0]); 1087 } else { 1088 /* Something unexpected happened -- deal with it. */ 1089 hd->scsi_ints = ints; 1090 hd->scsi_csr = 0; 1091 scsierror(hs, hd, ints); 1092 scsiabort(hs, hd, "intr"); 1093 if (hs->sc_flags & SCSI_IO) { 1094 hs->sc_flags &=~ SCSI_IO; 1095 dmafree(&hs->sc_dq); 1096 dq = hs->sc_sq.dq_forw; 1097 (dq->dq_driver->d_intr)(dq->dq_unit, -1); 1098 } 1099 } 1100 return(1); 1101 } 1102 1103 void 1104 scsifree(dq) 1105 register struct devqueue *dq; 1106 { 1107 register struct devqueue *hq; 1108 1109 hq = &scsi_softc[dq->dq_ctlr].sc_sq; 1110 remque(dq); 1111 if ((dq = hq->dq_forw) != hq) 1112 (dq->dq_driver->d_start)(dq->dq_unit); 1113 } 1114 1115 /* 1116 * (XXX) The following routine is needed for the SCSI tape driver 1117 * to read odd-size records. 1118 */ 1119 1120 #include "st.h" 1121 #if NST > 0 1122 int 1123 scsi_tt_oddio(ctlr, slave, unit, buf, len, b_flags, freedma) 1124 int ctlr, slave, unit, b_flags; 1125 u_char *buf; 1126 u_int len; 1127 { 1128 register struct scsi_softc *hs = &scsi_softc[ctlr]; 1129 struct scsi_cdb6 cdb; 1130 u_char iphase; 1131 int stat; 1132 1133 /* 1134 * First free any DMA channel that was allocated. 1135 * We can't use DMA to do this transfer. 1136 */ 1137 if (freedma) 1138 dmafree(hs->sc_dq); 1139 /* 1140 * Initialize command block 1141 */ 1142 bzero(&cdb, sizeof(cdb)); 1143 cdb.lun = unit; 1144 cdb.lbam = (len >> 16) & 0xff; 1145 cdb.lbal = (len >> 8) & 0xff; 1146 cdb.len = len & 0xff; 1147 if (buf == 0) { 1148 cdb.cmd = CMD_SPACE; 1149 cdb.lun |= 0x00; 1150 len = 0; 1151 iphase = MESG_IN_PHASE; 1152 } else if (b_flags & B_READ) { 1153 cdb.cmd = CMD_READ; 1154 iphase = DATA_IN_PHASE; 1155 } else { 1156 cdb.cmd = CMD_WRITE; 1157 iphase = DATA_OUT_PHASE; 1158 } 1159 /* 1160 * Perform command (with very long delays) 1161 */ 1162 scsi_delay(30000000); 1163 stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, iphase); 1164 scsi_delay(0); 1165 return (stat); 1166 } 1167 #endif 1168 #endif 1169