1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1986, 1990, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * %sccs.include.redist.c% 11 * 12 * from: Utah $Hdr: pte.h 1.13 92/01/20$ 13 * 14 * @(#)pte.h 8.1 (Berkeley) 06/10/93 15 */ 16 17 /* 18 * HP300 hardware segment/page table entries 19 */ 20 21 struct ste { 22 unsigned int sg_pfnum:20; /* page table frame number */ 23 unsigned int :8; /* reserved at 0 */ 24 unsigned int :1; /* reserved at 1 */ 25 unsigned int sg_prot:1; /* write protect bit */ 26 unsigned int sg_v:2; /* valid bits */ 27 }; 28 29 struct ste40 { 30 unsigned int sg_ptaddr:24; /* page table page addr */ 31 unsigned int :4; /* reserved at 0 */ 32 unsigned int sg_u; /* hardware modified (dirty) bit */ 33 unsigned int sg_prot:1; /* write protect bit */ 34 unsigned int sg_v:2; /* valid bits */ 35 }; 36 37 struct pte { 38 unsigned int pg_pfnum:20; /* page frame number or 0 */ 39 unsigned int :3; 40 unsigned int pg_w:1; /* is wired */ 41 unsigned int :1; /* reserved at zero */ 42 unsigned int pg_ci:1; /* cache inhibit bit */ 43 unsigned int :1; /* reserved at zero */ 44 unsigned int pg_m:1; /* hardware modified (dirty) bit */ 45 unsigned int pg_u:1; /* hardware used (reference) bit */ 46 unsigned int pg_prot:1; /* write protect bit */ 47 unsigned int pg_v:2; /* valid bit */ 48 }; 49 50 typedef struct ste st_entry_t; /* segment table entry */ 51 typedef struct pte pt_entry_t; /* Mach page table entry */ 52 53 #define PT_ENTRY_NULL ((pt_entry_t *) 0) 54 #define ST_ENTRY_NULL ((st_entry_t *) 0) 55 56 #define SG_V 0x00000002 /* segment is valid */ 57 #define SG_NV 0x00000000 58 #define SG_PROT 0x00000004 /* access protection mask */ 59 #define SG_RO 0x00000004 60 #define SG_RW 0x00000000 61 #define SG_U 0x00000008 /* modified bit (68040) */ 62 #define SG_FRAME 0xfffff000 63 #define SG_IMASK 0xffc00000 64 #define SG_ISHIFT 22 65 #define SG_PMASK 0x003ff000 66 #define SG_PSHIFT 12 67 68 /* 68040 additions */ 69 #define SG4_MASK1 0xfe000000 70 #define SG4_SHIFT1 25 71 #define SG4_MASK2 0x01fc0000 72 #define SG4_SHIFT2 18 73 #define SG4_MASK3 0x0003f000 74 #define SG4_SHIFT3 12 75 #define SG4_ADDR1 0xfffffe00 76 #define SG4_ADDR2 0xffffff00 77 #define SG4_LEV1SIZE 128 78 #define SG4_LEV2SIZE 128 79 #define SG4_LEV3SIZE 64 80 81 #define PG_V 0x00000001 82 #define PG_NV 0x00000000 83 #define PG_PROT 0x00000004 84 #define PG_U 0x00000008 85 #define PG_M 0x00000010 86 #define PG_W 0x00000100 87 #define PG_RO 0x00000004 88 #define PG_RW 0x00000000 89 #define PG_FRAME 0xfffff000 90 #define PG_CI 0x00000040 91 #define PG_SHIFT 12 92 #define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT) 93 94 /* 68040 additions */ 95 #define PG_CMASK 0x00000060 /* cache mode mask */ 96 #define PG_CWT 0x00000000 /* writethrough caching */ 97 #define PG_CCB 0x00000020 /* copyback caching */ 98 #define PG_CIS 0x00000040 /* cache inhibited serialized */ 99 #define PG_CIN 0x00000060 /* cache inhibited nonserialized */ 100 #define PG_SO 0x00000080 /* supervisor only */ 101 102 #define HP_STSIZE (MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t)) 103 /* user process segment table size */ 104 #define HP_MAX_PTSIZE 0x400000 /* max size of UPT */ 105 #define HP_MAX_KPTSIZE 0x100000 /* max memory to allocate to KPT */ 106 #define HP_PTBASE 0x10000000 /* UPT map base address */ 107 #define HP_PTMAXSIZE 0x70000000 /* UPT map maximum size */ 108 109 /* 110 * Kernel virtual address to page table entry and to physical address. 111 */ 112 #define kvtopte(va) \ 113 (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT]) 114 #define ptetokv(pt) \ 115 ((((pt_entry_t *)(pt) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) 116 #define kvtophys(va) \ 117 ((kvtopte(va)->pg_pfnum << PGSHIFT) | ((int)(va) & PGOFSET)) 118 119