1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * %sccs.include.redist.c% 11 * 12 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 13 * 14 * @(#)cpu.h 7.7 (Berkeley) 06/27/91 15 */ 16 17 /* 18 * Exported definitions unique to hp300/68k cpu support. 19 */ 20 21 /* 22 * definitions of cpu-dependent requirements 23 * referenced in generic code 24 */ 25 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 26 27 /* 28 * function vs. inline configuration; 29 * these are defined to get generic functions 30 * rather than inline or machine-dependent implementations 31 */ 32 #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ 33 #undef NEED_FFS /* don't need ffs function */ 34 #undef NEED_BCMP /* don't need bcmp function */ 35 #undef NEED_STRLEN /* don't need strlen function */ 36 37 #define cpu_exec(p) /* nothing */ 38 #define cpu_wait(p) /* nothing */ 39 40 /* 41 * Arguments to hardclock, softclock and gatherstats 42 * encapsulate the previous machine state in an opaque 43 * clockframe; for hp300, use just what the hardware 44 * leaves on the stack. 45 */ 46 typedef struct intrframe { 47 int pc; 48 int ps; 49 } clockframe; 50 51 #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) 52 #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) 53 #define CLKF_PC(framep) ((framep)->pc) 54 55 56 /* 57 * Preempt the current process if in interrupt from user mode, 58 * or after the current trap/syscall if in system mode. 59 */ 60 #define need_resched() { want_resched++; aston(); } 61 62 /* 63 * Give a profiling tick to the current process from the softclock 64 * interrupt. On hp300, request an ast to send us through trap(), 65 * marking the proc as needing a profiling tick. 66 */ 67 #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } 68 69 /* 70 * Notify the current process (p) that it has a signal pending, 71 * process as soon as possible. 72 */ 73 #define signotify(p) aston() 74 75 #define aston() (astpending++) 76 77 int astpending; /* need to trap before returning to user mode */ 78 int want_resched; /* resched() was called */ 79 80 81 /* 82 * simulated software interrupt register 83 */ 84 extern unsigned char ssir; 85 86 #define SIR_NET 0x1 87 #define SIR_CLOCK 0x2 88 89 #define siroff(x) ssir &= ~(x) 90 #define setsoftnet() ssir |= SIR_NET 91 #define setsoftclock() ssir |= SIR_CLOCK 92 93 94 95 /* 96 * The rest of this should probably be moved to ../hp300/hp300cpu.h, 97 * although some of it could probably be put into generic 68k headers. 98 */ 99 100 /* values for machineid */ 101 #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ 102 #define HP_330 1 /* 16Mhz 68020+68851 MMU */ 103 #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ 104 #define HP_360 3 /* 25Mhz 68030 */ 105 #define HP_370 4 /* 33Mhz 68030+64K external cache */ 106 #define HP_340 5 /* 16Mhz 68030 */ 107 #define HP_375 6 /* 50Mhz 68030+32K external cache */ 108 109 /* values for mmutype (assigned for quick testing) */ 110 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 111 #define MMU_HP 0 /* HP proprietary */ 112 #define MMU_68851 1 /* Motorola 68851 */ 113 114 /* values for ectype */ 115 #define EC_PHYS -1 /* external physical address cache */ 116 #define EC_NONE 0 /* no external cache */ 117 #define EC_VIRT 1 /* external virtual address cache */ 118 119 /* values for cpuspeed (not really related to clock speed due to caches) */ 120 #define MHZ_8 1 121 #define MHZ_16 2 122 #define MHZ_25 3 123 #define MHZ_33 4 124 #define MHZ_50 6 125 126 #ifdef KERNEL 127 extern int machineid, mmutype, ectype; 128 extern char *intiobase, *intiolimit; 129 130 /* what is this supposed to do? i.e. how is it different than startrtclock? */ 131 #define enablertclock() 132 133 #endif 134 135 /* physical memory sections */ 136 #define ROMBASE (0x00000000) 137 #define INTIOBASE (0x00400000) 138 #define INTIOTOP (0x00600000) 139 #define EXTIOBASE (0x00600000) 140 #define EXTIOTOP (0x20000000) 141 #define MAXADDR (0xFFFFF000) 142 143 /* 144 * Internal IO space: 145 * 146 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 147 * 148 * Internal IO space is mapped in the kernel from ``intiobase'' to 149 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 150 * conversion between physical and kernel virtual addresses is easy. 151 */ 152 #define ISIIOVA(va) \ 153 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 154 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 155 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 156 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 157 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 158 159 /* 160 * External IO space: 161 * 162 * DIO ranges from select codes 0-63 at physical addresses given by: 163 * 0x600000 + (sc - 32) * 0x10000 164 * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for 165 * their control space and the remaining areas, [0x200000-0x400000) and 166 * [0x800000-0x1000000), are for additional space required by a card; 167 * e.g. a display framebuffer. 168 * 169 * DIO-II ranges from select codes 132-255 at physical addresses given by: 170 * 0x1000000 + (sc - 132) * 0x400000 171 * The address range of DIO-II space is thus [0x1000000-0x20000000). 172 * 173 * DIO/DIO-II space is too large to map in its entirety, instead devices 174 * are mapped into kernel virtual address space allocated from a range 175 * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. 176 */ 177 #define DIOBASE (0x600000) 178 #define DIOTOP (0x1000000) 179 #define DIOCSIZE (0x10000) 180 #define DIOIIBASE (0x01000000) 181 #define DIOIITOP (0x20000000) 182 #define DIOIICSIZE (0x00400000) 183 184 /* 185 * HP MMU 186 */ 187 #define MMUBASE IIOPOFF(0x5F4000) 188 #define MMUSSTP 0x0 189 #define MMUUSTP 0x4 190 #define MMUTBINVAL 0x8 191 #define MMUSTAT 0xC 192 #define MMUCMD MMUSTAT 193 194 #define MMU_UMEN 0x0001 /* enable user mapping */ 195 #define MMU_SMEN 0x0002 /* enable supervisor mapping */ 196 #define MMU_CEN 0x0004 /* enable data cache */ 197 #define MMU_BERR 0x0008 /* bus error */ 198 #define MMU_IEN 0x0020 /* enable instruction cache */ 199 #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ 200 #define MMU_WPF 0x2000 /* write protect fault */ 201 #define MMU_PF 0x4000 /* page fault */ 202 #define MMU_PTF 0x8000 /* page table fault */ 203 204 #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) 205 #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) 206 207 /* 208 * 68851 and 68030 MMU 209 */ 210 #define PMMU_LVLMASK 0x0007 211 #define PMMU_INV 0x0400 212 #define PMMU_WP 0x0800 213 #define PMMU_ALV 0x1000 214 #define PMMU_SO 0x2000 215 #define PMMU_LV 0x4000 216 #define PMMU_BE 0x8000 217 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 218 219 /* 680X0 function codes */ 220 #define FC_USERD 1 /* user data space */ 221 #define FC_USERP 2 /* user program space */ 222 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 223 #define FC_SUPERD 5 /* supervisor data space */ 224 #define FC_SUPERP 6 /* supervisor program space */ 225 #define FC_CPU 7 /* CPU space */ 226 227 /* fields in the 68020 cache control register */ 228 #define IC_ENABLE 0x0001 /* enable instruction cache */ 229 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 230 #define IC_CE 0x0004 /* clear instruction cache entry */ 231 #define IC_CLR 0x0008 /* clear entire instruction cache */ 232 233 /* additional fields in the 68030 cache control register */ 234 #define IC_BE 0x0010 /* instruction burst enable */ 235 #define DC_ENABLE 0x0100 /* data cache enable */ 236 #define DC_FREEZE 0x0200 /* data cache freeze */ 237 #define DC_CE 0x0400 /* clear data cache entry */ 238 #define DC_CLR 0x0800 /* clear entire data cache */ 239 #define DC_BE 0x1000 /* data burst enable */ 240 #define DC_WA 0x2000 /* write allocate */ 241 242 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 243 #define CACHE_OFF (DC_CLR|IC_CLR) 244 #define CACHE_CLR (CACHE_ON) 245 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 246 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 247